Image sensor and method of manufacturing the same

Abstract

The present disclosure relates to a kind of image sensor preparation method and image sensor, it relates to integrated circuit technical field, including: P-type substrate, and inlay in substrate and along the light-sensitive unit of sequentially distributed parallel to the first direction of substrate, buried gate and photoelectric conversion unit;Light-sensitive unit includes the first N-type epitaxial stack of sequentially stacked along the second direction of facing away substrate, photoelectric conversion unit includes the second N-type epitaxial stack of sequentially stacked along the second direction of facing away substrate;Buried gate includes multiple control gate and channel layer of alternately stacked along the second direction of facing away substrate and the common conductive layer of connecting each control gate, the bottom surface of the channel layer of top layer is lower than the top surface of substrate.At least can improve the electronic transmission efficiency of image sensor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an image sensor and a method for fabricating the image sensor. Background Technology

[0002] The CMOS image sensor (CIS) is the core light-sensing element of a camera. Simply put, its function is to convert the light captured by the lens into a digital image that can be processed by electronic devices.

[0003] However, the electron transfer speed in traditional CMOS image sensors is relatively slow, which cannot meet the requirements. Therefore, improving the electron transfer efficiency in image sensors has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide an image sensor and an image sensor fabrication method to address the technical problem of slow electronic transmission speed in existing image sensors.

[0005] In a first aspect, this disclosure provides an image sensor, including a P-type substrate, and a photosensitive unit, a buried gate, and a photoelectric conversion unit embedded in the substrate and sequentially distributed along a first direction parallel to the top surface of the substrate.

[0006] The photosensitive unit includes a first N-type epitaxial stack stacked sequentially along a second direction away from the substrate, and the photoelectric conversion unit includes a second N-type epitaxial stack stacked sequentially along the second direction; the photosensitive unit is fabricated before the photoelectric conversion unit.

[0007] The buried gate includes a common conductive layer, and control gates and channel layers that are alternately stacked along a second direction. The common conductive layer connects each control gate, and the bottom surface of the top channel layer is lower than the top surface of the substrate.

[0008] In the above embodiments, the image sensor incorporates multiple channel layers to form multiple superchannels, thereby improving electron transport efficiency. Furthermore, the bottom surface of the top channel layer is lower than the top surface of the substrate, ensuring that all channel layers can effectively transport electrons.

[0009] In some embodiments, both the first N-type epitaxial stack and the second N-type epitaxial stack include a plurality of sub-epitaxial layers stacked sequentially along the second direction;

[0010] Among them, adjacent sub-epithelial layers include different Group 5 elements.

[0011] In some embodiments, the photoelectric conversion unit is fabricated before the embedded gate. This avoids damage to the embedded gate during the formation of the photoelectric conversion unit.

[0012] In some embodiments, the top surface of the first N-type epitaxial stack is not lower than the top surface of the substrate, which ensures that the photogenerated electrons collected by the photosensitive unit are transferred to the photoelectric conversion unit.

[0013] In some embodiments, the top surface of the second N-type epitaxial stack is not lower than the top surface of the substrate.

[0014] In some embodiments, the first N-type epitaxial stack includes a first SiP epitaxial layer, a first SiAs epitaxial layer, a second SiP epitaxial layer, a second SiAs epitaxial layer, and a third SiP epitaxial layer stacked sequentially along a second direction.

[0015] In some embodiments, the second N-type epitaxial stack includes a third SiAs epitaxial layer and a fourth SiP epitaxial layer stacked sequentially along a second direction.

[0016] In some embodiments, the channel layer includes a SiB epitaxial layer.

[0017] Secondly, this disclosure provides a method for fabricating an image sensor, including:

[0018] A P-type substrate is provided, the top surface of which includes a dummy gate;

[0019] A first protective layer is formed covering the dummy gate and the top surface of the substrate;

[0020] The first protective layer and substrate on one side of the dummy gate are etched to form the first trench;

[0021] A photosensitive unit is formed within the first trench;

[0022] A second protective layer is formed, covering the first protective layer and the photosensitive unit;

[0023] The second protective layer, the first protective layer, and the substrate on the other side of the dummy gate are etched to form a second trench, with the dummy gate located between the first trench and the second trench;

[0024] A photoelectric conversion unit is formed within the second trench;

[0025] After depositing the passivation layer, the dummy gate and the substrate directly beneath it are etched away to form the gate trench;

[0026] A common conductive layer is formed in the gate trench, and control gates and channel layers are sequentially and alternately stacked in the direction away from the substrate. The common conductive layer connects each control gate. The channel layer, control gate and common conductive layer are used to jointly form a buried gate. The bottom surface of the top channel layer is lower than the top surface of the substrate.

[0027] In some embodiments, forming a photosensitive unit includes:

[0028] A first SiP epitaxial layer is formed at the bottom of the first trench using a selective epitaxial growth process;

[0029] A first SiAs epitaxial layer is formed on the top surface of the first SiP epitaxial layer in the first trench using a selective epitaxial growth process.

[0030] A second SiP epitaxial layer is formed on the top surface of the first SiAs epitaxial layer in the first trench using a selective epitaxial growth process.

[0031] A second SiAs epitaxial layer is formed on the top surface of the second SiP epitaxial layer in the first trench using a selective epitaxial growth process.

[0032] A third SiP epitaxial layer is formed on the top surface of the second SiAs epitaxial layer in the first trench using a selective epitaxial growth process. The first SiP epitaxial layer, the first SiAs epitaxial layer, the second SiP epitaxial layer, the second SiAs epitaxial layer, and the third SiP epitaxial layer are sequentially stacked along a second direction away from the substrate to jointly form a photosensitive unit.

[0033] In some embodiments, forming a photoelectric conversion unit includes:

[0034] A third SiAs epitaxial layer is formed at the bottom of the second trench using a selective epitaxial growth process;

[0035] A fourth SiP epitaxial layer is formed on the top surface of the third SiAs epitaxial layer in the second trench using a selective epitaxial growth process. The third SiAs epitaxial layer and the fourth SiP epitaxial layer, which are stacked sequentially along the second direction away from the substrate, are used to jointly constitute a photoelectric conversion unit.

[0036] In some embodiments, forming a buried grid includes:

[0037] The passivation layer, the second protective layer, the first protective layer, a portion of the dummy gate and the substrate directly below it are etched to form the first gate trench;

[0038] A first control gate is formed at the bottom of the first gate trench using a selective epitaxial growth process;

[0039] A first channel layer is formed on the top surface of the first control gate within the first gate trench using a selective epitaxial growth process.

[0040] A second control gate is formed on the top surface of the first channel layer within the first gate trench using a selective epitaxial growth process.

[0041] A second channel layer is formed on the top surface of the second control gate within the first gate trench using a selective epitaxial growth process.

[0042] A third control gate is formed on the top surface of the second channel layer within the first gate trench using a selective epitaxial growth process.

[0043] A third channel layer is formed on the top surface of the third control gate within the first gate trench using a selective epitaxial growth process.

[0044] A fourth control gate is formed on the top surface of the third channel layer within the first gate trench using a selective epitaxial growth process.

[0045] The passivation layer, the second protective layer, the first protective layer, the remaining dummy gate and the substrate directly below it are etched to form the second gate trench;

[0046] A common conductive layer is filled into the second gate trench, and the common conductive layer connects the first control gate, the second control gate, the third control gate, and the fourth control gate.

[0047] In some embodiments, the channel layer material includes SiB.

[0048] In some embodiments, the material of the control gate includes TiAl.

[0049] In some embodiments, the material of the common conductive layer includes Al.

[0050] The image sensor and its fabrication method in this disclosure can produce the following unexpected technical effects:

[0051] By embedding the gate and adding multiple channel layers to form multiple superchannels, electron transport efficiency is improved. Furthermore, the bottom surface of the top channel layer is lower than the top surface of the substrate to ensure that all channel layers can function as electron transport layers.

[0052] Furthermore, the photosensitive unit includes a first N-type epitaxial stack stacked sequentially along the second direction, and the photoelectric conversion unit includes a second N-type epitaxial stack stacked sequentially along the second direction. That is, the photosensitive unit and the photoelectric conversion unit are formed using an epitaxial growth process. Compared with the image sensor in a comparative embodiment, which uses high-energy ion implantation to form photodiodes and floating diffusion regions, this process is less prone to damage, thereby improving electron transmission efficiency.

[0053] In some embodiments, both the first N-type epitaxial stack and the second N-type epitaxial stack include multiple sub-epitaxy layers stacked sequentially along a second direction; wherein adjacent sub-epitaxy layers include different Group 5 elements, the first N-type epitaxial stack in the photosensitive unit forms a PN junction with the P-type substrate, and all epitaxial stacks in the photosensitive unit are N-type layers. Compared with the image sensor in a comparative embodiment, this forms a superchannel for storing electrons, resulting in high efficiency in storing photogenerated electrons. Furthermore, the multiple sub-epitaxy layers stacked in the N-type epitaxial stack generate a concentration gradient within them after optical excitation, optimizing the transport path of photogenerated carriers, reducing the recombination rate during diffusion, and improving the quantum efficiency of the photosensitive unit and the photoelectric conversion unit. Furthermore, since the atomic mass of pentavalent elements is higher than that of silicon, their mobility is lower during epitaxial growth, leading to uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel area. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the structure of an image sensor in a comparative embodiment;

[0056] Figure 2 This is a schematic flowchart of an image sensor fabrication method provided in one embodiment;

[0057] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first protective layer covering the dummy gate and the top surface of the substrate in step S20 of the image sensor fabrication method provided in one embodiment.

[0058] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching the first protective layer and substrate on one side of the dummy gate to form the first trench in step S30 of the image sensor fabrication method provided in one embodiment;

[0059] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a photosensitive unit in the first trench in step S40 of the image sensor fabrication method provided in one embodiment.

[0060] Figure 6 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching the second protective layer, the first protective layer, and the substrate on the other side of the dummy gate to form the second trench in step S60 of the image sensor fabrication method provided in one embodiment;

[0061] Figure 7 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a photoelectric conversion unit in the second trench in step S70 of the image sensor fabrication method provided in one embodiment;

[0062] Figure 8 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after depositing a passivation layer in step S80 of the image sensor fabrication method provided in one embodiment.

[0063] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching away the dummy gate and the substrate directly below it to form the first gate trench in step S80 of the image sensor fabrication method provided in one embodiment;

[0064] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a control gate and a channel layer alternately stacked in sequence along the direction away from the substrate in step S90 of the image sensor fabrication method provided in one embodiment;

[0065] Figure 11 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a common conductive layer connecting each control gate in the gate trench in step S90 of the image sensor fabrication method provided in one embodiment.

[0066] Figure 12 This is a schematic diagram of the structure of an image sensor provided in one embodiment.

[0067] Explanation of reference numerals in the attached figures:

[0068] 110. Substrate; 121. First protective layer; 122. Second protective layer; 123. Passivation layer; 130. Buried gate; 131. Dummy gate; 132. First control gate; 133. First channel layer; 134. Second control gate; 135. Second channel layer; 136. Third control gate; 137. Third channel layer; 138. Fourth control gate; 139. Common conductive layer; 141. First trench; 142. Second trench; 143. First gate trench; 150. Photosensitive unit; 151. First SiP epitaxial layer; 152. First SiAs epitaxial layer; 153. Second SiP epitaxial layer; 154. Second SiAs epitaxial layer; 155. Third SiP epitaxial layer; 160. Photoelectric conversion unit; 161. Third SiAs epitaxial layer; 162. Fourth SiP epitaxial layer; 200. Pixel circuit. Detailed Implementation

[0069] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0075] In this embodiment, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the stacking direction or the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment, the first direction can be the ox direction, and the second direction can be the oz direction. The "longitudinal section" in this embodiment is perpendicular to the surface of the substrate.

[0076] Please refer to Figure 1 In a comparative embodiment of the CMOS image sensor, high-energy ion implantation is required in the front-end process to form the photodiode (PD) and floating diffusion region (FD), which causes damage and slows down the electron transport speed of the transfer gate (Tx). Figure 1 The use of ion implantation to form photodiodes and floating diffusion regions in image sensors is one of the reasons for low electron transport efficiency.

[0077] Please refer to Figure 2 In some embodiments, this application provides a method for fabricating an image sensor, comprising:

[0078] Step S10: Provide a P-type substrate, the top surface of which includes a dummy gate;

[0079] Step S20: A first protective layer is formed covering the dummy gate and the top surface of the substrate;

[0080] Step S30: Etch the first protective layer and substrate on one side of the dummy gate to form the first trench;

[0081] Step S40: A photosensitive unit is formed in the first trench;

[0082] Step S50: A second protective layer is formed covering the first protective layer and the photosensitive unit;

[0083] Step S60: Etch the second protective layer, the first protective layer, and the substrate on the other side of the dummy gate to form a second trench, with the dummy gate located between the first trench and the second trench;

[0084] Step S70: A photoelectric conversion unit is formed in the second trench;

[0085] Step S80: After depositing the passivation layer, the dummy gate and the substrate directly below it are etched away to form a gate trench.

[0086] In step S90, a common conductive layer is formed in the gate trench, and control gates and channel layers are sequentially and alternately stacked in the direction away from the substrate. The common conductive layer connects each control gate. The channel layer, control gate and common conductive layer are used to jointly form a buried gate. The bottom surface of the top channel layer is lower than the top surface of the substrate.

[0087] In the image sensor fabrication method of this disclosure, multiple channel layers are added by embedding a gate to form multiple superchannels, thereby improving electron transport efficiency. Furthermore, the bottom surface of the top channel layer is lower than the top surface of the substrate to ensure that all channel layers can effectively transport electrons.

[0088] Please refer to Figure 3 In some embodiments, step S10 provides a P-type substrate 110, which may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 110 may be a single-layer structure or a multi-layer structure. For example, the substrate 110 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 110 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. In this embodiment, the substrate 110 is a P-type substrate, and boron (B) may be doped into the substrate 110 material. In addition, trivalent elements such as indium (In) and gallium (Ga) may also be used. The type of substrate 110 should not limit the scope of this disclosure.

[0089] Please continue to refer to this. Figure 3In some embodiments, a dummy gate 131 is formed on the back side of the substrate. The top surface of the substrate 110 can refer to its back side, thus forming a back-side illuminated (BSI) CMOS image sensor. The dummy gate 131 on the top surface of the substrate 110 can be made of polycrystalline silicon, amorphous silicon, silicon nitride, dielectric, or other materials, or a composite stacked structure. The dummy gate material can be deposited on the substrate 110 first, and then the dummy gate material can be patterned and etched to form the dummy gate structure. The position of the dummy gate 131 on the substrate 110 should correspond to the position of the buried gate 130 formed later in the substrate 110. It can be understood that the position occupied by the buried gate 130 can include directly above, below, or above the dummy gate 131. When the buried gate 130 is formed later, the dummy gate 131 will be removed. The dummy gate 131, which is temporarily present on the substrate 110, can protect the substrate 110 below during the formation of the photosensitive unit and the photoelectric conversion unit, and avoid damage to the substrate 110 below the dummy gate 131 during the process of forming the photosensitive unit and the photoelectric conversion unit.

[0090] Please continue to refer to this. Figure 3 In some embodiments, a first protective layer 121 is formed in step S20, covering the dummy gate 131 and the top surface of the substrate 110. The material of the first protective layer 121 may be silicon nitride (SiN) or silicon dioxide (SiO2), or it may be a multilayer stacked structure, etc. The first protective layer 121 may be formed by at least one of the processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0091] Please refer to Figure 4 In some embodiments, step S30 etches the first protective layer 121 and substrate 110 on one side of the dummy gate 131 to form a first trench 141. Exemplarily, the photosensitive unit, buried gate, and photoelectric conversion unit can be arranged sequentially along the first direction; therefore, the first trench 141 can be formed on the side opposite to the first direction of the dummy gate 131. In other examples, it can be at other locations. Specifically, a photoresist layer (not shown) can be spin-coated over the first protective layer 121 first. Then, at the location of the photosensitive unit on one side of the dummy gate 131, the photoresist is patterned to form a corresponding window, exposing the underlying first protective layer 121. Then, the first protective layer 121 and substrate 110 are dry-etched sequentially to form the first trench 141. The first trench 141 is used for the subsequent formation of the photosensitive unit. The specific shape and size of the first trench 141 can be defined according to the requirements of the photosensitive unit.

[0092] Please refer to Figure 5 Specifically, the photosensitive unit 150 includes a first N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110. The first N-type epitaxial stack is a multilayer sub-epitaxy layer sequentially formed along the second direction using a selective epitaxial growth process, compared to... Figure 1 The image sensor in this technology uses high-energy ion implantation to form photodiodes, which is less prone to damage compared to traditional methods. Figure 1 The transmission gate in the middle improves the efficiency of electron transmission.

[0093] Please continue to refer to this. Figure 5 In some embodiments, adjacent sub-epitaxial layers are made of different materials. For example, adjacent sub-epitaxial layers may contain different Group 5 elements, causing a concentration gradient to form within the multiple sub-epitaxial layers stacked in the first N-type epitaxial stack after photoexcitation. This optimizes the transport path of photogenerated carriers, reduces the recombination rate during diffusion, and improves the quantum efficiency of the photosensitive unit 150. Furthermore, since pentavalent elements have a higher atomic mass than silicon and lower mobility during epitaxial growth, resulting in uneven doping concentration in a single doped layer, growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0094] Please continue to refer to this. Figure 5 In some embodiments, the top surface of the first N-type epitaxial stack is not lower than the top surface of the substrate 110, which can ensure that the photogenerated electrons collected by the photosensitive unit 150 can be transferred to the photoelectric conversion unit.

[0095] Please continue to refer to this. Figure 5In some embodiments, step S40, forming the photosensitive unit 150 in the first trench 141 may include: forming a first SiP epitaxial layer 151 at the bottom of the first trench 141 using a selective epitaxial growth process; forming a first SiAs epitaxial layer 152 on the top surface of the first SiP epitaxial layer 151 in the first trench 141 using a selective epitaxial growth process; forming a second SiP epitaxial layer 153 on the top surface of the first SiAs epitaxial layer 152 in the first trench 141 using a selective epitaxial growth process; forming a second SiAs epitaxial layer 154 on the top surface of the second SiP epitaxial layer 153 in the first trench 141 using a selective epitaxial growth process; and forming a third SiP epitaxial layer 155 on the top surface of the second SiAs epitaxial layer 154 in the first trench 141 using a selective epitaxial growth process. A first SiP epitaxial layer 151, a first SiAs epitaxial layer 152, a second SiP epitaxial layer 153, a second SiAs epitaxial layer 154, and a third SiP epitaxial layer 155, sequentially stacked along a second direction away from the substrate 110, are used to jointly constitute the photosensitive unit 150. The SiAs epitaxial layer characterizes silicon materials containing arsenic (As), and the SiP epitaxial layer characterizes silicon materials containing phosphorus (P). The first SiP epitaxial layer 151, the first SiAs epitaxial layer 152, the second SiP epitaxial layer 153, the second SiAs epitaxial layer 154, and the third SiP epitaxial layer 155 constitute a first N-type epitaxial stack. The first N-type epitaxial stack in the photosensitive unit 150 can form a PN junction with the P-type substrate. The first N-type epitaxial stack in the photosensitive unit 150 includes multiple N-type sub-epitaxy layers, compared to... Figure 1 In the image sensor, each N-type sub-epitaxial layer forms a superchannel for storing electrons, thus improving the efficiency of storing photogenerated electrons.

[0096] Please continue to refer to this. Figure 5 In some embodiments, the thicknesses of the first SiP epitaxial layer 151, the second SiP epitaxial layer 153, and the third SiP epitaxial layer 155 can range from 10nm to 20nm, specifically 10nm, 15nm, or 20nm. The thicknesses of the first SiAs epitaxial layer 152 and the second SiAs epitaxial layer 154 can range from 20nm to 30nm, specifically 20nm, 25nm, or 30nm. The thicknesses of the first SiP epitaxial layer 151, the second SiP epitaxial layer 153, and the third SiP epitaxial layer 155 can be the same or different, and the thicknesses of the first SiAs epitaxial layer 152 and the second SiAs epitaxial layer 154 can be the same or different.

[0097] Please refer to Figure 5 and Figure 6 In some embodiments, step S50 involves forming a second protective layer 122 covering the first protective layer 121 and the photosensitive unit 150. Figure 6In this embodiment, the second protective layer 122 is made of the same material as the first protective layer 121. Where the first protective layer 121 is located, the second protective layer 122 covers the first protective layer 121; therefore, only the designation of the second protective layer 122 is shown. The material of the second protective layer 122 can be SiN or SiO2, or it can be a multilayer stacked structure, etc. At least one of the processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition can be used to form the second protective layer 122. In other embodiments, the material of the second protective layer 122 may also be different from the material of the first protective layer 121.

[0098] Please continue to refer to this. Figure 5 and Figure 6 In some embodiments, step S60 etches the second protective layer 122, the first protective layer 121, and the substrate 110 on the other side of the dummy gate 131 to form a second trench 142, with the dummy gate 131 located between the first trench 141 and the second trench 142. In this embodiment, the photosensitive unit, the dummy gate 131, and the second trench 142 formed in the first trench can be arranged sequentially along a first direction. Specifically, a photoresist layer can be spin-coated over the second protective layer 122 firstly, and then, at the location of the photoelectric conversion unit on the other side of the dummy gate 131, the photoresist is patterned to form a corresponding window exposing the underlying second protective layer 122. Then, the second protective layer 122, the first protective layer, and the substrate 110 are dry-etched sequentially to form the second trench 142. The second trench 142 is used for the subsequent formation of the photoelectric conversion unit. The specific shape and size of the second trench 142 can be defined according to the requirements of the photoelectric conversion unit.

[0099] For details, please refer to Figure 7 In some embodiments, the photoelectric conversion unit 160 includes a second N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110. The second N-type epitaxial stack is a multilayer sub-epitaxy layer sequentially formed along the second direction using a selective epitaxial growth process, compared to... Figure 1 The image sensor uses high-energy ion implantation to form a floating diffusion region, which is less prone to damage and thus improves electron transmission efficiency.

[0100] Please continue to refer to this. Figure 7 In some embodiments, adjacent sub-epitaxial layers are made of different materials, for example, adjacent sub-epitaxial layers include different Group 5 elements. This causes the multiple sub-epitaxial layers stacked in the second N-type epitaxial stack to generate a concentration gradient within them after photoexcitation, optimizing the transport path of photogenerated carriers, reducing the recombination rate during diffusion, and improving the quantum efficiency of the photoelectric conversion unit 160. Furthermore, since pentavalent elements have a higher atomic mass than silicon and a lower mobility during epitaxial growth, resulting in uneven doping concentration in a single doped layer, growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0101] In some embodiments, the top surface of the second N-type epitaxial stack is not lower than the top surface of the substrate 110.

[0102] Please continue to refer to this. Figure 6 and Figure 7 In some embodiments, step S70, forming the photoelectric conversion unit 160 within the second trench 142, may include: forming a third SiAs epitaxial layer 161 at the bottom of the second trench 142 using a selective epitaxial growth process; and forming a fourth SiP epitaxial layer 162 on the top surface of the third SiAs epitaxial layer 161 within the second trench 142 using a selective epitaxial growth process. The third SiAs epitaxial layer 161 and the fourth SiP epitaxial layer 162, sequentially stacked along a second direction away from the substrate 110, are used to jointly constitute the photoelectric conversion unit 160. The thickness of the third SiAs epitaxial layer 161 can range from 20 nm to 60 nm, specifically 20 nm, 30 nm, 40 nm, 50 nm, or 60 nm. The thickness of the fourth SiP epitaxial layer 162 can range from 10 nm to 50 nm, specifically 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm. The third SiAs epitaxial layer 161 and the fourth SiP epitaxial layer 162 constitute the second N-type epitaxial stack, which forms the photoelectric conversion unit 160. The photoelectric conversion unit 160 is composed of two N-type sub-epitaxy layers, which can increase the ion concentration in the region of the photoelectric conversion unit 160.

[0103] Please continue to refer to this. Figure 7 In some embodiments, the dummy gate 131 is located between the first trench 141 and the second trench 142, such that the buried gate ultimately formed at the corresponding position of the dummy gate 131 can control the transfer of electrons from the photosensitive unit 150 located in the first trench 141 to the photoelectric conversion unit 160 located in the second trench 142. The photosensitive unit 150 is fabricated before the photoelectric conversion unit 160, and the photoelectric conversion unit 160 is fabricated before the buried gate. This avoids damage to the buried gate during the formation of the photosensitive unit 150 and the photoelectric conversion unit 160.

[0104] Please refer to Figures 8-12 In some embodiments, Figures 8-10 and Figure 12 In this embodiment, the material of the passivation layer 123 is the same as the material of the first protective layer 121 and the second protective layer 122, thereby Figures 8-10 and Figure 12Only the reference numeral for passivation layer 123 is shown. The process of forming the buried gate 130 in steps S80 and S90 may include depositing the passivation layer 123. The passivation layer 123, the second protective layer 122, the first protective layer 121, a portion of the dummy gate 131 and the substrate 110 directly below it are etched to form the first gate trench 143. A first control gate 132 is formed at the bottom of the first gate trench 143 using a selective epitaxial growth process; a first channel layer 133 is formed on the top surface of the first control gate 132 within the first gate trench 143 using a selective epitaxial growth process; a second control gate 134 is formed on the top surface of the first channel layer 133 within the first gate trench 143 using a selective epitaxial growth process; a second channel layer 135 is formed on the top surface of the second control gate 134 within the first gate trench 143 using a selective epitaxial growth process; a third control gate 136 is formed on the top surface of the second channel layer 135 within the first gate trench 143 using a selective epitaxial growth process; a third channel layer 137 is formed on the top surface of the third control gate 136 within the first gate trench 143 using a selective epitaxial growth process; and a fourth control gate 138 is formed on the top surface of the third channel layer 137 within the first gate trench 143 using a selective epitaxial growth process. Etch passivation layer 123, second protective layer 122, first protective layer 121, remaining dummy gate 131 and substrate 110 directly below it to form second gate trench (not shown); fill the second gate trench with common conductive layer 139.

[0105] For details, please continue to refer to [the website / information]. Figure 8 In some embodiments, the passivation layer 123 can be made of SiN or SiO2, or it can be a multilayer stacked structure, etc. The materials of the passivation layer 123, the first protective layer 121, and the second protective layer 122 can be the same or different. The passivation layer 123 can be formed using at least one of the processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The formed passivation layer 123 covers the second protective layer 122 and the photoelectric conversion unit 160. The thickness of the formed passivation layer 123 can be in the range of 5nm to 15nm, specifically 5nm, 10nm, or 15nm, etc.

[0106] Please refer to Figure 9In some embodiments, a photoresist layer can be spin-coated onto the surface of the passivation layer 123 first. Then, at the location of the dummy gate 131, the photoresist is patterned to form a corresponding window, exposing the underlying passivation layer 123. Then, the passivation layer 123, the second protective layer 122, the first protective layer 121, part of the dummy gate 131, and the substrate 110 are sequentially etched using dry etching to form a first gate trench 143 in the buried gate 130 region. It should be noted that during the etching process to form the first gate trench 143, the dummy gate 131 is not completely removed because it occupies the corresponding position of the entire buried gate 130. Besides the channel layer and control gate formed in the first trench 141, the dummy gate 131 also occupies the position of the common conductive layer 139. The specific shape and size of the first gate trench 143 can be defined according to the requirements of the control gate and channel layer in the buried gate 130. The final height of the bottom of the first gate trench 143 can be close to the bottom height of the photosensitive unit 150.

[0107] In some embodiments, the buried gate 130 has at least two channel layers and at least three control gates. The bottom and top layers of the buried gate 130 are both control gates, arranged sequentially with the channel layers. Each control gate controls the transfer of electrons in the channel layer below it, and the bottom control gate controls the transfer of electrons in the P-type substrate 110. By adding multiple channel layers, the buried gate 130 forms multiple superchannels, thereby improving electron transport efficiency. Furthermore, the bottom surface of the top channel layer can be lower than the top surface of the substrate to ensure that all channel layers can function as electron transport layers.

[0108] Please refer to Figure 10In some embodiments, a selective epitaxial growth process is used to alternately form control gates and channel layers within the first gate trench 143. This may include a first control gate 132, a first channel layer 133, a second control gate 134, a second channel layer 135, a third control gate 136, a third channel layer 137, and a fourth control gate 138 arranged sequentially along the OZ direction. The thicknesses of the first control gate 132, second control gate 134, third control gate 136, and fourth control gate 138 can be the same or different, ranging from 10nm to 50nm, specifically 10nm, 20nm, 30nm, 40nm, or 50nm. The thicknesses of the first channel layer 133, second channel layer 135, and third channel layer 137 can also be the same or different, ranging from 10nm to 30nm, specifically 10nm, 20nm, or 30nm. In other embodiments, the number of control gate and channel layers can be increased or decreased as needed. The materials of the first control gate 132, the second control gate 134, the third control gate 136, and the fourth control gate 138 can be the same or different. For example, they can all include titanium aluminide (TiAl), or they can be replaced by titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or tantalum aluminum carbide (TaAlC). The materials of the first channel layer 133, the second channel layer 135, and the third channel layer 137 can be the same or different. For example, they can all include silicon boride (SiB), or they can be replaced by titanium nitride (TiN).

[0109] Please refer to Figure 11 , Figure 11 for Figure 10 A cross-sectional view after rotating 90°. The passivation layer 123, the remaining dummy gate 131, and the substrate 110 directly below it are etched to form a second gate trench (not shown). A common conductive layer 139 is then filled into the second gate trench. A photoresist layer can be spin-coated over the passivation layer 123 first. At the location of the remaining dummy gate 131, the photoresist is patterned to form a corresponding window, exposing the underlying passivation layer 123. Then, the passivation layer 123, the second protective layer 122, the first protective layer 121, the remaining dummy gate 131, and the substrate 110 are sequentially dry-etched to form the second gate trench in the buried gate 130 area. The specific shape and size of the second gate trench can be defined according to the requirements of the common conductive layer 139 in the buried gate 130. The final height of the bottom of the second gate trench can be consistent with the bottom height of the first gate channel, thereby ensuring that all control gates can be connected.

[0110] Please continue to refer to this. Figure 11A common conductive layer 139 is filled into the second gate trench, connecting the first control gate 132, the second control gate 134, the third control gate 136, and the fourth control gate 138. The bottom height of the control gates can be configured based on the height of the first control gate 132 to ensure connection of all control gates. The material of the common conductive layer 139 can include aluminum (Al), or tungsten (W) or cobalt (Co), or other alloy materials instead of Al. The resulting embedded gate 130 can be a vertical transfer gate (VTG) in an image sensor.

[0111] Please continue to refer to this. Figures 10-12 In some embodiments, an image sensor is provided, fabricated using the image sensor fabrication method described in any of the foregoing embodiments. The image sensor includes a P-type substrate 110, and photosensitive units 150, buried gates 130, and photoelectric conversion units 160 embedded within the substrate 110 and sequentially distributed along a first direction parallel to the top surface of the substrate 110. The photosensitive unit 150 includes a first N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110, and the photoelectric conversion unit 160 includes a second N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110. The photosensitive unit 150 is fabricated before the photoelectric conversion unit 160. The buried gate 130 includes a common conductive layer 139, and control gates and channel layers alternately stacked along a second direction away from the substrate 110. The common conductive layer 139 connects each control gate, and the bottom surface of the topmost channel layer is lower than the top surface of the substrate 110. The image sensor adds multiple channel layers to form multiple superchannels, thereby improving electron transport efficiency. Furthermore, the fact that the bottom surface of the top channel layer is lower than the top surface of the substrate ensures that all channel layers can function as electron transport layers.

[0112] Furthermore, the photosensitive unit 150 includes a first N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110, and the photoelectric conversion unit 160 includes a second N-type epitaxial stack sequentially stacked along a second direction away from the substrate 110. That is, the photosensitive unit 150 and the photoelectric conversion unit 160 are formed using an epitaxial growth process, compared to... Figure 1 The image sensor uses high-energy ion implantation to form photodiodes and floating diffusion regions, which is less prone to damage and thus improves electron transmission efficiency.

[0113] Please continue to refer to this. Figure 12 In some embodiments, both the first N-type epitaxial stack and the second N-type epitaxial stack include multiple sub-epitaxy layers stacked sequentially along a second direction away from the substrate 110; wherein adjacent sub-epitaxy layers include different Group 5 elements, the first N-type epitaxial stack in the photosensitive unit 150 forms a PN junction with the P-type substrate 110, and all epitaxial stacks in the photosensitive unit 150 are N-type layers, compared to Figure 1 The image sensor in the image forms a superchannel for storing electrons, resulting in high efficiency in storing photogenerated electrons. Furthermore, the multiple sub-epitaxy layers stacked in the N-type epitaxial layer generate a concentration gradient within them upon optical excitation, optimizing the transport path of photogenerated carriers, reducing recombination during diffusion, and improving the quantum efficiency of the photosensitive unit 150 and the photoelectric conversion unit 160. Furthermore, since pentavalent elements have a higher atomic mass than silicon and lower mobility during epitaxial growth, resulting in uneven doping concentration in a single doped layer, growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0114] Please continue to refer to this. Figure 12 In some embodiments, the photoelectric conversion unit 160 is fabricated before the embedded gate 130. This avoids damage to the embedded gate 130 during the formation of the photoelectric conversion unit 160.

[0115] Please continue to refer to this. Figure 12 In some embodiments, the top surface of the first N-type epitaxial stack is not lower than the top surface of the substrate 110, which can ensure that the photogenerated electrons collected by the photosensitive unit 150 can be transmitted to the photoelectric conversion unit 160.

[0116] Please continue to refer to this. Figure 12 In some embodiments, the top surface of the second N-type epitaxial stack is not lower than the top surface of the substrate 110.

[0117] Please continue to refer to this. Figure 12 In some embodiments, the first N-type epitaxial stack includes a first SiP epitaxial layer 151, a first SiAs epitaxial layer 152, a second SiP epitaxial layer 153, a second SiAs epitaxial layer 154 and a third SiP epitaxial layer 155 stacked sequentially along the second direction.

[0118] Please continue to refer to this. Figure 12 In some embodiments, the second N-type epitaxial stack includes a third SiAs epitaxial layer 161 and a fourth SiP epitaxial layer 162 stacked sequentially along the second direction.

[0119] In some embodiments, the channel layer includes a SiB epitaxial layer.

[0120] In some embodiments, please refer to Figures 10-12 The image sensor may also include a pixel circuit 200, wherein the source of the reset transistor (RST) and the gate of the source follower (SF) in the pixel circuit 200 are connected to the photoelectric conversion unit 160 in the above embodiment. The image sensor operates as follows:

[0121] Reset: Turn on the reset transistor (RST), connect the pixel power supply (VAAPIX) to the photoelectric conversion unit 160, and reset the potential of the photoelectric conversion unit 160 to a high level (clear electrons).

[0122] Transfer: When the embedded gate 130 is turned on, all the electrons collected by the photosensitive unit 150 are transferred to the photoelectric conversion unit 160. The electrons neutralize the positive charge of the photoelectric conversion unit 160, causing the potential of the photoelectric conversion unit 160 to decrease (the decrease is proportional to the light intensity).

[0123] Readout: The potential of photoelectric conversion unit 160 directly controls the gate of the source follower (SF). The source follower (SF) is a buffer / amplifier that converts the small voltage changes of photoelectric conversion unit 160 and drives the row select transistor (RS).

[0124] Output: The row selector (RS) is a switch that turns on when a row of pixels is selected, sending the voltage signal output by the source follower (SF) to the pixel output bus.

[0125] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. An image sensor, characterized in that, It includes a P-type substrate, and a photosensitive unit, a buried gate, and a photoelectric conversion unit embedded in the substrate and sequentially distributed along a first direction parallel to the top surface of the substrate; The photosensitive unit includes a first N-type epitaxial stack layer sequentially stacked along a second direction away from the substrate, and the photoelectric conversion unit includes a second N-type epitaxial stack layer sequentially stacked along the second direction; the photosensitive unit is fabricated prior to the photoelectric conversion unit. The buried gate includes a common conductive layer and control gates and channel layers alternately stacked along the second direction, the common conductive layer connecting each of the control gates, and the bottom surface of the topmost channel layer being lower than the top surface of the substrate.

2. The image sensor according to claim 1, characterized in that, Both the first N-type epitaxial stack and the second N-type epitaxial stack include a plurality of sub-epitaxy layers stacked sequentially along the second direction; The adjacent sub-epicentric layers include different fifth main group elements.

3. The image sensor according to claim 1, characterized in that, The photoelectric conversion unit is manufactured before the embedded gate.

4. The image sensor according to claim 1, characterized in that, The top surface of the first N-type epitaxial stack is not lower than the top surface of the substrate; and / or the top surface of the second N-type epitaxial stack is not lower than the top surface of the substrate.

5. The image sensor according to claim 1, characterized in that, Includes at least one of the following features: The first N-type epitaxial stack includes a first SiP epitaxial layer, a first SiAs epitaxial layer, a second SiP epitaxial layer, a second SiAs epitaxial layer, and a third SiP epitaxial layer stacked sequentially along the second direction; The second N-type epitaxial stack includes a third SiAs epitaxial layer and a fourth SiP epitaxial layer stacked sequentially along the second direction; The channel layer includes a SiB epitaxial layer.

6. A method for fabricating an image sensor, characterized in that, include: A P-type substrate is provided, wherein the top surface of the substrate includes a dummy gate; A first protective layer is formed covering the dummy gate and the top surface of the substrate; The first protective layer and the substrate on one side of the dummy gate are etched to form a first trench; A photosensitive unit is formed within the first trench; A second protective layer is formed covering the first protective layer and the photosensitive unit; The second protective layer, the first protective layer, and the substrate on the other side of the dummy gate are etched to form a second trench, and the dummy gate is located between the first trench and the second trench; A photoelectric conversion unit is formed within the second trench; After depositing the passivation layer, the dummy gate and the substrate directly beneath it are etched away to form a gate trench; A common conductive layer is formed in the gate trench, and control gates and channel layers are sequentially and alternately stacked in a direction away from the substrate. The common conductive layer connects each of the control gates. The channel layer, the control gate, and the common conductive layer are used to jointly form a buried gate. The bottom surface of the topmost channel layer is lower than the top surface of the substrate.

7. The image sensor fabrication method according to claim 6, characterized in that, The photosensitive unit comprises: A first SiP epitaxial layer is formed at the bottom of the first trench using a selective epitaxial growth process; A first SiAs epitaxial layer is formed on the top surface of the first SiP epitaxial layer in the first trench using a selective epitaxial growth process. A second SiP epitaxial layer is formed on the top surface of the first SiAs epitaxial layer in the first trench using a selective epitaxial growth process. A second SiAs epitaxial layer is formed on the top surface of the second SiP epitaxial layer in the first trench using a selective epitaxial growth process. A third SiP epitaxial layer is formed on the top surface of the second SiAs epitaxial layer in the first trench using a selective epitaxial growth process. The first SiP epitaxial layer, the first SiAs epitaxial layer, the second SiP epitaxial layer, the second SiAs epitaxial layer, and the third SiP epitaxial layer are sequentially stacked along a second direction away from the substrate to jointly constitute the photosensitive unit.

8. The image sensor fabrication method according to claim 6, characterized in that, The photoelectric conversion unit comprises: A third SiAs epitaxial layer is formed at the bottom of the second trench using a selective epitaxial growth process; A fourth SiP epitaxial layer is formed on the top surface of the third SiAs epitaxial layer in the second trench using a selective epitaxial growth process. The third SiAs epitaxial layer and the fourth SiP epitaxial layer, which are stacked sequentially along a second direction away from the substrate, are used to jointly constitute the photoelectric conversion unit.

9. The image sensor fabrication method according to claim 6, characterized in that, Forming the embedded grid includes: The passivation layer, the second protective layer, the first protective layer, a portion of the dummy gate and the substrate directly below it are etched to form a first gate trench; A first control gate is formed at the bottom of the first gate trench using a selective epitaxial growth process; A first channel layer is formed on the top surface of the first control gate within the first gate trench using a selective epitaxial growth process. A second control gate is formed on the top surface of the first channel layer within the first gate trench using a selective epitaxial growth process. A second channel layer is formed on the top surface of the second control gate within the first gate trench using a selective epitaxial growth process; A third control gate is formed on the top surface of the second channel layer within the first gate trench using a selective epitaxial growth process; A third channel layer is formed on the top surface of the third control gate within the first gate trench using a selective epitaxial growth process. A fourth control gate is formed on the top surface of the third channel layer within the first gate trench using a selective epitaxial growth process. The passivation layer, the second protective layer, the first protective layer, the remaining dummy gate and the substrate directly below it are etched to form a second gate trench; The common conductive layer is filled into the second gate trench, and the common conductive layer connects the first control gate, the second control gate, the third control gate, and the fourth control gate.

10. The image sensor fabrication method according to claim 6, characterized in that, Includes at least one of the following features: The material of the channel layer includes SiB; The material of the control gate includes TiAl; The material of the common conductive layer includes Al.

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