Image sensor and method of manufacturing an image sensor

Abstract

The present disclosure relates to an image sensor and a method for manufacturing the same, and belongs to the technical field of integrated circuits. The image sensor comprises a P-type substrate, photoelectric diodes, buried gates and readout diodes which are embedded in the substrate and are arranged in sequence along a first direction parallel to the substrate. The longitudinal section of the photoelectric diodes along the first direction is in the shape of T. The photoelectric diodes and the readout diodes each comprise an N-type epitaxial layer and a P-type epitaxial layer which are stacked in sequence along a second direction away from the substrate. The P-type epitaxial layers of the photoelectric diodes and the readout diodes are prepared synchronously in the same process step. The buried gate comprises a gate dielectric layer embedded in the substrate and a gate conductive layer which penetrates the gate dielectric layer along the second direction and extends into the substrate. The performance and reliability of the CIS can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an image sensor and a method for fabricating the image sensor. Background Technology

[0002] Complementary metal-oxide-semiconductor image sensors (CMOS Image Sensor, CIS) have advantages such as low cost, low power consumption and high integration, and have good application value in consumer electronics, automotive electronics, security monitoring and industrial and medical fields.

[0003] However, in traditional CIS manufacturing processes, the use of high-energy ion implantation in the front-end process to form photodiodes or other transistors can cause substrate damage and reduce the performance and reliability of other components on the substrate, thereby reducing the performance and reliability of the manufactured CIS. Summary of the Invention

[0004] Therefore, it is necessary to provide an image sensor and an image sensor fabrication method to address the technical problems of the need to improve the yield and performance of image sensors in the existing technology.

[0005] In a first aspect, this disclosure provides an image sensor, including a P-type substrate, and a photodiode, a buried gate, and a readout diode embedded in the substrate and sequentially distributed along a first direction parallel to the substrate; the photodiode has a "T"-shaped longitudinal section along the first direction; both the photodiode and the readout diode include an N-type epitaxial layer and a P-type epitaxial layer sequentially stacked along a second direction away from the substrate; the P-type epitaxial layers of the photodiode and the readout diode are fabricated simultaneously in the same process steps; the buried gate includes a gate dielectric layer buried in the substrate, and a gate conductive layer extending through the gate dielectric layer and into the substrate along the second direction, the top surface of the gate dielectric layer being not lower than the top surface of the substrate.

[0006] In some embodiments, the longitudinal section of the gate conductive layer along the first direction is T-shaped. A thinner gate bottom reduces the capacitance between the gate and the channel, while a wider top ensures low resistance without significantly increasing the bottom capacitance. This helps reduce Miller capacitance, thereby reducing switching losses.

[0007] In some embodiments, the gate conductive layer includes a horizontal portion extending along a first direction and a vertical portion extending along a second direction; wherein the horizontal portion covers the top surface of the gate dielectric layer. A wider top can increase the cross-sectional area of ​​the gate conductive layer, thereby significantly reducing the sheet resistance of the gate. This is critical for high-frequency switching applications, as it can shorten the gate charge / discharge time (reduce RC delay) and increase the device's operating frequency and switching speed.

[0008] In some embodiments, the N-type epitaxial layer of the photodiode includes a first sub-N-type epitaxial layer and a second sub-N-type epitaxial layer. The first sub-N-type epitaxial layer is embedded in the substrate, and its top surface is not higher than the top surface of the substrate. The second sub-N-type epitaxial layer penetrates the first sub-N-type epitaxial layer along a second direction and extends into the substrate. The P-type epitaxial layer of the photodiode covers the top surfaces of both the first and second sub-N-type epitaxial layers. The second sub-N-type epitaxial layer can circumferentially surround the first sub-N-type epitaxial layer, facilitating the generation of a concentration gradient within the N-type epitaxial layer of the photodiode. This difference optimizes the transport path of photogenerated carriers, reduces the recombination rate during diffusion, and improves quantum efficiency.

[0009] In some embodiments, the first sub-N-type epitaxial layer is fabricated before the N-type epitaxial layer of the readout diode. This facilitates the simultaneous fabrication of the remaining structure of the photodiode and the readout diode in the same process steps, reducing the complexity and cost of the fabrication process.

[0010] In some embodiments, the first sub-N-type epitaxial layer includes a SiAs epitaxial layer.

[0011] In some embodiments, the second sub-N-type epitaxial layer includes a SiP epitaxial layer.

[0012] In some embodiments, the P-type epitaxial layer of the photodiode includes a SiB epitaxial layer.

[0013] In some embodiments, the N-type epitaxial layer of the readout diode includes a SiP epitaxial layer.

[0014] In some embodiments, the P-type epitaxial layer of the readout diode includes a SiB epitaxial layer.

[0015] In some embodiments, the N-type epitaxial layer of the readout diode and the second sub-N-type epitaxial layer are fabricated simultaneously in the same process steps.

[0016] In some embodiments, the P-type epitaxial layer of the readout diode and the P-type epitaxial layer of the photodiode are fabricated simultaneously in the same process steps.

[0017] In some embodiments, the photodiode and the readout diode are fabricated prior to the embedded gate.

[0018] In some embodiments, an image sensor fabrication method is provided, comprising:

[0019] A P-type substrate is provided, the top surface of which includes a dummy gate, forming a protective layer covering the dummy gate and the top surface of the substrate;

[0020] After forming a first sub-N-type epitaxial layer in the substrate on one side of the dummy gate, the protective layer and substrate on both sides of the dummy gate are etched to form a first trench and a second trench penetrating the first sub-N-type epitaxial layer. The dummy gate is located between the first trench and the second trench.

[0021] During the process of forming the second sub-N-type epitaxial layer in the second trench, the N-type epitaxial layer of the readout diode is formed in the first trench; the first sub-N-type epitaxial layer and the second sub-N-type epitaxial layer are used to form the N-type epitaxial layer of the photodiode;

[0022] During the process of forming the P-type epitaxial layer of the photodiode covering the N-type epitaxial layer in the second trench, the P-type epitaxial layer of the readout diode covering the N-type epitaxial layer in the first trench is formed; the longitudinal section of the photodiode along the first direction parallel to the substrate is "T" shaped.

[0023] After depositing the passivation layer, the dummy gate and the substrate directly beneath it are etched away to form the gate trench;

[0024] After forming a gate dielectric layer that at least fills the gate trench in the gate trench, a gate conductive layer is formed that penetrates the gate dielectric layer and extends into the substrate in a second direction away from the substrate, wherein the top surface of the gate dielectric layer is not lower than the top surface of the substrate.

[0025] In some embodiments, a first sub-N-type epitaxial layer is formed in the substrate on one side of the dummy gate, including:

[0026] The protective layer and substrate on one side of the dummy gate are etched to obtain a groove;

[0027] A SiAs epitaxial layer is formed in the groove using a selective epitaxial growth process. The SiAs epitaxial layer is used to form the first sub-N-type epitaxial layer.

[0028] The image sensor and image sensor fabrication method in this disclosure have the following unexpected technical effects:

[0029] The photodiode has a T-shaped cross-section. The wide top of the T provides a larger light-receiving window, enabling the capture of more incident photons. This is particularly beneficial for small pixel sizes (e.g., <1.0 μm), effectively improving the fill factor and thus enhancing sensitivity. The narrower N-type region at the bottom creates a stronger electric field gradient, prompting photogenerated electrons to drift rapidly towards the buried gate, reducing electron residue and image hysteresis. The T-shaped profile also helps to bring the charge collection area closer to the buried gate entrance, improving charge transfer efficiency. The narrow bottom reduces the contact area between the photodiode and the high-defect-density silicon-isolation interface (e.g., trench sidewalls), thereby reducing dark current generation. The gate conductive layer extends vertically (in the second direction) through the gate dielectric layer and continues downward into the substrate, increasing the effective channel length and suppressing short-channel effects. The channel can be controlled from multiple directions (sidewalls, bottom), enhancing current switching capability and reducing subthreshold swing and off-state leakage current. The buried gate conductive layer is surrounded by the substrate (rather than across field oxygen), improving switching speed and reducing power consumption. The P-type epitaxial layers of photodiodes and readout diodes are fabricated simultaneously in the same process steps, which can reduce the complexity and cost of the fabrication process.

[0030] In addition, both the photodiode and the readout diode include N-type epitaxial layers and P-type epitaxial layers stacked sequentially along a second direction away from the substrate. Both are fabricated using epitaxial growth technology, which avoids the damage caused by the use of high-energy ion implantation processes in the front-end process and improves the performance and reliability of the fabricated CIS. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic flowchart of an image sensor fabrication method provided in one embodiment;

[0033] Figure 2 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a protective layer on the substrate in step S10 of the image sensor fabrication method provided in one embodiment.

[0034] Figure 3 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming a groove on the substrate in step S20 of the image sensor fabrication method provided in one embodiment;

[0035] Figure 4This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first sub-N-type epitaxial layer in a groove in step S20 of the image sensor fabrication method provided in one embodiment;

[0036] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first trench and the second trench in step S20 of the image sensor fabrication method provided in one embodiment.

[0037] Figure 6 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a photodiode and a readout diode on a substrate in steps S30 and S40 of the image sensor fabrication method provided in one embodiment.

[0038] Figure 7 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming a gate trench on a substrate in step S50 of the image sensor fabrication method provided in one embodiment.

[0039] Figure 8 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a buried gate on the substrate in step S60 of the image sensor fabrication method provided in one embodiment.

[0040] Explanation of reference numerals in the attached figures:

[0041] 10. Substrate; TX, Pseudo-gate; D1, Photodiode; D2, Readout Diode; 11. N-type epitaxial layer of readout diode; 12. P-type epitaxial layer of readout diode; 201. Trench; 21. First sub-N-type epitaxial layer; 22. Second sub-N-type epitaxial layer; 23. P-type epitaxial layer of photodiode; 301. Gate trench; 31. First gate oxide layer; 32. First conductive layer; 33. Protective layer; T1. First trench; T2. Second trench; 40. Passivation layer; 50. Buried gate; 51. First sub-gate dielectric layer; 52. Second sub-gate dielectric layer; 53. Gate conductive layer; 531. Vertical portion; 532. Horizontal portion. Detailed Implementation

[0042] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0048] In this embodiment of the disclosure, neglecting the flatness of the substrate surface, the first direction, such as the OX direction, is parallel to the top surface of the substrate. The second direction is perpendicular to the substrate (the thickness direction of the substrate), such as the OZ direction.

[0049] It should be noted that in the embodiments of this application, "coverage" means complete coverage. "Longitudinal section" refers to the section perpendicular to the top surface of the substrate.

[0050] Please refer to Figure 1 In some embodiments, an image sensor fabrication method is provided, comprising:

[0051] Step S10: Provide a P-type substrate, the top surface of which includes a dummy gate, and form a protective layer covering the dummy gate and the top surface of the substrate;

[0052] Step S20: After forming the first sub-N-type epitaxial layer in the substrate on one side of the dummy gate, the protective layer and substrate on both sides of the dummy gate are etched to form a first trench and a second trench penetrating the first sub-N-type epitaxial layer. The dummy gate is located between the first trench and the second trench.

[0053] Step S30: During the process of forming the second sub-N-type epitaxial layer in the second trench, an N-type epitaxial layer of the readout diode is formed in the first trench; the first sub-N-type epitaxial layer and the second sub-N-type epitaxial layer are used to constitute the N-type epitaxial layer of the photodiode;

[0054] Step S40: During the process of forming the P-type epitaxial layer of the photodiode covering the N-type epitaxial layer in the second trench, the P-type epitaxial layer of the readout diode covering the N-type epitaxial layer in the first trench is formed; the longitudinal section of the photodiode along the first direction is "T" shaped.

[0055] Step S50: After depositing the passivation layer, etch away the dummy gate and the substrate directly below it to form a gate trench;

[0056] Step S60: After forming a gate dielectric layer that at least fills the gate trench in the gate trench, a gate conductive layer is formed that penetrates the gate dielectric layer along the second direction and extends into the substrate, wherein the top surface of the gate dielectric layer is not lower than the top surface of the substrate.

[0057] As an example, please continue to refer to Figure 2 The substrate 10 may be, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, or a silicon carbide (SiC) substrate. Alternatively, for example, the substrate 10 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of protection of this disclosure.

[0058] For example, please refer to Figure 2 In semiconductor manufacturing, the processes for forming P-type substrates are mainly divided into two categories: 1. Global doping: During the wafer fabrication stage, boron (B) and other group III elements are doped into molten high-purity silicon using crystal growth processes such as Czochralski or zone melting, directly pulling out a uniformly doped P-type silicon ingot, which is then cut into wafers. 2. Regional / local doping: On an existing substrate, a P-type doped layer is formed in a specific region of the wafer using at least one of the following processes: epitaxial growth, in-situ doping, or thermal diffusion, to form a P-type substrate 10.

[0059] Please continue to refer to this. Figure 2 In some embodiments, a first gate oxide layer 31 can be formed on the top surface of the substrate 10 by a thermal oxidation process. The formation of the first gate oxide layer 31 by thermal oxidation of the substrate 10 can provide a lower interface trap density, which is key to ensuring the performance and reliability of metal-oxide-semiconductor field-effect transistors.

[0060] For example, to improve the quality and reliability of the first gate oxide layer 31, the surface of the substrate 10 must be thoroughly cleaned before growing the first gate oxide layer 31. A composite process combining dry oxygen-wet oxygen-dry oxygen can be used. For instance, during the growth stage of the first gate oxide layer 31, a high-quality thin oxide layer can first be generated by dry oxygen oxidation, then water vapor can be introduced to accelerate the growth rate, and finally dry oxygen can be used for densification. The material of the first gate oxide layer 31 may include silicon dioxide.

[0061] Please continue to refer to this. Figure 2 In some embodiments, after the formation of the first gate oxide layer 31, a doping gas (such as phosphine for N-type and borane for P-type) can be introduced simultaneously during the deposition process to directly form doped polycrystalline silicon. After doping, rapid thermal annealing (e.g., 950°C-1050°C, 10-30 seconds) is required to activate impurities and repair lattice damage, thereby reducing the resistance of the first conductive layer 32 formed on the top surface of the first gate oxide layer 31.

[0062] Please continue to refer to this. Figure 2 In some embodiments, a dry etching process can be used to remove the first gate oxide layer 31 and the first conductive layer 32 outside the buried gate region (not shown), and the first gate oxide layer 31 and the first conductive layer 32 retained in the buried gate region are used to form a dummy gate TX.

[0063] Please continue to refer to this. Figure 2 In some embodiments, after forming the dummy gate TX, a protective layer 33 covering the exposed surface of the substrate 10 can be formed using a deposition process. The material of the protective layer 33 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide nitride.

[0064] Please refer to Figures 3-4 In some embodiments, step S20, forming a first sub-N-type epitaxial layer 21 within the substrate 10 on the dummy gate TX side, includes:

[0065] Step S211: Etch the protective layer 33 and substrate 10 on the dummy gate TX side to obtain the groove 201;

[0066] Step S212: A SiAs epitaxial layer is formed in the groove 201 using a selective epitaxial growth process.

[0067] For example, please continue to refer to Figures 3-4 In step S211, photoresist is spin-coated and exposed and developed through a mask to open an etching window in the region on the dummy gate TX side. The protective layer 33 is dry-etched, stopping precisely on the top surface of the substrate 10 or shallowly etching the top surface of the substrate 10. The substrate 10 is dry-etched to the desired depth to obtain the groove 201. In step S212, a silicon source (such as dichlorosilane) and a dopant gas (such as arsine) can be used at a low temperature below 450 degrees Celsius to allow a high concentration of As atoms to accumulate on the silicon growth surface, acting as a surfactant to promote two-dimensional growth and form a SiAs epitaxial layer within the groove 201. The SiAs epitaxial layer is used to form the first sub-N-type epitaxial layer 21. The photoresist is then removed by oxygen plasma ashing. Residual polymers and particles are removed using SPM (H2SO4 / H2O) or SCl (NH4OH / H2O2 / H2O) solution. As has a lower diffusion coefficient in silicon than P, which allows for the formation of steeper doped interfaces and ultra-shallow junctions, helping to suppress short-channel effects. The thickness of the first sub-N-type epitaxial layer 21 is 20nm-30nm, such as 20nm, 22nm, 25nm, 27nm, 29nm, or 30nm.

[0068] Please refer to Figure 5In some embodiments, in step S20, after selectively epitaxially growing a first sub-N-type epitaxial layer 21 in the substrate 10 on one side of the dummy gate TX, the protective layers 33 and the substrate 10 on both sides of the dummy gate TX are etched, and a first trench T1 and a second trench T2 penetrating the first sub-N-type epitaxial layer 21 are formed simultaneously. The dummy gate TX is located between the first trench T1 and the second trench T2. The second trench T2 extends into the substrate 10 along the OZ direction. The remaining first sub-N-type epitaxial layer 21 can circumferentially surround the second trench T2.

[0069] Please refer to Figure 6 In some embodiments, the process parameters in step S30 may include: reaction gas (silane or dichlorosilane), doping gas (phosphine), temperature (600℃-800℃), and pressure (10 Torr-100 Torr). On the dielectric surface, the adsorbed silicon atoms have low mobility, and the oxidized surface inhibits nucleation; however, on a clean silicon surface, the epitaxial growth rate is high. Adding HCl gas can further suppress nucleation on the dielectric. SiP epitaxial layers are simultaneously grown on the bottom and sidewalls of the first trench T1 and the second trench T2. The doping concentration can be precisely controlled by adjusting the phosphine flow rate to ensure complete depletion and obtain high conversion gain. The SiP epitaxial layer in the second trench T2 is used to form the second sub-N-type epitaxial layer 22, and the SiP epitaxial layer in the first trench T1 is used to form the N-type epitaxial layer 11 of the readout diode. The first sub-N-type epitaxial layer 21 and the second sub-N-type epitaxial layer 22 are used to form the N-type epitaxial layer of the photodiode D1.

[0070] Please continue to refer to this. Figure 6In some embodiments, during step S40, during the formation of the P-type epitaxial layer 23 of the photodiode, a P-type epitaxial layer 12 of the readout diode is formed, covering the N-type epitaxial layer 11 of the readout diode within the first trench T1. The P-type epitaxial layer 23 of the photodiode covers the second sub-N-type epitaxial layer 22 within the second trench T2. The second sub-N-type epitaxial layer 22 within the second trench T2, together with the remaining first sub-N-type epitaxial layer 21 and the P-type epitaxial layer 23 of the photodiode directly above it, jointly constitutes the photodiode D1. The N-type epitaxial layer within the first trench T1 and the P-type epitaxial layer directly above it jointly constitute the readout diode D2. The first sub-N-type epitaxial layer 21 circumferentially surrounds the second sub-N-type epitaxial layer 22, and the first sub-N-type epitaxial layer 21 can serve as the main photogenerated charge collection region (depletion region). The second sub-N-type epitaxial layer 22 longitudinally penetrates the first sub-N-type epitaxial layer 21, forming a low-resistance channel through which photogenerated electrons can be quickly collected, reducing the transit time of charge carriers in the depletion region, thereby improving the device response speed, especially suitable for high-frequency or high-frame-rate imaging. The P-type epitaxial layer 23 of the photodiode forms pinning and isolation, effectively shielding the influence of silicon-dielectric interface defects (such as dangling bonds and metal contamination) on the photosensitive region, significantly reducing thermally excited dark current and white spot defects caused by interface states, and improving image noise. Since the P-type epitaxial layer 23 of the photodiode completely covers the N-type epitaxial layer of the photodiode D1, the longitudinal section of the photodiode D1 along the first direction is "T" shaped, which makes it easier for the entire N-type epitaxial layer to be completely depleted under low bias voltage. Photogenerated carriers are more easily swept into the collection region, reducing recombination loss and improving quantum efficiency, especially for long wavelengths (red light / near infrared).

[0071] Please refer to Figure 7 In some embodiments, in step S50, a passivation layer 40 is deposited, which covers the photodiode D1, the dummy gate TX, and the readout diode D2. The material of the passivation layer 40 may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. After the passivation layer 40 is formed, the dummy gate TX and the substrate 10 directly beneath it are etched away to form a gate trench 301 located between the photodiode D1 and the readout diode D2.

[0072] Please refer to Figure 8In some embodiments, in step S60, after forming a first sub-gate dielectric layer 51 on the inner surface of the gate trench 301, a second sub-gate dielectric layer 52 is formed on the surface of the first sub-gate dielectric layer 51. The first sub-gate dielectric layer 51 may include a TiN layer, and the second sub-gate dielectric layer 52 may include a TiAl layer. The first sub-gate dielectric layer 51 can serve as a barrier layer, a work function adjustment layer, and an anti-diffusion barrier; the second sub-gate dielectric layer 52 can reduce the overall gate resistance, adjust the effective work function, and improve the trench filling capability. The first sub-gate dielectric layer 51 and the second sub-gate dielectric layer 52 are used together to constitute the gate dielectric layer of the buried gate 50.

[0073] Please continue to refer to this. Figure 8 In some embodiments, in step S60, a chemical vapor deposition process can be used to form a gate conductive layer 53 that fills the remaining gate trench 301. The gate conductive layer 53 may include tungsten / cobalt to reduce gate resistance, reduce RC delay, and avoid filling voids. The longitudinal section of the gate conductive layer 53 is T-shaped. The widened top design increases the cross-sectional area of ​​the gate conductive layer 53, reduces the thin-film resistance of the gate, shortens the gate charge and discharge time (reduces RC delay), and improves the device switching frequency, making it particularly suitable for high-frequency power devices and RF circuits. The narrower bottom can significantly reduce Miller capacitance (Cgd), reduce switching losses, and improve efficiency. In addition, the T-shaped structure has a larger current carrying cross section and can disperse the current concentration effect, reducing the risk of electromigration failure of metal / polysilicon under high current or high temperature operating conditions and extending device life. The top surface of the gate dielectric layer embedded in the gate 50 is not lower than the top surface of the substrate 10. The top surface of the gate dielectric layer is flush with or slightly higher than the substrate 10, so that the gate electrode can control the channel from the sidewall and the top at the same time, thereby enhancing the gate control efficiency, reducing the off-state leakage current, and increasing the switching ratio.

[0074] Please continue to refer to this. Figure 8 In some embodiments, an image sensor is provided, including a P-type substrate 10, and a photodiode D1, a buried gate 50, and a readout diode D2 embedded in the substrate 10 and sequentially distributed along a first direction (e.g., the OX direction) parallel to the substrate 10; the longitudinal section of the photodiode D1 along the first direction is "T"-shaped; both the photodiode D1 and the readout diode D2 include an N-type epitaxial layer and a P-type epitaxial layer sequentially stacked along a second direction away from the substrate 10; the P-type epitaxial layers of the photodiode D1 and the readout diode D2 are fabricated simultaneously in the same process steps; the buried gate 50 includes a gate dielectric layer buried in the substrate 10, and a gate conductive layer 53 extending through the gate dielectric layer and into the substrate 10 along the second direction, the top surface of the gate dielectric layer being not lower than the top surface of the substrate 10.

[0075] For example, please continue to refer to Figure 8Photogenerated electrons are transferred to the readout diode D2, which serves as the storage node, via the buried gate 50. The readout diode D2 responds to the charge using its junction characteristics. The stored charge alters the electrical state of the readout diode D2 (such as the degree of forward bias), thus affecting the current flowing through it. The readout diode D2 can be configured in a circuit configuration (such as a source follower) to convert the current change back into a voltage signal output.

[0076] Please continue to refer to this. Figure 8 In some embodiments, the longitudinal section of the gate conductive layer 53 along the first direction is T-shaped. A thinner gate bottom reduces the capacitance between the gate and the channel, while a wider top ensures low resistance without significantly increasing the bottom capacitance. This helps reduce Miller capacitance, thereby reducing switching losses.

[0077] Please continue to refer to this. Figure 8 In some embodiments, the gate conductive layer 53 includes a horizontal portion 532 extending along a first direction and a vertical portion 531 extending along a second direction; wherein the horizontal portion 532 covers the top surface of the gate dielectric layer. A wider top can increase the cross-sectional area of ​​the gate conductive layer, thereby significantly reducing the sheet resistance of the gate. This is crucial for high-frequency switching applications, as it can shorten the gate charge / discharge time (reduce RC delay) and improve the device's operating frequency and switching speed.

[0078] Please continue to refer to this. Figure 8 In some embodiments, the N-type epitaxial layer of photodiode D1 includes a first sub-N-type epitaxial layer 21 and a second sub-N-type epitaxial layer 22. The first sub-N-type epitaxial layer 21 is embedded within the substrate 10, and its top surface is not higher than the top surface of the substrate 10. The second sub-N-type epitaxial layer 22 penetrates the first sub-N-type epitaxial layer 21 along a second direction and extends into the substrate 10. The P-type epitaxial layer 23 of the photodiode covers the top surfaces of both the first sub-N-type epitaxial layer 21 and the second sub-N-type epitaxial layer 22. The second sub-N-type epitaxial layer 22 can circumferentially surround the first sub-N-type epitaxial layer 21, facilitating the generation of a concentration gradient within the N-type epitaxial layer of photodiode D1. This difference optimizes the transport path of photogenerated carriers, reduces the recombination rate during diffusion, and improves quantum efficiency.

[0079] Please continue to refer to this. Figure 8 In some embodiments, the first sub-N-type epitaxial layer 21 is fabricated before the N-type epitaxial layer 11 of the readout diode. This facilitates the simultaneous fabrication of the remaining structure of the photodiode D1 and the readout diode D2 in the same process steps, reducing the complexity and cost of the fabrication process.

[0080] Please continue to refer to this. Figure 8 In some embodiments, the first sub-N-type epitaxial layer 21 includes a SiAs epitaxial layer.

[0081] Please continue to refer to this. Figure 8 In some embodiments, the second sub-N-type epitaxial layer 22 includes a SiP epitaxial layer.

[0082] Please continue to refer to this. Figure 8 In some embodiments, the P-type epitaxial layer of photodiode D1 includes a SiB epitaxial layer.

[0083] Please continue to refer to this. Figure 8 In some embodiments, the N-type epitaxial layer of the readout diode D2 includes a SiP epitaxial layer.

[0084] Please continue to refer to this. Figure 8 In some embodiments, the P-type epitaxial layer of the readout diode D2 includes a SiB epitaxial layer.

[0085] Please continue to refer to this. Figure 8 In some embodiments, the N-type epitaxial layer 11 of the readout diode and the second sub-N-type epitaxial layer 22 are fabricated simultaneously in the same process steps.

[0086] Please continue to refer to this. Figure 8 In some embodiments, the P-type epitaxial layer 12 of the readout diode and the P-type epitaxial layer 23 of the photodiode are fabricated simultaneously in the same process steps.

[0087] Please continue to refer to this. Figure 8 In some embodiments, photodiode D1 and readout diode D2 are fabricated before the buried gate 50.

[0088] Please continue to refer to this. Figures 1-8 The image sensor and image sensor fabrication method in this disclosure embodiment have the following unexpected technical effects:

[0089] The photodiode D1 has a T-shaped cross-section. The wide top of the T provides a larger light-receiving window, enabling it to capture more incident photons. This is particularly beneficial at small pixel sizes (e.g., <1.0 μm), effectively improving the fill factor and thus enhancing sensitivity. The narrower N-type region at the bottom creates a stronger electric field gradient, causing photogenerated electrons to drift rapidly towards the buried gate 50, reducing electron residue and image hysteresis. The T-shaped profile also helps to bring the charge collection area closer to the entrance of the buried gate 50, improving charge transfer efficiency. The narrow bottom reduces the contact area between the photodiode D1 and the high-defect-density silicon-isolation interface (such as trench sidewalls), thereby reducing dark current generation. The gate conductive layer 53 extends vertically (in the second direction) through the gate dielectric layer and continues downward into the substrate 10, which increases the effective channel length and suppresses the short-channel effect. It can control the channel from multiple directions (sidewalls, bottom), enhancing the ability to switch on and off current, and reducing subthreshold swing and off-state leakage current. The gate conductive layer buried in the gate is surrounded by the substrate 10 (rather than crossing the field oxide), which improves switching speed and reduces power consumption. The P-type epitaxial layers of photodiode D1 and readout diode D2 are fabricated simultaneously in the same process steps, reducing the complexity and cost of the fabrication process.

[0090] In addition, both photodiode D1 and readout diode D2 include N-type epitaxial layers and P-type epitaxial layers stacked sequentially along a second direction away from substrate 10. Both are fabricated using epitaxial growth technology, which avoids damage caused by high-energy ion implantation processes in the front-end process and improves the performance and reliability of the fabricated CIS.

[0091] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. An image sensor, characterized in that, It includes a P-type substrate, and a photodiode, a buried gate, and a readout diode embedded in the substrate and sequentially distributed along a first direction parallel to the substrate; The longitudinal section of the photodiode along the first direction is "T" shaped; Both the photodiode and the readout diode include an N-type epitaxial layer and a P-type epitaxial layer stacked sequentially along a second direction away from the substrate; the P-type epitaxial layers of the photodiode and the readout diode are fabricated simultaneously in the same process steps; The buried gate includes a gate dielectric layer buried in the substrate, and a gate conductive layer extending through the gate dielectric layer and into the substrate along the second direction, wherein the top surface of the gate dielectric layer is not lower than the top surface of the substrate.

2. The image sensor according to claim 1, characterized in that, The longitudinal section of the gate conductive layer along the first direction is "T" shaped.

3. The image sensor according to claim 1, characterized in that, The gate conductive layer includes a horizontal portion extending along the first direction and a vertical portion extending along the second direction; The horizontal portion covers the top surface of the gate dielectric layer.

4. The image sensor according to claim 1, characterized in that, The N-type epitaxial layer of the photodiode includes: The first sub-N-type epitaxial layer is embedded in the substrate, and its top surface is not higher than the top surface of the substrate; The second sub-N-type epitaxial layer penetrates the first sub-N-type epitaxial layer along the second direction and extends into the substrate; The P-type epitaxial layer of the photodiode covers the top surface of the first sub-N-type epitaxial layer and the top surface of the second sub-N-type epitaxial layer.

5. The image sensor according to claim 4, characterized in that, The first sub-N-type epitaxial layer is prepared before the N-type epitaxial layer of the readout diode.

6. The image sensor according to claim 4, characterized in that, Includes at least one of the following features: The first sub-N-type epitaxial layer includes a SiAs epitaxial layer; The second sub-N-type epitaxial layer includes a SiP epitaxial layer; The P-type epitaxial layer of the photodiode includes a SiB epitaxial layer; The N-type epitaxial layer of the readout diode includes a SiP epitaxial layer; The P-type epitaxial layer of the readout diode includes a SiB epitaxial layer.

7. The image sensor according to claim 5, characterized in that, The N-type epitaxial layer of the readout diode and the second sub-N-type epitaxial layer are fabricated simultaneously in the same process steps.

8. The image sensor according to any one of claims 1-7, characterized in that, The photodiode and the readout diode are fabricated prior to the embedded gate.

9. A method for fabricating an image sensor, characterized in that, include: A P-type substrate is provided, wherein the top surface of the substrate includes a dummy gate; A protective layer is formed covering the dummy gate and the top surface of the substrate; After forming a first sub-N-type epitaxial layer in the substrate on one side of the dummy gate, the protective layer and the substrate on both sides of the dummy gate are etched to form a first trench and a second trench penetrating the first sub-N-type epitaxial layer, and the dummy gate is located between the first trench and the second trench. During the process of forming the second sub-N-type epitaxial layer in the second trench, the N-type epitaxial layer of the readout diode is formed in the first trench; the first sub-N-type epitaxial layer and the second sub-N-type epitaxial layer are used to constitute the N-type epitaxial layer of the photodiode; During the process of forming the P-type epitaxial layer of the photodiode covering the N-type epitaxial layer in the second trench, the P-type epitaxial layer of the readout diode covering the N-type epitaxial layer in the first trench is formed; the longitudinal section of the photodiode along a first direction parallel to the substrate is "T" shaped. After depositing the passivation layer, the dummy gate and the substrate directly below it are etched away to form a gate trench; After forming a gate dielectric layer that at least fills the gate trench in the gate trench, a gate conductive layer is formed that penetrates the gate dielectric layer and extends into the substrate in a second direction away from the substrate, wherein the top surface of the gate dielectric layer is not lower than the top surface of the substrate.

10. The image sensor fabrication method according to claim 9, characterized in that, A first sub-N-type epitaxial layer is formed in the substrate on one side of the dummy gate, comprising: The protective layer and substrate on one side of the dummy gate are etched to obtain a groove; A SiAs epitaxial layer is formed in the groove using a selective epitaxial growth process, and the SiAs epitaxial layer is used to form the first sub-N-type epitaxial layer.

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