Image sensor and method of manufacturing an image sensor

Abstract

The present disclosure relates to an image sensor and a method for manufacturing the same, and belongs to the technical field of integrated circuits. The image sensor comprises a P-type substrate, an N-type floating diffusion region in the substrate, a transistor embedded in the P-type substrate, and a transfer gate. The transistor comprises a top N-type epitaxial layer, a P-type epitaxial layer, and a bottom N-type epitaxial layer stacked in sequence along a vertical direction of the substrate, and the P-type epitaxial layer is at least partially embedded in the substrate. The transfer gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region. The performance and reliability of the CIS can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an image sensor and a method for fabricating the image sensor. Background Technology

[0002] Complementary metal-oxide-semiconductor image sensors (CMOS Image Sensor, CIS) have advantages such as low cost, low power consumption and high integration, and have good application value in consumer electronics, automotive electronics, security monitoring and industrial and medical fields.

[0003] However, in traditional CIS manufacturing processes, the use of high-energy ion implantation in the front-end process to form photodiodes or other transistors can cause substrate damage and reduce the performance and reliability of other components on the substrate, thereby reducing the performance and reliability of the manufactured CIS. Summary of the Invention

[0004] Therefore, it is necessary to provide an image sensor and an image sensor fabrication method to address the technical problems of the need to improve the yield and performance of image sensors in the existing technology.

[0005] In a first aspect, this disclosure provides an image sensor, including a P-type substrate, an N-type floating diffusion region located within the substrate, a transistor embedded in the P-type substrate, and a transmission gate; the transistor includes a top N-type epitaxial layer, a P-type epitaxial layer, and a bottom N-type epitaxial layer stacked sequentially along a direction perpendicular to the substrate, wherein the P-type epitaxial layer is at least partially embedded within the substrate; wherein the transmission gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region, and the N-type epitaxial layer and the floating diffusion region are fabricated simultaneously in the same solid-state diffusion process.

[0006] In some embodiments, the bottom surface of the P-type epitaxial layer is lower than the top surface of the substrate, and the top surface of the P-type epitaxial layer is higher than the top surface of the substrate.

[0007] In some embodiments, the top N-type epitaxial layer is configured to be connected to the source power supply voltage.

[0008] In some embodiments, the thickness of the bottom N-type epitaxial layer is greater than that of the P-type epitaxial layer, which facilitates the generation of a concentration gradient within the bottom N-type epitaxial layer. This difference is used to optimize the transport path of photogenerated carriers, reduce the recombination rate during the diffusion process, and improve quantum efficiency.

[0009] In some embodiments, the bottom N-type epitaxial layer includes at least two stacked N-type photosensitive layers of different materials. The bottom N-type epitaxial layer may contain different Group 5 elements, and upon photoexcitation, a concentration gradient is generated within it. This difference optimizes the transport path of photogenerated carriers, reduces the recombination rate during diffusion, and improves quantum efficiency. Furthermore, since pentavalent elements have higher atomic masses than silicon and lower mobility during epitaxial growth, resulting in uneven doping concentrations in a single doped layer, growing different pentavalent elements in multiple stages can improve the uniformity of doping concentration in the pixel region.

[0010] In some embodiments, the transfer gate is fabricated before the transistor to avoid damaging the transistor during the fabrication of the transfer gate.

[0011] In some embodiments, the bottom N-type epitaxial layer includes a SiP epitaxial layer and a SiAs epitaxial layer, where SiP is used to characterize silicon materials containing P and SiAs is used to characterize silicon materials containing As.

[0012] In some embodiments, the P-type epitaxial layer includes a SiB epitaxial layer, where SiB is used to characterize silicon materials containing B.

[0013] In some embodiments, the top N-type epitaxial layer includes a SiP epitaxial layer.

[0014] In some embodiments, the floating diffusion region includes SiP, which is used to characterize silicon materials containing P.

[0015] In some embodiments, an image sensor fabrication method is provided, comprising:

[0016] A P-type substrate is provided, and after a transfer gate is formed on the substrate, a protective layer is formed covering the transfer gate and the substrate.

[0017] The protective layer and substrate on one side of the transmission gate are etched to form a trench;

[0018] A bottom N-type epitaxial layer, a P-type epitaxial layer, and a top N-type epitaxial layer are sequentially formed in the trench along the direction perpendicular to the substrate. The bottom surface of the P-type epitaxial layer is lower than the top surface of the substrate. During the formation of the top N-type epitaxial layer, an N-type floating diffusion region is simultaneously formed in the substrate. The transfer gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region.

[0019] In some embodiments, forming a bottom N-type epitaxial layer includes: forming a first sub-N-type photosensitive layer on the bottom surface and side surface of a trench using a selective epitaxial growth process; forming a second sub-N-type photosensitive layer on the first sub-N-type photosensitive layer using a selective epitaxial growth process, wherein the bottom surface of the second sub-N-type photosensitive layer is lower than the top surface of the substrate; and the first sub-N-type photosensitive layer and the second sub-N-type photosensitive layer are made of different materials.

[0020] In some embodiments, forming a top N-type epitaxial layer and an N-type floating diffusion region includes: after forming a P-type epitaxial layer, etching a protective layer away from the trench side of the transfer gate, forming an opening in the protective layer, the opening defining the floating diffusion region; the opening exposing a portion of the substrate; simultaneously forming an N-type semiconductor material layer on the top surface of the P-type epitaxial layer and on the top surface of the substrate within the opening; and simultaneously processing the semiconductor material layer using a solid-state diffusion process to form a top N-type epitaxial layer on the P-type epitaxial layer while forming the N-type floating diffusion region within the substrate.

[0021] The image sensor and image sensor fabrication method in this disclosure have the following unexpected technical effects:

[0022] In a vertical transistor, the top N-type epitaxial layer can be connected to the source power supply voltage (VSS), while the bottom N-type epitaxial layer can be connected to a fixed forward bias voltage (such as the drain power supply voltage VDD). The top N-type epitaxial layer can be used as a surface potential pinning layer to fix the surface potential and reduce surface recombination dark current. The P-type epitaxial layer can be used as a collection and storage region for photogenerated charges. The bottom N-type epitaxial layer can provide a drift electric field for photogenerated carriers. The transfer gate can control the transfer of charges stored in the transistor's base region (P-type epitaxial layer) to the floating diffusion region (FD). Incident light (entering from the back side) is mainly absorbed by the base region (P-type epitaxial layer) and the collector region (bottom N-type epitaxial layer), generating electron-hole pairs. The emitter (top N-type epitaxial layer) is connected to VSS, and the initial base potential is low (e.g., around 0V), so the emitter junction is zero-biased or slightly reverse-biased. After photogenerated holes enter the base region, they cannot cross the emitter junction (holes cannot enter the emitter), and thus accumulate in the base region. The accumulated hole concentration is proportional to the light intensity and integration time, achieving photoelectric integration. The accumulated holes in the base region are positively charged, causing the base region potential to gradually increase. The base region becomes a hole storage node. When the integration time ends, a high-level pulse is applied to the gate of the transfer gate (TX), opening the channel between the base region and the floating diffusion region. The change in the number of holes in the floating diffusion region causes a change in its potential, which can be amplified and output by a source follower (SF) to form a signal voltage proportional to the light intensity.

[0023] In addition, the top N-type epitaxial layer, P-type epitaxial layer and bottom N-type epitaxial layer are all prepared by epitaxial growth process, which avoids the damage caused by the use of high-energy ion implantation process in the front-end process and improves the performance and reliability of the fabricated CIS. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of an image sensor fabrication method provided in one embodiment;

[0026] Figure 2 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a protective layer on the substrate in step S10 of the image sensor fabrication method provided in one embodiment.

[0027] Figure 3 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming trenches on the substrate in step S20 of the image sensor fabrication method provided in one embodiment.

[0028] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a P-type epitaxial layer in the trench in step S30 of the image sensor fabrication method provided in one embodiment;

[0029] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming an N-type semiconductor material layer in the trench in step S30 of the image sensor fabrication method provided in one embodiment.

[0030] Figure 6 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after step S30 in the image sensor fabrication method provided in one embodiment, after forming a first plug, a second plug, and a third plug on a substrate.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10. Substrate; FD. Floating diffusion region; TX. Transfer gate; 20. Transistor; 201. Trench; 21. Bottom N-type epitaxial layer; 211. First sub-N-type photosensitive layer; 212. Second sub-N-type photosensitive layer; 22. P-type epitaxial layer; 23. Top N-type epitaxial layer; 231. N-type semiconductor material layer; 31. Gate oxide layer; 32. Gate conductive layer; 33. Protective layer; CT1. First plug; CT2. Second plug; CT3. Third plug; OX. Oxide layer. Detailed Implementation

[0033] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0039] In this embodiment of the disclosure, neglecting the flatness of the substrate surface, the direction perpendicular to the substrate (the thickness direction of the substrate) is, for example, the OZ direction. In this embodiment of the disclosure, the OX direction is parallel to the top surface of the substrate.

[0040] Please refer to Figure 1 In some embodiments, an image sensor fabrication method is provided, comprising:

[0041] Step S10: Provide a P-type substrate, form a transfer gate on the substrate, and then form a protective layer covering the transfer gate and the substrate;

[0042] Step S20: Etch the protective layer and substrate on one side of the transport gate to form a trench;

[0043] Step S30: A bottom N-type epitaxial layer, a P-type epitaxial layer, and a top N-type epitaxial layer are sequentially formed in the trench along the direction perpendicular to the substrate. The bottom surface of the P-type epitaxial layer is lower than the top surface of the substrate. During the formation of the top N-type epitaxial layer, an N-type floating diffusion region is simultaneously formed in the substrate. The transfer gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region.

[0044] As an example, please continue to refer to Figure 2The substrate 10 may be, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, or a silicon carbide (SiC) substrate. Alternatively, for example, the substrate 10 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of protection of this disclosure.

[0045] As an example, please continue to refer to Figure 2 In semiconductor manufacturing, the processes for forming P-type substrates are mainly divided into two categories: 1. Global doping: During the wafer fabrication stage, boron (B) and other group III elements are doped into molten high-purity silicon using crystal growth processes such as Czochralski or zone melting, directly pulling out a uniformly doped P-type silicon ingot, which is then cut into wafers. 2. Regional / local doping: On an existing substrate, a P-type doped layer is formed in a specific region of the wafer using at least one of the following processes: epitaxial growth, in-situ doping, or thermal diffusion, to form a P-type substrate 10.

[0046] Please continue to refer to this. Figure 2 In some embodiments, the gate oxide layer 31 can be formed on the top surface of the substrate 10 by a thermal oxidation process. The formation of the gate oxide layer 31 by thermal oxidation of the substrate 10 can provide a lower interface trap density, which is key to ensuring the performance and reliability of metal-oxide-semiconductor field-effect transistors.

[0047] For example, to improve the quality and reliability of the gate oxide layer 31, the substrate surface must be thoroughly cleaned before growing the gate oxide layer 31. A composite process combining dry oxygen-wet oxygen-dry oxygen can be used. For instance, during the growth stage of the gate oxide layer 31, a high-quality thin oxide layer can first be generated using dry oxygen oxidation, then water vapor can be introduced to accelerate the growth rate, and finally dry oxygen can be used for densification. The material of the gate oxide layer 31 may include silicon dioxide.

[0048] Please continue to refer to this. Figure 2 In some embodiments, after the gate oxide layer 31 is formed, a doping gas (such as phosphine for N-type and borane for P-type) can be introduced simultaneously during the deposition process to directly form doped polycrystalline silicon. After doping, rapid thermal annealing (e.g., 950°C-1050°C, 10-30 seconds) is required to activate impurities and repair lattice damage, thereby reducing the resistance of the gate conductive layer 32 formed on the top surface of the gate oxide layer 31.

[0049] Please continue to refer to this. Figure 2 In some embodiments, a dry etching process can be used to remove the gate oxide layer 31 and the gate conductive layer 32 outside the transmission gate region (not shown), and the gate oxide layer 31 and the gate conductive layer 32 remaining in the transmission gate region are used to form the transmission gate TX.

[0050] Please continue to refer to this. Figure 2 In some embodiments, after forming the transport gate TX, a protective layer 33 may be formed using a deposition process to cover the transport gate TX and the exposed surface of the substrate 10. The material of the protective layer 33 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide nitride.

[0051] Please refer to Figure 3 In some embodiments, in step S20, photoresist can be coated on the top surface of the protective layer 33, and exposed and developed using a mask to open an etching window on the TX side (e.g., the area between adjacent pixels) to expose the surface of the substrate 10. A high aspect ratio silicon etching process can be used to etch the protective layer 33 and the substrate 10 on the TX side of the transport gate to form the trench 201. The photoresist is then removed using oxygen plasma ashing. Residual polymers and particles are removed using SPM (H2SO4 / H2O) or SCI (NH4OH / H2O2 / H2O).

[0052] Please refer to Figure 4 In some embodiments, step S30, forming the bottom N-type epitaxial layer 21 includes:

[0053] Step S311: A first sub-N-type photosensitive layer 211 is formed on the bottom and side surfaces of the trench 201 using a selective epitaxial growth process.

[0054] For example, the first sub-N-type photosensitive layer 211 may include a SiP epitaxial layer. The process parameters in step S311 may include: a reaction gas (silane or dichlorosilane), a doping gas (phosphine), a temperature (600℃-800℃), and a pressure (10 Torr-100 Torr). On a dielectric surface, the adsorbed silicon atoms have low mobility, and the oxide surface inhibits nucleation; while on a clean silicon surface, the epitaxial growth rate is high. Adding HCl gas can further suppress nucleation on the dielectric. Growth occurs simultaneously on the bottom and sidewalls of trench 201. The growth rate on the sidewalls of trench 201 is typically slightly lower than that on the bottom; by optimizing the temperature and pressure, bottom-preferred growth can be achieved. The doping concentration of the first sub-N-type photosensitive layer 211 is typically low (e.g., 1×10⁻⁶). 16 cm -3 -1×10 17 cm -3 By adjusting the phosphine flow rate, the doping concentration can be precisely controlled to ensure complete depletion and achieve high conversion gain. The material of the first sub-N-type photosensitive layer 211 includes a SiP epitaxial layer. The thickness of the SiP epitaxial layer is 100nm-150nm, such as 100nm, 110nm, 120nm, 130nm, 140nm, or 150nm, to form a SiP epitaxial layer of suitable thickness, ensuring photoelectric conversion efficiency while avoiding excessive volume.

[0055] Step S312: A second sub-N-type photosensitive layer 212 is formed on the first sub-N-type photosensitive layer 211 using a selective epitaxial growth process. The bottom surface of the second sub-N-type photosensitive layer 212 is lower than the top surface of the substrate 10. The first sub-N-type photosensitive layer 211 and the second sub-N-type photosensitive layer 212 are made of different materials.

[0056] For example, the second sub-N-type photosensitive layer 212 may include a SiAs epitaxial layer. The thickness of the SiAs epitaxial layer is 95nm-105nm, such as 95nm, 100nm, or 105nm. The bottom N-type epitaxial layer 21 includes stacked N-type photosensitive layers of at least two different materials, achieving a longitudinal gradient distribution of N-type doping within the trench 201. This dual-layer stacked structure can optimize the collection and transfer of photogenerated electrons, suppress dark current, and improve the dynamic range and signal-to-noise ratio of small-size CMOS image sensors.

[0057] Please continue to refer to this. Figure 4 In some embodiments, in step S30, after forming the bottom N-type epitaxial layer 21, a P-type epitaxial layer 22 is grown on the surface of the bottom N-type epitaxial layer 21 using a selective epitaxial growth process. For example, a silicon source (such as dichlorosilane), a P-type dopant gas (such as borane), and hydrogen chloride (HCl) are introduced into the reaction chamber to control selectivity. The material of the P-type epitaxial layer 22 includes a SiB epitaxial layer. The thickness of the SiB epitaxial layer can be 9.5 nm to 10.5 nm, for example, 9.5 nm, 10 nm, or 10.5 nm.

[0058] Please continue to refer to this. Figure 4 In some embodiments, the bottom surface of the P-type epitaxial layer 22 is lower than the top surface of the substrate 10, and the top surface of the P-type epitaxial layer 22 is not lower than the top surface of the substrate 10. The thickness of the bottom N-type epitaxial layer 21 is greater than the thickness of the P-type epitaxial layer 22, which facilitates the generation of a concentration gradient inside the bottom N-type epitaxial layer 21. This difference is used to optimize the transport path of photogenerated carriers, reduce the recombination rate during the diffusion process, and improve quantum efficiency.

[0059] Please refer to Figure 5 In some embodiments, step S30, forming the top N-type epitaxial layer 23 and the N-type floating diffusion region FD, includes:

[0060] Step S321: After forming the P-type epitaxial layer 22, the protective layer 33 on the side of the transfer gate TX away from the trench 201 is etched, and an opening is formed in the protective layer 33. The opening is used to define the floating diffusion region FD; the opening exposes part of the substrate 10.

[0061] Step S322: Simultaneously form an N-type semiconductor material layer 231 on the top surface of the P-type epitaxial layer 22 and the top surface of the inner substrate 10;

[0062] Step S323: Simultaneously process the N-type semiconductor material layer 231 using solid-state diffusion process, so as to form an N-type floating diffusion region FD in the substrate 10 and a top N-type epitaxial layer 23 on the P-type epitaxial layer 22.

[0063] For example, please continue to refer to Figure 5 In step S321, photoresist can be spin-coated, exposed and developed using a mask, and an etching window can be opened above the protective layer 33 on the side of the transfer gate TX away from the trench 201. Anisotropic dry etching is used to etch the protective layer 33, with the endpoint exactly on the top surface of the substrate 10, forming an opening (not shown) within the protective layer 33. This opening defines the floating diffusion region FD; the opening exposes a portion of the substrate 10. After removing the photoresist using oxygen plasma ashing, residual polymer and native oxide layers are cleaned using SPM (H2SO4 / H2O) or dilute hydrofluoric acid (DHF).

[0064] For example, please continue to refer to Figure 5 In step S322, selective epitaxial growth and in-situ doping processes can be used to simultaneously form an N-type semiconductor material layer 231 on the top surface of the P-type epitaxial layer 22 and the top surface of the substrate 10 within the opening of the protective layer 33. For example, during the growth of the semiconductor material layer 231, a reactive gas (silane or dichlorosilane), a doping gas (phosphine), and a temperature of 600℃-800℃ can be introduced. This avoids damage caused by high-energy ion implantation processes, improving the performance and reliability of the fabricated CIS.

[0065] For example, please continue to refer to Figure 5 In step S323, phosphorus atoms are released from the N-type doped semiconductor material layer 231 at high temperature in a high-temperature furnace tube and diffuse toward the substrate 10. After a certain time, while a top N-type epitaxial layer 23 is formed on the top surface of the P-type epitaxial layer 22, an N-type floating diffusion region FD is formed in the substrate 10 below the opening of the protective layer 33. An oxide layer OX is retained in the opening of the protective layer 33, and an oxide layer OX is retained on the top surface of the top N-type epitaxial layer 23. Compared with ion implantation, solid-state diffusion is a non-plasma, low-temperature, low-damage process.

[0066] For example, please continue to refer to Figure 5 Following solid-state diffusion, laser annealing (LSA) is a highly effective process choice to activate doped impurities, repair lattice damage, and avoid unnecessary impurity diffusion or thermal budget overruns caused by prolonged high-temperature annealing. The energy density of LSA is 20 mJ / cm². 2 -30mJ / cm 2 For example, 20mJ / cm 2 25mJ / cm 2or 30mJ / cm 2 This process allows some interstitial impurity atoms to enter substitution sites, eliminating some point defects (such as vacancies and self-interstitial atoms). The heating depth is extremely shallow (approximately 20nm-50nm) and the duration is short (nanoseconds), maintaining the steep distribution at the time of implantation. It does not cause surface melting, therefore the surface roughness remains almost unchanged, and it does not generate defects that might result from melt recrystallization regions.

[0067] Please refer to Figure 6 In some embodiments, after forming the oxide layer OX, photoresist can be spin-coated and exposed and developed through a mask to form a first hole (not shown), a second hole (not shown), and a third hole (not shown) distributed along the OX direction. The first hole (not shown) penetrates the oxide layer OX on the top N-type epitaxial layer 23 and extends into the top N-type epitaxial layer 23. The second hole penetrates the protective layer 33 and exposes part of the gate conductive layer 32. The third hole penetrates the oxide layer OX on the floating diffusion region FD and exposes part of the floating diffusion region FD.

[0068] Please continue to refer to this. Figure 6 In some embodiments, after forming the first, second, and third holes, a first plug CT1 is formed in the first hole, a second plug CT2 is formed in the second hole, and a third plug CT3 is formed in the third hole. The first plug CT1 contacts the top N-type epitaxial layer 23 and can be connected to the source power supply voltage. The second plug CT2 contacts the gate conductive layer 32 and can be connected to the gate control voltage. The third plug CT3 contacts the floating diffusion region FD.

[0069] Please continue to refer to this. Figure 6 In some embodiments, an image sensor is provided, including a P-type substrate 10, an N-type floating diffusion region FD located within the substrate 10, a transistor 20 embedded in the P-type substrate 10, and a transmission gate TX; the transistor 20 includes a top N-type epitaxial layer 23, a P-type epitaxial layer 22, and a bottom N-type epitaxial layer 21 stacked sequentially along the direction perpendicular to the substrate 10, wherein the P-type epitaxial layer 22 is at least partially embedded within the substrate 10; wherein the transmission gate TX is located on the substrate 10 between the P-type epitaxial layer 22 and the floating diffusion region FD.

[0070] In some embodiments, the N-type epitaxial layer and the floating diffusion region (FD) are prepared simultaneously in the same solid-state diffusion process, which avoids damage caused by high-energy ion implantation processes and reduces the complexity and cost of the preparation process.

[0071] In some embodiments, the top N-type epitaxial layer 23 is configured to be connected to the source power supply voltage.

[0072] In some embodiments, the thickness of the bottom N-type epitaxial layer 21 is greater than the thickness of the P-type epitaxial layer 22, which facilitates the generation of a concentration gradient inside the bottom N-type epitaxial layer 21. This difference is used to optimize the transport path of photogenerated carriers, reduce the recombination rate during the diffusion process, and improve quantum efficiency.

[0073] In some embodiments, the transmission gate TX is fabricated before the transistor 20 to avoid damaging the transistor 20 during the fabrication of the transmission gate TX.

[0074] In some embodiments, the bottom N-type epitaxial layer 21 includes a SiP epitaxial layer and a SiAs epitaxial layer.

[0075] In some embodiments, the P-type epitaxial layer 22 includes a SiB epitaxial layer.

[0076] In some embodiments, the top N-type epitaxial layer 23 includes a SiP epitaxial layer.

[0077] In some embodiments, the floating diffusion region FD includes SiP.

[0078] For example, SiP is used to characterize silicon materials containing P.

[0079] For example, SiAs is used to characterize silicon materials containing As.

[0080] For example, SiB is used to characterize silicon materials containing B.

[0081] Please continue to refer to this. Figures 1-6 The image sensor and image sensor fabrication method in this disclosure embodiment have the following unexpected technical effects:

[0082] The top N-type epitaxial layer 23 of the vertically structured transistor 20 can be connected to the source power supply voltage (VSS), and the bottom N-type epitaxial layer 21 can be connected to a fixed positive bias voltage (such as the drain power supply voltage VDD). The top N-type epitaxial layer 23 can be used as a surface potential pinning layer to fix the surface potential and reduce surface recombination dark current. The P-type epitaxial layer 22 can be used as a collection and storage region for photogenerated charges. The bottom N-type epitaxial layer 21 can provide a drift electric field for photogenerated carriers. The transmission gate TX can control the transfer of charges stored in the base region (P-type epitaxial layer 22) of the transistor 20 to the floating diffusion region FD. Incident light (entering from the back side) is mainly absorbed by the base region (P-type epitaxial layer 22) and the collector region (bottom N-type epitaxial layer 21), generating electron-hole pairs. The emitter (top N-type epitaxial layer 23) is connected to VSS, and the initial potential of the base region is low (e.g., around 0V), so the emitter junction is zero-biased or slightly reverse-biased. After photogenerated holes enter the base region, they cannot cross the emitter junction (holes cannot enter the emitter), and thus accumulate in the base region. The accumulated hole concentration is proportional to the light intensity and integration time, achieving photoelectric integration. The accumulated holes in the base region are positively charged, causing the base region potential to gradually increase. The base region becomes a hole storage node. When the integration time ends, a high-level pulse is applied to the gate of the transmission gate TX, turning on the channel between the base region and the floating diffuser region FD. The change in the number of holes in the floating diffuser region FD causes a change in its potential, which can be amplified and output by a source follower (SF) to form a signal voltage proportional to the light intensity.

[0083] In addition, the top N-type epitaxial layer 23, the P-type epitaxial layer 22 and the bottom N-type epitaxial layer 21 are all prepared by epitaxial growth process, which avoids the damage caused by the use of high-energy ion implantation process in the front-end process and improves the performance and reliability of the prepared CIS.

[0084] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. An image sensor, characterized in that, It includes a P-type substrate, an N-type floating diffusion region located within the substrate, a transistor embedded in the P-type substrate, and a transmission gate; The transistor includes a top N-type epitaxial layer, a P-type epitaxial layer and a bottom N-type epitaxial layer stacked sequentially along the direction perpendicular to the substrate, wherein the P-type epitaxial layer is at least partially embedded in the substrate; The transmission gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region; the N-type epitaxial layer and the floating diffusion region are prepared simultaneously in the same solid-state diffusion process.

2. The image sensor according to claim 1, characterized in that, The bottom surface of the P-type epitaxial layer is lower than the top surface of the substrate, and the top surface of the P-type epitaxial layer is higher than the top surface of the substrate.

3. The image sensor according to claim 1, characterized in that, The top N-type epitaxial layer is configured to be connected to the source power supply voltage.

4. The image sensor according to claim 1, characterized in that, The thickness of the bottom N-type epitaxial layer is greater than the thickness of the P-type epitaxial layer.

5. The image sensor according to claim 1, characterized in that, The bottom N-type epitaxial layer includes at least two N-type photosensitive layers made of stacked materials.

6. The image sensor according to claim 1, characterized in that, The transmission gate is fabricated prior to the transistor.

7. The image sensor according to any one of claims 1-6, characterized in that, Includes at least one of the following features: The bottom N-type epitaxial layer includes a SiP epitaxial layer and a SiAs epitaxial layer; The P-type epitaxial layer includes a SiB epitaxial layer; The top N-type epitaxial layer includes a SiP epitaxial layer; The floating diffusion region includes SiP, which is used to characterize silicon materials containing P. SiAs is used to characterize silicon materials containing As; SiB is used to characterize silicon materials containing boron.

8. A method for fabricating an image sensor, characterized in that, include: Provides P-type substrates; After forming a transport gate on the substrate, a protective layer is formed covering the transport gate and the substrate; The protective layer and substrate on one side of the transmission gate are etched to form a trench; A bottom N-type epitaxial layer, a P-type epitaxial layer, and a top N-type epitaxial layer are sequentially formed in the trench along the direction perpendicular to the substrate, wherein the bottom surface of the P-type epitaxial layer is lower than the top surface of the substrate; wherein, during the formation of the top N-type epitaxial layer, an N-type floating diffusion region is simultaneously formed in the substrate, and the transmission gate is located on the substrate between the P-type epitaxial layer and the floating diffusion region.

9. The image sensor fabrication method according to claim 8, characterized in that, The formation of the bottom N-type epitaxial layer includes: A first sub-N-type photosensitive layer is formed on the bottom and side surfaces of the trench using a selective epitaxial growth process; A second sub-N-type photosensitive layer is formed on the first sub-N-type photosensitive layer using a selective epitaxial growth process. The bottom surface of the second sub-N-type photosensitive layer is lower than the top surface of the substrate. The first sub-N-type photosensitive layer and the second sub-N-type photosensitive layer are made of different materials.

10. The image sensor fabrication method according to claim 8 or 9, characterized in that, The formation of the top N-type epitaxial layer and the N-type floating diffusion region includes: After forming the P-type epitaxial layer, the protective layer opposite to the trench of the transmission gate is etched to form an opening in the protective layer, the opening being used to define the floating diffusion region; the opening exposes a portion of the substrate; An N-type semiconductor material layer is formed simultaneously on the top surface of the P-type epitaxial layer and the top surface of the inner substrate of the opening; The semiconductor material layer is processed simultaneously using a solid-state diffusion process to form the N-type floating diffusion region in the substrate, while simultaneously forming the top N-type epitaxial layer on the P-type epitaxial layer.

Images