A method for passivation recovery after wet cleaning of an HBC battery silicon wafer

Abstract

The application discloses a kind of HBC battery silicon wafer wet cleaning after passivation recovery method, belong to photovoltaic cell manufacturing technical field, comprising the following steps: S1, pretreatment step: after the ITO layer procedure etching cleaning with FeCl3 solution and / or alkali cleaning amorphous silicon layer procedure HBC battery silicon wafer, deionized water is successively used to wash, nitrogen is blown dry, remove the cleaning liquid, reaction by-product and impurity particles remaining on the surface of silicon wafer;S2, piece and gas establishment step: after the pretreatment HBC battery silicon wafer is loaded into muffle furnace chamber.The application is by annealing temperature strictly controlled at 300 DEG C~500 DEG C, annealing time is controlled at 10 seconds~30 seconds, with nitrogen or argon protective atmosphere and specific heating / cooling rate control, realizes the protection of HBC battery sensitive film layer and the efficient recovery of passivation effect, fills the technical blank of prior art in the field of HBC battery special low-temperature rapid annealing passivation recovery.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic cell manufacturing technology, and in particular relates to a method for passivation recovery after wet cleaning of HBC cell silicon wafers. Background Technology

[0002] As the photovoltaic industry continues to demand higher cell conversion efficiency, HBC cells, a novel high-efficiency cell integrating HJT heterojunction passivation technology and BC back contact structure, have attracted widespread attention in the industry. HBC cells use an N-type monocrystalline silicon wafer as a substrate. A passivation layer and an anti-reflection film are sequentially grown on the front side of the wafer, while an intrinsic amorphous silicon layer (i-layer) and a finger-shaped, cross-distributed N-type amorphous silicon layer (N-type...) are sequentially grown on the back side. + P-type amorphous silicon layer (P-type layer) and P-type amorphous silicon layer (P-type layer) + (Layer), and deposit an ITO transparent conductive layer.

[0003] In the actual mass production process of HBC cells, wet cleaning is an essential step. It is mainly used to selectively pattern the ITO layer, clean and remove the a-Si layer, and remove impurities from the silicon wafer surface. HBC cells contain an amorphous silicon passivation layer that is extremely sensitive to the process. After the silicon wafer has undergone multiple wet cleaning processes, the following problems are very likely to occur: (1) The a-Si passivation film is corroded by the cleaning solution, resulting in thinning or even local loss of the film layer; (2) The c-Si / a-Si interface is oxidized to form an oxide layer, which destroys the passivation effect of the interface; (3) Metal ion contamination in the residual cleaning solution on the silicon wafer surface; (4) Mechanical and chemical damage to the semiconductor surface caused by the wet process leads to an increase in dangling bonds.

[0004] The aforementioned problems lead to a significant increase in the interface defect density Dit, which ultimately manifests as a severe decrease in passivation effect, a reduction in minority carrier lifetime, and a deterioration in open-circuit voltage Voc and fill factor FF, ultimately affecting the cell's conversion efficiency.

[0005] In the existing technology, the main solutions for silicon wafer passivation recovery are as follows: (1) High temperature annealing (>600℃): Although high temperature annealing in conventional semiconductor processes can repair lattice damage and eliminate dangling bonds, HBC batteries contain temperature-sensitive ITO and amorphous silicon layers. High temperature annealing will destroy the crystal structure of ITO, reduce its conductivity, and cause the amorphous silicon layer to crystallize, affecting battery performance; (2) Hydrogen atmosphere annealing: dangling bonds are passivated by hydrogen at high temperature, but hydrogen is flammable and explosive, posing a safety hazard, and also faces temperature limitation issues; (3) Plasma treatment: Surface treatment is performed using hydrogen plasma or nitrogen plasma, but plasma treatment is a non-uniform treatment, making it difficult to achieve large-area uniform passivation, and may cause plasma damage to the a-Si layer; (4) Chemical passivation: Surface passivation is performed using hydrofluoric acid or other chemical reagents, but the chemical substances introduced by chemical passivation may react with other film layers of HBC batteries, and the passivation effect is not durable. Summary of the Invention

[0006] The purpose of this invention is to provide a passivation recovery method for HBC battery silicon wafers after wet cleaning. This method achieves rapid and effective recovery of the passivation effect of HBC batteries after multiple wet cleaning processes, while ensuring that the structure and performance of the ITO transparent conductive layer and the amorphous silicon layer are not affected, thereby solving the above-mentioned technical problems.

[0007] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A method for passivation recovery after wet cleaning of HBC battery silicon wafers, the method comprising the following steps: S1. Pretreatment steps: After the ITO layer is etched and cleaned with FeCl3 solution and / or the amorphous silicon layer is cleaned with alkaline solution, the HBC battery silicon wafer is rinsed with deionized water and dried with nitrogen to remove residual cleaning solution, reaction by-products and impurity particles on the silicon wafer surface. S2. Wafer loading and atmosphere setup steps: Load the pretreated HBC cell silicon wafers into the muffle furnace chamber, seal the furnace door and introduce nitrogen or argon protective atmosphere, control the gas flow rate to 5L / min~20L / min, purge the air in the chamber and maintain a positive pressure environment. S3. Low-temperature rapid annealing step: Start the muffle furnace heating and control the heating rate to 50℃ / s~100℃ / s to rapidly raise the chamber temperature to the annealing temperature of 300℃~500℃, and maintain the annealing time at this temperature for 10 seconds~30 seconds to repair the a-Si passivation film damage caused by wet cleaning, eliminate dangling bonds and interface defects at the c-Si / a-Si interface, reduce the interface state density Dit and improve the minority carrier lifetime of the silicon wafer. S4. Cooling Step: After the annealing process is completed, heating is stopped and the protective atmosphere is maintained for purging. The cooling rate is controlled at 20℃ / s to 50℃ / s to cool the silicon wafer to room temperature. This completes the passivation recovery process after wet cleaning of the HBC battery silicon wafer. The annealing process does not significantly affect the structure, conductivity, and optical properties of the ITO transparent conductive layer.

[0008] Preferably, in step S3, the annealing temperature is within the optimized temperature range of 380℃ to 420℃, and the annealing time is within the optimized time range of 15 seconds to 20 seconds; more preferably, the annealing temperature is 400℃, and the annealing time is 15 seconds, so as to achieve the best balance between passivation recovery effect and ITO layer performance protection, so that the PL brightness of the mask protection area is restored to more than 130% of the level before cleaning and the sheet resistance change rate of the ITO layer is less than 5%.

[0009] Preferably, in step S3, the muffle furnace uses infrared radiation heating or multi-segment resistance wire heating, and the heating element is a graphite heating element or a molybdenum alloy heating element; the chamber uses a quartz tube or ceramic lining structure to ensure the uniformity of the temperature field, and the temperature uniformity within the chamber is controlled within ±5℃; the rated operating temperature of the muffle furnace is above 800℃, and a single batch can simultaneously process 25 to 100 HBC battery silicon wafers of 166mm×166mm, 182mm×182mm, or 210mm×210mm specifications, with the processing cycle matching the production line to meet the needs of large-scale mass production.

[0010] Preferably, the purity of the protective atmosphere in step S2 is ≥99.999%, the oxygen content is ≤5ppm, and the water content is ≤3ppm; preferably, the nitrogen or argon gas is further deoxygenated and dehydrated by a gas purifier before being introduced into the chamber; during the annealing process, the chamber pressure is maintained at a slightly positive pressure of 0.05MPa to 0.15MPa to prevent external air from seeping in and causing secondary oxidation on the silicon wafer surface.

[0011] Preferably, before step S2, a passivation effect detection and evaluation step S1.5 for the wet cleaning process is included: using a photoluminescence (PL) tester or a microwave photoconductivity attenuation (μ-PCD) tester to detect the passivation effect of the HBC cell silicon wafer after wet cleaning, and measuring the PL brightness value or minority carrier lifetime value; when the PL brightness value is lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is lower than 70% of the baseline value before cleaning, it is determined that the annealing process needs to be performed; when the PL brightness value is not lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is not lower than 70% of the baseline value before cleaning, the annealing process is skipped and the process proceeds directly to the next step; the preset threshold is set based on the HBC cell mass production yield and efficiency requirements.

[0012] Preferably, after step S4, a passivation recovery effect verification step S5 is included: using a photoluminescence (PL) tester to test the PL brightness of the annealed HBC battery silicon wafer, comparing the PL brightness value after annealing with the PL brightness benchmark value before wet cleaning, and calculating the passivation recovery rate η = (PL after annealing - PL after alkaline cleaning) / (PL before cleaning - PL after alkaline cleaning) × 100%; when η ≥ 100%, the passivation recovery is deemed qualified and proceeds to the next process; when η < 100%, the passivation recovery is deemed unqualified and returns to the rework process; furthermore, step S5 also includes testing the sheet resistance of the ITO transparent conductive layer, using a four-probe sheet resistance tester to measure the change rate of the ITO layer sheet resistance before and after annealing, requiring the change rate to be less than 5% to ensure the stability of the ITO layer conductivity.

[0013] Preferably, the wet cleaning process includes at least one of a FeCl3 solution etching and cleaning process for the ITO layer and an alkaline cleaning process for the amorphous silicon layer; the concentration of the FeCl3 solution is 5wt% to 15wt%, the cleaning temperature is 20℃ to 40℃, and the cleaning time is 30 seconds to 120 seconds; the alkaline solution used in the alkaline cleaning process is one of NaOH solution, KOH solution, or TMAH tetramethylammonium hydroxide solution, the concentration of the alkaline solution is 1wt% to 10wt%, the cleaning temperature is 40℃ to 80℃, and the cleaning time is 30 seconds to 180 seconds; the passivation recovery method is applicable to silicon wafers after the FeCl3 solution etching and cleaning process, silicon wafers after the alkaline cleaning process, and silicon wafers that have undergone FeCl3 solution etching and cleaning and alkaline cleaning processes in sequence, and can effectively restore the passivation effect lost after each process.

[0014] Preferably, the method is implemented in the online production process of HBC battery manufacturing. After annealing, the HBC battery silicon wafers are directly transferred to the metallization electrode preparation process or the antireflection film deposition process via an automated conveyor. The process flow of the method is matched with the cycle time of the HBC battery production line, and the processing time for a single silicon wafer is 15 to 35 seconds. The method does not change the original wet cleaning process flow and parameters of the HBC battery, and is embedded as an independent post-processing process after the wet cleaning process and before other processes, so as to realize continuous production of the production line.

[0015] Preferably, the method further includes a post-annealing silicon wafer surface cleaning step S4.5: using deionized water or ultrapure water to perform a final cleaning of the HBC battery silicon wafer after annealing and cooling to remove volatile byproducts and particulate matter that may be generated during the annealing process, and then drying it with nitrogen gas; the resistivity of the ultrapure water is ≥18.2 MΩ·cm, and the total organic carbon (TOC) content is ≤10 ppb.

[0016] Preferably, the annealing treatment reduces the interface state density Dit of the HBC cell silicon wafer by more than 50%, increases the minority carrier lifetime by more than 30%, increases the open-circuit voltage Voc by 5mV to 20mV, increases the fill factor FF by 0.5% to 2%, and ultimately increases the HBC cell conversion efficiency by 0.3% to 1.0%. The annealing treatment has no significant adverse effects on the crystal structure, carrier concentration, mobility, and optical transmittance of the ITO transparent conductive layer. The sheet resistance change rate of the ITO layer is less than 5%, and the average transmittance change rate in the visible light band is less than 2%.

[0017] The beneficial effects of this invention are: This invention utilizes low-temperature rapid annealing to restore the PL brightness of HBC battery silicon wafers after wet cleaning to the level before cleaning or even higher within an extremely short time of 10 to 30 seconds. It exhibits high passivation recovery efficiency and significant effects.

[0018] This invention strictly controls the annealing temperature within a low temperature range of 300℃ to 500℃, which is below the damage temperature threshold (>500℃) of the ITO layer and the amorphous silicon layer. This protects the crystal structure, conductivity and optical properties of the ITO transparent conductive layer from damage, while preventing the crystallization of the amorphous silicon layer and ensuring the integrity of each functional film layer of the HBC battery.

[0019] The annealing process used in this invention is compatible with existing HBC battery production lines and can be implemented during online production without changing the original process flow, ensuring smooth process integration.

[0020] This invention uses a muffle furnace as the annealing equipment, which has low equipment cost, simple operation, and controllable cost of protective atmosphere such as nitrogen or argon, making it suitable for large-scale mass production.

[0021] This invention is applicable not only to passivation recovery after FeCl3 solution etching and cleaning of ITO layers, but also to passivation recovery after alkaline cleaning of amorphous silicon layers, and can handle various wet cleaning scenarios in the HBC battery manufacturing process.

[0022] This invention uses PL brightness testing to quantitatively evaluate the passivation recovery effect, which facilitates real-time monitoring and quality control of the process. Attached Figure Description

[0023] The advantages of the present invention, both above and / or other aspects, will become clearer and more readily understood through the following detailed description taken in conjunction with the accompanying drawings, which are merely illustrative and do not limit the invention, wherein: Figure 1 This is a process flow diagram of a passivation recovery method for HBC battery silicon wafers after wet cleaning, according to an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the effect of different annealing times on passivation recovery in one embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the effect of different annealing temperatures on passivation recovery in one embodiment of the present invention. Detailed Implementation

[0024] In the following text, reference will be made to the appendix. Figure 1-3 This invention describes an embodiment of a passivation recovery method for HBC battery silicon wafers after wet cleaning.

[0025] The embodiments described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation or scope of the invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0026] The accompanying drawings in this specification are schematic diagrams to aid in illustrating the concept of the invention, and schematically show the shapes of the various parts and their interrelationships. Please note that, in order to clearly demonstrate the structure of the components in the embodiments of the invention, the drawings are not drawn to the same scale. The same reference numerals are used to indicate the same parts.

[0027] Example: A method for passivation recovery after wet cleaning of HBC battery silicon wafers, the method comprising the following steps: S1. Pretreatment steps: After the ITO layer is etched and cleaned with FeCl3 solution and / or the amorphous silicon layer is cleaned with alkaline solution, the HBC battery silicon wafer is rinsed with deionized water and dried with nitrogen to remove residual cleaning solution, reaction by-products and impurity particles on the silicon wafer surface. S2. Wafer loading and atmosphere setup steps: Load the pretreated HBC cell silicon wafers into the muffle furnace chamber, seal the furnace door and introduce nitrogen or argon protective atmosphere, control the gas flow rate to 5L / min~20L / min, purge the air in the chamber and maintain a positive pressure environment. S3. Low-temperature rapid annealing step: Start the muffle furnace heating and control the heating rate to 50℃ / s~100℃ / s to rapidly raise the chamber temperature to the annealing temperature of 300℃~500℃, and maintain the annealing time at this temperature for 10 seconds~30 seconds to repair the a-Si passivation film damage caused by wet cleaning, eliminate dangling bonds and interface defects at the c-Si / a-Si interface, reduce the interface state density Dit and improve the minority carrier lifetime of the silicon wafer. S4. Cooling Step: After the annealing process is completed, heating is stopped and the protective atmosphere is maintained for purging. The cooling rate is controlled at 20℃ / s to 50℃ / s to cool the silicon wafer to room temperature. This completes the passivation recovery process after wet cleaning of the HBC battery silicon wafer. The annealing process does not significantly affect the structure, conductivity, and optical properties of the ITO transparent conductive layer.

[0028] In step S3, the annealing temperature is within the optimized temperature range of 380℃ to 420℃, and the annealing time is within the optimized time range of 15 seconds to 20 seconds. Preferably, the annealing temperature is 400℃ and the annealing time is 15 seconds, so as to achieve the best balance between passivation recovery effect and ITO layer performance protection, so that the PL brightness of the mask protection area is restored to more than 130% of the level before cleaning and the sheet resistance change rate of the ITO layer is less than 5%.

[0029] In step S3, the muffle furnace uses infrared radiation heating or multi-segment resistance wire heating, with the heating element being a graphite heating element or a molybdenum alloy heating element. The chamber uses a quartz tube or ceramic lining structure to ensure the uniformity of the temperature field, and the temperature uniformity within the chamber is controlled within ±5℃. The rated operating temperature of the muffle furnace is above 800℃, and it can process 25 to 100 HBC battery silicon wafers of 166mm×166mm, 182mm×182mm, or 210mm×210mm specifications in a single batch. The processing cycle matches the production line, meeting the needs of large-scale mass production.

[0030] The protective atmosphere in step S2 has a purity of ≥99.999%, an oxygen content of ≤5ppm, and a water content of ≤3ppm. Preferably, the nitrogen or argon gas is further deoxygenated and dehydrated by a gas purifier before being introduced into the chamber. During the annealing process, the chamber pressure is maintained at a slightly positive pressure of 0.05MPa to 0.15MPa to prevent external air from seeping in and causing secondary oxidation on the silicon wafer surface.

[0031] Before step S2, a passivation effect detection and evaluation step S1.5 for the wet cleaning process is included: the passivation effect of the HBC cell silicon wafer after wet cleaning is detected using a photoluminescence (PL) tester or a microwave photoconductivity attenuation (μ-PCD) tester, and the PL brightness value or minority carrier lifetime value is measured; when the PL brightness value is lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is lower than 70% of the baseline value before cleaning, it is determined that the annealing process needs to be performed; when the PL brightness value is not lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is not lower than 70% of the baseline value before cleaning, the annealing process is skipped and the process proceeds directly to the next step; the preset threshold is set based on the HBC cell mass production yield and efficiency requirements.

[0032] Following step S4, a passivation recovery effect verification step S5 is also included: A photoluminescence (PL) tester is used to test the PL brightness of the annealed HBC battery silicon wafer. The PL brightness value after annealing is compared with the baseline PL brightness value before wet cleaning, and the passivation recovery rate η is calculated as: η = (PL after annealing - PL after alkaline cleaning) / (PL before cleaning - PL after alkaline cleaning) × 100%. When η ≥ 100%, the passivation recovery is deemed qualified and proceeds to the next process; when η < 100%, the passivation recovery is deemed unqualified and returns to the rework process. Furthermore, step S5 also includes testing the sheet resistance of the ITO transparent conductive layer. A four-probe sheet resistance tester is used to measure the change rate of the ITO layer sheet resistance before and after annealing, requiring the change rate to be less than 5% to ensure the stability of the ITO layer's conductivity.

[0033] The wet cleaning process includes at least one of FeCl3 solution etching and cleaning of the ITO layer and alkaline cleaning of the amorphous silicon layer; the concentration of the FeCl3 solution is 5wt% to 15wt%, the cleaning temperature is 20℃ to 40℃, and the cleaning time is 30 seconds to 120 seconds; the alkaline cleaning process uses one of NaOH solution, KOH solution, or TMAH tetramethylammonium hydroxide solution, the concentration of the alkaline solution is 1wt% to 10wt%, the cleaning temperature is 40℃ to 80℃, and the cleaning time is 30 seconds to 180 seconds; the passivation recovery method is applicable to silicon wafers after FeCl3 solution etching and cleaning, silicon wafers after alkaline cleaning, and silicon wafers that have undergone FeCl3 solution etching and cleaning and alkaline cleaning in sequence, and can effectively restore the passivation effect lost after each process.

[0034] The method is implemented in the online production process of HBC battery manufacturing. After annealing, the HBC battery silicon wafers are directly transferred to the metallization electrode preparation process or the antireflection film deposition process via an automated conveyor. The process flow of the method is matched with the cycle time of the HBC battery production line, and the processing time for a single silicon wafer is 15 to 35 seconds. The method does not change the original wet cleaning process flow and parameters of HBC batteries. It is embedded as an independent post-processing step after the wet cleaning step and before other steps, so as to realize continuous production of the production line.

[0035] The method further includes a post-annealing silicon wafer surface cleaning step S4.5: using deionized water or ultrapure water to perform a final cleaning of the HBC battery silicon wafer after annealing and cooling to remove volatile byproducts and particulate matter that may be generated during the annealing process, and then drying it with nitrogen gas; the resistivity of the ultrapure water is ≥18.2 MΩ·cm and the total organic carbon (TOC) content is ≤10 ppb.

[0036] The annealing treatment reduces the interface state density Dit of the HBC cell silicon wafer by more than 50%, increases the minority carrier lifetime by more than 30%, increases the open-circuit voltage Voc by 5mV to 20mV, increases the fill factor FF by 0.5% to 2%, and ultimately increases the HBC cell conversion efficiency by 0.3% to 1.0%. The annealing treatment has no significant adverse effects on the crystal structure, carrier concentration, mobility, and optical transmittance of the ITO transparent conductive layer. The sheet resistance change rate of the ITO layer is less than 5%, and the average transmittance change rate in the visible light band is less than 2%.

[0037] Example 1: Standard process verification: The HBC cell silicon wafer uses the M6 ​​specification (166mm×166mm), with an N-type monocrystalline silicon substrate resistivity of 1Ω·cm~3Ω·cm, a wafer thickness of 160μm, a SiNx passivation layer on the front side, a MgF2 / SiNx double-layer antireflection film, and a 5nm intrinsic amorphous silicon i-layer and a 10nm N-type amorphous silicon N-layer on the back side. + Layer and P-type amorphous silicon P + The layers are arranged in a finger-like, intersecting pattern, with each finger being 500 μm wide and spaced 500 μm apart. A top layer is covered with an 80 nm ITO transparent conductive layer (sheet resistance 43 Ω / □). The wet cleaning process involves etching with a 10 wt% FeCl3 solution at 25°C for 60 seconds to remove the unmasked ITO layer, followed by 5 wt% FeCl3 solution. The amorphous silicon layer not protected by the mask was removed by alkaline washing with NaOH solution at 60℃ for 120s. Passivation recovery process: S1 Rinse three times with deionized water and dry with nitrogen; S2 Place the silicon wafer in a muffle furnace chamber and purge the air with nitrogen at 10L / min; S3 Heating rate is 80℃ / s to 400℃ and hold for 15s; S4 Natural cooling rate is 30℃ / s to room temperature. Test results: The PL brightness of the masked area increased from 14185 after alkaline washing to 27410, an increase of 34.7% compared with 20355 before washing; the PL brightness of the non-masked area was 23-25, which is basically consistent with the original silicon; the ITO sheet resistance changed from 43Ω / □ to 42Ω / □, with a change rate of 2.3% <5%. This embodiment verifies the efficient recovery capability of the present invention method for the passivation effect after wet cleaning of HBC cells under standard process parameters.

[0038] The test results are shown in the table below: Test results show that after low-temperature annealing, the PL brightness of the masked area increased from 14185 after alkaline washing to 27410, which is 34.7% higher than 20355 before washing, and the passivation effect was significantly restored. In contrast, the non-masked area had a very low PL brightness (23-25) because the a-Si layer had been completely cleaned, which is basically the same as the original silicon, indicating that the a-Si layer in the non-masked area has been completely removed, achieving the expected process objective.

[0039] The sheet resistance test results of the ITO layer show that the sheet resistance of the ITO layer after annealing is 42Ω / □, which is basically consistent with the 43Ω / □ before annealing. The change rate is less than 5%, indicating that the annealing process of the present invention has no significant impact on the performance of the ITO layer.

[0040] Example 2: Low-temperature long-time process verification: The only difference between Example 2 and Example 1 is that the annealing temperature in step S3 is adjusted to 300℃ and the annealing time is extended to 30s. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1. The wet cleaning process parameters are consistent with those in Example 1. Passivation recovery process: S1 Surface pretreatment; S2 Introducing nitrogen at 10L / min; S3 Controlling the heating rate at 80℃ / s to raise the chamber temperature to 300℃ and maintaining it at 300℃ for 30s; S4 Natural cooling to room temperature. Experimental data: The PL brightness of the mask area slowly increased from 14185 after alkaline cleaning to 21500, an increase of only 5.6% compared to 20355 before cleaning. The passivation recovery rate was about 30 percentage points lower than that of Example 1; the PL brightness of the non-masked region was basically consistent with that of the original silicon; the ITO sheet resistance changed from 43Ω / □ to 42.5Ω / □, with a change rate of 1.2% < 5%. The analysis shows that at the lower annealing temperature of 300℃, the lattice repair kinetics of the a-Si layer is relatively slow. Even if the annealing time is extended to 30s, the degree of dangling bond elimination and interface state density reduction is still insufficient, resulting in an unsatisfactory passivation recovery effect. This example verifies the key influence of annealing temperature on the passivation recovery effect, proving that although 300℃ as the lower limit of the annealing temperature of this invention can achieve a certain passivation recovery, the effect is limited.

[0041] Example 3: High-Temperature Short-Time Process Verification: The only difference between Example 3 and Example 1 is that the annealing temperature in step S3 is adjusted to 500℃ and the annealing time is shortened to 10s. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1. The wet cleaning process parameters are consistent with those in Example 1. Passivation recovery process: S1 Surface pretreatment; S2 Introducing nitrogen at 10L / min; S3 Controlling the heating rate at 80℃ / s to rapidly raise the chamber temperature to 500℃ and maintain it at 500℃ for only 10s; S4 Natural cooling to room temperature. Experimental data: The PL brightness of the masked area increased from 14185 after alkaline cleaning to 26800, an increase of 31.7% compared to 20355 before cleaning. The passivation recovery degree is close to that of Example 1. The PL brightness of the non-masked area is 26, which is similar to that of the original silicon. The results are basically the same; however, the ITO sheet resistance increased from 43Ω / □ to 46Ω / □, with a change rate of 7.0% > 5%, which exceeds the limit requirement for protecting the performance of the ITO layer in this invention. Analysis shows that at an annealing temperature of 500℃, the lattice repair speed of the a-Si layer is significantly accelerated, and a good passivation recovery effect can be achieved within 10s. However, 500℃ is close to the damage temperature threshold of the ITO layer. Long-term or repeated exposure to this temperature will cause microscopic changes in the crystal structure of the ITO layer, resulting in a decrease in carrier mobility and an increase in sheet resistance. This embodiment verifies that although 500℃, as the upper limit of the annealing temperature of this invention, can achieve good passivation recovery under short-term conditions, it has a slight impact on the performance of the ITO layer, and the exposure time needs to be strictly controlled.

[0042] Example 4: Validation of the suboptimal temperature long-term process: The only difference between Example 4 and Example 1 is that the annealing temperature in step S3 is adjusted to 380℃ and the annealing time is extended to 20s. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1. The wet cleaning process parameters are consistent with those in Example 1. Passivation recovery process: S1 Surface pretreatment; S2 Introducing nitrogen at 10L / min; S3 Controlling the heating rate at 80℃ / s to raise the chamber temperature to 380℃ and maintaining it at 380℃ for 20s; S4 Natural cooling to room temperature. Experimental data: The PL brightness of the masked area increased from 14185 after alkaline cleaning to 25600, an increase of 25.8% compared to 20355 before cleaning, indicating good passivation recovery effect; the PL brightness of the non-masked area was 25... The results are basically consistent with those of the original silicon. The sheet resistance of ITO changes from 43Ω / □ to 42Ω / □, with a change rate of 2.3% < 5%, which has virtually no impact on the performance of the ITO layer. Analysis shows that although the annealing temperature of 380℃ is lower than 400℃ in Example 1, by extending the annealing time from 15s to 20s, the impact of the temperature reduction on the lattice repair kinetics can be compensated to a certain extent, achieving a better passivation recovery effect while maintaining good protection of the ITO layer performance. This example verifies the flexibility of the combination of annealing temperature and time parameters of the present invention, proving that good passivation recovery effect and ITO layer performance protection can be achieved in the temperature range of 380℃ to 420℃ with an annealing time of 15s to 20s.

[0043] Example 5: Validation of the suboptimal temperature long-term process: The only difference between Example 5 and Example 1 is that the annealing temperature in step S3 is adjusted to 420℃ and the annealing time is extended to 18s. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1. The wet cleaning process parameters are consistent with those in Example 1. Passivation recovery process: S1 Surface pretreatment; S2 Introducing nitrogen at 10L / min; S3 Controlling the heating rate at 80℃ / s to raise the chamber temperature to 420℃ and maintaining it at 420℃ for 18s; S4 Natural cooling to room temperature. Experimental data: The PL brightness of the masked area increased from 14185 after alkaline cleaning to 27900, an increase of 37.1% compared to 20355 before cleaning. The passivation recovery effect is excellent and the best among all examples. The PL brightness of the non-masked area is 25, which is basically the same as that of the original silicon. Consistent; the ITO sheet resistance changed from 43Ω / □ to 44.5Ω / □, with a change rate of 3.5% < 5%, which has virtually no impact on the performance of the ITO layer. Analysis shows that the annealing temperature of 420℃ is slightly higher than 400℃ in Example 1, resulting in faster lattice repair of the a-Si layer, more complete elimination of dangling bonds and reduction of interface state density, thus the passivation recovery effect is better than that of 400℃. Although the temperature rises to 420℃, which is close to the damage temperature threshold of the ITO layer, the ITO layer is not significantly affected because the annealing time is controlled within a short range of 18s. This example and Example 4 together verify the wide process window of the present invention in the annealing temperature range of 380℃ to 420℃, and good passivation recovery effects can be achieved by different combinations of temperature and time.

[0044] Example 6: Argon protective atmosphere process verification: The only difference between Example 6 and Example 1 is that in step S2, the protective atmosphere is replaced by argon instead of nitrogen, and the gas flow rate is adjusted from 10L / min to 15L / min. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1, and the wet cleaning process parameters are consistent with Example 1. In step S3, the annealing temperature is kept at 400℃ and the annealing time is kept at 15s. Passivation recovery process: S1 Surface pretreatment; S2 Introducing 15L / min of argon to purge the air in the cavity; S3 Heating rate of 80℃ / s to 400℃ and holding for 15s; S4 Natural cooling to room temperature. Experimental data: The PL brightness of the mask area increased from 14185 after alkaline cleaning to 27300, an increase of 34.2% compared to 20355 before cleaning. Passivation recovery effect. The results are essentially the same as in Example 1 using a nitrogen protective atmosphere, with differences of less than 0.5%. The PL brightness (24) in the non-masked area is essentially the same as that of the original silicon. The ITO sheet resistance changes from 43Ω / □ to 42Ω / □, with a change rate of 2.3% (<5%), which has virtually no impact on the ITO layer performance. Analysis shows that argon, as an inert gas, has similar chemical inertness to nitrogen. Both can effectively prevent secondary oxidation of the silicon wafer surface during annealing, providing a good inert environment for a-Si layer lattice repair and dangling bond elimination. Therefore, using an argon protective atmosphere can achieve passivation recovery effects comparable to those of a nitrogen protective atmosphere. This example verifies the substitutability of the protective atmosphere of the present invention, proving that both nitrogen and argon can be used as the protective atmosphere of the present invention, thus broadening the industrial application options of the method of the present invention.

[0045] Example 7: Forced air cooling rapid cooling process verification: The only difference between Example 7 and Example 1 is that in step S4, natural cooling is replaced with forced air cooling, and the cooling rate is increased from 30℃ / s to 50℃ / s. The specifications and structure of the HBC battery silicon wafer are the same as in Example 1. The wet cleaning process parameters are consistent with Example 1. In step S3, the annealing temperature is kept at 400℃ and the annealing time is kept at 15s. In step S2, the protective atmosphere is kept at nitrogen and the flow rate is kept at 10L / min. Passivation recovery process: S1 Surface pretreatment; S2 Introducing nitrogen at 10L / min; S3 Heating rate is increased from 80℃ / s to 400℃ and held for 15s; S4 After annealing, the forced air cooling system is started, and the cooling rate is controlled at 50℃ / s to rapidly cool the silicon wafer to room temperature. Experimental data: The PL brightness of the mask area increased from 14185 after alkaline cleaning to 27000, compared to 2035 before cleaning. The passivation recovery effect was 32.7% higher than that of Example 1 using natural cooling; the PL brightness of the non-mask area was 25, which was basically the same as that of the original silicon; the ITO sheet resistance changed from 43Ω / □ to 42Ω / □, with a change rate of 2.3% < 5%, which had almost no impact on the performance of the ITO layer. The analysis showed that the forced air cooling method could increase the cooling rate to 50℃ / s, shorten the annealing time of a single silicon wafer by about 8s to 12s, and improve the matching degree of the production line cycle time; at the same time, the cooling rate of 50℃ / s is within the cooling rate parameter range of the present invention (20℃ / s to 50℃ / s), and does not cause thermal shock damage to the silicon wafer. The passivation recovery effect is comparable to that of the natural cooling method. This example verifies the flexibility of the cooling method of the present invention, and proves that both natural cooling and forced air cooling methods are applicable to the present invention. They can be flexibly selected according to the production line cycle time requirements, which improves the industrial applicability of the method of the present invention.

[0046] In summary, this method for restoring passivation after wet cleaning of HBC battery silicon wafers achieves efficient restoration of the protection and passivation effect of the sensitive film layer of HBC batteries by strictly controlling the annealing temperature to 300℃~500℃ and the annealing time to 10 seconds~30 seconds, combined with a nitrogen or argon protective atmosphere and specific heating / cooling rate control. This fills the technological gap in the field of low-temperature rapid annealing passivation restoration for HBC batteries.

[0047] The technical features disclosed above are not limited to the combinations of the disclosed features with other features. Those skilled in the art can also make other combinations of the technical features according to the purpose of the invention to achieve the purpose of the invention.

Claims

1. A method for passivation recovery after wet cleaning of HBC battery silicon wafers, characterized in that, The method includes the following steps: S1. Pretreatment steps: After the ITO layer is etched and cleaned with FeCl3 solution and / or the amorphous silicon layer is cleaned with alkaline solution, the HBC battery silicon wafer is rinsed with deionized water and dried with nitrogen to remove residual cleaning solution, reaction by-products and impurity particles on the silicon wafer surface. S2. Wafer loading and atmosphere setup steps: Load the pretreated HBC cell silicon wafers into the muffle furnace chamber, seal the furnace door and introduce nitrogen or argon protective atmosphere, control the gas flow rate to 5L / min~20L / min, purge the air in the chamber and maintain a positive pressure environment. S3. Low-temperature rapid annealing step: Start the muffle furnace heating and control the heating rate to 50℃ / s~100℃ / s to rapidly raise the chamber temperature to the annealing temperature of 300℃~500℃, and maintain the annealing time at this temperature for 10 seconds~30 seconds to repair the a-Si passivation film damage caused by wet cleaning, eliminate dangling bonds and interface defects at the c-Si / a-Si interface, reduce the interface state density Dit and improve the minority carrier lifetime of the silicon wafer. S4. Cooling Step: After the annealing process is completed, heating is stopped and the protective atmosphere is maintained for purging. The cooling rate is controlled at 20℃ / s to 50℃ / s to cool the silicon wafer to room temperature. This completes the passivation recovery process after wet cleaning of the HBC battery silicon wafer. The annealing process does not significantly affect the structure, conductivity, and optical properties of the ITO transparent conductive layer.

2. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 1, characterized in that, In step S3, the annealing temperature is within the optimized temperature range of 380℃ to 420℃, and the annealing time is within the optimized time range of 15 seconds to 20 seconds. Preferably, the annealing temperature is 400℃ and the annealing time is 15 seconds, so as to achieve the best balance between passivation recovery effect and ITO layer performance protection, so that the PL brightness of the mask protection area is restored to more than 130% of the level before cleaning and the sheet resistance change rate of the ITO layer is less than 5%.

3. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 2, characterized in that, In step S3, the muffle furnace uses infrared radiation heating or multi-segment resistance wire heating, with the heating element being a graphite heating element or a molybdenum alloy heating element. The chamber uses a quartz tube or ceramic lining structure to ensure the uniformity of the temperature field, and the temperature uniformity within the chamber is controlled within ±5℃. The rated operating temperature of the muffle furnace is above 800℃, and it can process 25 to 100 HBC battery silicon wafers of 166mm×166mm, 182mm×182mm, or 210mm×210mm specifications in a single batch. The processing cycle matches the production line, meeting the needs of large-scale mass production.

4. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 3, characterized in that, The protective atmosphere in step S2 has a purity of ≥99.999%, an oxygen content of ≤5ppm, and a water content of ≤3ppm. Preferably, the nitrogen or argon gas is further deoxygenated and dehydrated by a gas purifier before being introduced into the chamber. During the annealing process, the chamber pressure is maintained at a slightly positive pressure of 0.05MPa to 0.15MPa to prevent external air from seeping in and causing secondary oxidation on the silicon wafer surface.

5. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 4, characterized in that, Before step S2, a passivation effect detection and evaluation step S1.5 for the wet cleaning process is included: the passivation effect of the HBC cell silicon wafer after wet cleaning is detected using a photoluminescence (PL) tester or a microwave photoconductivity attenuation (μ-PCD) tester, and the PL brightness value or minority carrier lifetime value is measured; when the PL brightness value is lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is lower than 70% of the baseline value before cleaning, it is determined that the annealing process needs to be performed; when the PL brightness value is not lower than 80% of the baseline value before cleaning or the minority carrier lifetime value is not lower than 70% of the baseline value before cleaning, the annealing process is skipped and the process proceeds directly to the next step; the preset threshold is set based on the HBC cell mass production yield and efficiency requirements.

6. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 5, characterized in that, Following step S4, a passivation recovery effect verification step S5 is also included: A photoluminescence (PL) tester is used to test the PL brightness of the annealed HBC battery silicon wafer. The PL brightness value after annealing is compared with the baseline PL brightness value before wet cleaning, and the passivation recovery rate η is calculated as: η = (PL after annealing - PL after alkaline cleaning) / (PL before cleaning - PL after alkaline cleaning) × 100%. When η ≥ 100%, the passivation recovery is deemed qualified and proceeds to the next process; when η < 100%, the passivation recovery is deemed unqualified and returns to the rework process. Furthermore, step S5 also includes testing the sheet resistance of the ITO transparent conductive layer. A four-probe sheet resistance tester is used to measure the change rate of the ITO layer sheet resistance before and after annealing, requiring the change rate to be less than 5% to ensure the stability of the ITO layer's conductivity.

7. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 6, characterized in that, The wet cleaning process includes at least one of FeCl3 solution etching and cleaning of the ITO layer and alkaline cleaning of the amorphous silicon layer; the concentration of the FeCl3 solution is 5wt% to 15wt%, the cleaning temperature is 20℃ to 40℃, and the cleaning time is 30 seconds to 120 seconds; the alkaline cleaning process uses one of NaOH solution, KOH solution, or TMAH tetramethylammonium hydroxide solution, the concentration of the alkaline solution is 1wt% to 10wt%, the cleaning temperature is 40℃ to 80℃, and the cleaning time is 30 seconds to 180 seconds; the passivation recovery method is applicable to silicon wafers after FeCl3 solution etching and cleaning, silicon wafers after alkaline cleaning, and silicon wafers that have undergone FeCl3 solution etching and cleaning and alkaline cleaning in sequence, and can effectively restore the passivation effect lost after each process.

8. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 7, characterized in that, The method is implemented in the online production process of HBC battery manufacturing. After annealing, the HBC battery silicon wafers are directly transferred to the metallization electrode preparation process or the antireflection film deposition process via an automated conveyor. The process flow of the method is matched with the cycle time of the HBC battery production line, and the processing time for a single silicon wafer is 15 to 35 seconds. The method does not change the original wet cleaning process flow and parameters of HBC batteries. It is embedded as an independent post-processing step after the wet cleaning step and before other steps, so as to realize continuous production of the production line.

9. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 8, characterized in that, The method further includes a post-annealing silicon wafer surface cleaning step S4.5: using deionized water or ultrapure water to perform a final cleaning of the HBC battery silicon wafer after annealing and cooling to remove volatile byproducts and particulate matter that may be generated during the annealing process, and then drying it with nitrogen gas; the resistivity of the ultrapure water is ≥18.2 MΩ·cm and the total organic carbon (TOC) content is ≤10 ppb.

10. The passivation recovery method for HBC battery silicon wafers after wet cleaning according to claim 9, characterized in that, The annealing treatment reduces the interface state density Dit of the HBC cell silicon wafer by more than 50%, increases the minority carrier lifetime by more than 30%, increases the open-circuit voltage Voc by 5mV to 20mV, increases the fill factor FF by 0.5% to 2%, and ultimately increases the HBC cell conversion efficiency by 0.3% to 1.0%. The annealing treatment has no significant adverse effects on the crystal structure, carrier concentration, mobility, and optical transmittance of the ITO transparent conductive layer. The sheet resistance change rate of the ITO layer is less than 5%, and the average transmittance change rate in the visible light band is less than 2%.

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