A method for reducing thermal and mechanical stress in thin silicon wafer production

Abstract

The application discloses a thin silicon wafer preparation method for reducing thermal stress and mechanical stress, and belongs to the technical field of photovoltaic cell manufacturing. The method comprises the following steps: step S1, a PN junction is prepared by low-stress boron diffusion, a tubular high-temperature oxidation diffusion furnace is used for boron diffusion, the deposition temperature is controlled to be 840-880 DEG C, and the advancing temperature is controlled to be 1000-1030 DEG C. The four processes of stage gradient cooling, low-temperature PECVD, low-pressure spray cleaning and ALD single-inserted wafer passivation are optimized in cooperation, the precise control of the thermal stress and the mechanical stress of the thin silicon wafer is realized, and the effect is remarkable. The broken wafer rate is reduced from 1.5%-2.5% to 0.3%-0.8%, a decrease of 63%-86%; the edge defect rate is reduced by more than 80%; the edge leakage rate is reduced by 82%-85% compared with the traditional process; the deviation of the cell efficiency consistency is less than or equal to 0.03%; the average cell efficiency is improved by 0.4-0.6 percentage points. Meanwhile, the process is compatible with the existing TOPCon production line, large-scale equipment modification is not needed, and only parameter adjustment is needed for mass production, so that the cost is reduced and the efficiency is increased, and the yield and reliability are effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic cell manufacturing technology, and in particular relates to a method for preparing thin silicon wafers that reduces thermal and mechanical stress. Background Technology

[0002] As the photovoltaic industry rapidly develops towards "cost reduction and efficiency improvement," thinner silicon wafers have become a core trend in the industry. Thin silicon wafers with a thickness of 110-120μm are widely used in TOPCon cell production because they can significantly reduce silicon material consumption and increase the cell output per unit of silicon material. However, thin silicon wafers themselves have low mechanical strength and high brittleness, posing many technical challenges in traditional manufacturing processes. In the traditional TOPCon cell manufacturing process, silicon wafers need to undergo multiple high-temperature process steps, including high-temperature boron diffusion, preparation of tunnel oxide and polycrystalline silicon layers, and metallization sintering. In these processes, the heating and cooling rates are relatively fast (usually ≥5℃ / min), and the temperature difference between the inside and outside of the silicon wafer is large, generating significant thermal stress. For thin silicon wafers with a thickness of only 110-120μm, thermal stress can easily lead to edge chipping, microcracks, or even fragmentation. The fragmentation rate of traditional processes is as high as 1.5%-2.5%, which seriously affects production yield and cost control.

[0003] Thin silicon wafers are prone to mechanical damage such as edge chipping and microcracks during cutting, transport and processing. In addition, the edge passivation treatment in traditional processes is insufficient (such as using back-to-back dual-insertion method), which leads to serious edge recombination and prominent edge leakage problems, resulting in decreased cell conversion efficiency and increased defect rate.

[0004] In existing processes, the parameter designs for each step, such as cleaning, diffusion, oxidation, deposition, and passivation, are independent of each other. There is no systematic and coordinated optimization for the low stress requirements of thin silicon wafers. The independent optimization of each step cannot fundamentally solve the problems of stress accumulation and edge defects, making it difficult to meet the yield and consistency requirements of large-scale mass production.

[0005] Currently, the processing of thin silicon wafers is mostly focused on adjusting parameters of a single process step, such as lowering the temperature of a single step or adjusting the process parameters at a single point. This has not formed a systematic low-stress process combination. This "single-point optimization" approach cannot fundamentally solve the problems of stress accumulation and edge defects in the thin silicon wafer manufacturing process, and it is difficult to meet the comprehensive requirements of yield, efficiency and reliability for the development of TOPCon cells to achieve thinner wafers. Summary of the Invention

[0006] The purpose of this invention is to provide a method for preparing thin silicon wafers that reduces thermal and mechanical stress. It employs a synergistic optimization of four processes: staged gradient cooling, low-temperature PECVD, low-pressure spray cleaning, and ALD single-insertion passivation. This achieves precise control of thermal and mechanical stress in the thin silicon wafers, resulting in significant improvements: the breakage rate is reduced from 1.5%-2.5% to 0.3%-0.8%, a decrease of 63%-86%; the edge defect rate is reduced by more than 80%; the edge leakage rate is reduced by 82%-85% compared to traditional processes; the cell efficiency consistency deviation is ≤0.03%; and the average cell efficiency is increased by 0.4-0.6 percentage points. Furthermore, this process is compatible with existing TOPCon production lines, requiring no large-scale equipment modifications; only parameter adjustments are needed for mass production. This significantly reduces costs and increases efficiency, effectively improving yield and reliability, thus solving the aforementioned technical problems.

[0007] The technical solution of this invention to solve the above-mentioned technical problems is as follows: A method for preparing thin silicon wafers to reduce thermal and mechanical stress, comprising the following steps, wherein each step synergistically controls stress: Step S1: Low-stress boron diffusion is used to prepare PN junctions. Boron diffusion is performed in a tubular high-temperature oxidation diffusion furnace. The deposition temperature is controlled at 840-880℃, the advance temperature is controlled at 1000-1030℃, and the heating rate is controlled at 8-10℃ / min. The cooling process adopts a staged gradient cooling, including a first cooling stage from the advance temperature to 900℃ at a cooling rate of 2.0-3.0℃ / min for 50-55min, and a second cooling stage from the advance temperature to 800℃ at a cooling rate of 3.0-4.0℃ / min for 25-30min. The furnace pressure is maintained at 210-220mbar. The diffusion furnace adopts 1-6 temperature zones for zone temperature control, with each zone independently controlled. The temperature difference between different locations inside the tube is ≤5℃. Step S2: Preparation of low-stress tunneling oxide layer and polycrystalline silicon deposition and crystallization. The SiO2 tunneling layer and polycrystalline silicon layer are prepared by plasma-enhanced chemical vapor deposition (PECVD). The overall process temperature is controlled in the low-temperature range of 430-450℃, the oxidation time is controlled in the range of 80-90s, and the polycrystalline silicon deposition time is controlled in the range of 400-450s. A uniform SiO2 tunneling layer with a thickness of 1.0-1.5nm and a polycrystalline silicon layer with a thickness of 115-120nm are prepared. The process temperature is kept constant and the fluctuation is ≤±5℃. Step S3: Low-stress cleaning of silicon wafers. An improved RCA cleaning process is used to clean the boron-diffused silicon wafers. The acid pickling solution ratio is HF:H2O2:HCl = 1:2:3 (volume ratio). The cleaning temperature is controlled at 30-35℃, and the cleaning time is controlled at 100-120s. Low-pressure spraying is used during the cleaning process, with the spray pressure controlled within the range of 0.05-0.1MPa. After cleaning, nitrogen and air temperature are used for drying, with the drying air velocity controlled at 1-2m / s. The drying tank temperature is set at 95-100℃. Step S4: Edge passivation enhancement. Atomic layer deposition (ALD) process is used to deposit Al2O3 passivation layers on the front and back sides of the silicon wafer. Single wafer insertion method is used. The deposition temperature is controlled at 200-250℃. The deposition thickness in a single cycle is controlled at 5-8nm. Alumina passivation film is deposited independently on both the front and back sides of the silicon wafer.

[0008] Preferably, in step S1, the cooling rate of the first cooling stage of the staged gradient cooling is preferably 2.5℃ / min, and the process time is preferably 52min; the cooling rate of the second cooling stage is preferably 3.5℃ / min, and the process time is preferably 28.5min. This two-stage cooling method gradually reduces the temperature difference between the surface and the core of the silicon wafer during the cooling process. Compared with the traditional one-step cooling process (cooling rate 4.5℃ / min), it reduces the temperature difference constraint between the inside and outside of the silicon wafer by more than 50%, effectively avoiding edge chipping, microcracks and fragmentation caused by thermal stress accumulation. The zoned temperature control in step S1 includes dividing the tubular high-temperature oxidation diffusion furnace into 1-6 independent temperature control zones along the silicon wafer transport direction. Each temperature zone has its own temperature parameters and is controlled independently, so that the temperature difference experienced by the silicon wafer at different positions in the tubular furnace is ≤5℃. Preferably, the temperature set values ​​of the 1-6 temperature zones are symmetrically or approximately symmetrically distributed from the center to both ends to avoid thermal stress differences in different areas of the silicon wafer caused by uneven temperature distribution inside the tube. The heating rate mentioned in step S1 is controlled within the range of 8-10℃ / min, which is higher than the heating rate of ≥5℃ / min in traditional processes (mostly 6℃ / min in practice). By reasonably controlling the heating gradient, the temperature difference between the inside and outside of the silicon wafer is kept within an acceptable range during the heating process; at the same time, the heating rate is not lower than 8℃ / min to ensure production efficiency. The tubular high-temperature oxidation diffusion furnace described in step S1 has a quartz tube material and an inner diameter of 200-300mm. It can process 200-400 silicon wafers per batch. The boron source is either BBr3 or BN, and it is introduced by a carrier gas method, with nitrogen as the carrier gas.

[0009] Preferably, the overall process temperature of the PECVD process in step S2 is 430-450℃, which is 300-370℃ lower than the 750-800℃ of the traditional LPCVD thermal oxidation process. This low-temperature process significantly reduces the temperature difference between the preparation process of the tunnel oxide layer and the polycrystalline silicon layer and the silicon wafer after boron diffusion, avoiding significant thermal stress caused by the silicon wafer undergoing high temperature again after boron diffusion. The process temperature fluctuation is ≤±5℃, avoiding the accumulation of new thermal stress caused by temperature fluctuation. In step S2, the thickness of the SiO2 tunneling layer is 1.0-1.5 nm, preferably 1.0-1.2 nm; the thickness of the polycrystalline silicon layer is 115-120 nm, preferably 115-118 nm; the SiO2 tunneling layer and the polycrystalline silicon layer together form the tunneling oxide passivation contact structure of the TOPCon cell, achieving low-stress fabrication while ensuring passivation effect.

[0010] Preferably, the pressure of the low-pressure spray in step S3 is 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. The improved RCA cleaning process in step S3 also includes a standard RCA cleaning step performed before the acid washing step 2, including SC1 cleaning (NH4OH:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃) and SC2 cleaning (HCl:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃), which are used to remove organic matter, particles and metal ion contamination from the silicon wafer surface.

[0011] Preferably, the ALD single-insertion method in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are completely exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The ALD single-insertion method described in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are fully exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The deposition thickness in step S4 is 5-8 nm, preferably 5-6 nm; the double-sided deposited alumina passivation film is deposited independently on the front and back sides of the silicon wafer, so that the edges of the front and back sides of the silicon wafer are protected by high-quality Al2O3 passivation; the deposition temperature is controlled in the range of 200-250℃, preferably 200-220℃. In step S4, the number of deposition cycles in the ALD process is determined based on the target thickness and the deposition rate per cycle. The typical deposition rate per cycle is 0.1-0.2 nm / cycle; the total number of deposition cycles is 25-80, preferably 25-60. In step S4, the aluminum source precursor used in the ALD process is trimethylaluminum (TMA), and the oxygen source precursor is one or more of H2O or O3. During the deposition process, the precursor pulse time, cleaning time, and chamber pressure are optimized according to the target film thickness and uniformity requirements.

[0012] Preferably, a silicon wafer transfer step is included between the four steps S1 to S4. The transfer of the silicon wafer between each step adopts a low-stress transfer method, including one or more of robotic arm transfer or conveyor belt transfer. During the transfer process, the silicon wafer is subjected to uniform force to avoid mechanical collisions and vibrations. The process parameters in steps S1-S4 of the method work together to form a low-stress process combination: the staged gradient cooling in step S1 minimizes the stress level of the silicon wafer after boron diffusion; the low-temperature PECVD process in step S2 significantly reduces the temperature rise in the subsequent deposition process (from the end temperature of boron diffusion to 430-450℃); the low-pressure spraying and nitrogen drying in step S3 avoid introducing mechanical and thermal stresses during the cleaning and drying process; the single-insertion ALD process in step S4 completes edge passivation under low-temperature conditions, avoiding secondary thermal stress on the thin silicon wafer caused by high temperature; the four steps work together to achieve precise stress control throughout the entire thin silicon wafer fabrication process.

[0013] Preferably, the thin silicon wafer is either a single-crystal silicon wafer or a quasi-single-crystal silicon wafer, and the initial surface state of the silicon wafer is the surface state after wire cutting, grinding and etching treatment, with the silicon wafer (100) crystal plane orientation.

[0014] Preferably, the thin silicon wafers prepared using this method have a fragmentation rate ≤0.8%, an edge defect rate ≤0.3%, a cell efficiency consistency deviation ≤0.03%, and an edge leakage rate that is more than 80% lower than that of traditional processes. Specifically, when the thickness of the thin silicon wafer is 110μm, the fragmentation rate is ≤0.3%, the edge defect rate is ≤0.2%, and the edge leakage rate is 85% lower than that of traditional processes; when the thickness of the thin silicon wafer is 115μm, the fragmentation rate is ≤0.5%, the edge defect rate is ≤0.25%, and the edge leakage rate is 83% lower than that of traditional processes; when the thickness of the thin silicon wafer is 120μm, the fragmentation rate is ≤0.8%, the edge defect rate is ≤0.3%, and the edge leakage rate is 82% lower than that of traditional processes.

[0015] Preferably, this method is applicable to the TOPCon photovoltaic cell manufacturing field, including n-type TOPCon cells and p-type TOPCon cells; the entire process combination is compatible with existing TOPCon cell production lines, requiring no large-scale equipment modification, and only the process parameters (temperature, time, pressure, rate, etc.) need to be adjusted to achieve mass production application; preferably, this method is applicable to GW-level TOPCon cell mass production lines.

[0016] A thin silicon wafer with a thickness of 110-120 μm, a fragmentation rate ≤0.8%, an edge defect rate ≤0.3%, a cell efficiency consistency deviation ≤0.03%, and an edge leakage rate that is more than 80% lower than that of thin silicon wafers prepared by traditional processes; both the front and back sides of the thin silicon wafer are covered with an Al2O3 passivation film, and the Al2O3 passivation film coverage in the edge area is ≥95%; the thin silicon wafer is used to prepare TOPCon photovoltaic cells.

[0017] Preferably, the aforementioned.

[0018] The beneficial effects of this invention are: This invention reduces the thermal and mechanical stress of thin silicon wafers to a minimum through low-stress synergistic design of each process step, including staged gradient cooling, low-temperature PECVD process, and low-pressure spray cleaning. The breakage rate is reduced from 1.5%-2.5% in traditional processes to 0.3%-0.8%, significantly improving production yield.

[0019] This invention deposits double-sided Al2O3 passivation films using an ALD single-insertion method, improving the passivation quality of the front and back edges of silicon wafers, reducing the edge defect rate by more than 80%, and reducing the edge leakage rate by 82%-85% compared to traditional processes.

[0020] The entire process combination of the present invention is compatible with existing TOPCon battery production lines, requiring no large-scale equipment modification. Mass production can be achieved simply by adjusting process parameters, significantly reducing modification costs.

[0021] The low-stress process of this invention reduces internal defects in silicon wafers, enhances edge passivation to improve battery stability, and extends battery life. At the same time, it avoids efficiency dispersion caused by stress, with battery efficiency consistency deviation ≤0.03%, significantly improving battery performance consistency. Attached Figure Description

[0022] The advantages of the present invention, both above and / or other aspects, will become clearer and more readily understood through the following detailed description taken in conjunction with the accompanying drawings, which are merely illustrative and do not limit the invention, wherein: Figure 1 This is a flowchart of a low-stress fabrication process for thin silicon wafers according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the temperature-time curve of a staged gradient cooling according to an embodiment of the present invention. Detailed Implementation

[0023] In the following text, reference will be made to the appendix. Figure 1-2 This invention describes an embodiment of a method for preparing thin silicon wafers that reduces thermal and mechanical stress.

[0024] The embodiments described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation or scope of the invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0025] The accompanying drawings in this specification are schematic diagrams to aid in illustrating the concept of the invention, and schematically show the shapes of the various parts and their interrelationships. Please note that, in order to clearly demonstrate the structure of the components in the embodiments of the invention, the drawings are not drawn to the same scale. The same reference numerals are used to indicate the same parts.

[0026] Example: A method for fabricating thin silicon wafers to reduce thermal and mechanical stress includes the following steps, in which each step synergistically controls stress: Step S1: Low-stress boron diffusion is used to prepare PN junctions. Boron diffusion is performed in a tubular high-temperature oxidation diffusion furnace. The deposition temperature is controlled at 840-880℃, the advance temperature is controlled at 1000-1030℃, and the heating rate is controlled at 8-10℃ / min. The cooling process adopts a staged gradient cooling, including a first cooling stage from the advance temperature to 900℃ at a cooling rate of 2.0-3.0℃ / min for 50-55min, and a second cooling stage from the advance temperature to 800℃ at a cooling rate of 3.0-4.0℃ / min for 25-30min. The furnace pressure is maintained at 210-220mbar. The diffusion furnace adopts 1-6 temperature zones for zone temperature control, with each zone independently controlled. The temperature difference between different locations inside the tube is ≤5℃. Step S2: Preparation of low-stress tunneling oxide layer and polycrystalline silicon deposition and crystallization. The SiO2 tunneling layer and polycrystalline silicon layer are prepared by plasma-enhanced chemical vapor deposition (PECVD). The overall process temperature is controlled in the low-temperature range of 430-450℃, the oxidation time is controlled in the range of 80-90s, and the polycrystalline silicon deposition time is controlled in the range of 400-450s. A uniform SiO2 tunneling layer with a thickness of 1.0-1.5nm and a polycrystalline silicon layer with a thickness of 115-120nm are prepared. The process temperature is kept constant and the fluctuation is ≤±5℃. Step S3: Low-stress cleaning of silicon wafers. An improved RCA cleaning process is used to clean the boron-diffused silicon wafers. The acid pickling solution ratio is HF:H2O2:HCl = 1:2:3 (volume ratio). The cleaning temperature is controlled at 30-35℃, and the cleaning time is controlled at 100-120s. Low-pressure spraying is used during the cleaning process, with the spray pressure controlled within the range of 0.05-0.1MPa. After cleaning, nitrogen and air temperature are used for drying, with the drying air velocity controlled at 1-2m / s. The drying tank temperature is set at 95-100℃. Step S4: Edge passivation enhancement. Atomic layer deposition (ALD) process is used to deposit Al2O3 passivation layers on the front and back sides of the silicon wafer. Single wafer insertion method is used. The deposition temperature is controlled at 200-250℃. The deposition thickness in a single cycle is controlled at 5-8nm. Alumina passivation film is deposited independently on both the front and back sides of the silicon wafer.

[0027] In step S1, the cooling rate of the first cooling stage of the phased gradient cooling is preferably 2.5℃ / min, and the process time is preferably 52min; the cooling rate of the second cooling stage is preferably 3.5℃ / min, and the process time is preferably 28.5min. This two-stage cooling method gradually reduces the temperature difference between the surface and the core of the silicon wafer during the cooling process. Compared with the traditional one-step cooling process (cooling rate 4.5℃ / min), it reduces the temperature difference constraint between the inside and outside of the silicon wafer by more than 50%, effectively avoiding edge chipping, microcracks and fragmentation caused by thermal stress accumulation. The zoned temperature control in step S1 includes dividing the tubular high-temperature oxidation diffusion furnace into 1-6 independent temperature control zones along the silicon wafer transport direction. Each temperature zone has its own temperature parameters and is controlled independently, so that the temperature difference experienced by the silicon wafer at different positions in the tubular furnace is ≤5℃. Preferably, the temperature set values ​​of the 1-6 temperature zones are symmetrically or approximately symmetrically distributed from the center to both ends to avoid thermal stress differences in different areas of the silicon wafer caused by uneven temperature distribution inside the tube. The heating rate mentioned in step S1 is controlled within the range of 8-10℃ / min, which is higher than the heating rate of ≥5℃ / min in traditional processes (mostly 6℃ / min in practice). By reasonably controlling the heating gradient, the temperature difference between the inside and outside of the silicon wafer is kept within an acceptable range during the heating process; at the same time, the heating rate is not lower than 8℃ / min to ensure production efficiency. The tubular high-temperature oxidation diffusion furnace described in step S1 has a quartz tube material and an inner diameter of 200-300mm. It can process 200-400 silicon wafers per batch. The boron source is either BBr3 or BN, and it is introduced by a carrier gas method, with nitrogen as the carrier gas.

[0028] The overall process temperature of the PECVD process in step S2 is 430-450℃, which is 300-370℃ lower than the 750-800℃ of the traditional LPCVD thermal oxidation process. This low-temperature process significantly reduces the temperature difference between the preparation of the tunnel oxide layer and the polycrystalline silicon layer and the silicon wafer after boron diffusion, avoiding significant thermal stress caused by the silicon wafer undergoing high temperature again after boron diffusion. The process temperature fluctuation is ≤±5℃, avoiding the accumulation of new thermal stress caused by temperature fluctuation. In step S2, the thickness of the SiO2 tunneling layer is 1.0-1.5 nm, preferably 1.0-1.2 nm; the thickness of the polycrystalline silicon layer is 115-120 nm, preferably 115-118 nm; the SiO2 tunneling layer and the polycrystalline silicon layer together form the tunneling oxide passivation contact structure of the TOPCon cell, achieving low-stress fabrication while ensuring passivation effect.

[0029] The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. The improved RCA cleaning process in step S3 also includes a standard RCA cleaning step performed before the acid washing step 2, including SC1 cleaning (NH4OH:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃) and SC2 cleaning (HCl:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃), which are used to remove organic matter, particles and metal ion contamination from the silicon wafer surface.

[0030] The ALD single-insertion method described in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are fully exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The ALD single-insertion method described in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are fully exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The deposition thickness in step S4 is 5-8 nm, preferably 5-6 nm; the double-sided deposited alumina passivation film is deposited independently on the front and back sides of the silicon wafer, so that the edges of the front and back sides of the silicon wafer are protected by high-quality Al2O3 passivation; the deposition temperature is controlled in the range of 200-250℃, preferably 200-220℃. In step S4, the number of deposition cycles in the ALD process is determined based on the target thickness and the deposition rate per cycle. The typical deposition rate per cycle is 0.1-0.2 nm / cycle; the total number of deposition cycles is 25-80, preferably 25-60. In step S4, the aluminum source precursor used in the ALD process is trimethylaluminum (TMA), and the oxygen source precursor is one or more of H2O or O3. During the deposition process, the precursor pulse time, cleaning time, and chamber pressure are optimized according to the target film thickness and uniformity requirements.

[0031] Between steps S1 to S4, there is also a silicon wafer transfer step. The transfer of silicon wafers between each step adopts a low-stress transfer method, including one or more of robotic arm transfer or conveyor belt transfer. During the transfer process, the silicon wafer is subjected to uniform force to avoid mechanical collisions and vibrations. The process parameters in steps S1-S4 of the method work together to form a low-stress process combination: the staged gradient cooling in step S1 minimizes the stress level of the silicon wafer after boron diffusion; the low-temperature PECVD process in step S2 significantly reduces the temperature rise in the subsequent deposition process (from the end temperature of boron diffusion to 430-450℃); the low-pressure spraying and nitrogen drying in step S3 avoid introducing mechanical and thermal stresses during the cleaning and drying process; the single-insertion ALD process in step S4 completes edge passivation under low-temperature conditions, avoiding secondary thermal stress on the thin silicon wafer caused by high temperature; the four steps work together to achieve precise stress control throughout the entire thin silicon wafer fabrication process.

[0032] The thin silicon wafer is either a single-crystal silicon wafer or a quasi-single-crystal silicon wafer. The initial surface state of the silicon wafer is the surface state after wire cutting, grinding and etching treatment, and the silicon wafer (100) crystal plane direction.

[0033] The thin silicon wafers prepared using this method have a fragmentation rate of ≤0.8%, an edge defect rate of ≤0.3%, a cell efficiency consistency deviation of ≤0.03%, and an edge leakage rate that is more than 80% lower than that of traditional processes. Specifically, when the thickness of the thin silicon wafer is 110μm, the fragmentation rate is ≤0.3%, the edge defect rate is ≤0.2%, and the edge leakage rate is 85% lower than that of traditional processes; when the thickness of the thin silicon wafer is 115μm, the fragmentation rate is ≤0.5%, the edge defect rate is ≤0.25%, and the edge leakage rate is 83% lower than that of traditional processes; when the thickness of the thin silicon wafer is 120μm, the fragmentation rate is ≤0.8%, the edge defect rate is ≤0.3%, and the edge leakage rate is 82% lower than that of traditional processes.

[0034] This method is applicable to the manufacturing of TOPCon photovoltaic cells, including n-type TOPCon cells and p-type TOPCon cells. The entire process combination is compatible with existing TOPCon cell production lines, requiring no large-scale equipment modifications. Mass production applications can be achieved simply by adjusting process parameters (temperature, time, pressure, rate, etc.). Preferably, this method is applicable to GW-level TOPCon cell mass production lines.

[0035] A thin silicon wafer with a thickness of 110-120 μm, a fragmentation rate ≤0.8%, an edge defect rate ≤0.3%, a cell efficiency consistency deviation ≤0.03%, and an edge leakage rate that is more than 80% lower than that of thin silicon wafers prepared by traditional processes; both the front and back sides of the thin silicon wafer are covered with an Al2O3 passivation film, and the Al2O3 passivation film coverage in the edge area is ≥95%; the thin silicon wafer is used to prepare TOPCon photovoltaic cells.

[0036] Example 1: This embodiment provides a method for preparing thin silicon wafers that reduces thermal and mechanical stress. The detailed process flow and specific steps are as follows: Step S1: Preparation of PN junction by low-stress boron diffusion Boron diffusion was performed using a tubular high-temperature oxidation diffusion furnace (furnace tube inner diameter 250mm, processing 300 silicon wafers per batch). The boron source was BBr3, and the carrier gas was high-purity nitrogen. Specific parameters were: deposition temperature 840℃, deposition time 20min; advance temperature 1000℃, advance time 30min; heating rate 8℃ / min; the cooling process employed a two-stage gradient cooling: the first cooling stage decreased from 1000℃ to 900℃ at a rate of 2.5℃ / min over 52min; the second cooling stage decreased from 900℃ to 800℃ at a rate of 3.5℃ / min over 28.5min. The furnace pressure was maintained at 210mbar; the diffusion furnace was configured with 1-6 independently controlled temperature zones along the silicon wafer transport direction, each zone with individual PID temperature control, and the temperature difference within the tube ≤5℃.

[0037] Step S2: Preparation of low-stress tunneling oxide layer and deposition and crystallization of polycrystalline silicon A PECVD system was used for the continuous deposition of a tunneling oxide layer and a polycrystalline silicon layer. The overall process temperature was 430℃ (significantly lower than the 780℃ of the traditional LPCVD process), with temperature fluctuations of ≤±3℃. The oxidation time was 80s, and the polycrystalline silicon deposition time was 400s, resulting in a uniform SiO2 tunneling layer with a thickness of 1.0nm and a polycrystalline silicon layer of 115nm.

[0038] Step S3: Low-stress cleaning of silicon wafers The cleaning process was improved using RCA cleaning. The ratio of the pickling solution was: HF (49%): H2O2 (30%): HCl (37%) = 1:2:3 (volume ratio). The cleaning temperature was 30℃ and the cleaning time was 100s. The spray pressure was 0.08MPa. The nitrogen blowing speed was 1m / s and the drying tank temperature was 95℃.

[0039] Step S4: Edge passivation enhancement An Al2O3 passivation layer was deposited using an ALD device, with TMA (trimethylaluminum) as the aluminum source and H2O as the oxygen source. A single wafer insertion method was used, with a deposition temperature of 200℃ and a deposition thickness of 5nm. Alumina passivation films were deposited independently on both the front and back sides of the silicon wafer.

[0040] Performance test data: Tests showed that the thin silicon wafer fragmentation rate of this embodiment was 0.3%, the edge defect rate was 0.2%, the battery efficiency consistency deviation was ≤0.03%, the edge leakage rate was reduced by 85% compared with the traditional process, and the average battery efficiency reached 25.2%, which fully meets the requirements for large-scale mass production of TOPCon batteries.

[0041] Example 2: This embodiment provides a method for preparing thin silicon wafers that reduces thermal and mechanical stress. The detailed process flow and specific steps are as follows: Step S1: Preparation of PN junction by low-stress boron diffusion Boron diffusion was performed using a tubular high-temperature oxidation diffusion furnace (300mm inner diameter, processing 400 silicon wafers per batch). The boron source was BBr3, and the carrier gas was high-purity nitrogen. Specific parameters were: deposition temperature 880℃, deposition time 25 min; advance temperature 1030℃, advance time 35 min; heating rate 10℃ / min; the cooling process employed a two-stage gradient cooling: the first cooling stage involved reducing the temperature from 1030℃ to 900℃ at a rate of 2.5℃ / min over 52 min; the second cooling stage involved reducing the temperature from 900℃ to 800℃ at a rate of 3.5℃ / min over 28.5 min. The furnace pressure was maintained at 220 mbar; the diffusion furnace was equipped with independent temperature control in six zones, with a temperature difference within the tubes ≤5℃.

[0042] Step S2: Preparation of low-stress tunneling oxide layer and deposition and crystallization of polycrystalline silicon A PECVD system was used for the continuous deposition of a tunneling oxide layer and a polycrystalline silicon layer. The overall process temperature was 450℃, with temperature fluctuations ≤±3℃. The oxidation time was 90s, and the polycrystalline silicon deposition time was 450s, resulting in a uniform SiO2 tunneling layer with a thickness of 1.5nm and a polycrystalline silicon layer with a thickness of 120nm.

[0043] Step S3: Low-stress cleaning of silicon wafers The cleaning process was modified RCA. The acid pickling solution ratio was HF:H2O2:HCl = 1:2:3 (volume ratio). The cleaning temperature was 35℃ and the cleaning time was 120s. The spray pressure was 0.1MPa. The nitrogen blowing speed was 2m / s and the drying tank temperature was 95℃.

[0044] Step S4: Edge passivation enhancement An Al2O3 passivation layer was deposited using an ALD device with TMA as the aluminum source and H2O as the oxygen source. A single wafer insertion method was used, the deposition temperature was 250℃, the deposition thickness was 5nm, and the aluminum oxide passivation film was deposited independently on both the front and back sides of the silicon wafer.

[0045] Performance test data: Testing revealed that the thin silicon wafer fragmentation rate in this embodiment was 0.8%, the edge defect rate was 0.3%, the cell efficiency consistency deviation was ≤0.02%, the edge leakage rate was reduced by 82% compared to traditional processes, and the average cell efficiency reached 25.4%, fully meeting the requirements for large-scale mass production of TOPCon cells. While this embodiment features a relatively thick silicon wafer (120μm), resulting in superior mechanical strength compared to 110μm silicon wafers, thermal stress control still requires process optimization.

[0046] Example 3: This embodiment provides a method for preparing thin silicon wafers that reduces thermal and mechanical stress. It is specifically designed for 115 μm thick monocrystalline silicon wafers, serving as an intermediate thickness between Embodiment 1 and Embodiment 2. The detailed process flow and specific steps are as follows: Step S1: Preparation of PN junction by low-stress boron diffusion Boron diffusion was performed using a tubular high-temperature oxidation diffusion furnace (furnace tube inner diameter 270mm, processing 350 silicon wafers per batch). The boron source was BBr3, and the carrier gas was high-purity nitrogen. Specific parameters were: deposition temperature 860℃, deposition time 22min; advance temperature 1015℃, advance time 32min; heating rate 9℃ / min; the cooling process employed a two-stage gradient cooling: the first cooling stage decreased from 1015℃ to 900℃ at a rate of 2.2℃ / min over 52min; the second cooling stage decreased from 900℃ to 800℃ at a rate of 3.2℃ / min over 31min. The furnace pressure was maintained at 215mbar; the diffusion furnace was equipped with independent temperature control in 6 temperature zones, with a temperature difference within the tube ≤4℃.

[0047] Step S2: Preparation of low-stress tunneling oxide layer and deposition and crystallization of polycrystalline silicon A PECVD system was used for the continuous deposition of a tunneling oxide layer and a polycrystalline silicon layer. The overall process temperature was 440℃, with temperature fluctuations ≤±3℃. The oxidation time was 85s, and the polycrystalline silicon deposition time was 420s, resulting in a uniform SiO2 tunneling layer with a thickness of 1.2nm and a polycrystalline silicon layer with a thickness of 118nm.

[0048] Step S3: Low-stress cleaning of silicon wafers A modified RCA cleaning process was used for cleaning. The acid pickling solution ratio was HF:H2O2:HCl = 1:2:3 (volume ratio). The cleaning temperature was 32℃, and the cleaning time was 110s. The spray pressure was 0.09MPa. The nitrogen blowing speed was 1.5m / s, and the drying tank temperature was 97℃.

[0049] Step S4: Edge passivation enhancement An Al2O3 passivation layer was deposited using an ALD device with TMA as the aluminum source and H2O as the oxygen source. A single wafer insertion method was used, the deposition temperature was 220℃, the deposition thickness was 6nm, and the aluminum oxide passivation film was deposited independently on both the front and back sides of the silicon wafer.

[0050] Performance test data: Testing revealed that the thin silicon wafer fragmentation rate in this embodiment was 0.5%, the edge defect rate was 0.25%, the cell efficiency consistency deviation was ≤0.025%, the edge leakage rate was reduced by 83% compared to traditional processes, and the average cell efficiency reached 25.3%, fully meeting the requirements for large-scale mass production of TOPCon cells. This embodiment verifies the versatility and adaptability of the method of the present invention on thin silicon wafers of different thicknesses (110-120μm).

[0051] Comprehensive Comparative Analysis of Examples In summary, regarding fragmentation rate: the fragmentation rates of the three embodiments of this invention (0.3%-0.8%) are significantly lower than those of the comparative example (2.2%), with a reduction of 63.6%-86.4%, among which Example 1 (the thinnest silicon wafer at 110μm) shows the most significant improvement in fragmentation rate; regarding edge defect rate: the edge defect rates of the three embodiments of this invention (0.2%-0.3%) are significantly lower than those of the comparative example (1.5%), with a reduction of 80%-86.7%, demonstrating that the ALD single-insertion method has a significant effect on improving edge passivation; regarding efficiency consistency: the three embodiments of this invention... The efficiency consistency deviation (≤0.03%) was better than that of the comparative example (≤0.08%), proving that the low-stress process significantly improved the consistency of battery performance. Regarding edge leakage: the edge leakage rate of the three embodiments of the present invention was reduced by 82%-85% compared with the traditional process, proving that double-sided ALD passivation has a significant effect on reducing edge leakage. Regarding battery efficiency: the average battery efficiency of the three embodiments of the present invention (25.2%-25.4%) was higher than that of the comparative example (24.8%), with an efficiency improvement of 0.4-0.6 percentage points, proving that the low-stress process has a positive effect on improving battery conversion efficiency.

[0052] In summary, this method for preparing thin silicon wafers with reduced thermal and mechanical stress achieves precise control of thermal and mechanical stress through the synergistic optimization of four major processes: staged gradient cooling, low-temperature PECVD, low-pressure spray cleaning, and ALD single-insertion passivation. The results are significant: the breakage rate is reduced from 1.5%-2.5% to 0.3%-0.8%, a decrease of 63%-86%; the edge defect rate is reduced by more than 80%; the edge leakage rate is reduced by 82%-85% compared to traditional processes; the cell efficiency consistency deviation is ≤0.03%; and the average cell efficiency is improved by 0.4-0.6 percentage points. Furthermore, this process is compatible with existing TOPCon production lines, requiring no large-scale equipment modifications; only parameter adjustments are needed for mass production. This results in significant cost reduction and efficiency improvement, effectively enhancing yield and reliability.

[0053] The technical features disclosed above are not limited to the combinations of the disclosed features with other features. Those skilled in the art can also make other combinations of the technical features according to the purpose of the invention to achieve the purpose of the invention.

Claims

1. A method for preparing thin silicon wafers with reduced thermal and mechanical stress, characterized in that, The process includes the following steps, each working in synergy to control stress: Step S1: Low-stress boron diffusion is used to prepare PN junctions. Boron diffusion is performed in a tubular high-temperature oxidation diffusion furnace. The deposition temperature is controlled at 840-880℃, the advance temperature is controlled at 1000-1030℃, and the heating rate is controlled at 8-10℃ / min. The cooling process adopts a staged gradient cooling, including a first cooling stage from the advance temperature at a cooling rate of 2.0-3.0℃ / min for 50-55min to 900℃, and a second cooling stage at a cooling rate of 3.0-4.0℃ / min for 25-30min to 800℃. The furnace pressure is maintained at 210-220mbar. The diffusion furnace adopts 1-6 temperature zones for zone temperature control, with each zone independently controlled. The temperature difference between different locations inside the tube is ≤5℃. Step S2: Preparation of low-stress tunneling oxide layer and polycrystalline silicon deposition and crystallization. The SiO2 tunneling layer and polycrystalline silicon layer are prepared by plasma-enhanced chemical vapor deposition (PECVD). The overall process temperature is controlled in the low-temperature range of 430-450℃, the oxidation time is controlled in the range of 80-90s, and the polycrystalline silicon deposition time is controlled in the range of 400-450s. A uniform SiO2 tunneling layer with a thickness of 1.0-1.5nm and a polycrystalline silicon layer with a thickness of 115-120nm are prepared. The process temperature is kept constant and the fluctuation is ≤±5℃. Step S3: Low-stress cleaning of silicon wafers. An improved RCA cleaning process is used to clean the boron-diffused silicon wafers. The acid pickling solution ratio is HF:H2O2:HCl = 1:2:3 (volume ratio). The cleaning temperature is controlled at 30-35℃, and the cleaning time is controlled at 100-120s. Low-pressure spraying is used during the cleaning process, with the spray pressure controlled within the range of 0.05-0.1MPa. After cleaning, nitrogen and air temperature are used for drying, with the drying air velocity controlled at 1-2m / s. The drying tank temperature is set at 95-100℃. Step S4: Edge passivation enhancement. Atomic layer deposition (ALD) process is used to deposit Al2O3 passivation layers on the front and back sides of the silicon wafer. Single wafer insertion method is used. The deposition temperature is controlled at 200-250℃. The deposition thickness in a single cycle is controlled at 5-8nm. Alumina passivation film is deposited independently on both the front and back sides of the silicon wafer.

2. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 1, characterized in that, In step S1, the cooling rate of the first cooling stage of the phased gradient cooling is preferably 2.5℃ / min, and the process time is preferably 52min; the cooling rate of the second cooling stage is preferably 3.5℃ / min, and the process time is preferably 28.5min. This two-stage cooling method gradually reduces the temperature difference between the surface and the core of the silicon wafer during the cooling process. Compared with the traditional one-step cooling process (cooling rate 4.5℃ / min), it reduces the temperature difference constraint between the inside and outside of the silicon wafer by more than 50%, effectively avoiding edge chipping, microcracks and fragmentation caused by thermal stress accumulation. The zoned temperature control in step S1 includes dividing the tubular high-temperature oxidation diffusion furnace into 1-6 independent temperature control zones along the silicon wafer transport direction. Each temperature zone has its own temperature parameters and is controlled independently, so that the temperature difference experienced by the silicon wafer at different positions in the tubular furnace is ≤5℃. Preferably, the temperature set values ​​of the 1-6 temperature zones are symmetrically or approximately symmetrically distributed from the center to both ends to avoid thermal stress differences in different areas of the silicon wafer caused by uneven temperature distribution inside the tube. The heating rate mentioned in step S1 is controlled within the range of 8-10℃ / min, which is higher than the heating rate of ≥5℃ / min in traditional processes (mostly 6℃ / min in practice). By reasonably controlling the heating gradient, the temperature difference between the inside and outside of the silicon wafer is kept within an acceptable range during the heating process; at the same time, the heating rate is not lower than 8℃ / min to ensure production efficiency. The tubular high-temperature oxidation diffusion furnace described in step S1 has a quartz tube material and an inner diameter of 200-300mm. It can process 200-400 silicon wafers per batch. The boron source is either BBr3 or BN, and it is introduced by a carrier gas method, with nitrogen as the carrier gas.

3. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 2, characterized in that, The overall process temperature of the PECVD process in step S2 is 430-450℃, which is 300-370℃ lower than the 750-800℃ of the traditional LPCVD thermal oxidation process. This low-temperature process significantly reduces the temperature difference between the preparation of the tunnel oxide layer and the polycrystalline silicon layer and the silicon wafer after boron diffusion, avoiding significant thermal stress caused by the silicon wafer undergoing high temperature again after boron diffusion. The process temperature fluctuation is ≤±5℃, avoiding the accumulation of new thermal stress caused by temperature fluctuation. In step S2, the thickness of the SiO2 tunneling layer is 1.0-1.5 nm, preferably 1.0-1.2 nm; the thickness of the polycrystalline silicon layer is 115-120 nm, preferably 115-118 nm; the SiO2 tunneling layer and the polycrystalline silicon layer together form the tunneling oxide passivation contact structure of the TOPCon cell, achieving low-stress fabrication while ensuring passivation effect.

4. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 3, characterized in that, The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; The pressure of the low-pressure spray in step S3 is preferably 0.08-0.1 MPa, which is more than 30% lower than the spray pressure of 0.15 MPa or more in the traditional cleaning process, significantly reducing the mechanical impact stress of the high-pressure fluid on the surface of the thin silicon wafer; the cleaning temperature is controlled in the low temperature range of 30-35℃, which is 10-20℃ lower than the temperature of the traditional cleaning process (usually 40-50℃), further reducing the thermal stress caused by temperature changes; In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. In step S3, the nitrogen temperature and drying air velocity are preferably 1-2 m / s, which is more than 33% lower than the air velocity of 3 m / s or more in the traditional drying process, significantly reducing the impact of airflow on the thin silicon wafer; the drying tank temperature is preferably 95-100℃, which is 60-70℃ higher than the cleaning temperature, forming a gentle temperature gradient, which ensures the drying effect while avoiding thermal stress caused by sudden temperature changes. The improved RCA cleaning process in step S3 also includes a standard RCA cleaning step performed before the acid washing step 2, including SC1 cleaning (NH4OH:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃) and SC2 cleaning (HCl:H2O2:H2O=1:1:5, volume ratio, temperature 70-80℃), which are used to remove organic matter, particles and metal ion contamination from the silicon wafer surface.

5. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 4, characterized in that, The ALD single-insertion method described in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are fully exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The ALD single-insertion method described in step S4 is as follows: each silicon wafer is placed separately in the carrier of the ALD deposition chamber, and the front and back edges of the silicon wafer are fully exposed to the precursor airflow, with no adjacent silicon wafers blocking the edge area; compared with the traditional back-to-back dual-insertion method, the single-insertion method increases the Al2O3 passivation film coverage of the front and back edge areas of the silicon wafer from below 60% to above 95%; The deposition thickness in step S4 is 5-8 nm, preferably 5-6 nm; the double-sided deposited alumina passivation film is deposited independently on the front and back sides of the silicon wafer, so that the edges of the front and back sides of the silicon wafer are protected by high-quality Al2O3 passivation; the deposition temperature is controlled in the range of 200-250℃, preferably 200-220℃. In step S4, the number of deposition cycles in the ALD process is determined based on the target thickness and the deposition rate per cycle. The typical deposition rate per cycle is 0.1-0.2 nm / cycle; the total number of deposition cycles is 25-80, preferably 25-60. In step S4, the aluminum source precursor used in the ALD process is trimethylaluminum (TMA), and the oxygen source precursor is one or more of H2O or O3. During the deposition process, the precursor pulse time, cleaning time, and chamber pressure are optimized according to the target film thickness and uniformity requirements.

6. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 5, characterized in that, Between steps S1 to S4, there is also a silicon wafer transfer step. The transfer of silicon wafers between each step adopts a low-stress transfer method, including one or more of robotic arm transfer or conveyor belt transfer. During the transfer process, the silicon wafer is subjected to uniform force to avoid mechanical collisions and vibrations. The process parameters in steps S1-S4 of the method work together to form a low-stress process combination: the staged gradient cooling in step S1 minimizes the stress level of the silicon wafer after boron diffusion; the low-temperature PECVD process in step S2 significantly reduces the temperature rise in the subsequent deposition process (from the end temperature of boron diffusion to 430-450℃); the low-pressure spraying and nitrogen drying in step S3 avoid introducing mechanical and thermal stresses during the cleaning and drying process; the single-insertion ALD process in step S4 completes edge passivation under low-temperature conditions, avoiding secondary thermal stress on the thin silicon wafer caused by high temperature; the four steps work together to achieve precise stress control throughout the entire thin silicon wafer fabrication process.

7. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 6, characterized in that, The thin silicon wafer is either a single-crystal silicon wafer or a quasi-single-crystal silicon wafer. The initial surface state of the silicon wafer is the surface state after wire cutting, grinding and etching treatment, and the silicon wafer (100) crystal plane direction.

8. The method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 7, characterized in that, The thin silicon wafers prepared using this method have a fragmentation rate of ≤0.8%, an edge defect rate of ≤0.3%, a cell efficiency consistency deviation of ≤0.03%, and an edge leakage rate that is more than 80% lower than that of traditional processes. Specifically, when the thin silicon wafer thickness is 110μm, the fragmentation rate is ≤0.3%, the edge defect rate is ≤0.2%, and the edge leakage rate is 85% lower than that of traditional processes; when the thin silicon wafer thickness is 115μm, the fragmentation rate is ≤0.5%, the edge defect rate is ≤0.25%, and the edge leakage rate is 83% lower than that of traditional processes; when the thin silicon wafer thickness is 120μm, the fragmentation rate is ≤0.8%, the edge defect rate is ≤0.3%, and the edge leakage rate is 82% lower than that of traditional processes.

9. A method for preparing a thin silicon wafer with reduced thermal and mechanical stress according to claim 8, characterized in that, This method is applicable to the manufacturing of TOPCon photovoltaic cells, including n-type TOPCon cells and p-type TOPCon cells; The entire process is compatible with existing TOPCon battery production lines, requiring no large-scale equipment modifications. Mass production applications can be achieved simply by adjusting process parameters (temperature, time, pressure, rate, etc.). Preferably, this method is suitable for GW-level TOPCon battery mass production lines.

10. A thin silicon wafer, prepared by a method for reducing thermal and mechanical stress as described in any one of claims 1-9, characterized in that, The thin silicon wafer has a thickness of 110-120 μm, a fragmentation rate of ≤0.8%, an edge defect rate of ≤0.3%, a cell efficiency consistency deviation of ≤0.03%, and an edge leakage rate that is more than 80% lower than that of thin silicon wafers prepared by traditional processes. Both the front and back sides of the thin silicon wafer are covered with an Al2O3 passivation film, and the Al2O3 passivation film coverage in the edge area is ≥95%. The thin silicon wafer is used to prepare TOPCon photovoltaic cells.

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