High-temperature multi-field coupling annealing process and preparation method of TOPCon cell

Abstract

The application provides a high-temperature multi-field coupling annealing process and a preparation method of a TOPCon cell, and belongs to the technical field of the TOPCon cell; the annealing process comprises the following steps: stage 1: heating to 600-700 DEG C under an oxygen-containing atmosphere, and keeping the temperature for 2-5 minutes to form an oxidation protective layer; stage 2: applying a direct current electric field to both sides of the silicon wafer, and stepwise heating to 800-850 DEG C; stage 3: alternately performing oxygen-containing atmosphere treatment and protective atmosphere treatment at 800-850 DEG C; stage 4: applying a pulse electric field when the temperature is lowered to 750-800 DEG C; and stage 5: stepwise lowering the temperature to 300-400 DEG C, and introducing a protective gas; through the synergistic regulation of the temperature field, the electric field and the atmosphere field in each stage of annealing, the lattice defect is deeply repaired, the doping atoms are efficiently activated, the internal stress is fully released, and the hydrogen passivation is stabilized, so that the photoelectric conversion efficiency and the long-term reliability of the TOPCon cell are effectively improved, and the hidden crack rate is reduced.

Description

Technical Field

[0001] This invention relates to the field of TOPCon battery technology, and in particular to a high-temperature multi-field coupling annealing process and a method for preparing TOPCon batteries. Background Technology

[0002] TOPCon (Tunnel Oxide Passivation Contact) cells are one of the mainstream technologies for high-efficiency crystalline silicon solar cells. Their core structure consists of a tunneling oxide layer and a doped polycrystalline silicon layer sequentially arranged on the back side. These two layers together form a passivation contact structure. Through the synergistic effect of chemical passivation and field-effect passivation, the recombination rate of minority carriers is effectively reduced, significantly improving the open-circuit voltage and conversion efficiency of the cell.

[0003] In the industrial production of TOPCon batteries, high-temperature annealing processes (including polycrystalline silicon crystallization annealing and doping activation annealing) are crucial in determining battery performance. However, existing annealing processes still face many technical challenges.

[0004] First, existing annealing processes typically employ isothermal treatment, which involves holding the anneal at a fixed temperature for an extended period. Since different defects in the crystal lattice have different formation energies, a single temperature condition is insufficient for selectively repairing defects with varying formation energies, leading to incomplete lattice damage repair and impacting minority carrier lifetime.

[0005] Secondly, during high-temperature processing, uneven thermal expansion and contraction generate internal stress within the silicon wafer. This stress cannot be effectively released under constant temperature or simple cooling modes, easily leading to microcracks and warping of the silicon wafer. The microcrack problem is particularly prominent after module encapsulation, manifesting as a persistently high rate of microcracks, severely impacting product yield and long-term reliability.

[0006] Third, conventional annealing processes have limited electroactivation rates for doped atoms. Some doped atoms fail to occupy substitutional sites in the crystal lattice, thus failing to effectively provide charge carriers and affecting charge carrier transport efficiency and fill factor.

[0007] In addition, hydrogen passivation is usually involved in the annealing process to improve the passivation effect. However, the stability of hydrogen passivation under the existing process is insufficient. The performance of the finished battery fluctuates repeatedly under light and dark storage conditions. The efficiency is significantly improved after light injection, but the degradation is large after dark storage, which affects the long-term stability of the product.

[0008] To address the aforementioned issues, some improvements have been proposed in existing technologies. For example, the multi-stage variable-temperature annealing process disclosed by Heguang Tongcheng Photovoltaic Technology (publication number CN121285091A) achieves gradual repair of lattice damage through stepped heating and cooling, which improves the microcrack problem to some extent. However, it still has shortcomings in terms of defect repair depth, doping activation efficiency, and hydrogen passivation stability, and the improvement in microcrack rate has not reached the ideal level.

[0009] Therefore, there is an urgent need for a high-temperature multi-field coupling annealing process and a method for preparing TOPCon batteries to solve the technical problems in the existing technology, such as incomplete defect repair, insufficient release of internal stress leading to high microcrack rate, limited electroactivation rate of doped atoms, poor hydrogen passivation stability, and limitation to single temperature field control. Summary of the Invention

[0010] To address the aforementioned technical problems, this invention provides a high-temperature multi-field coupling annealing process and a method for preparing TOPCon cells. The aim is to achieve in-depth repair of lattice defects, efficient activation of doped atoms, full release of internal stress, and stabilization of hydrogen passivation through the synergistic control of temperature field, electric field, and atmosphere field at each stage of annealing. This will improve the photoelectric conversion efficiency and long-term reliability of TOPCon cells and reduce the microcrack rate.

[0011] To achieve the above objectives, this application proposes a high-temperature multi-field coupled annealing process, comprising the following stages performed sequentially: Heating and pre-oxidation stage: The silicon wafer is placed in an annealing furnace and heated to a first preset temperature at a first preset heating rate in an oxygen-containing atmosphere, and held at the temperature for a first preset time to form an oxide protective layer on the surface of the silicon wafer. High-temperature steady-state annealing stage: Within the second preset temperature range, oxygen-containing atmosphere treatment and protective atmosphere treatment are alternately performed to repair lattice damage through alternating atmospheres; Step-down cooling and stress release stage: The temperature is gradually reduced to the fourth preset temperature at the first preset cooling rate, and then held at each temperature step for the fourth preset time. Protective gas is introduced to gradually release the stress inside the silicon wafer.

[0012] As a further solution, the first preset heating rate is 2-5℃ / s, the first preset temperature is 600-700℃, the first preset time is 2-5min, and the thickness of the formed oxide protective layer is 1-3nm.

[0013] As a further solution, an electric field-assisted stepped heating stage is also provided between the heating and pre-oxidation stage and the high-temperature steady-state annealing stage: A DC electric field is applied to both sides of the silicon wafer, and the temperature is increased to a second preset temperature in steps at a second preset heating rate. The temperature is held at each temperature step for a second preset time, so as to use the electric field force to promote the directional migration of doped atoms and activate doped atoms with different activation energies in sequence.

[0014] As a further solution, the second preset heating rate is 1-3℃ / s, the number of heating steps is 2-4, the holding time for each step is 3-8min, and the second preset temperature is 800-850℃.

[0015] As a further solution, in the electric field-assisted stepped heating stage, the applied DC electric field is perpendicular to the silicon wafer surface, and the electric field strength increases gradually with the temperature step. The electric field strength is 5-20 V / cm in the temperature range of 600-700℃, 20-35 V / cm in the temperature range of 700-800℃, and 35-50 V / cm in the temperature range of 800-850℃.

[0016] As a further solution, the oxygen-containing atmosphere is a mixture of oxygen and a protective gas; wherein the oxygen volume fraction is 5%-20%, the oxygen flow rate is 1-5 slm, and the treatment time for each oxygen-containing atmosphere is 30-90 seconds. The protective gas flow rate for the protective atmosphere treatment is 10-30 slm, and the duration of each protective atmosphere treatment is 2-5 minutes; the oxygen atmosphere treatment is performed first, followed by the protective atmosphere treatment, and a total of 2-4 cycles are performed. The protective gas includes nitrogen and / or argon, and the furnace atmosphere composed of the protective gas is the protective atmosphere.

[0017] As a further solution, a variable-temperature electric field control stage is also provided between the high-temperature steady-state annealing stage and the stepped cooling and stress release stage: During the cooling process, a pulsed electric field is applied within a third preset temperature range for a third preset time, so as to promote the redistribution and bonding of hydrogen atoms using the pulsed electric field.

[0018] As a further solution, the parameters of the applied pulsed electric field in the variable temperature electric field control stage are as follows: pulse frequency of 50-500Hz, electric field strength of 10-100V / cm, pulse duty cycle of 30%-70%, and pulse waveform of square wave or sine wave; the third preset temperature range is 750-800℃, the third preset time is 5-15min, and the atmosphere inside the furnace is maintained as a protective atmosphere when the pulsed electric field is applied.

[0019] As a further solution, in the stepped cooling and stress release stage, the first preset cooling rate is 1-4℃ / s, the number of cooling steps is 3-5, the holding time for each step is 5-10min, the fourth preset temperature is 300-400℃, and the gas flow rate of the protective gas is 10-30slm.

[0020] On the other hand, the present invention also provides a method for preparing TOPCon cells, which uses a high-temperature multi-field coupling annealing process as described in any one of the above methods to perform annealing on silicon wafers.

[0021] Compared with related technologies, the high-temperature multi-field coupling annealing process and TOPCon battery preparation method provided by this invention have the following advantages: 1. This invention achieves stepwise repair of lattice defects through alternating atmosphere treatment in an electric field-assisted stepped heating stage and a high-temperature steady-state annealing stage. In the heating stage, an applied DC electric field lowers the defect formation energy, allowing simple point defects with low formation energy to be preferentially repaired at lower temperatures. The stepped heating, combined with a gradient increase in electric field strength, ensures that defects with different formation energies are repaired sequentially. In the high-temperature steady-state annealing stage, the alternating cycle of oxygen-containing and protective atmospheres further promotes lattice structure reconstruction and defect annihilation, avoiding the problems of incomplete repair or excessive oxidation under a single atmosphere. Through these synergistic effects, the bulk recombination center density is significantly reduced, minority carrier lifetime is improved, and thus the open-circuit voltage of the battery is increased. The open-circuit voltage of Example 1 reaches 0.7375V, higher than 0.7367V in Comparative Example 1 and 0.7368V in Comparative Example 2.

[0022] 2. In this invention, a DC electric field perpendicular to the silicon wafer surface is applied during the heating stage. The electric field promotes the directional migration of phosphorus dopant atoms, allowing them to occupy more favorable substitutional positions in the crystal lattice. The step-by-step heating combined with the gradient increase in electric field strength activates dopant atoms with different activation energies sequentially, avoiding excessive diffusion of dopant atoms at high temperatures. Simultaneously, the controllable oxide layer formed by oxygen-containing atmosphere treatment during the high-temperature steady-state annealing stage can regulate the diffusion behavior of dopant atoms, further optimizing the dopant distribution. The synergistic effect of the electric field and atmosphere significantly improves the electroactivation rate of dopant atoms, resulting in superior lateral resistance characteristics and fill factor. The fill factor of Example 1 reaches 87.01%, higher than 86.90% in Comparative Example 1 and 86.93% in Comparative Example 2.

[0023] 3. This invention employs a stepped cooling and stress release stage. Through the design of multiple cooling steps and multi-level insulation platforms, the internal stress of the silicon wafer is gradually and uniformly released during the cooling process. The insulation platform after each cooling step provides sufficient time for stress release, avoiding thermal shock damage caused by rapid cooling, and significantly reducing microcracks and warping of the silicon wafer caused by thermal stress. The microcrack rate of Example 1 is only 0.25%, which is about 71% lower than that of Comparative Example 1 (0.87%) and about 54% lower than that of Comparative Example 2 (0.54%), resulting in a significant improvement in product yield and mechanical reliability.

[0024] 4. This invention incorporates a variable-temperature electric field control stage during the cooling process, applying a pulsed electric field within the temperature range of 750-800℃. The periodic energy input generated by the pulsed electric field promotes the redistribution and stable bonding of hydrogen atoms. The frequency and duty cycle of the pulsed electric field can adjust the intensity and period of energy injection, achieving precise control over the migration behavior of hydrogen atoms and solving the problem of instability of hydrogen passivation in light-dark storage cycles in existing technologies. Stability test results show that the efficiency decay of Example 1 after 72 hours of dark storage is only 0.03 percentage points, far lower than the 0.14 percentage points of Comparative Example 1 and the 0.09 percentage points of Comparative Example 2, significantly improving the long-term reliability of the product.

[0025] 5. This invention achieves a comprehensive effect of deep lattice defect repair, efficient activation of doped atoms, full release of internal stress, and hydrogen passivation stabilization through the synergistic control of temperature field, electric field, and atmosphere field at each stage of annealing, resulting in a significant improvement in the photoelectric conversion efficiency of TOPCon cells. The conversion efficiency of Example 1 reached 27.22%, an increase of 0.05 percentage points compared to Comparative Example 1's 27.17%, and an increase of 0.08 percentage points compared to Comparative Example 2's 27.14%. Simultaneously, key electrical performance parameters such as open-circuit voltage and fill factor were also improved, demonstrating superior overall performance compared to existing technologies. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram illustrating the steps of a TOPCon battery fabrication method provided by the present invention; Figure 2This is a schematic diagram of the steps of a high-temperature multi-field coupling annealing process provided by the present invention; The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] like Figure 1 As shown, this invention provides a method for fabricating TOPCon batteries. Its core improvement lies in the synergistic control of multiple fields—temperature, electric, and atmospheric—during the high-temperature annealing process (existing methods mainly focus on controlling the single factor of temperature, without fully considering the synergistic effect of multi-field coupling such as electric and atmospheric fields on defect repair and doping activation). This achieves deep repair of lattice defects, efficient activation of doped atoms, full release of internal stress, and stabilization through hydrogen passivation. Except for the annealing process, other steps can employ conventional processes in this field.

[0031] The method for preparing the TOPCon battery includes the following steps S1-S11: Step S1: Provide an N-type silicon wafer substrate and perform double-sided texturing and cleaning. An N-type single-crystal silicon wafer is selected as the substrate, with a resistivity preferably of 0.5-2.0 Ω·cm and a thickness preferably of 130-150 μm. The silicon wafer undergoes double-sided texturing and cleaning to form a pyramid-shaped textured surface, reducing surface reflectivity and improving light absorption efficiency. After texturing, the surface reflectivity of the silicon wafer is typically below 10%.

[0032] Step S2: Perform boron diffusion on the front side of the silicon wafer to form a boron-doped emitter. Boron diffusion is performed on the front side of the silicon wafer using a conventional diffusion process. Boron trichloride (BCl3) or other boron-containing gases can be used as the boron source. The diffusion temperature is 900-1100℃, and the resulting sheet resistance is 120-600 Ω / □. The junction depth can be adjusted according to process requirements, typically 0.5-1.5 μm. A boron-doped emitter is used to form a PN junction, enabling the separation of photogenerated carriers.

[0033] Step S3: Remove the boron diffusion layer and borosilicate glass layer from the back and sides of the silicon wafer. During boron diffusion, a boron diffusion layer inevitably forms on the back and sides of the silicon wafer, while a borosilicate glass layer is formed on the surface. Unwanted diffusion layers and glass layers are removed using methods such as acid etching or laser etching to ensure the cleanliness and interface quality of the subsequent back-side structure.

[0034] Step S4: Sequentially deposit a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of the silicon wafer. On the back side of the silicon wafer, a tunneling oxide layer is first deposited using PECVD (plasma-enhanced chemical vapor deposition) or LPCVD (low-pressure chemical vapor deposition), followed by an intrinsic polycrystalline silicon layer. The tunneling oxide layer is typically made of silicon dioxide (SiO2) with a thickness of 1.0-2.0 nm, preferably 1.2-1.8 nm. The tunneling oxide layer provides chemical passivation while allowing majority carriers to transport through the tunneling effect and blocking minority carriers from reaching the interface. The intrinsic polycrystalline silicon layer has a thickness of 80-200 nm, preferably 100-150 nm.

[0035] Step S5: Phosphorus doping is performed on the intrinsic polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer. The intrinsic polycrystalline silicon layer was phosphorus-doped using ion implantation or thermal diffusion methods to become a phosphorus-doped polycrystalline silicon layer. The phosphorus doping concentration was 1×10⁻⁶. 20 -5×10 20 cm -3 Preferably 2×10 20 -3×10 20 cm -3 The phosphorus-doped polycrystalline silicon layer provides field-effect passivation, which, together with the tunneling oxide layer, forms a passivation contact structure.

[0036] Step S6: Annealing treatment is performed using a high-temperature multi-field coupling annealing process. The silicon wafer that has undergone the above steps is placed in an annealing furnace for the high-temperature multi-field coupling annealing treatment of this invention. The annealing treatment causes the phosphorus-doped polycrystalline silicon layer to crystallize and activates the doped atoms, allowing them to occupy substitutional sites in the crystal lattice and exert electrical activity.

[0037] like Figure 2 As shown, the annealing process includes the following five stages performed sequentially: Stage 1, Heating and Pre-oxidation Stage: Under an oxygen-containing atmosphere, the temperature is increased to 600-700℃ at a heating rate of 2-5℃ / s, and held for 2-5 minutes to form an oxide protective layer with a thickness of 1-3nm on the silicon wafer surface. This oxide protective layer can prevent the outward diffusion of dopant atoms during subsequent high-temperature processing, and at the same time avoid contamination of the silicon wafer surface by impurities in the furnace. The preferred heating rate is 3-4℃ / s, the preferred temperature is 650-680℃, and the preferred holding time is 3-4 minutes.

[0038] Phase 2, Electric Field-Assisted Stepped Heating Phase: A DC electric field is applied to both sides of the silicon wafer, and the temperature is raised to 800-850℃ in a stepped manner. The stepped heating refers to raising the temperature to the first temperature step at a certain rate, holding it at that temperature for a certain time, then continuing to raise the temperature to the next temperature step and holding it thereafter, repeating this process step by step until the target temperature is reached. The heating rate in this phase is 1-3℃ / s, each step is held for 3-8 minutes, and there are 2-4 heating steps. The DC electric field is applied perpendicular to the silicon wafer surface, and the electric field strength increases gradually with the temperature step. Specifically, the electric field strength is 5-20 V / cm in the 600-700℃ range, 20-35 V / cm in the 700-800℃ range, and 35-50 V / cm in the 800-850℃ range. The electric field promotes the directional migration of doped atoms, allowing them to occupy more favorable substitutional positions in the crystal lattice. Stepwise heating combined with a gradient increase in electric field strength activates doped atoms with different activation energies sequentially, preventing excessive diffusion of doped atoms at high temperatures. Simultaneously, the electric field lowers the defect formation energy, allowing simple point defects with low formation energies to be preferentially repaired at lower temperatures.

[0039] Phase 3, High-Temperature Steady-State Annealing: Within the temperature range of 800-850℃, alternating oxygen-containing atmosphere treatment and protective atmosphere treatment are performed. The oxygen-containing atmosphere treatment uses a mixture of oxygen and a protective gas, with an oxygen volume fraction of 5%-20% and an oxygen flow rate of 1-5 slm. Each oxygen-containing atmosphere treatment lasts 30-90 seconds. During the protective atmosphere treatment, a protective gas is introduced, and each treatment lasts 2-5 minutes. This alternating cycle is performed for a total of 2-4 cycles.

[0040] In one cycle, an oxygen-containing mixed gas is first introduced for oxidation treatment, followed by the introduction of a pure protective gas for purging and deep repair; the oxygen-containing atmosphere treatment aims to use oxygen to repair lattice damage and form an oxide layer on the surface.

[0041] Perform protective atmosphere treatment (annealing / repair): Stop oxygen supply and introduce pure N2 and / or Ar gas (flow rate 10–30 slm) for 2–5 minutes. Protective atmosphere treatment is used to further repair lattice defects in an oxygen-free environment, while using the protective gas to purge residual oxygen and reaction byproducts out of the furnace, providing a clean environment for the next oxidation cycle.

[0042] First, an oxygen-containing atmosphere treatment is performed, followed by a protective atmosphere treatment. The "oxygen-first, then protective" cycle (2-4 times in total) used in this embodiment conforms to the process logic of material annealing, which involves first oxidizing the surface and then performing deep repair through pure atmosphere annealing.

[0043] Nitrogen or argon can be used as the protective gas. Oxygen-containing atmosphere treatment can form a controllable oxide layer on the polycrystalline silicon surface, regulating the diffusion behavior of dopant atoms; protective atmosphere treatment promotes lattice structure reconstruction and defect annihilation. Alternating cycles of these two treatments can achieve deep repair of lattice damage while avoiding the negative impact of excessive oxidation on the passivation layer.

[0044] Phase 4, Variable Temperature Electric Field Control Phase: During the cooling process, a pulsed electric field is applied within the temperature range of 750-800℃ for 5-15 minutes. The parameters of the pulsed electric field are as follows: pulse frequency 50-500Hz, electric field strength 10-100V / cm, pulse duty cycle 30%-70%, and pulse waveform either square or sine wave. The furnace atmosphere is maintained as a protective atmosphere during the application of the pulsed electric field. The periodic energy input generated by the pulsed electric field promotes the redistribution and bonding of hydrogen atoms, enhancing the hydrogen passivation effect. The frequency and duty cycle of the pulsed electric field can adjust the intensity and period of energy injection, achieving precise control over the migration behavior of hydrogen atoms and solving the problem of unstable hydrogen passivation in existing technologies.

[0045] Phase 5, Stepped Cooling and Stress Release Phase: Cooling is performed in a stepped manner to 300-400℃. This stepped cooling refers to cooling to the first temperature step at a certain rate, holding at that temperature for a certain time, then continuing to cool to the next temperature step and holding, and so on until the target temperature is reached. The cooling rate in this phase is 1-4℃ / s, with each step held for 5-10 minutes, and 3-5 cooling steps in total. Protective gas is continuously introduced during the cooling process at a flow rate of 10-30 slm. The design of multiple cooling steps and holding platforms allows for the gradual and uniform release of stress within the silicon wafer, significantly reducing microcracks and warping caused by thermal stress. The holding platform after each cooling step provides sufficient time for stress release, avoiding thermal shock damage caused by rapid cooling.

[0046] Step S7: Remove the phosphorus-doped polysilicon layer and tunnel oxide layer around the front and edges of the silicon wafer. During the annealing process described above, a small amount of phosphorus-doped polysilicon layer and tunneling oxide layer may remain on the front side and edges of the silicon wafer, affecting the performance of the front emitter. These are removed using methods such as alkaline etching or plasma etching to ensure that the PN junction characteristics of the battery remain unaffected.

[0047] Step S8: Deposit a front passivation anti-reflection layer on the front side of the silicon wafer. A front passivation antireflection layer is deposited on the front side of the silicon wafer. The front passivation antireflection layer preferably comprises a stacked structure of an alumina layer and a silicon nitride layer. First, an alumina layer is deposited using ALD (Atomic Layer Deposition) with a thickness of 3-15 nm, preferably 5-12 nm; then, a silicon nitride layer is deposited using PECVD with a thickness of 60-90 nm, preferably 65-80 nm. The alumina layer exhibits excellent field-effect passivation performance, effectively reducing the recombination rate on the front surface; the silicon nitride layer combines passivation and antireflection functions, improving light incidentness.

[0048] Step S9: Deposit a back passivation layer on the back side of the silicon wafer. A back passivation layer is deposited on the back side of the silicon wafer using PECVD. The back passivation layer is a silicon nitride layer or a silicon oxynitride layer, with a thickness of 80-150 nm, preferably 100-130 nm. The back passivation layer further protects the passivation contact structure on the back side and also serves to reduce reflection.

[0049] Step S10: Metallize the front and back sides of the silicon wafer to form electrodes. Silver paste is printed on the front side of the silicon wafer using screen printing to form the front gate electrodes; silver paste and aluminum paste are printed on the back side of the silicon wafer to form the back electrodes. The electrodes are used to collect and conduct photocurrent.

[0050] Step S11: Perform sintering treatment The metallized silicon wafers are sintered to ensure good ohmic contact between the metal paste and the silicon wafer. The peak sintering temperature is 750-950℃, preferably 780-850℃; the sintering time is 30-90 seconds. After sintering, the wafers are allowed to cool naturally to obtain the finished TOPCon battery.

[0051] Example 1 In one specific embodiment, the method for preparing the TOPCon battery includes the following steps S1-S11: Step S1: Select an N-type single-crystal silicon wafer substrate with a resistivity of 1.0 Ω·cm and a thickness of 140 μm, and perform double-sided texturing and cleaning. After texturing, a pyramid-shaped textured surface is formed on the silicon wafer surface, with a reflectivity of 8%.

[0052] Step S2: Boron diffusion is performed on the front side of the silicon wafer: BCl3 is used as the boron source, the diffusion temperature is 1000℃, the diffusion time is 2 hours, the diffusion sheet resistance is 160Ω / □, and the junction depth is 0.8μm.

[0053] Step S3: Use acid washing to remove the boron diffusion layer and borosilicate glass layer on the back and sides of the silicon wafer.

[0054] Step S4: A tunneling oxide layer and an intrinsic polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer using the LPCVD method. The tunneling oxide layer is SiO2 with a thickness of 1.5 nm; the intrinsic polycrystalline silicon layer has a thickness of 120 nm.

[0055] Step S5: Phosphorus doping of the intrinsic polycrystalline silicon layer is performed using ion implantation, with a phosphorus doping concentration of 2.5 × 10⁻⁶. 20 cm -3 .

[0056] Step S6: Annealing is performed using a high-temperature multi-field coupling annealing process. Stage 1, Heating and Pre-oxidation Stage: Place the silicon wafer in an annealing furnace and heat it to 650°C at a heating rate of 3°C / s under an oxygen-containing atmosphere (oxygen flow rate 2 slm, nitrogen flow rate 5 slm), and hold it at that temperature for 3 minutes. Phase 2, Electric Field Assisted Step-by-Step Heating Phase: A DC electric field is applied to both sides of the silicon wafer, with the direction of the electric field perpendicular to the surface of the silicon wafer. The electric field strength is 10V / cm in the 600-700℃ range, 25V / cm in the 700-800℃ range, and 40V / cm in the 800-850℃ range. The temperature is increased to 830℃ in steps at a heating rate of 2℃ / s, with each step held for 5 minutes. There are 3 heating steps in total. Phase 3, High-temperature steady-state annealing phase: In the temperature range of 830℃, alternating oxygen atmosphere treatment (oxygen flow rate 3 slm, nitrogen flow rate 12 slm, treatment time 60 seconds) and protective atmosphere treatment (nitrogen flow rate 15 slm, treatment time 3 minutes) are performed for a total of 3 cycles. Stage 4, Temperature-Variable Electric Field Control Stage: When the temperature drops to 780℃, a pulsed electric field is applied with a pulse frequency of 200Hz, an electric field strength of 50V / cm, a pulse duty cycle of 50%, a square wave pulse waveform, a nitrogen atmosphere inside the furnace, and a processing time of 10 minutes. Phase 5, Stepped Cooling and Stress Release Phase: The temperature is gradually reduced to 350℃ at a cooling rate of 2.5℃ / s. The cooling steps are: 830℃ → 700℃ (hold for 6 minutes) → 700℃ → 550℃ (hold for 7 minutes) → 550℃ → 400℃ (hold for 8 minutes) → 400℃ → 350℃ (hold for 5 minutes). Nitrogen gas is continuously introduced as a protective gas during the cooling process, with a gas flow rate of 20slm.

[0057] Step S7: Remove the phosphorus-doped polysilicon layer and tunnel oxide layer on the front and edge of the silicon wafer using an alkaline etching method.

[0058] Step S8: Deposit a front passivation anti-reflection layer on the front side of the silicon wafer: First, deposit an aluminum oxide layer with a thickness of 10 nm using the ALD method; then deposit a silicon nitride layer with a thickness of 75 nm using the PECVD method.

[0059] Step S9: Deposit a silicon nitride layer as a back passivation layer on the back of the silicon wafer using the PECVD method, with a thickness of 120nm.

[0060] Step S10: Silver paste and aluminum paste are printed on the front and back sides of the silicon wafer using a screen printing method to form electrode grid lines.

[0061] Step S11: Perform sintering treatment. The peak sintering temperature is 780℃ and the sintering time is 60 seconds. After cooling, the finished TOPCon battery is obtained.

[0062] Example 2 In a more specific embodiment, this embodiment is basically the same as Embodiment 1, except that the annealing process parameters in step S6 are different: Stage 1, Heating and Pre-oxidation Stage: Heating to 680℃ at a rate of 4℃ / s and holding for 4 minutes; Stage 2, electric field-assisted stepped heating stage: electric field strengths of 15V / cm, 30V / cm, and 45V / cm, respectively, heating up to 850℃ at a rate of 1.5℃ / s, with 4 heating steps; Stage 3, High-temperature steady-state annealing stage: In the temperature range of 850℃, the oxygen atmosphere treatment time is 45 seconds, the protective atmosphere treatment time is 4 minutes, and the cycle is repeated twice. Stage 4, Temperature-Variable Electric Field Control Stage: When the temperature drops to 770℃, a pulsed electric field is applied with a pulse frequency of 300Hz, an electric field strength of 80V / cm, a pulse duty cycle of 40%, and a processing time of 8 minutes. Stage 5, Stepped cooling and stress release stage: The cooling rate is 3℃ / s, and the number of cooling steps is 4.

[0063] Comparative Example 1 In a specific comparative example, this comparative example is basically the same as Example 1, except that step S6 adopts a conventional constant temperature annealing process: under a nitrogen atmosphere, the temperature is 820°C, the temperature is held for 30 minutes, and natural cooling is adopted.

[0064] Comparative Example 2 In a more specific comparative example, this comparative example is basically the same as Example 1, except that step S6 adopts multi-stage variable temperature annealing but does not apply electric field regulation, and only performs step-by-step temperature field control.

[0065] Test Example 1 This test example focuses on the electrical performance testing of TOPCon batteries prepared in Examples 1 and 2, as well as Comparative Examples 1 and 2. The test results are shown in Table 1 below: Table 1 Test Result Comparison Table The test results show that Examples 1 and 2, employing the multi-field coupling annealing process of this invention, significantly outperform the comparative examples in terms of open-circuit voltage, fill factor, and conversion efficiency, while also substantially reducing the microcrack rate. Specifically, Example 1 achieved a conversion efficiency of 27.22%, an increase of 0.05 percentage points compared to Comparative Example 1; the microcrack rate of Example 1 was 0.25%, a reduction of approximately 71% compared to 0.87% in Comparative Example 1 and approximately 54% compared to 0.54% in Comparative Example 2. This indicates that the synergistic control of temperature, electric, and atmospheric fields can effectively improve battery performance and product yield.

[0066] Test Example 2 In this test example, the solar cells prepared in Example 1 and Comparative Examples 1-2 were subjected to light injection treatment (light intensity 1000W / m²). 2 The temperature was 60℃ for 24 hours, and then the cells were stored in a dark room for 72 hours. The change in conversion efficiency before and after storage was tested, and the results are shown in Table 2 below. Table 2 Comparison of Changes in Exchange Efficiency Test results show that the efficiency degradation of the solar cell prepared using the process of this invention is only 0.03 percentage points after dark storage, which is much lower than 0.14 percentage points for Comparative Example 1 and 0.09 percentage points for Comparative Example 2. This indicates that the pulsed electric field applied during the temperature-controlled electric field stage effectively promotes the uniform distribution and stable bonding of hydrogen atoms, significantly improves the stability of hydrogen passivation, and solves the problem of instability of hydrogen passivation in the light-dark storage cycle in the prior art. The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A high-temperature multi-field coupled annealing process, characterized in that, This includes the following stages performed sequentially: Heating and pre-oxidation stage: The silicon wafer is placed in an annealing furnace and heated to a first preset temperature at a first preset heating rate in an oxygen-containing atmosphere, and held at the temperature for a first preset time to form an oxide protective layer on the surface of the silicon wafer. High-temperature steady-state annealing stage: Within the second preset temperature range, oxygen-containing atmosphere treatment and protective atmosphere treatment are alternately performed to repair lattice damage through alternating atmospheres; Step-down cooling and stress release stage: The temperature is gradually reduced to the fourth preset temperature at the first preset cooling rate, and then held at each temperature step for the fourth preset time. Protective gas is introduced to gradually release the stress inside the silicon wafer.

2. The high-temperature multi-field coupled annealing process method according to claim 1, characterized in that, The first preset heating rate is 2-5℃ / s, the first preset temperature is 600-700℃, the first preset time is 2-5min, and the thickness of the formed oxide protective layer is 1-3nm.

3. The high-temperature multi-field coupled annealing process method according to claim 1, characterized in that, Between the heating and pre-oxidation stage and the high-temperature steady-state annealing stage, an electric field-assisted stepped heating stage is also provided: A DC electric field is applied to both sides of the silicon wafer, and the temperature is increased to a second preset temperature in steps at a second preset heating rate. The temperature is held at each temperature step for a second preset time, so as to use the electric field force to promote the directional migration of doped atoms and activate doped atoms with different activation energies in sequence.

4. The high-temperature multi-field coupled annealing process method according to claim 3, characterized in that, The second preset heating rate is 1-3℃ / s, the number of heating steps is 2-4, the holding time for each step is 3-8min, and the second preset temperature is 800-850℃.

5. The high-temperature multi-field coupled annealing process method according to claim 4, characterized in that, During the electric field-assisted stepped heating stage, the applied DC electric field is perpendicular to the silicon wafer surface, and the electric field strength increases gradually with the temperature step. The electric field strength is 5-20 V / cm in the 600-700℃ temperature range, 20-35 V / cm in the 700-800℃ temperature range, and 35-50 V / cm in the 800-850℃ temperature range.

6. The high-temperature multi-field coupled annealing process method according to claim 1, characterized in that, The oxygen-containing atmosphere is a mixture of oxygen and a protective gas; wherein the oxygen volume fraction is 5%-20%, the oxygen flow rate is 1-5 slm, and the treatment time for each oxygen-containing atmosphere is 30-90 seconds. The protective gas flow rate for the protective atmosphere treatment is 10-30 slm, and the duration of each protective atmosphere treatment is 2-5 minutes; the oxygen atmosphere treatment is performed first, followed by the protective atmosphere treatment, and a total of 2-4 cycles are performed. The protective gas includes nitrogen and / or argon, and the furnace atmosphere composed of the protective gas is the protective atmosphere.

7. The high-temperature multi-field coupled annealing process method according to claim 1, characterized in that, Between the high-temperature steady-state annealing stage and the stepped cooling and stress release stage, a variable-temperature electric field control stage is also provided: During the cooling process, a pulsed electric field is applied within a third preset temperature range for a third preset time, so as to promote the redistribution and bonding of hydrogen atoms using the pulsed electric field.

8. The high-temperature multi-field coupled annealing process method according to claim 7, characterized in that, During the variable temperature electric field control stage, the parameters of the applied pulsed electric field are as follows: pulse frequency is 50-500Hz, electric field strength is 10-100V / cm, pulse duty cycle is 30%-70%, and pulse waveform is square wave or sine wave; the third preset temperature range is 750-800℃, the third preset time is 5-15min, and the atmosphere inside the furnace is maintained as a protective atmosphere when the pulsed electric field is applied.

9. The high-temperature multi-field coupled annealing process method according to claim 1, characterized in that, In the stepped cooling and stress release stage, the first preset cooling rate is 1-4℃ / s, the number of cooling steps is 3-5, the holding time for each step is 5-10min, the fourth preset temperature is 300-400℃, and the gas flow rate of the protective gas is 10-30slm.

10. A method for preparing a TOPCon battery, characterized in that, The silicon wafer is annealed using a high-temperature multi-field coupling annealing process method as described in any one of claims 1-8.

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