Back contact cell and method of making same, stacked cell, photovoltaic module

Abstract

The application relates to the photovoltaic field and provides a back contact cell, a preparation method of the back contact cell, a laminated cell and a photovoltaic module, and at least the performance of the back contact cell can be improved. The preparation method of the back contact cell comprises the following steps: obtaining a substrate, the substrate comprises a first surface, a second surface and a third surface connecting the first surface and the second surface, the first surface comprises a preset area, and the second surface comprises a first area and a second area; a first doped layer is formed on the second surface, the third surface and the preset area; a first mask layer is formed on the surface of the first doped layer; a second mask layer is formed on the surface of the first mask layer on the second surface and the third surface; a first wet process is performed to remove the first mask layer on the preset area; the second mask layer, the first mask layer and the first doped layer on the second area are removed; a texturing process is performed to remove the first doped layer on the preset area and form a textured structure on the first surface and the second area; and a first passivation layer is formed.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a back contact battery and its preparation method, a tandem battery, and a photovoltaic module. Background Technology

[0002] As fossil fuels are gradually depleted, solar energy is becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts sunlight into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy.

[0003] Back-contact solar cells are a type of solar cell where all the grid lines are located on the back of the cell. Because there are no metal grid electrodes obstructing the front of the cell, back-contact solar cells have increased light absorption efficiency, significantly improving short-circuit current and effectively increasing conversion efficiency, making them a promising technology for future development. Summary of the Invention

[0004] This application provides a back contact battery and its preparation method, a tandem battery, and a photovoltaic module, which at least helps to improve the performance of the back contact battery.

[0005] This application provides a method for fabricating a back-contact battery. The method includes: obtaining a substrate, the substrate including a first surface, a second surface, and a third surface connecting the first surface and the second surface, the first surface including a predetermined region adjacent to the third surface, and the second surface including a first region and a second region; forming a first doped layer located on the second surface, the third surface, and the predetermined region; forming a first mask layer located on the surface of the first doped layer; forming a second mask layer located on the surface of the first mask layer on the second surface and the third surface; performing a first wet process to remove the first mask layer located in the predetermined region; removing the second mask layer, the first mask layer, and the first doped layer in the second region; performing a texturing process to remove the first doped layer in the predetermined region and form a textured structure on the first surface and the second region; forming a first passivation layer located on the first surface and on the side of the first doped layer on the third surface away from the substrate, the material of the first passivation layer including amorphous silicon.

[0006] Optionally, when forming the first doped layer, the method for preparing the back contact battery further includes: forming a plating portion, the plating portion being located on the first surface; wherein, the first wet process is further used to remove the plating portion.

[0007] Optionally, the thickness of the first passivation layer is 3nm to 30nm.

[0008] Optionally, the material of the first mask layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide; the material of the second mask layer includes amorphous silicon.

[0009] Optionally, the thickness of the first mask layer is 20nm~60nm; the thickness of the second mask layer is 7nm~15nm.

[0010] Optionally, the texturing process is further used to remove the second mask layer; after the texturing process and before the formation of the first passivation layer, the method for preparing the back contact battery further includes: performing a second wet process to remove the first mask layer.

[0011] Optionally, after forming the first passivation layer, the method for preparing the back contact battery further includes: forming a second passivation layer, wherein the second passivation layer is located on the surface of the first passivation layer on the first surface and the third surface that is away from the substrate.

[0012] Optionally, the process temperature for forming the second passivation layer is 170℃~250℃; the process pressure for forming the second passivation layer is 50Pa~200Pa.

[0013] Optionally, after forming the second passivation layer, the method for fabricating the back contact battery further includes: forming a second doped layer, the second doped layer being at least located on the second region; forming a first electrode and a second electrode, the first electrode being electrically connected to the first doped layer, and the second electrode being electrically connected to the second doped layer.

[0014] Optionally, obtaining the substrate includes: obtaining an initial substrate; performing a cutting process to cut the initial substrate into at least two substrates.

[0015] This application also provides a back contact battery. The back contact battery is fabricated using any of the back contact battery fabrication methods described above. The back contact battery includes a substrate, the substrate including a first surface, a second surface, and a third surface connecting the first surface and the second surface, the second surface including a first region and a second region; a first doped layer located on the second surface and the third surface; a first passivation layer located on the first surface, and on the side of the third surface where the first doped layer faces away from the substrate, the material of the first passivation layer including amorphous silicon; wherein the second region of the first surface and the second surface has a textured structure.

[0016] This application also provides a tandem solar cell. The tandem solar cell includes: a crystalline silicon bottom cell, which is a back contact cell prepared by any of the above-described back contact cell preparation methods, or a back contact cell prepared by any of the above-described methods; and a perovskite top cell, which is located on one side of the bottom cell.

[0017] This application also provides a photovoltaic module. The photovoltaic module includes: a battery string, which is formed by connecting multiple back-contact batteries prepared by any of the above-described back-contact battery preparation methods, or by connecting multiple back-contact batteries prepared by any of the above-described methods, or by connecting multiple stacked batteries prepared by any of the above-described methods; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer opposite to the battery string.

[0018] The technical solution provided in this application has at least the following advantages: In the back contact battery fabrication method provided in this application, a first mask layer is formed on the surface of the first doped layer, and a second mask layer is formed on the surface of the first mask layer on the second and third surfaces. A first wet process is used to remove the first mask layer in a predetermined area to ensure that the first doped layer in the predetermined area can be removed during the subsequent texturing process, and a textured structure can be formed in the predetermined area. When the first mask layer in the predetermined area is removed by the first wet process, the presence of the second mask layer can protect the first doped layer and the first mask layer on the third and second surfaces from being etched. During the texturing process, the first mask layer on the surface of the first doped layer can protect the first doped layer from being etched and ensure that no textured structure is formed on the third surface. This helps to avoid damage to the third surface caused by the texturing process and improves the performance of the back contact battery. Furthermore, the first doped layer remaining on the third surface can be used to passivate the third surface, which also helps to improve the performance of the back contact battery.

[0019] Furthermore, since the first doped layer in the preset region and the second region is not protected by the first mask layer, the first doped layer in the preset region and the second region will be removed. This allows for the formation of a textured structure in the first surface and the second region, which can improve the light utilization rate of the first surface and the second region, thus improving the performance of the back contact battery. A first passivation layer is formed on the side of the first doped layer on the first surface and the third surface that is away from the substrate. The material of the first passivation layer includes amorphous silicon. The first passivation layer can passivate the substrate, which also helps to improve the performance of the back contact battery. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating a method for preparing a back contact battery according to an embodiment of this application; Figure 2 A schematic diagram of a substrate obtained in the preparation method of the back contact battery provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure after the first doped layer is formed in the preparation method of the back contact battery provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure after the first mask layer is formed in the method for preparing the back contact battery provided in the embodiments of this application; Figure 5 This is a schematic diagram of a structure after the second mask layer is formed in the method for preparing a back contact battery according to an embodiment of this application; Figure 6 A schematic diagram of the structure after the first wet process in the preparation method of the back contact battery provided in the embodiments of this application; Figure 7 This is a schematic diagram of a structure after removing the second mask layer, the first mask layer, and the first doped layer in the second region in the fabrication method of the back contact battery provided in the embodiments of this application; Figure 8 This is a schematic diagram of a structure after texturing in the preparation method of the back contact battery provided in the embodiments of this application; Figure 9 A schematic diagram of the structure after the second wet process in the preparation method of the back contact battery provided in the embodiments of this application; Figure 10 This is a schematic diagram of a structure after the formation of the first passivation layer in the preparation method of the back contact battery provided in the embodiments of this application; Figure 11 This is a schematic diagram of a structure after the formation of the second passivation layer in the preparation method of the back contact battery provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure after the formation of the second doped layer in the fabrication method of the back contact battery provided in the embodiments of this application; Figure 13This is a schematic diagram of the structure after the formation of the first electrode and the second electrode in the method for preparing the back contact battery provided in the embodiments of this application; Figure 14 This is a schematic diagram of a stacked battery provided in an embodiment of this application; Figure 15 This is a schematic diagram of another structure of the stacked battery provided in an embodiment of this application; Figure 16 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures: 10. Substrate; 101. First surface; 102. Second surface; 103. Third surface; 104. Preset area; 105. First region; 106. Second region; 11. First doped layer; 111. Doped silicon glass layer; 12. First mask layer; 13. Second mask layer; 14. First passivation layer; 15. Second passivation layer; 16. Second doped layer; 17. First electrode; 18. Second electrode; 19. Interface passivation layer; 20. First conductive layer; 21. Second conductive layer; 30. Crystalline silicon bottom cell; 31. Perovskite top cell; 311. First transport layer; 312. Perovskite functional layer; 313. Second transport layer; 314. Transparent conductive layer; 315. Anti-reflective layer; 40. Back contact cell; 41. Encapsulation layer; 42. Cover plate; 421. First cover plate; 422. Second cover plate; 43. Solder ribbon. Detailed Implementation

[0023] The fabrication method of a back contact battery in related technologies includes: providing a substrate, the substrate including a first surface, a second surface, and a third surface connecting the first surface and the second surface, the second surface including a first region and a second region; forming a first doped layer, the first doped layer being located on the second surface, the third surface, and a portion of the first surface, typically employing a texturing operation to form a textured structure on the first surface and the second region; wherein, the texturing solution in the texturing operation can remove the first doped layer in the corresponding region and form a textured structure on the substrate surface. In the fabrication method of related technologies, when performing the texturing operation on the first surface and the second region, the first doped layer on the third surface is simultaneously removed, and a textured structure is formed on the third surface, which can damage the third surface and affect the performance of the back contact battery. In addition, after the first doped layer on the third surface is removed, the third surface loses the first doped layer and undergoes passivation, which also has a negative impact on the back contact battery.

[0024] Therefore, the performance of back-contact batteries in related technologies needs to be improved.

[0025] Therefore, this application provides a back contact battery and its fabrication method, a tandem battery, and a photovoltaic module. In the fabrication method of the back contact battery, when the first mask layer in the preset area is removed by a first wet process, the presence of a second mask layer protects the first doped layer and the first mask layer on the third and second surfaces from etching. During the texturing process, the first mask layer protects the first doped layer from etching and ensures that no textured structure forms on the third surface, thus avoiding damage to the third surface during texturing and improving the performance of the back contact battery. Furthermore, the first doped layer remaining on the third surface can be used to passivate the third surface, which also helps improve the performance of the back contact battery. Forming a textured structure on the first and second surfaces improves the light utilization rate of the first and second surfaces, which is beneficial to improving the performance of the back contact battery. The first passivation layer can passivate the substrate, which also helps improve the performance of the back contact battery.

[0026] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0029] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may cover both above and below orientation depending on the context in which the term is used, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0030] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0031] In the description of the embodiments of this application, "electrically connected to one component" means that both components are made of conductive materials, and the two components are in direct contact and connected or connected via other conductive materials. When the photovoltaic module is generating electricity, current flows between the two components. "Electrically contacting one component to another" means that the two components are not only in contact, but also, because both components are made of conductive materials, current flows between the two components when the photovoltaic module is generating electricity.

[0032] In the description of embodiments of this application, the terms "about," "approximately," "roughly," or "about" for a numerical value referring to a specific parameter include the numerical value, and those skilled in the art will understand that the deviation from the numerical value is within the acceptable tolerance of the specific parameter. For example, "about" or "about" for a numerical value may include additional numerical values ​​that are in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0033] In the accompanying drawings corresponding to the embodiments of this application, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0034] In the description of embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when describing a component on the surface of another component, or a component "directly" on another component, or a component surface on which another component is formed or disposed, it indicates that there is no intermediate component between the two components. For simplicity and clarity, various components may be drawn at any scale. In the drawings, some components may be omitted for simplicity.

[0035] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "the component" is also intended to include the plural form unless the context clearly indicates otherwise.

[0036] The “components” mentioned above can refer to layers, membranes, regions, parts, plates, or structures, etc.

[0037] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0038] Figure 1 This is a flowchart illustrating a method for preparing a back contact battery according to an embodiment of this application. Figure 2 This is a schematic diagram of a substrate obtained in the fabrication method of the back contact battery provided in this application embodiment. Figure 3 This is a schematic diagram of the structure after the formation of the first doped layer in the fabrication method of the back contact battery provided in the embodiments of this application. Figure 4 This is a schematic diagram of the structure after the first mask layer is formed in the fabrication method of the back contact battery provided in this application embodiment. Figure 5 This is a schematic diagram of the structure after the second mask layer is formed in the method for fabricating a back contact battery according to an embodiment of this application. Figure 6 This is a schematic diagram of the structure after the first wet process in the preparation method of the back contact battery provided in the embodiments of this application. Figure 7 This is a schematic diagram of a structure after removing the second mask layer, the first mask layer, and the first doped layer in the second region in the fabrication method of the back contact battery provided in this application embodiment. Figure 8 This is a schematic diagram of the structure after the texturing process in the preparation method of the back contact battery provided in the embodiments of this application. Figure 9 This is a schematic diagram of a structure after the second wet process in the preparation method of the back contact battery provided in the embodiments of this application. Figure 10 This is a schematic diagram of the structure after the first passivation layer is formed in the preparation method of the back contact battery provided in the embodiments of this application.

[0039] refer to Figures 1 to 10 The preparation method of the back contact battery includes at least the following steps: Step S1: Obtain a substrate 10. The substrate 10 includes a first surface 101, a second surface 102, and a third surface 103 connecting the first surface 101 and the second surface 102. The first surface 101 includes a preset area 104 adjacent to the third surface 103. The second surface 102 includes a first area 105 and a second area 106.

[0040] Step S2: Form a first doped layer 11, which is located on the second surface 102, the third surface 103 and the preset region 104.

[0041] Step S3: Form a first mask layer 12, which is located on the surface of the first doped layer 11.

[0042] Step S4: Form a second mask layer 13, which is located on the surface of the first mask layer 12 on the second surface 102 and the third surface 103.

[0043] Step S5: Perform the first wet process to remove the first mask layer 12 located in the preset area 104.

[0044] Step S6: Remove the second mask layer 13, the first mask layer 12 and the first doped layer 11 from the second region 106.

[0045] Step S7: Perform a texturing process to remove the first doped layer 11 of the preset area 104 and form a textured structure on the first surface 101 and the second area 106.

[0046] Step S8: Form a first passivation layer 14, which is located on the first surface 101 and the side of the first doped layer 11 on the third surface 103 away from the substrate 10. The material of the first passivation layer 14 includes amorphous silicon.

[0047] The manufacturing method of the back contact battery provided in the embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0048] refer to Figure 2 The substrate 10 is used to receive light and generate photogenerated carriers. In some embodiments, the substrate 10 may be a semiconductor substrate 10.

[0049] In some embodiments, the material of the substrate 10 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, and microcrystalline silicon.

[0050] In some embodiments, the substrate 10 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc.

[0051] The substrate 10 can also be a sapphire substrate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0052] The substrate 10 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0053] The substrate 10 includes a first surface 101 and a second surface 102 facing each other. In some embodiments, the back-contact cell used in a single-glass photovoltaic module is considered a single-sided cell, in which case the first surface 101 can serve as a light-receiving surface for receiving sunlight, and the second surface 102 serves as a back-lighting surface. In some embodiments, the back-contact cell used in a double-glass module or a bifacial module is considered a bifacial cell, in which case both the first surface 101 and the second surface 102 can serve as light-receiving surfaces and can both be used to receive sunlight. It is understood that the back-lighting surface referred to in the embodiments of this application can also receive sunlight, but the degree of sunlight reception is weaker than that of the light-receiving surface, and therefore it is defined as a back-lighting surface.

[0054] The first surface 101 has a preset area 104 adjacent to the third surface 103. The preset area 104 is also the edge area of ​​the first surface 101.

[0055] refer to Figure 2 and Figure 3 It should be noted that the preset area 104 is defined artificially. After the first doped layer 11 is formed in step S2, the area where the first doped layer 11 is located on the first surface 101 does not have the preset area 104 in the back contact battery obtained in actual production.

[0056] In some embodiments, the second surface 102 includes a first region 105 and a second region 106.

[0057] refer to Figure 2 and Figure 8 It should be noted that zone 105 is the area on the second surface 102 that has not undergone the flocking process, and zone 106 is the area on the second surface 102 that has undergone the flocking process. Zones 105 and 106 are artificially divided areas. In reality, there is no clear dividing line between zone 105 and zone 106. Furthermore, Figures 2 to 10 The second side 102 is only shown to include two first zones 105 and two second zones 106. In fact, the number of first zones 105 and second zones 106 can be adjusted according to actual needs. This application does not limit the number of first zones 105 and second zones 106.

[0058] Continue to refer to Figure 2In some embodiments, obtaining the substrate 10 includes: obtaining an initial substrate (not shown); and performing a dicing process to cut the initial substrate into at least two substrates 10. Compared to the approach of first forming a first doped layer, a first passivation layer, and other films on the initial substrate and then dicing (referred to as post-dicing), this application adopts the method of first dicing the initial substrate to obtain the substrate 10, and then forming a first doped layer 11 and a first passivation layer 14, etc., on the substrate 10. This ensures that the first doped layer 11 and other films are present on the diced surface for passivation, which can save the step of forming a passivation layer on the diced surface after post-dicing, and is beneficial to improving the fabrication efficiency of the back contact battery.

[0059] refer to Figure 3 The first doped layer 11 has N-type doping elements or P-type doping elements.

[0060] The material of the first doped layer 11 may include doped polycrystalline silicon, doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon. For example, the first doped layer 11 may be doped polycrystalline silicon with an N-type dopant element.

[0061] In some embodiments, the method for forming the first doped layer 11 may include forming an intrinsic layer by chemical vapor deposition, the intrinsic layer being located on the second surface 102, the third surface 103, and the predetermined region 104; followed by a high-temperature doping process to form the first doped layer 11. The high-temperature doping process typically involves a high process temperature (greater than 300°C), causing some material in the intrinsic layer to diffuse outwards from the predetermined region 104 of the first surface 101 during the doping process, forming a wraparound portion.

[0062] refer to Figure 3 and Figure 4 In some embodiments, when forming the first doped layer 11, a doped silicon glass layer 111 is also formed on the surface of the first doped layer 11. The first mask layer 12 formed in step S3 is located on the surface of the doped silicon glass layer 111 facing away from the first doped layer 11, that is, the doped silicon glass layer 111 is located between the first mask layer 12 and the first doped layer 11. In other embodiments, when forming the first doped layer, a doped silicon glass layer may not be formed on the surface of the first doped layer.

[0063] The doping elements in the silicon glass layer 111 are the same as those in the first doped layer 11.

[0064] In some cases, the first doped layer 11 contains an N-type dopant element, and the material of the doped silicon glass layer 111 includes PSG (Phosphosilicate Glass). In other cases, the first doped layer 11 contains a P-type dopant element, and the material of the doped silicon glass layer 111 includes BSG (Borosilicate Glass).

[0065] refer to Figures 4 to 8 The method for fabricating a back contact battery includes forming a first mask layer 12. The first mask layer 12 is used to protect the first doped layer 11 from being etched during the texturing process and to protect the third surface 103 from damage, thereby improving the performance of the back contact battery. Furthermore, the first doped layer 11 retained on the third surface 103 can be used to passivate the third surface 103, which also helps to improve the performance of the back contact battery.

[0066] In some embodiments, the material of the first mask layer 12 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. Thus, the first mask layer 12 can protect the first doped layer 11 of the third surface 103 from damage by the texturing solution during the texturing process, thereby preventing the formation of a textured structure on the third surface 103 and protecting the third surface 103. Furthermore, the first doped layer 11 retained on the third surface 103 can be used to passivate the third surface 103, which also helps improve the performance of the back contact battery.

[0067] In some embodiments, the thickness of the first mask layer 12 can be 20nm to 60nm, for example, 20nm to 30nm, 30nm to 40nm, 40nm to 50nm, or 50nm to 60nm. For example, the thickness of the first mask layer 12 can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, or 60nm. A thickness within the above range can provide sufficient protection for the first doped layer 11 during the texturing process, preventing damage to the first doped layer 11 under the first mask layer 12.

[0068] The first mask layer 12 can be formed by chemical vapor deposition. For example, a tubular chemical vapor deposition apparatus or a plate chemical vapor deposition apparatus can be used to form the first mask layer 12.

[0069] refer to Figures 5 to 8 The method for fabricating a back contact battery includes forming a second mask layer 13. The second mask layer 13 is used to protect the first mask layer 12 from being removed by the etching solution of the first wet process during the first wet process.

[0070] In some embodiments, the material of the second mask layer 13 may include amorphous silicon. In other embodiments, the material of the second mask layer 13 may include microcrystalline silicon or polycrystalline silicon. Thus, the second mask layer 13 can protect the first mask layer 12 from being removed by the etching solution of the first wet process.

[0071] The second mask layer 13 can be formed by chemical vapor deposition. Specifically, a plate-type chemical vapor deposition apparatus can be used to form the second mask layer 13.

[0072] In some embodiments, the thickness of the second mask layer 13 can be 7nm to 15nm, for example 7nm to 9nm, 9nm to 11nm, 11nm to 13nm, or 13nm to 15nm. The thickness of the second mask layer 13 within the above range can provide sufficient protection for the first mask layer 12 during the first wet process, preventing damage to the first mask layer 12 beneath the second mask layer 13.

[0073] refer to Figures 6 to 8 In some embodiments, the method for fabricating the back contact battery includes performing a first wet process to remove the first mask layer 12 located in the preset region 104. This is to avoid the presence of the first mask layer 12 in the preset region 104 preventing the formation of a textured structure in the preset region 104 during the texturing process, thereby ensuring the consistency of the textured structure of the first surface 101.

[0074] In some embodiments, when forming the first doped layer 11, the method for fabricating the back contact cell further includes: forming a plating portion (not shown), the plating portion being located on the first surface 101; wherein, a first wet process is further used to remove the plating portion. This avoids affecting the consistency of the texture structure of the first surface 101 due to the presence of the plating portion. That is, removing the plating portion through the first wet process helps improve the consistency of the texture structure of the first surface 101, thereby improving the consistency of the quality of the subsequent film deposited on the first surface 101, and consequently improving the aesthetic appearance of the back contact cell.

[0075] In some embodiments, the first doped layer 11 is formed by a high-temperature doping process, which forms a plating portion on the first surface 101. The plating portion is located on the first surface 101 and is adjacent to the first doped layer 11 in the preset region 104.

[0076] The material of the coating includes at least one of silicon oxide, doped silicon glass, or crystalline silicon.

[0077] When removing the first mask layer 12 of the preset region 104, the first mask layer 12 at the corner between the preset region 104 and the third surface 103 is also removed. In some cases, there is a doped silicon glass layer 111 between the first mask layer 12 and the first doped layer 11, and the doped silicon glass layer 111 of the preset region 104 is also removed when removing the first mask layer 12 of the preset region 104.

[0078] In some embodiments, the etching solution used in the first wet process is an acidic solution. For example, the material of the etching solution in the first wet process may include hydrofluoric acid, with a concentration of 15% to 50%, such as 15% to 25%, 25% to 35%, or 35% to 50%. Optionally, the concentration of hydrofluoric acid may be 15%, 20%, 25%, 30%, 35%, 42.5%, or 50%.

[0079] In some embodiments, the process temperature of the first wet process can be 10°C to 40°C, for example, 10°C to 20°C, 20°C to 30°C, or 30°C to 40°C. Optionally, the process temperature of the first wet process can be 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, or 40°C.

[0080] The process time of the first wet process can be 1 min to 5 min, for example, 1 min to 2 min, 2 min to 3 min, 3 min to 4 min, or 4 min to 5 min. Optionally, the process time of the first wet process can be 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, 4 min, 4.5 min, or 5 min.

[0081] refer to Figures 6 to 8 The fabrication method of the back contact battery also includes removing the second mask layer 13, the first mask layer 12, and the first doped layer 11 from the second region 106. This allows the subsequent texturing process to form a textured structure in the second region 106, thereby improving the light utilization rate of the second region 106 and enhancing the performance of the back contact battery.

[0082] The method for removing the second mask layer 13, the first mask layer 12 and the first doped layer 11 of the second region 106 can be a laser etching process.

[0083] In some embodiments, a doped silicon glass layer 111 is provided between the first doped layer 11 and the first mask layer 12. When removing the mask layer, the first mask layer 12 and the first doped layer 11 of the second region 106, the doped silicon glass layer 111 of the second region 106 is also removed.

[0084] refer to Figure 8The method for preparing the back contact battery includes performing a texturing process to remove the first doped layer 11 of the preset region 104 and to form a textured structure on the first surface 101 and the second region 106.

[0085] In some embodiments, the texturing solution used in the texturing process is an alkaline solution (such as a solution containing sodium hydroxide or potassium hydroxide), which can remove the first doped layer 11 of the preset region 104 and form a textured structure.

[0086] In some embodiments, the texture structure includes a velvety structure (such as a pyramid structure), a topographic structure composed of grooves and protrusions, or other topographic structures different from the flat surface. The texture structure can increase the internal reflection of incident light, so that the incident light is reflected multiple times in the texture structure and finally absorbed by the substrate 10, thereby improving the photoelectric conversion efficiency.

[0087] In some embodiments, the texturing process includes a first texturing step and a second texturing step. In the first texturing step, the alkali concentration of the texturing solution can be 1.8% to 2.7%, the process temperature can be 73°C to 79°C, and the process duration is 550s to 600s. In the second texturing step, the alkali concentration of the texturing solution can be 0.1% to 0.3%, the process temperature can be 57°C to 63°C, and the process duration is 50s to 120s. This facilitates the formation of a pyramidal structure with a roughened apex, which better reflects incident light.

[0088] For example, the alkali concentration of the texturing solution in the first texturing step can be 1.8%~2.1%, 2.1%~2.4%, or 2.4%~2.7%. Optionally, the alkali concentration of the texturing solution in the first texturing step can be 1.8%, 1.95%, 2.1%, 2.25%, 2.4%, 2.55%, or 2.7%.

[0089] For example, the process temperature of the first flocking step can be 73℃~75℃, 75℃~77℃, or 77℃~79℃. Optionally, the process temperature of the first flocking step can be 73℃, 74℃, 75℃, 76℃, 77℃, 78℃, or 79℃.

[0090] For example, the process time of the first flocking step can be 550s~565s, 565s~580s, or 580s~600s. Optionally, the process time of the first flocking step can be 550s, 557.5s, 565s, 572.5s, 580s, 590s, or 600s.

[0091] For example, the alkali concentration of the texturing solution in the second texturing step can be 0.1%~0.18%, 0.18%~0.22%, or 0.22%~0.3%. Optionally, the alkali concentration of the texturing solution in the second texturing step can be 0.1%, 0.14%, 0.18%, 0.2%, 0.22%, 0.26%, or 0.3%.

[0092] For example, the process temperature of the second texturing step can be 57℃~59℃, 59℃~61℃, or 61℃~63℃. Optionally, the process temperature of the second texturing step can be 57℃, 58℃, 59℃, 60℃, 61℃, 62℃, or 63℃.

[0093] For example, the process time of the second flocking step can be 50s~70s, 70s~90s, or 90s~120s. Optionally, the process time of the second flocking step can be 50s, 60s, 70s, 80s, 90s, 100s, 105s, or 120s.

[0094] refer to Figure 9 and Figure 10 The method for fabricating the back contact battery further includes forming a first passivation layer 14. The first passivation layer 14 is used to passivate defects in the substrate 10.

[0095] In some embodiments, the first passivation layer 14 may be formed using a chemical vapor deposition process.

[0096] The material of the first passivation layer 14 may include amorphous silicon. In some embodiments, the material of the first passivation layer 14 may also include microcrystalline silicon, which comprises an amorphous phase and tiny grains.

[0097] In some embodiments, during the process of forming the first passivation layer 14 comprising amorphous silicon material, silane and hydrogen are typically provided so that the final first passivation layer 14 comprising amorphous silicon material may contain hydrogen ions. These hydrogen ions can be used to passivate defects in the substrate 10 and also contribute to improving the performance of the back contact battery.

[0098] In some embodiments, the thickness of the first passivation layer 14 can be 3nm to 30nm, for example, 3nm to 7nm, 7nm to 15nm, 15nm to 20nm, or 20nm to 25nm. For example, the thickness of the first passivation layer 14 can be 3nm, 5nm, 7nm, 11nm, 15nm, 17.5nm, 20nm, 22.5nm, or 25nm. A thickness within the above range can effectively passivate the substrate 10 and avoid wasting resources due to an excessively large thickness of the first passivation layer 14.

[0099] refer to Figure 9 and Figure 10In some embodiments, the texturing process is also used to remove the second mask layer 13; after the texturing process and before the formation of the first passivation layer 14, the method for preparing the back contact battery further includes: performing a second wet process to remove the first mask layer 12. This avoids the presence of the first mask layer 12, which could affect the electrical connection performance between the subsequently formed first electrode and the first doped layer 11.

[0100] In some embodiments, a doped silicon glass layer 111 is provided between the first mask layer 12 and the first doped layer 11, and the second wet process is also used to remove the doped silicon glass layer 111.

[0101] In some embodiments, the etching solution used in the second wet process is an acidic solution. For example, the material of the etching solution in the second wet process may include hydrofluoric acid, with a concentration of 10% to 30%, such as 10% to 18%, 18% to 22%, or 22% to 30%. Optionally, the concentration of hydrofluoric acid may be 10%, 14%, 18%, 20%, 22%, 26%, or 30%.

[0102] In some embodiments, the process temperature of the second wet process can be 10°C to 40°C, for example, 10°C to 20°C, 20°C to 30°C, or 30°C to 40°C. For example, the process temperature of the second wet process can be 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, or 40°C.

[0103] The process time for the second wet process can be 500s to 1000s, for example, 500s to 600s, 600s to 700s, 700s to 800s, 800s to 900s, or 900s to 1000s. Optionally, the process time for the second wet process can be 500s, 550s, 600s, 650s, 700s, 750s, 800s, 850s, 900s, 950s, or 1000s.

[0104] Figure 11 This is a schematic diagram of a structure after the formation of the second passivation layer in the preparation method of the back contact battery provided in the embodiments of this application.

[0105] refer to Figure 11 In some embodiments, after forming the first passivation layer 14, the method for preparing the back contact battery further includes forming a second passivation layer 15, wherein the second passivation layer 15 is located on the surface of the first passivation layer 14 on the first surface 101 and the third surface 103 that is away from the substrate 10.

[0106] The second passivation layer 15 can passivate the substrate 10 and suppress carrier recombination in the substrate 10. The second passivation layer 15 can be formed by chemical vapor deposition.

[0107] In some embodiments, the second passivation layer 15 may be formed using a plasma-enhanced chemical vapor deposition process.

[0108] The material of the second passivation layer 15 includes silicon nitride or silicon oxynitride. Thus, the second passivation layer 15 can not only passivate the substrate 10, but also play a good role in reducing reflection, reducing the reflection of incident light by the substrate 10, and improving the utilization rate of incident light by the substrate 10.

[0109] In some embodiments, the thickness of the second passivation layer 15 can be 50nm to 95nm, for example, 50nm to 65nm, 65nm to 80nm, or 80nm to 95nm. For example, the thickness of the second passivation layer 15 can be 50nm, 55nm, 57.5nm, 65nm, 72.5nm, 75nm, 80nm, 87.5nm, or 95nm. A thickness of the second passivation layer 15 within the above range can effectively passivate the substrate 10 and avoid wasting resources due to an excessively large thickness of the second passivation layer 15.

[0110] In some embodiments, the process temperature for forming the second passivation layer 15 can be 170°C to 250°C, for example, 170°C to 190°C, 190°C to 210°C, 210°C to 230°C, or 230°C to 250°C. Optionally, the process temperature for forming the second passivation layer 15 can be 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C to 250°C. The process pressure for forming the second passivation layer 15 can be 50 Pa to 200 Pa, for example, 50 Pa to 100 Pa, 100 Pa to 150 Pa, or 150 Pa to 200 Pa. Optionally, the process pressure for forming the second passivation layer 15 can be 50 Pa, 75 Pa, 100 Pa, 125 Pa, 150 Pa, 175 Pa, or 200 Pa. The process temperature and pressure for forming the second passivation layer 15 are within the above range. The temperature and pressure are relatively low, so as not to affect the degree of crystallization in the first passivation layer 14, thus ensuring the passivation effect of amorphous silicon.

[0111] Figure 12 This is a schematic diagram of the structure after the formation of the second doped layer in the fabrication method of the back contact battery provided in this application embodiment. Figure 13 This is a schematic diagram of the structure after the formation of the first electrode and the second electrode in the preparation method of the back contact battery provided in the embodiments of this application.

[0112] refer to Figure 12 and Figure 13In some embodiments, after forming the second passivation layer 15, the method for preparing the back contact battery further includes: forming a second doped layer 16, the second doped layer 16 being located at least on the second region 106; forming a first electrode 17 and a second electrode 18, the first electrode 17 being electrically connected to the first doped layer 11, and the second electrode 18 being electrically connected to the second doped layer 16.

[0113] The material of the second doped layer 16 may include, but is not limited to, doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0114] The dopant elements in the second doped layer 16 have different conductivity types than the dopant elements in the first doped layer 11. For example, the dopant elements in the first doped layer 11 are either P-type or N-type, and the dopant elements in the second doped layer 16 are either P-type or N-type.

[0115] In some cases, the second doped layer 16 is located on the side of the first doped layer 11 in the second region 106 and a portion of the first region 105 facing away from the substrate 10, and also on the side of the first doped layer 11 in the third surface 103 facing away from the substrate 10. In other cases, the second doped layer 16 is located on the side of the first doped layer 11 in the second region 106 and a portion of the first region 105 facing away from the substrate 10. In still other cases, the second doped layer 16 is located only in the second region 106.

[0116] In some embodiments, the method of forming the second doped layer 16 includes: forming an initial doped layer (not shown) located in the second region 106 and the side of the first doped layer 11 in the first region 105 facing away from the substrate 10; and then etching away the initial doped layer on the first region 105 to form the second doped layer 16.

[0117] The first electrode 17 is located in the first region 105 and is electrically connected to the first doped layer 11 for collecting charge carriers. The second electrode 18 is located in the second region 106 and is electrically connected to the second doped layer 16 for collecting charge carriers.

[0118] The metallic material of the first electrode 17 includes at least one of gold, silver, copper, nickel, aluminum, and tin. The metallic material of the second electrode 18 includes at least one of gold, silver, copper, nickel, aluminum, and tin.

[0119] refer to Figures 11 to 13 In some embodiments, after forming the second passivation layer 15 and before forming the second doped layer 16, the method for preparing the back contact cell further includes: forming an interface passivation layer 19, wherein the interface passivation layer 19 is at least located in the second region 106.

[0120] In some cases, the interface passivation layer 19 is located on the side of the first doped layer 11 in the second region 106 and a portion of the first region 105 facing away from the substrate 10, and also on the side of the first doped layer 11 in the third surface 103 facing away from the substrate 10. In other cases, the interface passivation layer 19 is located on the side of the first doped layer 11 in the second region 106 and a portion of the first region 105 facing away from the substrate 10. In still other cases, the interface passivation layer 19 is located only in the second region 106.

[0121] The interface passivation layer 19 is located between the second doped layer 16 and the substrate 10.

[0122] The interface passivation layer 19 is used to passivate surface defects of the substrate 10. The interface passivation layer 19 is called an "interface passivation layer" because, relative to the second region 106, the interface passivation layer 19 mainly serves to passivate surface defects of the substrate 10.

[0123] The method for forming the interface passivation layer 19 can be chemical vapor deposition.

[0124] The material of the interface passivation layer 19 may include, but is not limited to, amorphous silicon (such as intrinsic amorphous silicon or micro-doped amorphous silicon), silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0125] In some embodiments, after the second passivation layer 15 is formed and before the first conductive layer 20 and the second conductive layer 21 are formed, the first conductive layer 20 is located in the first doped layer 11 of the first region 105 away from the surface of the substrate 10, the first electrode 17 is electrically connected to the first conductive layer 20, the second conductive layer 21 is located in the second doped layer 16 of the second region 106 away from the surface of the substrate 10, and the second electrode 18 is electrically connected to the second conductive layer 21.

[0126] The first conductive layer 20 can reduce the contact resistance between the first electrode 17 and the first doped layer 11, thereby improving the efficiency of the first electrode 17 in collecting charge carriers. The material of the first conductive layer 20 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0127] The second conductive layer 21 can reduce the contact resistance between the second electrode 18 and the second doped layer 16, thereby improving the efficiency of the second electrode 18 in collecting charge carriers. The material of the second conductive layer 21 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0128] The method of forming the first conductive layer 20 and the second conductive layer 21 may include: forming an initial conductive layer (not shown), wherein the initial conductive layer is a first doped layer 11 located in the first region 105 away from the surface of the substrate 10, and a second doped layer 16 located in the second region 106 away from the surface of the substrate 10; and etching a portion of the initial conductive layer to form the first conductive layer 20 and the second conductive layer 21.

[0129] In the above-described method for fabricating a back contact battery, during the texturing process, the first mask layer 12 protects the first doped layer 11 from etching and ensures that the third surface 103 does not form a textured structure. This avoids damage to the third surface 103 during the texturing process, thereby improving the performance of the back contact battery. Furthermore, the first doped layer 11 retained on the third surface 103 can be used to passivate the third surface 103, which also contributes to improving the performance of the back contact battery. Forming a textured structure on the first surface 101 and the second region 106 improves the light utilization rate of the first surface 101 and the second region 106, which is beneficial for improving the performance of the back contact battery. The first passivation layer 14 can passivate the substrate 10, which also contributes to improving the performance of the back contact battery.

[0130] Accordingly, another aspect of this application embodiment also provides a back contact battery. This back contact battery can be prepared using the preparation method of the back contact battery in any of the above embodiments. It should be noted that the parts that are the same as or corresponding to the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated below.

[0131] refer to Figure 13 The back contact cell includes a substrate 10, a first doped layer, and a first passivation layer. The substrate 10 includes a first surface 101, a second surface 102, and a third surface 103 connecting the first surface 101 and the second surface 102. The second surface 102 includes a first region 105 and a second region 106. The first doped layer is located on the second surface 102 and the third surface 103. The first passivation layer is located on the first surface 101, and the first doped layer on the third surface 103 is located on the side facing away from the substrate 10. The material of the first passivation layer includes amorphous silicon. The second region 106 of the first surface 101 and the second surface 102 has a textured structure.

[0132] In some embodiments, the back contact battery may further include a second passivation layer 15, a second doped layer 16, a first electrode 17, and a second electrode 18. The second passivation layer 15 is located on the surface of the first passivation layer 14 on the first surface 101 and the third surface 103 that is away from the substrate 10. The second doped layer 16 is located at least in the second region 106. The first electrode 17 is located in the first region 105 and is electrically connected to the first doped layer. The second electrode 18 is located in the second region 106 and is electrically connected to the second doped layer.

[0133] In some embodiments, the back contact cell may further include an interface passivation layer 19. The interface passivation layer 19 is located between the second doped layer 16 and the substrate 10.

[0134] In some embodiments, the back contact battery may further include: a first conductive layer 20 and a second conductive layer 21. The first conductive layer 20 is located on the surface of the first doped layer in the first region 105 that is away from the substrate 10, and the first electrode 17 is electrically connected to the first conductive layer 20. The second conductive layer 21 is located on the surface of the second doped layer in the second region 106 that is away from the substrate 10, and the second electrode 18 is electrically connected to the second conductive layer 21.

[0135] In the back contact battery provided above, a first doped layer and a first passivation layer are provided on the third surface 103, both of which can be used to passivate defects in the substrate 10 and improve the performance of the back contact battery. The first surface 101 and the second region 106 form a textured structure, which can improve the light utilization rate of the first surface 101 and the second region 106, and is beneficial to improving the performance of the back contact battery.

[0136] Accordingly, another aspect of this application also provides a stacked battery. The stacked battery includes a back-contact battery prepared by any of the above-described methods for preparing a back-contact battery, or a back-contact battery as described in any of the above embodiments. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0137] Figure 14 This is a schematic diagram of a stacked battery provided in an embodiment of this application.

[0138] refer to Figure 14 The tandem solar cell includes a crystalline silicon bottom cell 30 and a perovskite top cell 31. The crystalline silicon bottom cell 30 is a back contact cell prepared by the back contact cell preparation method in any of the preceding embodiments, or the crystalline silicon bottom cell 30 is a back contact cell in any of the preceding embodiments; the perovskite top cell 31 is located on one side of the crystalline silicon bottom cell 30.

[0139] Figure 15 Another structural schematic diagram of the stacked battery provided in this application embodiment.

[0140] refer to Figure 15 In some embodiments, the perovskite top solar cell 31 may include: a first transport layer 311, a perovskite functional layer 312, a second transport layer 313, a transparent conductive layer 314, and an anti-reflection layer 315 stacked together. The first transport layer 311 is directly opposite the crystalline silicon bottom solar cell 30.

[0141] In some examples, the first transport layer 311 can be one of an electron transport layer and a hole transport layer, and the second transport layer 313 can be the other of an electron transport layer and a hole transport layer.

[0142] In some embodiments, the bandgap width of the perovskite top cell 31 is greater than that of the crystalline silicon bottom cell 30. Therefore, stacking the perovskite top cell 31 on top of the crystalline silicon bottom cell 30 can give the stacked cell a wider spectral response range, thereby maximizing the utilization of solar energy and improving the efficiency of the cell.

[0143] In some embodiments, the tandem solar cell may further include an intermediate connecting layer (not shown) for electrically connecting the crystalline silicon bottom cell 30 and the perovskite top cell 31.

[0144] In some embodiments, the intermediate connection layer is generally a tunnel junction or a very thin metal or transparent electrode composite layer. Optionally, the intermediate connection layer can be a transparent conductive oxide, which has good optoelectronic properties, high photon transmittance and high conductivity, thereby enabling the perovskite top cell 31 and the crystalline silicon bottom cell 30 to maintain good ohmic contact.

[0145] In some embodiments, the tandem battery can be configured as a 2T (two-terminal series / two-terminal stacked) structure or a 4T (four-terminal series / four-terminal stacked) structure. The tandem battery can also be configured as a 3T (three-terminal series / three-terminal stacked) structure. The three-terminal stacked structure is mainly used in tandem batteries manufactured by combining a back-contact battery with a perovskite top battery, which produces three electrodes. In the four-terminal tandem battery, the two sub-cells are manufactured independently, and they are only optically connected; their circuits are independent. It can be understood that the perovskite top battery 31 and the crystalline silicon bottom battery 30 are merely physically stacked, and in reality, they each output independently. Therefore, the four-terminal tandem battery will have two positive electrodes and two negative electrodes.

[0146] Accordingly, in another aspect, this application also provides a photovoltaic module, which includes a back contact cell prepared by the method described in any of the above embodiments, or a back contact cell described in any of the above embodiments, or a tandem cell described in the above embodiments. It should be noted that the parts that are the same as or corresponding to the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated below.

[0147] Figure 16 This is a partial cross-sectional structural diagram of a photovoltaic module provided in an embodiment of this application.

[0148] refer to Figure 16 The photovoltaic module includes: a battery string, which is formed by connecting multiple back contact batteries prepared by any of the above-described back contact battery preparation methods 40, or by connecting multiple back contact batteries 40 as described above, or by connecting multiple stacked batteries as described above; an encapsulation layer 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulation layer 41 away from the battery string.

[0149] Multiple back-contact batteries 40 can be electrically connected through solder strips 43.

[0150] In some embodiments, the encapsulation layer 41 includes a first encapsulation sublayer and a second encapsulation sublayer. The first encapsulation sublayer covers one of the front and back sides of the back contact battery 40, and the second encapsulation sublayer covers the other of the front and back sides of the back contact battery 40. Specifically, at least one of the first and second encapsulation sublayers can be an organic encapsulation layer such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first and second encapsulation sublayers can also be an EP film, EPE film, or PVP film. Among them, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film, POE film, and EVA film; and PVP film refers to a co-extruded film formed by stacking POE film, EVA film, and POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0151] In some cases, the first encapsulation sublayer and the second encapsulation sublayer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of the first encapsulation sublayer and the second encapsulation sublayer. That is, the first encapsulation sublayer and the second encapsulation sublayer have formed an integral encapsulation layer 41.

[0152] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulation layer 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 may include a first cover plate 421 and a second cover plate 422, wherein the first cover plate 421 is opposite to the first encapsulation sub-layer, and the second cover plate 422 is opposite to the second encapsulation sub-layer.

[0153] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for preparing a back contact battery, characterized in that, include: A substrate is obtained, the substrate including a first surface, a second surface and a third surface connecting the first surface and the second surface, the first surface including a preset area adjacent to the third surface, and the second surface including a first area and a second area; A first doped layer is formed, which is located on the second surface, the third surface, and the preset region; A first mask layer is formed, wherein the first mask layer is located on the surface of the first doped layer; A second mask layer is formed, which is located on the surface of the first mask layer on the second surface and the third surface; Perform a first wet process to remove the first mask layer located in the preset area; Remove the second mask layer, the first mask layer, and the first doped layer from the second region; A texturing process is performed to remove the first doped layer in the preset area and to form a textured structure on the first surface and the second area. A first passivation layer is formed on the first surface and on the side of the third surface opposite to the substrate of the first doped layer, the material of the first passivation layer comprising amorphous silicon.

2. The method for preparing a back contact battery according to claim 1, characterized in that, The method for fabricating the back contact cell during the formation of the first doped layer further includes: A plating wrap is formed, the plating wrap being located on the first surface; The first wet process is also used to remove the plating portion.

3. The method for preparing a back contact battery according to claim 1, characterized in that, The thickness of the first passivation layer is 3nm~30nm.

4. The method for preparing a back contact battery according to claim 1, characterized in that, The material of the first mask layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide; the material of the second mask layer includes amorphous silicon.

5. The method for preparing a back contact battery according to claim 1, characterized in that, The thickness of the first mask layer is 20nm~60nm; the thickness of the second mask layer is 7nm~15nm.

6. The method for preparing a back contact battery according to claim 1, characterized in that, The texturing process is also used to remove the second mask layer; After the texturing process and before the formation of the first passivation layer, the method for preparing the back contact battery further includes: A second wet process is performed to remove the first mask layer.

7. The method for preparing a back contact battery according to any one of claims 1 to 6, characterized in that, After forming the first passivation layer, the method for fabricating the back contact battery further includes: A second passivation layer is formed on the surface of the first passivation layer on the first and third surfaces that is away from the substrate.

8. The method for preparing a back contact battery according to claim 7, characterized in that, The process temperature for forming the second passivation layer is 170℃~250℃; the process pressure for forming the second passivation layer is 50Pa~200Pa.

9. The method for preparing a back contact battery according to claim 7, characterized in that, After forming the second passivation layer, the method for preparing the back contact battery further includes: A second doped layer is formed, wherein the second doped layer is located at least on the second region; A first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first doped layer, and the second electrode is electrically connected to the second doped layer.

10. The method for preparing a back contact battery according to claim 1, characterized in that, Obtaining the substrate includes: Obtain the initial base; A cutting process is performed to cut the initial substrate into at least two substrates.

11. A back-contact battery, characterized in that, The back contact battery is prepared by the method for preparing a back contact battery according to any one of claims 1 to 10, wherein the back contact battery comprises: The substrate includes a first surface, a second surface, and a third surface connecting the first surface and the second surface, wherein the second surface includes a first region and a second region; A first doped layer is located on the second surface and the third surface; A first passivation layer is located on the first surface, and the first doped layer on the third surface is located on the side opposite to the substrate. The material of the first passivation layer includes amorphous silicon. The second region of the first surface and the second surface has a textured structure.

12. A stacked battery, characterized in that, include: A crystalline silicon bottom cell, wherein the crystalline silicon bottom cell is a back contact cell prepared by the method of preparing a back contact cell as described in any one of claims 1 to 10, or a back contact cell as described in claim 11; A perovskite top cell, wherein the perovskite top cell is located on one side of the bottom cell.

13. A photovoltaic module, characterized in that, include: The battery string is formed by connecting multiple back contact batteries prepared by the method of preparing back contact batteries as described in any one of claims 1 to 10, or by connecting multiple back contact batteries as described in claim 11, or by connecting multiple stacked batteries as described in claim 12. An encapsulation layer that covers the surface of the battery string; A cover plate that covers the surface of the encapsulation layer opposite to the battery string.

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