Semimetal-semiconductor van der waals heterojunction, method of making and photodetector

Abstract

The application belongs to the technical field of nano-optoelectronic technology, and provides a semi-metal-semiconductor van der Waals heterojunction, a preparation method thereof and a photoelectric detector. The heterojunction comprises an insulating layer substrate, a two-dimensional semiconductor material layer and a two-dimensional semi-metal material layer are arranged on the surface of the insulating layer substrate, part of the structure of the two-dimensional semiconductor material layer and part of the structure of the two-dimensional semi-metal material layer are overlapped, and a heterojunction light absorption region is formed; a metal electrode comprises a source electrode and a drain electrode, the source electrode is electrically connected with the two-dimensional semiconductor material layer, and the drain electrode is electrically connected with the two-dimensional semi-metal material layer. The application realizes adjustable interface band bending in the nanometer scale, significantly improves the separation and transportation efficiency of carriers, effectively reduces the dark current and improves the response speed.

Description

Technical Field

[0001] This invention belongs to the field of nano-optoelectronics technology, and particularly relates to semi-metal-semiconductor van der Waals heterojunctions, their preparation methods, and photodetectors. Background Technology

[0002] High-speed photoelectric detection technology has significant application value in modern optoelectronics, high-speed communication, quantum imaging, and ultrafast spectroscopy. With the continuous improvement of frame rate and resolution in imaging systems, the performance requirements for photodetectors in terms of response speed, signal-to-noise ratio (SNR), and dark current are becoming increasingly stringent. However, the performance of traditional photodetectors is largely limited by the separation and transport efficiency of photogenerated carriers at the interface. Inefficient interface charge separation not only prolongs the device's response time but also increases dark-state noise, thus restricting imaging quality and the system's temporal resolution.

[0003] To overcome the aforementioned bottlenecks, researchers have focused on improving carrier separation efficiency through interface bandgap engineering. Band shifts at the heterojunction interface can create a built-in electric field, which drives the rapid separation of photogenerated electron-hole pairs at the interface, serving as the core driving force for achieving efficient photoelectric conversion. Two-dimensional layered materials and their constructed van der Waals heterojunctions are considered ideal platforms for building high-performance photodetectors due to their atomically flat interfaces, dangling-bond-free surface states, and tunable band structures. By rationally selecting the work function and electron affinity of the material, ideal band alignment can be achieved at the heterojunction interface, thereby obtaining a strong built-in electric field.

[0004] However, existing heterojunction photodetectors based on two-dimensional materials still face significant challenges. On the one hand, the Fermi level pinning effect, prevalent in traditional metal-semiconductor contacts or semiconductor-semiconductor heterojunctions, severely limits the effective control of the interface Schottky barrier height, resulting in a much lower actual band bending degree than theoretically expected and insufficient built-in electric field strength. On the other hand, most existing studies only focus on the impact of a single factor, either barrier height or barrier width, on carrier separation efficiency, failing to consider both factors synergistically to comprehensively assess the contribution of band bending to the separation driving force. This leads to a lack of systematic guidance for optimizing the band structure of heterojunction interfaces. These factors collectively make it difficult to further improve the separation efficiency of photogenerated carriers, and there is still considerable room for improvement in device dark current suppression and response speed. Summary of the Invention

[0005] The purpose of this invention is to provide a semi-metal-semiconductor van der Waals heterojunction, its preparation method, and a photodetector to solve the above-mentioned problems. By rationally selecting materials and designing interfaces, a heterojunction interface with significant band bending can be constructed, while effectively suppressing the Fermi level pinning effect, thereby maximizing the built-in electric field of the interface and simultaneously reducing dark current and improving response speed.

[0006] To achieve the above objectives, the present invention provides the following solution: a half-metal-semiconductor van der Waals heterojunction, comprising: An insulating substrate has a two-dimensional semiconductor material layer and a two-dimensional semi-metallic material layer disposed on its surface. Parts of the structure of the two-dimensional semiconductor material layer and part of the structure of the two-dimensional semi-metallic material layer overlap to form a heterojunction light absorption region. The metal electrode includes a source electrode and a drain electrode, wherein the source electrode is electrically connected to the two-dimensional semiconductor material layer and the drain electrode is electrically connected to the two-dimensional semi-metallic material layer.

[0007] Preferably, the insulating substrate is made of silicon oxide and the thickness of the insulating substrate is 90-300 nm.

[0008] Preferably, the two-dimensional semiconductor material layer is made of tungsten diselenide, molybdenum disulfide, or tellurene, the thickness of the two-dimensional semiconductor material layer is 0.6–20 nm, the surface channel length of the two-dimensional semiconductor material is 1–5 μm, and the channel width is 5–10 μm. The two-dimensional semi-metallic material layer is made of niobium diselenide, vanadium diselenide, or graphene, and the thickness of the two-dimensional semi-metallic material layer is 0.6–20 nm.

[0009] A method for preparing a half-metal-semiconductor van der Waals heterojunction, comprising the following preparation steps: The insulating substrate is subjected to a hydrophilic treatment; A two-dimensional semiconductor material layer was prepared by mechanical exfoliation and then transferred onto an insulating substrate. Annealing enhances the bonding force between the two-dimensional semiconductor material layer and the insulating substrate, followed by patterning and etching of the two-dimensional semiconductor material layer to form a pre-contact region. A two-dimensional semi-metallic material layer was prepared by mechanical exfoliation and then transferred onto an insulating substrate, overlapping with the pre-contact area. Annealing is performed to enhance the adhesion between the two-dimensional semi-metallic material layer and the insulating substrate; Source and drain electrodes are deposited to obtain a semi-metal-semiconductor van der Waals heterojunction.

[0010] Preferably, the mechanical peeling method for the two-dimensional semi-metallic material layer or the two-dimensional semiconductor material layer includes: The two-dimensional semi-metallic material layer or two-dimensional semiconductor material layer is thinned several times with blue film tape and then attached to the PDMS stamp. Find a two-dimensional semi-metallic material layer or a two-dimensional semiconductor material layer of suitable thickness as the target material layer, and achieve the peeling of the two-dimensional semi-metallic material layer or the two-dimensional semiconductor material layer.

[0011] Preferably, the method for transferring the target material layer to the insulating substrate includes: The target material layer is precisely positioned relative to the insulating substrate under real-time monitoring with an optical microscope; The PDMS sample stage is lowered to slowly bring the target material layer close to the insulating substrate. After the two come into contact, the temperature is raised to 80°C and then slowly cooled.

[0012] Preferably, the patterning etching method includes: The part that needs to be etched is patterned on the surface of a two-dimensional semiconductor material layer by electron beam exposure; The patterned parts are etched using plasma containing SF6 and O2; The SF6 gas flow rate is 10–50 sccm, the O2 gas flow rate is 5–20 sccm, the power is 5–20 W, and the etching time is 5–15 s.

[0013] Preferably, the annealing method includes: After transferring the target material layer onto the insulating substrate, a vacuum annealing furnace was used with an argon atmosphere of 10–50 sccm at a temperature of 120°C for 1 hour at a heating rate of 5°C / min, followed by natural cooling.

[0014] Preferably, the source electrode and drain electrode are deposited by thermal evaporation.

[0015] A photodetector comprising the aforementioned semi-metal-semiconductor van der Waals heterojunction.

[0016] Compared with the prior art, the present invention has the following advantages and technical effects: 1. This invention constructs a van der Waals heterojunction by introducing a two-dimensional semi-metallic material with a high work function, effectively avoiding the Fermi level pinning effect in traditional metal contacts and achieving precise control over the height of the interface Schottky barrier. Furthermore, the band curvature at the heterojunction interface forms a strong built-in electric field, effectively suppressing dark-state thermally excited carrier injection and significantly reducing the dark current of the photodetector; the large band curvature accelerates the separation and transport efficiency of photogenerated carriers, improving the device's response speed.

[0017] 2. Based on the aforementioned low dark current and high response speed characteristics, this invention reduces background noise during the imaging process, resulting in clearer imaging effects with shorter exposure times. This feature effectively solves the imaging blurring problem of high-speed moving objects, improves the signal-to-noise ratio and temporal resolution of the imaging system, and enables the photodetector to be adapted to high-quality, high-frame-rate fast imaging applications, providing an effective interface bandgap engineering strategy for high-speed imaging of two-dimensional optoelectronic devices.

[0018] 3. The method of the present invention has a certain degree of universality and is not limited to the few materials used. Any material that can be constructed to form a similar band structure can be studied by this method, thus broadening the research scope of van der Waals heterojunctions based on two-dimensional semi-metal-semiconductor materials. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the semi-metal-semiconductor van der Waals heterojunction of the present invention; Figure 2 This is a scanning electron microscope image of the semi-metal-semiconductor van der Waals heterojunction of the present invention. Figure 3 This is a comparison diagram of the transfer curves of the half-metal-semiconductor heterojunction and the ordinary Schottky junction of the present invention; Figure 4 This is a comparison of the light output curves of the half-metal-semiconductor heterojunction and the ordinary Schottky junction of the present invention; Figure 5 A comparison of the light response speeds of a metal-semiconductor heterojunction and a conventional Schottky junction, used to invent the invention; Figure 6 This is a schematic diagram of a typical Schottky junction. Among them, 1. source electrode; 2. two-dimensional semi-metallic material layer; 3. two-dimensional semiconductor material layer; 4. insulating substrate; 5. drain electrode. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Example 1: Reference Figures 1-5 This invention provides a half-metal-semiconductor van der Waals heterojunction, comprising: An insulating substrate 4 has a two-dimensional semiconductor material layer 3 and a two-dimensional semi-metallic material layer 2 disposed on its surface. Part of the structure of the two-dimensional semiconductor material layer 3 and part of the structure of the two-dimensional semi-metallic material layer 2 overlap to form a heterojunction light absorption region. The metal electrode includes a source electrode 1 and a drain electrode 5. The source electrode 1 is electrically connected to the two-dimensional semiconductor material layer 3, and the drain electrode 5 is electrically connected to the two-dimensional semi-metallic material layer 2.

[0024] The main function of the insulating substrate 4 is to serve as the underlying support structure, providing a physical platform for the two-dimensional semiconductor material layer and the two-dimensional semi-metal material layer, while also achieving electrical isolation between the device and the underlying silicon substrate to prevent the formation of leakage channels. The main function of the two-dimensional semiconductor material layer 3 is to serve as a channel for the generation and transport of photogenerated carriers. Its overlapping region with the two-dimensional semi-metal material layer constitutes the heterojunction light absorption region, and it also serves as the contact layer of the source electrode, providing a carrier transport path. The main function of the two-dimensional semi-metal material layer 2 is to serve as a high work function electrode material. A van der Waals heterojunction is constructed with a two-dimensional semiconductor material layer, forming a high Schottky barrier and significant band bending at the interface. Simultaneously, the contact layer, serving as the drain electrode, effectively weakens the Fermi level pinning effect due to its low density of states, enhancing the built-in electric field strength. The main function of source electrode 1 is as the carrier injection end, injecting carriers into the semiconductor channel. The main function of drain electrode 5 is as the carrier outflow end, electrically connected to the two-dimensional half-metal material layer, collecting photogenerated carriers separated at the heterojunction interface and transported to the half-metal layer, forming a complete photocurrent loop. Overall, this invention achieves tunable interface band bending at the nanoscale, significantly improving carrier separation and transport efficiency, effectively reducing dark current, and increasing response speed.

[0025] In this embodiment, the two-dimensional semi-metallic material layer 2 serves as the drain, and partially overlaps with the bottom two-dimensional semiconductor material layer 3 to form a heterojunction, such as... Figure 1 As shown, the vertical structure formed by the two-dimensional semi-metallic material layer 2 and the two-dimensional semiconductor material layer 3 can improve area efficiency.

[0026] Further optimization of the scheme: the thickness of source electrode 1 and drain electrode 5 is 30-100nm, and the composition is pure gold, or chromium metal and pure gold.

[0027] Further optimization of the scheme: the insulating substrate 4 is made of silicon oxide material, and the thickness of the insulating substrate 4 is 90-300nm.

[0028] Further optimization of the scheme: the two-dimensional semiconductor material layer 3 is made of tungsten diselenide, molybdenum disulfide or tellurene, the thickness of the two-dimensional semiconductor material layer 3 is 0.6 to 20 nm, the surface channel length of the two-dimensional semiconductor material is 1 to 5 μm, and the channel width is 5 to 10 μm; The two-dimensional semi-metallic material layer 2 is made of niobium diselenide, vanadium diselenide, or graphene, and the thickness of the two-dimensional semi-metallic material layer 2 is 0.6–20 nm.

[0029] Example 2: A method for preparing a half-metal-semiconductor van der Waals heterojunction, used to prepare the half-metal-semiconductor van der Waals heterojunction of Example 1, includes the following preparation steps: The insulating substrate 4 is subjected to a hydrophilic treatment; A two-dimensional semiconductor material layer 3 was prepared by mechanical exfoliation and then transferred onto an insulating substrate 4. Annealing is performed to enhance the bonding force between the two-dimensional semiconductor material layer 3 and the insulating substrate 4. Then, the two-dimensional semiconductor material layer 3 is patterned and etched to form a pre-contact region. A two-dimensional semi-metallic material layer 2 was prepared by mechanical exfoliation and then transferred to an insulating substrate 4, overlapping with the pre-contact region. Annealing is performed to enhance the bonding force between the two-dimensional semi-metallic material layer 2 and the insulating substrate 4; Source electrode 1 and drain electrode 5 are deposited to obtain a semi-metal-semiconductor van der Waals heterojunction.

[0030] To further optimize the scheme, the insulating substrate 4 was subjected to hydrophilic treatment using oxygen plasma etching, with an oxygen flow rate of 10–50 sccm, a power of 20–50 W, and an etching time of 20–60 s.

[0031] Further optimization of the scheme includes mechanical peeling methods for the two-dimensional semi-metallic material layer 2 or the two-dimensional semiconductor material layer 3, including: After the two-dimensional semi-metallic material layer 2 or the two-dimensional semiconductor material layer 3 is thinned several times with blue film tape, it is attached to the PDMS stamp. Find a two-dimensional semi-metallic material layer 2 or a two-dimensional semiconductor material layer 3 of suitable thickness as the target material layer, and achieve the peeling of the two-dimensional semi-metallic material layer 2 or the two-dimensional semiconductor material layer 3.

[0032] Further optimization of the scheme, the method for transferring the target material layer to the insulating substrate 4 includes: The target material layer is precisely positioned relative to the insulating substrate 4 under real-time monitoring with an optical microscope; The PDMS sample stage is lowered to slowly bring the target material layer close to the insulating substrate 4. After the two come into contact, the temperature is raised to 80°C and then slowly cooled.

[0033] Further optimization of the scheme, the patterned etching method includes: The part to be etched is patterned on the surface of the two-dimensional semiconductor material layer 3 by electron beam exposure; The patterned parts are etched using plasma containing SF6 and O2; The SF6 gas flow rate is 10–50 sccm, the O2 gas flow rate is 5–20 sccm, the power is 5–20 W, and the etching time is 5–15 s.

[0034] Further optimization of the scheme includes annealing methods such as: After the target material layer was transferred onto the insulating substrate 4, it was annealed in a vacuum furnace with an argon atmosphere of 10–50 sccm at a temperature of 120°C for 1 hour at a heating rate of 5°C / min, followed by natural cooling.

[0035] The scheme was further optimized by using thermal evaporation to deposit the source electrode 1 and the drain electrode 5.

[0036] Example 1: In this embodiment, a semi-metal-semiconductor van der Waals heterojunction is constructed using multilayer niobium diselenide as the two-dimensional semi-metal material layer 2 and tungsten diselenide as the two-dimensional semiconductor material layer 3. Its structural composition is as follows: Figure 1 As shown, its preparation method is as follows: S1, the insulating substrate 4 with a thickness of 300nm is ultrasonically cleaned with acetone and isopropanol in sequence to remove impurities and organic matter on the surface of the insulating substrate 4. Then, the substrate surface is hydrophilically treated with oxygen plasma, with a gas flow rate of 20sccm, a power of 20W, and an etching time of 30s.

[0037] S2. Using a mechanical peeling method, the two-dimensional semiconductor material layer 3 is repeatedly folded and thinned with blue film tape, and then further bonded to PDMS. The target material of suitable thickness is found by optical microscope, and the target material is accurately transferred to the insulating substrate 4 using a precision transfer platform.

[0038] Specifically, under the control of the precision transfer platform, the two-dimensional semiconductor material layer 3 sample is precisely positioned with the target insulating substrate 4 under real-time monitoring of an optical microscope; the PDMS sample stage is lowered so that the two-dimensional semiconductor material layer 3 slowly approaches the target insulating substrate 4. After the two come into contact, the sample is heated to 80°C by a temperature control platform and then slowly cooled to allow the adhesion between the PDMS stamp and the sample to be released gradually, thereby transferring the two-dimensional semiconductor material layer 3 to the target position without damage and with precision.

[0039] S3, the transferred two-dimensional semiconductor material layer 3 and insulating substrate 4 are annealed. The annealing is carried out in an argon atmosphere with a gas flow rate of 50 sccm, a heating rate of 5˚C / min, an annealing temperature of 120˚C, and a time of 1h. S4, after annealing, a layer of polymethyl methacrylate is spin-coated onto the surface of the two-dimensional semiconductor material layer 3. The areas to be etched away are patterned using electron beam lithography. Then, etching is performed using SF6 and O2 plasma, with an SF6 flow rate of 15 sccm, an O2 flow rate of 5 sccm, a power of 8 W, and an etching time of 6 s, resulting in strips of the two-dimensional semiconductor material layer 3 with dimensions of 40 × 10 μm. Figure 2 As shown.

[0040] S5. Using a mechanical peeling method, the two-dimensional semi-metallic material layer 2 is repeatedly folded and thinned with blue film tape, and then further bonded to PDMS. The target material of suitable thickness is found through an optical microscope, and the target two-dimensional semi-metallic material layer 2 is accurately transferred to the insulating substrate 4 using a precision transfer platform.

[0041] S6. Anneal the transferred two-dimensional semi-metallic material layer 2. The annealing is carried out in an argon atmosphere with a gas flow rate of 50 sccm, a heating rate of 5˚C / min, an annealing temperature of 120˚C, and a time of 1h. S7. After annealing, a layer of polymethyl methacrylate is spin-coated onto the sample surface. The positions of the source electrode 1 and the drain electrode 5 are patterned by electron beam exposure, with an exposure voltage of 30kV, an exposure dose of 360, and development for 30s. Then, thermal evaporation is performed to deposit pure gold source electrode 1 and drain electrode 5, with an evaporation rate of 0.05nm / s.

[0042] The scanning electron microscope image of the half-metal-semiconductor heterojunction prepared in this embodiment is shown below. Figure 2 The transfer curve of the semi-metal-semiconductor heterojunction prepared in this embodiment is shown in the figure. Figure 3 .

[0043] from Figure 2 As can be seen, the material of the prepared semi-metal-semiconductor heterojunction is intact and is hardly damaged during the processing, which is beneficial to the performance of the transistor.

[0044] from Figure 4As can be seen, the photocurrent-to-dark-current ratio of the semi-metal-semiconductor heterojunction is significantly higher than that of the ordinary Schottky junction, indicating that it has superior photoresponse capability under illumination. A higher photocurrent-to-dark-current ratio means that the device can more effectively suppress dark current and enhance photogenerated signal output, further proving that the semi-metal-semiconductor heterojunction forms a stronger built-in electric field at the interface, thereby accelerating the separation and transport process of photogenerated carriers. To quantitatively evaluate the strength of the built-in electric field of the heterojunction, curvature (ρ) is introduced as a key performance parameter. Curvature (ρ) is used to characterize the degree of band bending at the heterojunction interface and its impact on carrier separation capability: a larger curvature corresponds to more significant band bending and a stronger built-in electric field, which can provide a greater driving force for photogenerated electron-hole pairs, thereby improving the separation efficiency of carriers at the interface and ultimately achieving superior photoelectric response performance.

[0045] The formula for calculating curvature is defined as follows: Among them, W H It is the barrier height, W D It is the width of the barrier. It is the work function of a semimetal. It is the electron affinity of semiconductor materials. It is the dielectric constant of a semiconductor. It has a built-in electric field. It is the elementary charge. It is the carrier concentration.

[0046] like Figure 3 As shown, by extracting and calculating the parameters of the two transfer curves, the band curvature of the half-metal-semiconductor heterojunction can be determined. The work function of the conventional Schottky junction is approximately 0.19, while its band curvature is approximately 0.20. Although the band curvature values ​​are similar, the half-metal-semiconductor heterojunction designed in this application exhibits significantly better performance than the conventional Schottky junction. Specifically, thanks to the high work function and low density of states characteristic of half-metal materials, this scheme effectively weakens the Fermi level pinning effect at the heterojunction interface and optimizes the interface contact state. Based on this, the heterojunction can construct a larger built-in electric field, thereby significantly improving the separation efficiency of photogenerated carriers.

[0047] Among them, the ordinary Schottky junction is a transistor constructed using the same few-layer WSe2 structure, as shown in the figure. Figure 6 As shown, it consists of an insulating layer 4, a two-dimensional semiconductor material layer 3, an asymmetric metal source electrode 1, and a drain electrode 5. Its fabrication method is as follows: A. Clean the substrate. The 300nm thick silicon dioxide insulating substrate is ultrasonically cleaned with acetone and isopropanol in sequence to remove impurities and organic matter on the substrate surface. Then, the substrate surface is hydrophilically treated with oxygen plasma (gas flow rate of 20sccm, power of 20W, etching time of 30s).

[0048] B. Mechanical stripping and transfer of two-dimensional tungsten diselenide material: The two-dimensional semiconductor material layer 3 (tungsten diselenide bulk material) was repeatedly folded and thinned using blue film tape, and further bonded to PDMS. A target material of suitable thickness was located using an optical microscope, and the target material was precisely transferred onto the substrate using a precision transfer platform. The transferred two-dimensional semiconductor material layer 3 and the insulating substrate 4 were then annealed in an argon atmosphere at a flow rate of 50 sccm, a heating rate of 5˚C / min, an annealing temperature of 120˚C, and a time of 1 h.

[0049] C. Deposition of Metal Electrodes: A layer of PMMA was spin-coated onto the substrate surface after material transfer, and patterned using electron beam lithography (EBRT) at a voltage of 30 kV and an exposure dose of 360. The contact electrode region was a rectangle 10 μm long and 5 μm wide, with a channel length of 5 μm. After development of the exposed substrate, a 30 nm thick pure gold electrode was thermally deposited as the source electrode 1 at an evaporation rate of 0.05 nm / s. A second exposure was performed, spin-coating another layer of PMMA onto the substrate surface after the metal electrode on one side was deposited, and patterned using EBRT. A 30 nm thick platinum electrode was thermally deposited as the drain electrode 5. Finally, a conventional Schottky junction with WSe2 as the channel material was fabricated. Its performance is shown in [link to performance data]. Figure 4 The dashed line portion of the transition curve.

[0050] Example 2: Similar to Example 1, the only difference is that the half-metal-semiconductor heterojunction uses mechanically stripped half-metal material as one side electrode, while the ordinary Schottky junction uses asymmetric electrodes as source and drain electrodes respectively. The specific method for fabricating a half-metal-semiconductor heterojunction is as follows: First, the two-dimensional semiconductor material layer 3, made of tungsten diselenide, is peeled off onto the insulating substrate 4. Then, the two-dimensional semi-metallic material layer 2, made of niobium diselenide, is mechanically peeled off and transferred to the insulating substrate 4 with the two-dimensional semiconductor material layer 3. Subsequently, an electron beam exposure process is performed for patterning. The source electrode 1 and the drain electrode 5 are both pure gold electrodes.

[0051] The fabrication process for a conventional Schottky junction involves the following steps: First, multiple layers of tungsten diselenide are stripped onto a silicon dioxide substrate, followed by spin-coating a layer of PMMA onto the substrate surface. Patterning is then performed using electron beam lithography, employing a voltage of 30 kV and an exposure dose of 360. The contact electrode region is a rectangle 10 μm long and 5 μm wide, with a channel length of 5 μm. After development of the exposed substrate, a 30 nm thick pure gold electrode is deposited via thermal evaporation as the metal source electrode 1, at an evaporation rate of 0.05 nm / s. Following resist removal, a second exposure is performed. A layer of PMMA is spin-coated onto the substrate surface after the deposition of one metal electrode, and patterning is then performed using electron beam lithography. A 30 nm thick platinum electrode is deposited via thermal evaporation as the metal drain electrode 5.

[0052] A comparison of the illumination output curves of the half-metal-semiconductor heterojunction and the ordinary Schottky junction prepared in this embodiment is shown below. Figure 4 .

[0053] pass Figure 4 The parameters were extracted from the output curves and calculated to show that the photocurrent ratio of the half-metal-semiconductor heterojunction is greater than 100 and the open-circuit voltage is 0.36, while the photocurrent ratio of the ordinary Schottky junction is greater than 10 and the open-circuit voltage is 0.08. This proves that the half-metal-semiconductor heterojunction forms a stronger built-in electric field at the interface.

[0054] pass Figure 5 The parameters were extracted from the transient photocurrent-time curve, and the response speed of the half-metal-semiconductor heterojunction was calculated. τ r =11.2μs, τ f =11.2μs), the response speed of a typical Schottky junction ( τ r =0.89ms, τ f =1.41ms), proving that the semi-metal-semiconductor heterojunction forms a stronger built-in electric field at the interface, thereby accelerating the separation and transport process of photogenerated carriers.

[0055] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0056] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A semi-metal-semiconductor van der Waals heterojunction, characterized in that, include: An insulating substrate (4) is provided with a two-dimensional semiconductor material layer (3) and a two-dimensional semi-metal material layer (2) on its surface. Part of the structure of the two-dimensional semiconductor material layer (3) and part of the structure of the two-dimensional semi-metal material layer (2) overlap to form a heterojunction light absorption region. The metal electrode includes a source electrode (1) and a drain electrode (5), wherein the source electrode (1) is electrically connected to the two-dimensional semiconductor material layer (3) and the drain electrode (5) is electrically connected to the two-dimensional semi-metallic material layer (2).

2. The semi-metal-semiconductor van der Waals heterojunction according to claim 1, characterized in that: The insulating substrate (4) is made of silicon oxide and has a thickness of 90-300 nm.

3. The semi-metal-semiconductor van der Waals heterojunction according to claim 1, characterized in that: The two-dimensional semiconductor material layer (3) is made of tungsten diselenide, molybdenum disulfide or tellurene. The thickness of the two-dimensional semiconductor material layer (3) is 0.6 to 20 nm. The surface channel length of the two-dimensional semiconductor material is 1 to 5 μm and the channel width is 5 to 10 μm. The two-dimensional semi-metallic material layer (2) is made of niobium diselenide, vanadium diselenide or graphene, and the thickness of the two-dimensional semi-metallic material layer (2) is 0.6 to 20 nm.

4. A method for preparing a half-metal-semiconductor van der Waals heterojunction, used to prepare the half-metal-semiconductor van der Waals heterojunction as described in claim 1, characterized in that, The preparation steps include the following: The insulating substrate (4) is subjected to a hydrophilic treatment; A two-dimensional semiconductor material layer (3) was prepared by mechanical peeling and then transferred to an insulating substrate (4). Annealing process enhances the bonding force between the two-dimensional semiconductor material layer (3) and the insulating substrate (4), followed by patterning and etching of the two-dimensional semiconductor material layer (3) to form a pre-contact area; A two-dimensional semi-metallic material layer (2) was prepared by mechanical peeling and then transferred to an insulating substrate (4) to overlap with the pre-contact area. Annealing is performed to enhance the bonding force between the two-dimensional semi-metallic material layer (2) and the insulating substrate (4); Deposit source electrode (1) and drain electrode (5) to obtain a semi-metal-semiconductor van der Waals heterojunction.

5. The method for preparing a half-metal-semiconductor van der Waals heterojunction according to claim 4, characterized in that: The mechanical peeling method for the two-dimensional semi-metallic material layer (2) or the two-dimensional semiconductor material layer (3) includes: The two-dimensional semi-metallic material layer (2) or the two-dimensional semiconductor material layer (3) is thinned several times with blue film tape and then attached to the PDMS stamp. Find a two-dimensional semi-metallic material layer (2) or a two-dimensional semiconductor material layer (3) of suitable thickness as the target material layer, and realize the peeling of the two-dimensional semi-metallic material layer (2) or the two-dimensional semiconductor material layer (3).

6. The method for preparing a semi-metal-semiconductor van der Waals heterojunction according to claim 5, characterized in that: Methods for transferring the target material layer to the insulating substrate (4) include: The target material layer is precisely positioned relative to the insulating substrate (4) under real-time monitoring with an optical microscope; The PDMS sample stage is lowered to slowly bring the target material layer close to the insulating substrate (4). After the two come into contact, the temperature is raised to 80°C and then slowly cooled.

7. The method for preparing a half-metal-semiconductor van der Waals heterojunction according to claim 4, characterized in that: The patterning etching method includes: The part to be etched is patterned on the surface of the two-dimensional semiconductor material layer (3) by electron beam exposure; Using SF6 and O 2的 Plasma etches the patterned areas; The SF6 gas flow rate is 10–50 sccm, the O2 gas flow rate is 5–20 sccm, the power is 5–20 W, and the etching time is 5–15 s.

8. The method for preparing a half-metal-semiconductor van der Waals heterojunction according to claim 6, characterized in that: The annealing process includes: After the target material layer is transferred onto the insulating substrate (4), a vacuum annealing furnace is used with an argon atmosphere of 10-50 sccm, a temperature of 120°C, a time of 1 hour, a heating rate of 5°C / min, and then the material is allowed to cool naturally.

9. The method for preparing a semi-metal-semiconductor van der Waals heterojunction according to claim 4, characterized in that: The source electrode (1) and drain electrode (5) are deposited by thermal evaporation.

10. A photodetector, characterized in that, Includes the semi-metal-semiconductor van der Waals heterojunction as described in any one of claims 1-3.

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