A back contact cell and a method of manufacturing the same

Abstract

The present application relates to the technical field of solar cells, in particular to a back contact cell and a preparation method thereof. The back contact cell comprises an N-type silicon substrate, a composite passivation isolation layer, a global passivation layer and a metallization structure. The back surface of the N-type silicon substrate is provided with p + emitters and n + back surfaces, and gap regions are formed between the p + emitters and n + back surfaces; the composite passivation isolation layer covers at least the gap regions, and the composite passivation isolation layer comprises an intrinsic amorphous silicon layer and an intrinsic SiO x layer; the global passivation layer covers at least the p + emitters, n + back surfaces and the composite passivation isolation layer; and the metallization structure comprises a seed silver layer, a full copper layer and an insulating protective layer. By setting the gap regions, the composite passivation isolation layer, the low-temperature global passivation layer and the low-silver-consumption metallization structure, the composite loss of the back contact cell can be reduced, the silver consumption can be reduced, the yield can be improved, and the reliability can be enhanced.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a back contact cell and its preparation method. Background Technology

[0002] Back-contact (BC) cells represent a high-efficiency technology in the field of crystalline silicon solar cells. Their core characteristic is that both the positive and negative electrodes are located on the back of the cell, completely eliminating the obstruction of the front-side metal grid lines and maximizing the utilization of incident light, thereby achieving higher photoelectric conversion efficiency. This is a core R&D direction for the photovoltaic industry to reduce the cost per kilowatt-hour and overcome efficiency bottlenecks. The core processes of BC cells focus on selective back-side doping, interface passivation, electrode isolation, and metallization. The performance of these processes directly determines the cell's conversion efficiency, production yield, and mass production feasibility. Currently, the mass production of mainstream BC cells faces challenges such as high process complexity, high silver consumption, and low yield, which still restricts their large-scale industrialization.

[0003] Currently, mainstream BC (Bright Crystal Cell) technologies include interdigitated back contact (IBC) and polycrystalline silicon oxide back contact (POLO-BC), with their core R&D goals being to reduce surface recombination, improve electrode isolation performance, simplify process flow, and reduce manufacturing costs. Among these, for N-type silicon substrate BC cells, insufficient temperature compatibility between the passivation layer and the encapsulating separator, significant recombination losses in the positive and negative doping gaps, and persistently high silver consumption in metallization have become key bottlenecks for large-scale mass production.

[0004] The existing core structure of N-type BC cells includes: an N-type silicon substrate and a front-side SiO2 / SiN substrate. x Anti-reflection passivation layer, p-layers arranged alternately on the back side + emitter and n + Back field, covering the back of AlO x / SiN x The system consists of a stacked passivation layer and metal electrodes; the metallization is achieved using a traditional all-silver paste printing process; and the gaps between the positive and negative doped regions are created using a single SiN electrode. x Layer isolation; the passivation layer is entirely AlO x / SiN x A two-layer structure was constructed using PECVD to deposit AlO2. x / SiN x The stacked passivation layer is deposited at a temperature controlled between 170 and 190°C, eliminating the need for high-temperature annealing. This addresses issues such as electrode warping and interface defects caused by high-temperature passivation. Low-temperature deposition also improves the compatibility between passivation and packaging.

[0005] The aforementioned N-type BC batteries cannot meet the mass production requirements of high efficiency, low power consumption, and high yield, specifically due to the following issues: Significant composite loss in the interstitial region: p +emitter and n + The gap region between the back fields uses only a single SiN. x Layer isolation prevents effective passivation of dangling bonds on the silicon surface in the gap region, resulting in high interface state density, low minority carrier lifetime, and high leakage current. This directly leads to loss of open-circuit voltage (Voc) and photoelectric conversion efficiency (PCE), making it difficult to fully unleash the efficiency potential of BC cells.

[0006] Insufficient compatibility between passivation and isolation: AlO x / SiN x Although the double-layer passivation structure enables low-temperature deposition, AlO x Layers and SiN x The interfacial bonding is weak, making the film layer prone to peeling during subsequent metallization; and single SiN x The insulation performance of the separator is limited, which cannot effectively prevent lateral leakage between the positive and negative electrodes, resulting in a decrease in battery reliability.

[0007] High metallization cost and low yield: The traditional all-silver paste printing metallization process consumes far more silver than TOPCon cells. The cost of silver paste accounts for more than 50% of the non-silicon cost of the cell, which greatly increases the manufacturing cost. At the same time, all-silver paste printing has strict requirements for grid line precision and is prone to problems such as short circuits and open circuits, resulting in low cell yield and limiting the expansion of mass production scale.

[0008] Poor process adaptability: AlO x Layer deposition requires the use of a special trimethylaluminum precursor, which has high material procurement costs and is difficult to obtain; moreover, its passivation layer has poor synergy with the metallization process, making process parameter control difficult and unable to be directly adapted to existing BC battery mass production line equipment, resulting in high equipment modification costs and hindering the large-scale promotion of the technology.

[0009] In view of this, the present invention is hereby proposed. Summary of the Invention

[0010] The primary objective of this invention is to provide a back-contact battery that solves the problems of significant composite loss in the gap region, insufficient compatibility between passivation and isolation, high metallization cost, and low yield by setting a composite passivation isolation layer in the gap region, a low-temperature global passivation layer, and a low-silver-loss metallization structure.

[0011] The second objective of this invention is to provide a method for preparing the aforementioned back contact battery, which employs a low-temperature deposition process and conventional precursor materials, simplifies the process steps, adapts to existing back contact battery mass production line equipment, reduces equipment modification costs, improves process stability, and promotes the large-scale application of back contact batteries.

[0012] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: This invention provides a back contact battery, comprising: an N-type silicon substrate, an anti-reflection passivation layer, a composite passivation isolation layer, a global passivation layer, and a metallization structure; The front side of the N-type silicon substrate is sequentially provided with n + Front surface field and the anti-reflection passivation layer; The back side of the N-type silicon substrate has alternating p-type motifs. + emitter and n + Back field, the p + emitter and n + A gap region is formed between the back fields; The composite passivation isolation layer at least covers the gap region, and the composite passivation isolation layer includes an intrinsic amorphous silicon layer and an intrinsic SiO layer. x layer; The global passivation layer at least covers p. + emitter, n + Back field and the composite passivation isolation layer; The metallization structure includes a seed silver layer, a full-coverage copper layer, and an insulating protective layer; the seed silver layer fills the contact hole penetrating the global passivation layer and extends along the main gate line and fine gate line pattern on the surface of the global passivation layer; the full-coverage copper layer covers the surface of the seed silver layer; the insulating protective layer covers the edge of the full-coverage copper layer and covers the surface of the global passivation layer corresponding to the gap region.

[0013] Furthermore, it includes at least one of the following features (1) to (3); (1) The n + The sheet resistance of the front surface field is 20~40Ω; (2) The anti-reflection passivation layer includes a SiO2 layer and a SiN layer. x layer; (3) The total thickness of the anti-reflection passivation layer is 80~120nm.

[0014] Furthermore, it includes at least one of the following features (1) to (3); (1) The P + The sheet resistance of the emitter is 50~80Ω; (2) The n + The sheet resistance of the back field is 30~50Ω; (3) The P + emitter and n + The width of each back field is independently 0.8~1.2mm.

[0015] Furthermore, the width of the gap region is 100~150μm; And / or, the composite passivation isolation layer completely covers the gap region and extends to both sides of the p + emitter and n + The back field extends by 40~50μm respectively.

[0016] Furthermore, in the composite passivation isolation layer, the thickness of the intrinsic amorphous silicon layer is 2-5 nm; the intrinsic SiO... x The thickness of the layer is 5~10nm; the intrinsic amorphous silicon layer is close to the N-type silicon substrate, and the intrinsic SiO x The layer is located on the side of the intrinsic amorphous silicon layer away from the N-type silicon substrate.

[0017] Furthermore, the global passivation layer includes AlO. x Layers and SiN x Layer; the AlO x The thickness of the layer is 10~20nm, and the SiN x The thickness of the layer is 50~80nm.

[0018] Furthermore, it includes at least one of the following features (1) to (6); (1) The aperture of the contact hole is 50~80μm; (2) The pore density of the contact holes is 1000~1200 holes / cm². 2 ; (3) The thickness of the seed silver layer is 5~10μm; (4) The thickness of the full-coverage copper layer is 20~40μm; (5) The insulating protective layer includes SiN x layer; (6) The thickness of the insulating protective layer is 10~15nm.

[0019] The present invention also provides a method for preparing the back contact battery as described above, comprising the following steps: S1. Pre-treat the N-type single-crystal silicon wafer to obtain an N-type silicon substrate; S2. Sequentially prepare n on the front side of the N-type silicon substrate. + Front surface field and anti-reflection passivation layer; S3. Alternating p-shaped structures are fabricated on the back side of the N-type silicon substrate. + emitter and n + The back field is then used to deposit a composite passivation isolation layer and a global passivation layer sequentially using low-temperature PECVD. S4, in the p + emitter and n + Contact holes are provided above the back area; S5. Silver paste is printed onto the contact holes, main grid lines and fine grid lines using screen printing. After curing, a seed silver layer is obtained. Then, a full-coverage copper layer is deposited on the surface of the seed silver layer. Finally, an insulating protective layer is deposited.

[0020] Further, in step S3, the deposition method of the composite passivation isolation layer includes: using low-temperature PECVD to sequentially deposit an intrinsic amorphous silicon layer and an intrinsic SiO layer at 150~180℃. x layer.

[0021] Further, in step S3, the deposition method of the global passivation layer includes: using low-temperature PECVD to sequentially deposit AlO at 175~180℃. x Layers and SiN x layer.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: The back contact battery and its fabrication method provided by this invention, through the synergistic effect of the gap composite passivation isolation layer, the low-temperature global passivation layer, and the low-silver-loss metallization structure, can achieve reduced recombination loss, decreased silver consumption, improved yield, and enhanced reliability of the back contact battery; wherein, the intrinsic amorphous silicon and intrinsic SiO are disposed in the gap region. x The composite passivation isolation layer effectively passivates dangling bonds on the silicon surface and reduces interface state density, while providing excellent insulation performance, thereby significantly reducing recombination loss and lateral leakage. The low-temperature global passivation layer is deposited using a PECVD process at ≤180℃, which is fully compatible with the encapsulation isolation adhesive, avoiding film peeling and reliability degradation caused by high-temperature processes. The low-silver-loss metallization structure adopts a three-layer design of seed silver layer, full-coverage copper layer, and insulating protective layer, which significantly reduces silver consumption and metallization cost, while improving electrode conductivity and long-term stability. In addition, the entire process temperature is controlled below 180℃, and all processes use conventional precursor materials and existing production line equipment, without the need for additional dedicated equipment. It can be directly adapted to existing back contact battery mass production lines, with low equipment modification costs, which is conducive to large-scale industrialization. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a cross-sectional structural diagram of the back contact battery of the present invention.

[0025] Figure 2This is a line drawing of the back electrode pattern of the back contact battery of the present invention. Detailed Implementation

[0026] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0027] See Figure 1 In some embodiments of the present invention, a back contact (BC) battery is provided, comprising: an N-type silicon substrate, an anti-reflection passivation layer, a composite passivation isolation layer, a global passivation layer, and a metallization structure; The front side of the N-type silicon substrate is sequentially provided with n + Front surface field (n + -FSF) and anti-reflection passivation layer; The back side of the N-type silicon substrate has alternating p-type moieties. + emitter and n + Backstage, p + emitter and n + A gap region is formed between the back fields. The composite passivation isolation layer at least covers the gap region, and the composite passivation isolation layer includes an intrinsic amorphous silicon (a-Si) layer and an intrinsic SiO layer. x layer; The global passivation layer at least covers p + emitter, n + Back field and composite passivation isolation layer; The metallization structure includes a seed silver layer, a full-coverage copper layer, and an insulating protective layer. The seed silver layer fills the contact holes that penetrate the global passivation layer (electrically connected to the underlying doped region) and extends along the main gate line and fine gate line pattern on the surface of the global passivation layer. The full-coverage copper layer covers the surface of the seed silver layer. The insulating protective layer covers the edge of the full-coverage copper layer and covers the corresponding surface of the global passivation layer above the gap region.

[0028] The back contact battery of the present invention is a low-recombination, high-isolation, and low-temperature passivable back contact battery. Through the synergistic effect of the design of the gap region composite passivation isolation layer, the optimization of the low-temperature global passivation layer, and the design of the low-silver-loss metallization structure, the recombination loss of the back contact battery can be reduced, the silver loss can be decreased, the yield can be improved, and the reliability can be enhanced. It has low gap recombination, high isolation compatibility and low silver-loss metallization characteristics, thereby reducing the interface state density, suppressing lateral leakage and reducing the metallization cost.

[0029] This invention addresses the significant recombination loss in the gap region by designing an efficient recombination passivation isolation structure, thereby reducing the interface state density in the gap region, decreasing minority carrier recombination, and improving the open-circuit voltage and photoelectric conversion efficiency of the battery.

[0030] This invention addresses the problems of insufficient compatibility between passivation layers and isolation requirements, easy film detachment, and lateral leakage. By optimizing the passivation layer structure and material selection, it improves the interfacial adhesion and insulation performance of the passivation layer while maintaining low-temperature deposition (≤180℃), thereby enhancing battery reliability.

[0031] This invention addresses the problems of high silver consumption and low yield in metallization by designing a low-silver-consumption metallization structure to replace the traditional all-silver-paste printing process. This reduces silver consumption to below 30mg / piece while increasing the metallization yield to over 98%, significantly reducing manufacturing costs.

[0032] In some embodiments of the present invention, the thickness of the N-type silicon substrate is 150~180μm (e.g., 150μm, 160μm, 170μm or 180μm, etc.); the resistivity of the N-type silicon substrate is 1~3Ω·cm (e.g., 1Ω·cm, 2Ω·cm or 3Ω·cm, etc.).

[0033] N-type silicon substrates serve as the core carrier of batteries, providing a channel for carrier transport.

[0034] In some embodiments of the present invention, the front side of the N-type silicon substrate has a textured structure; preferably, the roughness of the front side of the N-type silicon substrate with the textured structure is 0.5~1.0 μm (e.g., 0.5 μm, 0.7 μm or 1 μm, etc.).

[0035] An N-type silicon substrate with a textured surface is used, which improves incident light absorption efficiency and reduces light reflection. The surface roughness of the N-type silicon substrate with the textured surface is 0.5~1.0μm, which is suitable for the deposition of the anti-reflection passivation layer on the front side, ensuring maximum light absorption efficiency.

[0036] In some embodiments of the present invention, n + Front surface field (n + The sheet resistance of the -FSF is 20~40Ω (e.g., 20Ω, 30Ω or 40Ω, etc.).

[0037] An n-type silicon substrate is formed on the front side. + The front surface field is used to collect front-side charge carriers and reduce carrier recombination.

[0038] In some embodiments of the present invention, the anti-reflection passivation layer includes a SiO2 layer and a SiN layer. x Layers; wherein, the SiO2 layer is close to the N-type silicon substrate, and the SiN layer is close to the N-type silicon substrate. x The layer is located on the side of the SiO2 layer away from the N-type silicon substrate.

[0039] In some embodiments of the present invention, the total thickness of the anti-reflection passivation layer is 80~120nm (e.g., 80nm, 100nm or 120nm, etc.).

[0040] In some embodiments of the present invention, the thickness of the SiO2 layer in the anti-reflection passivation layer is 10-20 nm (e.g., 10 nm, 15 nm, or 20 nm, etc.), and the thickness of the SiN layer is... x The thickness of the layer is 70~100nm (e.g., 70nm, 80nm, 90nm or 100nm).

[0041] In n + - An anti-reflection passivation layer of SiO2 / SiNx stacked is deposited on the surface of the FSF, with a total thickness of 80~120nm; wherein, the thickness of the SiO2 layer is 10~20nm and the thickness of the SiNx layer is 10~20nm. x The layer is 70~100nm thick, which can reduce the light reflectivity to below 5% and passivate the front interface to reduce carrier loss.

[0042] In some embodiments of the present invention, P + The sheet resistance of the emitter is 50~80Ω (e.g., 50Ω, 60Ω, 70Ω or 80Ω, etc.).

[0043] In some embodiments of the present invention, n + The sheet resistance of the back field is 30~50Ω (e.g., 30Ω, 40Ω or 50Ω, etc.).

[0044] In some embodiments of the present invention, P + emitter and n + The width of each back field is independently 0.8 to 1.2 mm (e.g., 0.8 mm, 1 mm, or 1.2 mm, etc.).

[0045] In some embodiments of the present invention, the width of the gap region is 100~150μm (e.g., 100μm, 130μm or 150μm, etc.).

[0046] In some embodiments of the present invention, the composite passivation isolation layer completely covers the gap region and extends to both sides of p + emitter and n + The back field extends by 40~50μm; preferably 50μm.

[0047] In some embodiments of the present invention, the thickness of the intrinsic amorphous silicon (a-Si) layer in the composite passivation isolation layer is 2-5 nm (e.g., 2 nm, 3 nm, 4 nm, or 5 nm, etc.), and the intrinsic SiO2 layer is... xThe thickness of the layer is 5~10nm (5nm, 8nm or 10nm, etc.); the intrinsic amorphous silicon layer is close to the N-type silicon substrate, and the intrinsic silicon oxide layer is located on the side of the intrinsic amorphous silicon layer away from the N-type silicon substrate.

[0048] To address the significant recombination loss in the interstitial region, an intrinsic a-Si layer with a thickness of 2–5 nm and an intrinsic SiO layer with a thickness of 5–10 nm are formed in the interstitial region. x The composite passivation isolation layer completely covers the gap area and extends to both sides P + emitter and n + The back surface area (p+ / n+ doped regions) extends to 40~50μm, forming a continuous passivation isolation structure. The intrinsic amorphous silicon layer is closely attached to the N-type silicon substrate, efficiently passivating dangling bonds on the silicon surface and reducing interface state density; the intrinsic SiO... x The layer is located above the intrinsic amorphous silicon layer, providing high insulation performance and preventing lateral leakage in the p+ / n+ region.

[0049] In some embodiments of the present invention, the global passivation layer includes AlO. x Layers and SiN x Layer; AlO x The layer thickness is 10~20nm (e.g., 10nm, 15nm, or 20nm, etc.), SiN x The layer thickness is 50~80nm (e.g., 50nm, 65nm, or 80nm, etc.); AlO x The layer is close to the N-type silicon substrate, SiN x Layer located in AlO x The side of the layer furthest from the N-type silicon substrate.

[0050] To address the issue of insufficient passivation layer compatibility, the entire back surface of the N-type silicon substrate (including P-type silicon) is treated with passivation layers. + emitter, n + AlO (with a thickness of 10-20 nm) is sequentially applied to the back field and composite passivation isolation layer. x Layers and SiN with a thickness of 50~80nm x This layer forms a global passivation layer. Among them, AlO x The layer can form a stable negative charge (Qf≈-5×10). 11 cm -2 ), achieving efficient field passivation; SiN x The layer further enhances the passivation effect, protecting the underlying composite passivation isolation layer and doped region.

[0051] In some embodiments of the present invention, the aperture of the contact hole is 50~80μm (e.g., 50μm, 60μm, 70μm or 80μm, etc.).

[0052] In some embodiments of the present invention, the pore density of the contact holes is 1000~1200 holes / cm². 2 (For example, 1000 pieces / cm) 2 1100 pieces / cm 2 Or 1200 pieces / cm 2 wait).

[0053] The contact holes are located in the p+ and n+ regions; in p + emitter and n + Contact holes are formed above the back field area, with a hole diameter of 50~80μm and a hole density of 1000~1200 holes / cm². 2 The contact holes are only opened in the p+ / n+ region, and not in the gap region. This ensures insulation, avoids lateral leakage, provides a channel for ohmic contact between the metal electrode and the p+ / n+ region, and reduces contact resistance.

[0054] In some embodiments of the present invention, the thickness of the seed silver layer is 5 to 10 μm (e.g., 5 μm, 8 μm or 10 μm, etc.).

[0055] In some embodiments of the present invention, the thickness of the full-coverage copper layer is 20~40μm (e.g., 20μm, 30μm or 40μm, etc.).

[0056] In some embodiments of the present invention, the insulating protective layer includes SiN. x layer.

[0057] In some embodiments of the present invention, the thickness of the insulating protective layer is 10-15 nm (e.g., 10 nm, 12 nm or 15 nm, etc.).

[0058] To address the issues of high silver consumption and low yield, a three-layer structure consisting of a seed silver layer, a full-coverage copper layer, and an insulating protective layer is adopted to replace the traditional all-silver paste printing process. The seed silver layer is located at the contact holes, main grid lines, and fine grid lines (consistent with the arrangement of the main and fine grid lines, see [reference]). Figure 2 The seed silver layer, with a thickness of 5-10 μm, acts as a conductive seed, significantly reducing the amount of silver required. A fully encapsulated copper layer, 20-40 μm thick, completely covers the seed silver layer, utilizing copper's low resistivity (1.7 μΩ·cm) to reduce electrode resistance and prevent oxidation of the seed silver layer. The insulating protective layer is made of SiN with a thickness of 10-15 nm. x A layer is placed at the edge and gap of the full-coverage copper layer to prevent copper ion migration, improve electrode isolation reliability, and avoid short circuit problems.

[0059] In some embodiments of the present invention, a method for preparing the above-mentioned back contact battery is provided, comprising the following steps: S1. Pre-treat the N-type single-crystal silicon wafer to obtain an N-type silicon substrate; S2. Sequentially fabricate n-type silicon substrates on the front side. + Front surface field and anti-reflection passivation layer; S3. Fabricate alternating p-type silicon substrates on the back side of an N-type silicon substrate. + emitter and n + The back field is then used to deposit a composite passivation isolation layer and a global passivation layer sequentially using low-temperature PECVD. S4, in p + emitter and n + Contact holes are provided above the back area; S5. Silver paste is printed onto the contact holes, main grid lines and fine grid lines using screen printing. After curing, a seed silver layer is obtained. Then, a full-coverage copper layer is deposited on the surface of the seed silver layer. Finally, an insulating protective layer is deposited.

[0060] The method for preparing back contact batteries of the present invention can achieve efficient, low-consumption, and high-yield mass production of back contact batteries, improve battery reliability, adapt to existing production line equipment, and lower the industrialization threshold.

[0061] To address the issue of poor process adaptability, this invention simplifies the passivation and metallization process steps, uses conventional precursor materials, adapts to existing back contact battery mass production line equipment, reduces equipment modification costs, improves process stability and mass production feasibility, and promotes the large-scale application of back contact batteries.

[0062] In some embodiments of the present invention, in step S1, the thickness of the N-type single crystal silicon wafer is 150~180μm and the resistivity is 1~3Ω·cm.

[0063] In some embodiments of the present invention, step S1 includes pretreatment including cleaning, front texturing, and back polishing.

[0064] After cleaning, the front side of the N-type monocrystalline silicon wafer is texturized. The roughness of the front side after texturization is 0.5~1.0μm. The texturization process adopts a conventional alkaline texturization process to form a textured surface structure, remove surface oil, oxide layer and impurities, and improve light absorption efficiency. Then, the back side of the N-type monocrystalline silicon wafer is polished to ensure flatness, laying the foundation for subsequent doping and passivation layer deposition.

[0065] In some embodiments of the present invention, in step S2, n + The method for preparing the front surface field includes phosphorus diffusion; preferably, the temperature of phosphorus diffusion is 850~900℃ (e.g., 850℃, 870℃ or 900℃, etc.), and the time is 30~40min (e.g., 30min, 35min or 40min, etc.); preferably, the equipment for phosphorus diffusion is a diffusion furnace.

[0066] An n-type silicon substrate is formed on its front side using a phosphorus diffusion process. + The front surface field (n+-FSF) controls the sheet resistance to be 20~40Ω.

[0067] In some embodiments of the present invention, step S2, the preparation of the anti-reflection passivation layer includes: sequentially depositing a SiO2 layer and a SiN layer using PECVD. x The deposition layer is then subjected to annealing; preferably, the deposition temperature is 175~180℃, the annealing temperature is 175~180℃, and the annealing time is 8~10min; preferably, the deposition temperature is 180℃, the annealing temperature is 180℃, and the annealing time is 10min.

[0068] SiO2 / SiN was deposited on the n+-FSF surface using PECVD. x The anti-reflection passivation layer is stacked, deposited at a temperature of 175~180℃, with a SiO2 layer thickness of 10~20nm and SiN... x The thickness of the layer is 70~100nm, and after deposition, it is annealed at 175~180℃ for 8~10min to ensure the adhesion of the film layer.

[0069] In some embodiments of the present invention, in step S3, alternating p-shaped patterns are formed on the back side of the N-type silicon substrate by laser patterning and diffusion processes. + emitter and n + Backstage, p + emitter and n + A gap region is formed between the back fields; preferably, P + The emitter is fabricated using boron diffusion, with a sheet resistance controlled to be 50~80Ω; n + The back field was prepared using phosphorus diffusion, with the sheet resistance controlled at 30~50Ω; p + emitter and n + The width of the back field is 0.8~1.2mm; p + emitter and n + The width of the gap region between the back fields is 100~150μm.

[0070] Alternating back-side doping (p+ emitter, n+ back field) and interstitial region formation: A laser patterning process is used to draw p+ and n+ doped regions corresponding to the fine gate line arrangement on the back side of the N-type silicon substrate (see [link to documentation]). Figure 2 ); p was prepared by boron diffusion using a mask diffusion process. + The emitter is then used to prepare n via phosphorus diffusion. + Back field, then remove the mask to form alternating p + emitter, n +Back field and interstitial region; the temperature for boron diffusion is 800~850℃ (e.g., 800℃, 820℃ or 850℃, etc.) and the time is 25~35min (25min, 30min or 35min, etc.); the temperature for phosphorus diffusion is 820~870℃ (e.g., 820℃, 850℃ or 870℃, etc.) and the time is 20~30min (20min, 25min or 30min, etc.).

[0071] In some embodiments of the present invention, step S3, the deposition method of the composite passivation isolation layer includes: using low-temperature PECVD, sequentially depositing an intrinsic amorphous silicon layer and an intrinsic SiO at 150~180℃ (e.g., 150℃, 160℃, 170℃ or 180℃, etc.). x layer.

[0072] The composite passivation isolation layer is deposited using a low-temperature PECVD process at 150~180℃, which does not require high-temperature annealing and is fully compatible with the subsequent encapsulation isolation adhesive.

[0073] In some embodiments of the present invention, step S3, the deposition method of the composite passivation isolation layer includes: sequentially depositing an intrinsic amorphous silicon layer and an intrinsic SiO layer. x Layer, forming a composite passivation isolation layer; the composite passivation isolation layer completely covers the gap area and extends to both sides p + emitter and n + The back field extends 40~50μm respectively; preferably, the deposition method of the composite passivation isolation layer is low-temperature PECVD, the deposition temperature is 150~180℃ (e.g., 150℃, 160℃, 170℃ or 180℃, etc.), the deposition power is 150~200W (e.g., 150W, 170W or 200W, etc.), the reaction gas includes silane, oxygen and argon, the silane flow rate is 50~80sccm, the oxygen flow rate is 30~50sccm, and the argon flow rate is 200~300sccm.

[0074] Using a low-temperature PECVD process of 150~180℃, an intrinsic amorphous silicon layer with a thickness of 2~5nm and an intrinsic SiO layer with a thickness of 5~10nm are deposited in the interstitial region. x Layer, forming a composite passivation isolation layer; ensuring the composite layer completely covers the gap area, and extends to both sides p + emitter and n + The back field extends by 40~50μm to form a continuous passivation isolation structure.

[0075] Design of interstitial region composite passivation isolation structure: using an intrinsic amorphous silicon layer with a thickness of 2~5nm and an intrinsic SiO layer with a thickness of 5~10nm. x The composite passivation isolation layer of the layer, the intrinsic amorphous silicon layer for efficient passivation of silicon surface dangling bonds, and the intrinsic SiO xThe layers achieve insulation and isolation, and the two work together to solve the problems of composite loss and lateral leakage in the gap area at the same time; the entire process is low-temperature deposition and is compatible with encapsulation and isolation adhesives.

[0076] In some embodiments of the present invention, in step S3, the global passivation layer deposition method includes: using low-temperature PECVD to sequentially deposit AlO at 175~180°C (e.g., 180°C). x Layers and SiN x layer.

[0077] In some embodiments of the present invention, step S3, the deposition of the global passivation layer includes: sequentially depositing AlO x Layers and SiN x A layer is formed to create a global passivation layer; preferably, the global passivation layer is deposited using low-temperature PECVD at a temperature of 175~180℃, with AlO₂... x The reaction gases for layer deposition include trimethylaluminum and oxygen, SiN x The reaction gases used in the layer deposition include silane and ammonia.

[0078] To address the issue of insufficient compatibility of the passivation layer, an AlO layer with a thickness of 10-20 nm was deposited on the entire back side (including p+ / n+ doped regions and a composite passivation isolation layer). x Layers with a thickness of 50~80nm SiN x This layer forms a global passivation layer. AlO x The layer is deposited using PECVD at 175~180℃, which can form a stable negative charge (Qf≈-5×10). 11 cm -2 ), achieving efficient field passivation; SiN x This layer further enhances the passivation effect, protecting the underlying composite passivation isolation layer and doped regions. This global passivation layer is deposited at low temperatures throughout the process and is compatible with both the composite passivation isolation layer and the encapsulation adhesive, preventing film peeling or adhesive damage caused by high temperatures.

[0079] Optimization of the low-temperature global passivation layer: using a low-temperature AlO layer with a thickness of 10~20nm. x Layers and SiN with a thickness of 50~80nm x The global passivation layer is deposited by PECVD at 175~180℃ without high-temperature annealing, achieving both efficient field passivation and interface passivation, and is compatible with composite passivation isolation layers and encapsulation isolation adhesives. Using conventional materials can reduce process costs and complexity, and solve the problems of poor passivation layer compatibility and high material costs.

[0080] In some embodiments of the present invention, in step S3, after the global passivation layer is deposited, it is annealed at 175~180°C for 10~15 min; preferably, it is annealed at 180°C for 15 min; to improve the film adhesion and passivation effect.

[0081] In some embodiments of the present invention, in step S4, a laser drilling process is used to drill holes in p. + emitter and n + Contact holes are provided above the back field area.

[0082] Using laser drilling technology, in p + emitter and n + Contact holes are made in the back field region with a diameter of 50~80μm and a hole density of 1000~1200 holes / cm². The hole positions are strictly controlled to ensure that no holes are made in the gap region to avoid damaging its insulation and to provide a channel for the subsequent ohmic contact between the metal electrode and the p+ / n+ region.

[0083] In some embodiments of the present invention, in step S5, the curing temperature is 175~180°C; preferably 180°C; and the curing time is 15~20 min (e.g., 15 min, 18 min or 20 min, etc.).

[0084] In some embodiments of the present invention, in step S5, the deposition method of the full-coverage copper layer includes electroplating or electroless copper plating; preferably, the electroplating temperature is 50~60°C and the current density is 2~3A / dm³. 2 The process after deposition also includes washing and drying.

[0085] In some embodiments of the present invention, step S5 includes the following method for depositing the insulating protective layer: using PECVD to deposit the insulating protective layer on the edge of the full-coverage copper layer and the global passivation layer corresponding to the gap region; preferably, the deposition temperature is 120~150°C.

[0086] To address the issues of high silver consumption and low yield, a three-layer structure consisting of a seed silver layer, a full-coverage copper layer, and an insulating protective layer is adopted to replace the traditional all-silver paste printing process. The seed silver layer uses low-temperature silver paste and is screen-printed onto the contact holes, main grid lines, and fine grid lines (within the same arrangement as the main grid lines and fine grid lines, see [reference]). Figure 2 Cured in an oven at 175~180℃ for 15~20min, forming a 5~10μm thick seed silver layer with silver consumption ≤30mg / piece, serving as a conductive seed and significantly reducing silver usage; Fully encapsulated copper layer: deposited on the surface of the seed silver layer using electroplating or chemical plating, with a thickness of 20~40μm, ensuring complete encapsulation of the seed silver layer, followed by cleaning and drying; utilizing the low resistivity of copper (1.7μΩ·cm) to reduce electrode resistance and prevent oxidation of the seed silver layer; Insulating protective layer: using SiN with a thickness of 10~15nm.x The copper layer is deposited by PECVD at the edges and gaps of the copper layer to prevent copper ion migration, improve electrode isolation reliability, and avoid short circuit problems.

[0087] The low-silver-consumption metallization structure design adopts a three-layer structure consisting of a seed silver layer, a full-coverage copper layer, and an insulating protective layer. The seed silver layer is cured at low temperature with a silver consumption of ≤30mg / piece. The full-coverage copper layer reduces resistance and prevents oxidation. The insulating protective layer prevents copper migration. This design replaces traditional full-silver paste printing, which can reduce costs while improving yield. It solves the problems of high silver consumption and low yield, and is in line with the trend of low-silver development in the photovoltaic industry.

[0088] The entire process temperature of this invention is ≤180℃, making it compatible with existing production line equipment.

[0089] Example 1 The method for preparing a back contact battery provided in this embodiment includes the following steps: S1. Select an N-type single crystal silicon wafer with a thickness of 160μm and a resistivity of 2Ω·cm, and perform cleaning, front alkaline texturing, and back polishing in sequence to obtain an N-type silicon substrate; the front surface roughness of the N-type silicon substrate is 0.8μm; S2. Place the N-type silicon substrate in a diffusion furnace and use phosphorus diffusion to prepare an n-type silicon substrate with a sheet resistance of 30Ω on the front side. + Front surface field; phosphorus diffusion temperature is 880℃, time is 35min; After phosphorus diffusion, a 15 nm thick SiO2 layer and an 85 nm thick SiN layer were sequentially deposited using PECVD. x The layer was deposited at a temperature of 180℃, and then annealed at 180℃ for 10 minutes to form an anti-reflection passivation layer. S3. Using laser patterning, p+ and n+ doped regions are patterned on the back side of an N-type silicon substrate; using mask diffusion, a p+ doped region with a sheet resistance of 65Ω is prepared by boron diffusion. + Emitter; boron diffusion temperature was 830℃, time was 30 min; then, an n-type electrode with a sheet resistance of 40 Ω was prepared by phosphorus diffusion. + Back field; phosphorus diffusion temperature was 850℃ for 25 min; then the mask was removed to form alternating p + emitter and n + Backstage, p + emitter and n + The width of the back field is 1mm, p + emitter and n + A gap region is formed between the back fields, and the width of the gap region is 130μm; An intrinsic amorphous silicon layer with a thickness of 3 nm and an intrinsic SiO layer with a thickness of 8 nm were sequentially deposited using low-temperature PECVD.x Layer, forming a composite passivation isolation layer; the composite passivation isolation layer completely covers the gap area and extends to both sides p + emitter and n + The back field was extended by 50 μm; the deposition temperature of the low-temperature PECVD was 180℃, the power was 170W, the reaction gases were silane, oxygen and argon, the flow rate of silane was 60 sccm, the flow rate of oxygen was 40 sccm, and the flow rate of argon was 250 sccm. AlO2 with a thickness of 15 nm was sequentially deposited on the entire surface of an N-type silicon substrate using low-temperature PECVD. x Layer and SiN with a thickness of 65nm x Layer; the deposition temperature of low-temperature PECVD is 180℃, AlO x The reaction gases for the layer deposition are trimethylaluminum and oxygen, SiN x The reaction gases for the layer deposition were silane and ammonia; after deposition, the layers were annealed at 180°C for 15 min. S4. Using laser drilling technology, in p + emitter and n + Contact holes are formed above the back field area. The diameter of the contact holes is 60 μm, and the pore density is 1100 holes / cm³. 2 No holes are made in the gap area; S5. Screen print silver paste onto the contact holes, main grid lines and fine grid lines, and cure in an oven at 180℃ for 20 minutes to form a seed silver layer with a thickness of 8μm. Silver consumption ≤30mg / piece. A 30 μm thick full-coverage copper layer was deposited on the surface of the seed silver layer by electroplating at a temperature of 50 °C and a current density of 2 A / dm³. 2 The silver layer completely encapsulates the seed; after deposition, it is washed and dried. Using PECVD, a 13 nm thick SiN layer was deposited on the global passivation layer corresponding to the edges and gap regions of the full-coverage copper layer at 130 °C. x layer.

[0090] Example 2 The method for preparing a back contact battery provided in this embodiment includes the following steps: S1. Select an N-type single crystal silicon wafer with a thickness of 150μm and a resistivity of 1Ω·cm, and perform cleaning, front alkaline texturing, and back polishing in sequence to obtain an N-type silicon substrate; the front surface roughness of the N-type silicon substrate is 0.5μm; S2. Place the N-type silicon substrate in a diffusion furnace and use phosphorus diffusion to prepare an n-type silicon substrate with a sheet resistance of 20Ω on the front side. + Front surface field; phosphorus diffusion temperature is 850℃, time is 30min; After phosphorus diffusion, a 10 nm thick SiO2 layer and a 70 nm thick SiN layer were sequentially deposited using PECVD. x The layer was deposited at a temperature of 180℃, and then annealed at 180℃ for 10 minutes to form an anti-reflection passivation layer. S3. Using laser patterning, p+ and n+ doped regions are patterned on the back side of an N-type silicon substrate; using mask diffusion, a p+ doped region with a sheet resistance of 50Ω is prepared by boron diffusion. + Emitter; boron diffusion temperature 800℃, time 25min; then phosphorus diffusion to prepare an n-type electrode with a sheet resistance of 30Ω. + Back field; phosphorus diffusion temperature was 820℃, time was 20 min; then the mask was removed to form alternating p + emitter and n + Backstage, p + emitter and n + The width of the back field is 0.8mm, p + emitter and n + A gap region is formed between the back fields, and the width of the gap region is 100μm; A 2 nm thick intrinsic amorphous silicon layer and a 5 nm thick intrinsic SiO layer were sequentially deposited using low-temperature PECVD. x Layer, forming a composite passivation isolation layer; the composite passivation isolation layer completely covers the gap area and extends to both sides p + emitter and n + The back field is extended by 50 μm; the deposition temperature of low-temperature PECVD is 180℃, the power is 150W, the reaction gases are silane, oxygen and argon, the silane flow rate is 50 sccm, the oxygen flow rate is 30 sccm, and the argon flow rate is 200 sccm. AlO2 with a thickness of 10 nm was sequentially deposited on the entire surface of an N-type silicon substrate using low-temperature PECVD. x Layer and SiN with a thickness of 50nm x Layer; the deposition temperature of low-temperature PECVD is 180℃, AlO x The reaction gases for the layer deposition are trimethylaluminum and oxygen, SiN x The reaction gases for the layer deposition were silane and ammonia; after deposition, the layers were annealed at 180°C for 15 min. S4. Using laser drilling technology, in p + emitter and n + Contact holes are formed above the back field area. The diameter of the contact holes is 50 μm, and the pore density is 1000 holes / cm². 2 No holes are made in the gap area; S5. Screen print silver paste onto the contact holes, main grid lines and fine grid lines, and cure in an oven at 180℃ for 15 minutes to form a seed silver layer with a thickness of 5μm. Silver consumption ≤30mg / tablet. A 20 μm thick full-coverage copper layer was deposited on the surface of the seed silver layer by electroplating at a temperature of 50 °C and a current density of 2 A / dm². 2 The silver layer completely encapsulates the seed; after deposition, it is washed and dried. Using PECVD, a 10 nm thick SiN layer was deposited on the global passivation layer corresponding to the edges and gap regions of the full-coverage copper layer at 120 °C. x layer.

[0091] Example 3 The method for preparing a back contact battery provided in this embodiment includes the following steps: S1. Select an N-type single crystal silicon wafer with a thickness of 180μm and a resistivity of 3Ω·cm, and perform cleaning, front alkaline texturing, and back polishing in sequence to obtain an N-type silicon substrate; the front surface roughness of the N-type silicon substrate is 1.0μm; S2. Place the N-type silicon substrate in a diffusion furnace and use phosphorus diffusion to prepare an n-type silicon substrate with a sheet resistance of 40Ω on the front side. + Front surface field; phosphorus diffusion temperature is 900℃, time is 40min; After phosphorus diffusion, a 20 nm thick SiO2 layer and a 100 nm thick SiN layer were sequentially deposited using PECVD. x The layer was deposited at a temperature of 180℃, and then annealed at 180℃ for 10 minutes to form an anti-reflection passivation layer. S3. Using laser patterning, p+ and n+ doped regions are patterned on the back side of an N-type silicon substrate; using mask diffusion, a p+ doped region with a sheet resistance of 80Ω is prepared by boron diffusion. + Emitter; boron diffusion temperature was 850℃, time was 35 min; then, an n-type electrode with a sheet resistance of 50 Ω was prepared by phosphorus diffusion. + Back field; phosphorus diffusion temperature was 870℃, time was 30 min; then the mask was removed to form alternating p + emitter and n + Backstage, p + emitter and n + The width of the back field is 1.2mm, p + emitter and n + A gap region is formed between the back fields, and the width of the gap region is 150μm; A 5 nm thick intrinsic amorphous silicon layer and a 10 nm thick intrinsic SiO layer were sequentially deposited using low-temperature PECVD. xLayer, forming a composite passivation isolation layer; the composite passivation isolation layer completely covers the gap area and extends to both sides p + emitter and n + The back field was extended by 50 μm; the deposition temperature of the low-temperature PECVD was 180℃, the power was 200W, and the reaction gases were silane, oxygen and argon. The flow rate of silane was 80 sccm, the flow rate of oxygen was 50 sccm, and the flow rate of argon was 300 sccm. AlO2 with a thickness of 20 nm was sequentially deposited on the entire surface of an N-type silicon substrate using low-temperature PECVD. x Layer and SiN with a thickness of 80nm x Layer; the deposition temperature of low-temperature PECVD is 180℃, AlO x The reaction gases for the layer deposition are trimethylaluminum and oxygen, SiN x The reaction gases for the layer deposition were silane and ammonia; after deposition, the layers were annealed at 180°C for 15 min. S4. Using laser drilling technology, in p + emitter and n + Contact holes are formed above the back field area. The diameter of the contact holes is 80 μm, and the pore density is 1200 holes / cm². 2 No holes are made in the gap area; S5. Screen print silver paste to the contact holes, main grid lines and fine grid lines, and cure in an oven at 180℃ for 20 minutes to form a seed silver layer with a thickness of 10μm. Silver consumption ≤30mg / tablet. A 40 μm thick full-coverage copper layer was deposited on the surface of the seed silver layer by electroplating at a temperature of 60 °C and a current density of 3 A / dm³. 2 The silver layer completely encapsulates the seed; after deposition, it is washed and dried. Using PECVD, a 15 nm thick SiN layer was deposited on the global passivation layer corresponding to the edges and gap regions of the full-coverage copper layer at 150 °C. x layer.

[0092] Comparative Example 1 The method for preparing the back contact battery provided in this comparative example includes the following steps: S1. Select an N-type single crystal silicon wafer with a thickness of 160μm and a resistivity of 2Ω·cm, and perform cleaning, front alkaline texturing, and back polishing in sequence to obtain an N-type silicon substrate; the front surface roughness of the N-type silicon substrate is 0.8μm; S2. Place the N-type silicon substrate in a diffusion furnace and use phosphorus diffusion to prepare an n-type silicon substrate with a sheet resistance of 30Ω on the front side. + Front surface field; phosphorus diffusion temperature is 880℃, time is 35min; After phosphorus diffusion, PECVD was used to sequentially deposit a 12 nm thick SiO2 layer and an 85 nm thick SiN layer on the front side of the N-type silicon substrate. x The layer was deposited at a temperature of 180℃, and then annealed at 180℃ for 10 minutes to form an anti-reflection passivation layer. S3. Using laser patterning, p+ and n+ doped regions are patterned on the back side of an N-type silicon substrate; using mask diffusion, a p+ doped region with a sheet resistance of 65Ω is prepared by boron diffusion. + Emitter; boron diffusion temperature was 830℃, time was 30 min; then, an n-type electrode with a sheet resistance of 40 Ω was prepared by phosphorus diffusion. + Back field; phosphorus diffusion temperature was 850℃ for 25 min; then the mask was removed to form alternating p + emitter and n + Backstage, p + emitter and n + The width of the back field is 1mm, p + emitter and n + A gap region is formed between the back fields, and the width of the gap region is 130μm; SiN with a thickness of 8 nm was deposited using low-temperature PECVD. x Layer, SiN x The layer completely covers the gap area; the deposition temperature of low-temperature PECVD is 180℃; AlO2 with a thickness of 15 nm was sequentially deposited on the entire surface of an N-type silicon substrate using low-temperature PECVD. x Layer and SiN with a thickness of 65nm x Layer; the deposition temperature of low-temperature PECVD is 170~190℃, AlO x The reaction gases for the layer deposition are trimethylaluminum and oxygen, SiN x The reaction gases for the layer deposition are silane and ammonia; no annealing treatment is required. S4. Using laser drilling technology, in p + emitter and n + Contact holes are formed above the back field area. The diameter of the contact holes is 60 μm, and the pore density is 1100 holes / cm³. 2 No holes are made in the gap area; S5. It adopts a whole silver paste screen printing process, which involves paste preparation, precise alignment, whole-sided printing, leveling and drying, and constant temperature curing at 180℃ to form a seed silver layer with a thickness of 12~18μm and a silver consumption of 125~135mg / piece.

[0093] Test case The photoelectric performance and reliability of the back contact batteries of Examples 1-3 and Comparative Example 1 were tested, and the results are shown in Table 1.

[0094] The decay rate was tested under thermal cycling (-40℃~85℃, 1000 cycles) and damp heat (85℃, 85%RH, 1000h).

[0095] Table 1

[0096] The composite loss is significantly reduced and the efficiency is significantly improved: The composite passivation isolation layer in Examples 1-3 can reduce the interface state density in the gap region from 3×10 in Comparative Example 1. 11 cm -2 Reduced to 7×10 10 cm -2 Below, the passivation efficiency is >95%, and the recombination rate in the interstitial region is <100s. -1 This effectively suppresses leakage current. Combined with the global low-temperature AlO₂ on the back side... x / SiN x The passivation layer improves battery Voc and PCE by more than 27%, with the finished product PCE reaching over 27%, which is better than the level of less than 26.5% in Comparative Example 1. It can specifically solve the problem of significant recombination loss in the gap region.

[0097] Excellent passivation and isolation compatibility, significantly enhanced reliability: All passivation layers are deposited at a low temperature of ≤180℃, fully compatible with the transparent separator used for back contact battery packaging (temperature resistance 150~200℃), avoiding film peeling and separator damage caused by high-temperature annealing. Simultaneously, the composite passivation separator exhibits excellent insulation performance. Combined with a hole-free design in the gap area, lateral leakage is effectively prevented. Thermal cycling and damp heat testing show a degradation rate of <2%, superior to the over 3% degradation rate of Comparative Example 1, thus resolving the issue of insufficient passivation and isolation compatibility.

[0098] The metallization process significantly reduces silver consumption and manufacturing costs: Using the metallization structure of this invention, silver consumption is ≤30mg / piece, less than 20% of that in Comparative Example 1 (125~135mg / piece). Combined with the low resistivity of copper, this reduces silver consumption while ensuring that electrode resistance does not increase. Based on current silver paste prices, the cost of metallization per surface is reduced by 35%~40%, alleviating the industrialization pain point of high silver consumption in back-contact batteries, enhancing market competitiveness, and solving the problem of high metallization costs in existing technologies.

[0099] Simple process, strong adaptability to mass production: The passivation layer uses conventional SiO2. x , a-Si, AlO x SiN xMaterials are readily available, requiring no dedicated precursors, resulting in low material costs and easy procurement. The manufacturing process utilizes existing PECVD, laser patterning, screen printing, and electroplating equipment from back-contact battery mass production lines, eliminating the need for additional specialized equipment. The process steps are simplified, parameters are easily controlled, and it can be directly adapted to existing production lines, minimizing equipment modification costs. This addresses the issue of poor compatibility with existing technologies and facilitates large-scale deployment.

[0100] Significantly improved metallization yield: The seed silver layer is printed only with main grid lines and fine grid lines, requiring lower printing precision than existing technologies using full silver paste printing; the copper layer fully encapsulates and protects the seed silver layer, avoiding short circuits and open circuits that are common in existing silver paste printing technologies. Simultaneously, the gap area is fully insulated, further reducing the risk of short circuits. Battery metallization yield has increased from ≤96% to ≥98%, improving mass production efficiency and reducing production costs.

[0101] The structure is stable and adaptable to various packaging scenarios: the composite passivation isolation layer and the global passivation layer are tightly bonded, and the film shedding rate is <0.1%; the copper layer full-encapsulation structure can effectively prevent silver and copper oxidation, and the insulating protective layer can prevent copper ion migration, making the battery adaptable to various packaging scenarios such as double glass and single glass. It has strong adaptability and wide applicability. Compared with the problem of single packaging adaptability of existing technologies, it has a wider range of industrial application value.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A back-contact battery, characterized in that, include: N-type silicon substrate, anti-reflection passivation layer, composite passivation isolation layer, global passivation layer and metallization structure; The front side of the N-type silicon substrate is sequentially provided with n + Front surface field and the anti-reflection passivation layer; The back side of the N-type silicon substrate has alternating p-type motifs. + emitter and n + Back field, the p + emitter and n + A gap region is formed between the back fields; The composite passivation isolation layer at least covers the gap region, and the composite passivation isolation layer includes an intrinsic amorphous silicon layer and an intrinsic SiO layer. x layer; The global passivation layer at least covers p. + emitter, n + Back field and the composite passivation isolation layer; The metallization structure includes a seed silver layer, a full-coverage copper layer, and an insulating protective layer; the seed silver layer fills the contact holes that penetrate the global passivation layer and extends along the main gate line and fine gate line pattern on the surface of the global passivation layer; The full-coverage copper layer covers the surface of the seed silver layer; the insulating protective layer covers the edge of the full-coverage copper layer and also covers the surface of the global passivation layer corresponding to the gap region.

2. The back contact battery according to claim 1, characterized in that, Includes at least one of the following features (1) to (3); (1) The n + The sheet resistance of the front surface field is 20~40Ω; (2) The anti-reflection passivation layer includes a SiO2 layer and a SiN layer. x layer; (3) The total thickness of the anti-reflection passivation layer is 80~120nm.

3. The back contact battery according to claim 1, characterized in that, Includes at least one of the following features (1) to (3); (1) The P + The sheet resistance of the emitter is 50~80Ω; (2) The n + The sheet resistance of the back field is 30~50Ω; (3) The P + emitter and n + The width of each back field is independently 0.8~1.2mm.

4. The back contact battery according to claim 1, characterized in that, The width of the gap region is 100~150μm; And / or, the composite passivation isolation layer completely covers the gap region and extends to both sides of the p + emitter and n + The back field extends by 40~50μm respectively.

5. The back contact battery according to claim 1, characterized in that, In the composite passivation isolation layer, the thickness of the intrinsic amorphous silicon layer is 2~5nm, and the intrinsic SiO2 layer... x The thickness of the layer is 5~10nm; the intrinsic amorphous silicon layer is close to the N-type silicon substrate, and the intrinsic SiO x The layer is located on the side of the intrinsic amorphous silicon layer away from the N-type silicon substrate.

6. The back contact battery according to claim 1, characterized in that, The global passivation layer includes AlO. x Layers and SiN x Layer; the AlO x The thickness of the layer is 10~20nm, and the SiN x The thickness of the layer is 50~80nm.

7. The back contact battery according to claim 1, characterized in that, Includes at least one of the following features (1) to (6); (1) The aperture of the contact hole is 50~80μm; (2) The pore density of the contact holes is 1000~1200 holes / cm². 2 ; (3) The thickness of the seed silver layer is 5~10μm; (4) The thickness of the full-coverage copper layer is 20~40μm; (5) The insulating protective layer includes SiN x layer; (6) The thickness of the insulating protective layer is 10~15nm.

8. The method for preparing a back contact battery according to any one of claims 1 to 7, characterized in that, Includes the following steps: S1. Pre-treat the N-type single-crystal silicon wafer to obtain an N-type silicon substrate; S2. Sequentially prepare n on the front side of the N-type silicon substrate. + Front surface field and anti-reflection passivation layer; S3. Alternating p-shaped structures are fabricated on the back side of the N-type silicon substrate. + emitter and n + The back field is then used to deposit a composite passivation isolation layer and a global passivation layer sequentially using low-temperature PECVD. S4, in the p + emitter and n + A contact hole is provided above the back field area; S5. Silver paste is printed onto the contact holes, main grid lines and fine grid lines using screen printing. After curing, a seed silver layer is obtained. Then, a full-coverage copper layer is deposited on the surface of the seed silver layer. Finally, an insulating protective layer is deposited.

9. The method for preparing a back contact battery according to claim 8, characterized in that, In step S3, the deposition method of the composite passivation isolation layer includes: using low-temperature PECVD to sequentially deposit an intrinsic amorphous silicon layer and an intrinsic SiO layer at 150~180℃. x layer.

10. The method for preparing a back contact battery according to claim 8, characterized in that, In step S3, the deposition method of the global passivation layer includes: using low-temperature PECVD to sequentially deposit AlO at 175~180℃. x Layers and SiN x layer.

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