A back contact battery and its preparation method

Abstract

This invention relates to the field of photovoltaic cell technology, and in particular to a back-contact cell and its fabrication method. The back-contact cell provided by this invention includes: an N-type silicon substrate, a three-dimensional stepped interdigitated structure, a laser stealth isolation structure, a partitioned metallization structure, and a segmented micro-busbar structure; the P-type substrate of the three-dimensional stepped interdigitated structure... + The launch area is higher than N + Base region; laser stealth isolation structure is set in P + Launch area and N + Between base regions, at a depth less than P + The thickness of the emitter region; the partitioned metallization structure includes silver and copper fine grids; the segmented micro-gate includes silver and copper micro-gates; both the silver and copper micro-gates include several gate segments. The back-contact battery of this invention, through the collaborative design of various structures, achieves reduced carrier transport loss, reduced metal cost, balanced heat dissipation, improved reliability, and adaptability to multiple scenarios.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a back contact cell and its preparation method. Background Technology

[0002] Back contact (BC) photovoltaic cells are the core development direction of high-efficiency crystalline silicon solar cells. Their core advantage lies in integrating the P / N contact area and metal electrodes entirely on the back of the silicon wafer, with no grid lines blocking the front side. This allows for 100% sunlight incidence, significantly improving light absorption efficiency and short-circuit current, which is significantly better than traditional photovoltaic cell technologies such as PERC and TOPCon.

[0003] As the photovoltaic industry iterates towards higher power, lower cost, and higher reliability, scenarios such as residential rooftops, building-integrated photovoltaics (BIPV), and portable photovoltaic devices place higher demands on the structural design and metallization solutions of BC cells. Currently, the back P / N region of BC cells (IBC, HPBC, etc.) mostly adopts a planar interdigitated structure, and the metallization is mostly an integral silver grid design. Although it can meet basic power generation needs, there are obvious bottlenecks in current transmission efficiency, metal cost control, and heat dissipation uniformity.

[0004] Currently, the structure of BC cells is as follows: using an N-type silicon substrate, with alternating planar P-type silicon atoms on the back side. + Launch area and N + The base region and the main gate are distributed in a planar interdigitated pattern, and electrical isolation is achieved through laser-etched insulating trenches; the metallization adopts an integral silver gate structure, with both the fine gate and the main gate made of high-purity silver, featuring a planar rigid design, fully covering P + N + The back of the area forms an ohmic contact; the back of the battery has no layered design, P + N + The region and the metal electrode are on the same plane, and heat dissipation relies solely on the thermal conductivity of the silver grid itself and a single insulating heat dissipation layer covering the back, without directional heat dissipation or zoned optimization design. The fabrication process of this BC cell is as follows: after silicon wafer pretreatment, a polycrystalline silicon layer is deposited by LPCVD process, then P / N region doping and annealing activation are achieved by photolithography masking and ion implantation, isolation trenches are formed by laser etching, followed by printing silver paste to form an integral silver grid electrode, metallization interconnection is completed by sintering, and finally an antireflection layer is deposited on the front side to complete the cell fabrication.

[0005] The aforementioned BC battery and its fabrication process are compatible with existing BC battery mass production equipment, but they have not been optimized for differentiated performance in terms of P / N region carrier transport characteristics and metallization costs, and have not broken through the technical framework of planar structure and single metallization; specifically, they have the following drawbacks: High carrier transport loss limits conversion efficiency improvement: planar interdigitated structure makes P +Launch area and N + With the base regions on the same plane, charge carriers need to travel a long distance laterally to reach the metal electrodes. The long transmission path and high resistance easily lead to carrier recombination losses, resulting in a low fill factor (FF) of the battery. This makes it impossible to fully utilize the high current advantage of BC batteries, and the conversion efficiency is difficult to exceed 26%, which is inconsistent with the current industry trend of BC battery efficiency exceeding 27%.

[0006] High metallization costs hinder large-scale promotion: The integrated silver grid design results in a large amount of silver paste used, with each cell using approximately 120-150mg of silver. Meanwhile, the price of silver continues to rise, making metallization costs account for more than 60% of non-silicon costs. This makes it impossible to achieve low-cost mass production of BC cells, limiting their promotion in the low-to-mid-end photovoltaic market. This contradicts the photovoltaic industry's demand for cost reduction and efficiency improvement, and is also the core cost disadvantage of BC cells compared to TOPCon and other routes.

[0007] Uneven heat dissipation and obvious hot spot effect: planar structure leads to P + N + The heat is concentrated on the same plane, and the thermal uniformity of the integral silver grid is poor, resulting in concentrated carrier recombination in P. + Heat cannot be dissipated quickly, easily forming hot spots and causing the battery temperature to rise by 25-35°C. For every 1°C increase in temperature, the conversion efficiency decreases by approximately 0.26%, while also accelerating battery aging, shortening its lifespan, and affecting long-term outdoor reliability.

[0008] Poor contact stability between the metal electrode and the P / N region: The contact between the integral silver gate and the planar P / N region is a surface contact, resulting in uneven contact pressure and a tendency for poor contact and cold solder joints. This leads to increased contact resistance, further increasing current transmission losses. Furthermore, the rigid silver gate has a significantly different coefficient of thermal expansion than the silicon wafer (silver 19×10⁻⁶). -6 / ℃, Silicon 3×10 -6 The silicon wafer is prone to silver gate detachment and microcracks due to temperature changes and mechanical stress, which reduces the yield of mass production and is the main point of yield loss in the mass production process.

[0009] Poor structural adaptability and inability to meet the needs of multiple scenarios: The rigid design of the planar interdigitated fingers and the overall silver grid is difficult to adapt to thin silicon wafers and flexible module scenarios below 130μm; moreover, the front light management effect is limited and the reflectivity is high, which cannot fully tap the light absorption potential of BC cells. This is inconsistent with the current development direction of BC cells towards thinner wafers and high bifaciality, and it is also difficult to adapt to the installation requirements of emerging application scenarios such as BIPV.

[0010] In view of this, the present invention is hereby proposed. Summary of the Invention

[0011] The primary objective of this invention is to provide a back-contact battery that solves the problems of high carrier transport loss, high metallization cost, uneven heat dissipation, poor stability, and poor structural adaptability in the prior art.

[0012] The second objective of this invention is to provide a method for preparing the aforementioned back contact battery, which is compatible with existing back contact battery mass production processes, requires no additional specialized equipment, and can directly achieve mass production.

[0013] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: This invention provides a back-contact battery, comprising: an N-type silicon substrate, a front anti-reflection layer, a three-dimensional stepped interdigitated structure, a laser stealth isolation structure, a partitioned metallization structure, and a segmented micro grid structure; The front antireflection layer is disposed on the front side of the N-type silicon substrate; The three-dimensional stepped interdigitated structure is disposed on the back side of the N-type silicon substrate, comprising alternating P-type interdigitated structures. + Launch area and N + The base region, the P + The height of the launch area is higher than that of N. + The height of the base region; The laser stealth isolation structure is disposed on P + The emission area and the N + Between the base regions, the depth of the laser stealth isolation structure is less than that of P. + The thickness of the emission region; the laser stealth isolation structure is filled with a SiO2 insulating layer; The partitioned metallization structure includes a component disposed in the P + The silver grid on the emission region and the N + Copper grid on the base region; The segmented micro gate includes components disposed on the P + The silver microgate on the emitter and the N-type + The base region contains a copper micro-gate; the silver micro-gate intersects perpendicularly with the silver fine gate; the copper micro-gate intersects perpendicularly with the copper fine gate; both the silver micro-gate and the copper micro-gate include several gate segments.

[0014] Furthermore, the P + The launch area and the N + The height difference of the base region is 3~8μm; And / or, the P + The emission area and the N + The interdigitation width of the base region is 200~300μm, and the spacing is 150~200μm.

[0015] Furthermore, the P +The emitter region is a boron-doped polycrystalline silicon layer with a thickness of 60-80 nm and a boron doping concentration of 7.5 × 10⁻⁶. 19 ~8×10 19 cm -3 ; And / or, the N + The base region is a phosphorus-doped polycrystalline silicon layer with a thickness of 60-80 nm and a phosphorus doping concentration of 3.5 × 10⁻⁶ nm. 19 ~4×10 19 cm -3 .

[0016] Furthermore, it includes at least one of the following features (1) to (3); (1) The width of the laser stealth isolation structure is 18~25μm; (2) The depth of the laser stealth isolation structure and the P + The difference in thickness of the emission region is 5~10nm; (3) The thickness of the SiO2 insulating layer is 10~15nm.

[0017] Furthermore, the linewidth of the silver grid is 12~18μm and the height is 10~15μm; And / or, the linewidth of the copper fine gate is 20~28μm and the height is 5~8μm.

[0018] Furthermore, the length of a single main grid segment of the segmented micro grid is 2-5 mm, and the spacing between adjacent main grid segments is 8-12 mm.

[0019] Furthermore, the front antireflection layer includes SiN x Anti-reflection layer; the SiN x The thickness of the antireflection layer is 70~90nm.

[0020] The present invention also provides a method for preparing the back contact battery as described above, comprising the following steps: S1. Pre-treat the N-type single crystal silicon wafer to obtain an N-type silicon substrate; S2. Deposit an intrinsic polycrystalline silicon layer on the back side of the N-type silicon substrate; S3. Boron ion implantation is performed on the P-region and phosphorus ion implantation is performed on the N-region of the intrinsic polycrystalline silicon layer, followed by annealing to form P... + Launch area and N + Base region; S4. Wet etching is used to etch the N... + The base region is etched down, so that the P + The height of the launch area is higher than that of N. + The height of the base region; S5, Etching the P+ The launch area and the N + A laser stealth isolation structure is formed in the region between the base regions; then a SiO2 insulating layer is deposited within the laser stealth isolation structure. S6. Screen printing is used on P + The emitter region is printed with a fine silver grid, in the N + Base region printed copper grid; S7, screen printing is used on P + The emitter region is printed with a silver microgate, in the N + Copper microgates are printed in the base area and then dried after printing. S8. Deposit a front antireflection layer on the front side of the N-type silicon substrate; S9. Perform sintering.

[0021] Furthermore, step S4 includes at least one of the following features (1) to (3); (1) The depth of the inscription is 3~8μm; (2) The etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid and nitric acid; (3) The temperature of the wet etching is 25~30℃ and the time is 5~8min.

[0022] Furthermore, in step S5, picosecond laser etching is used to etch the P... + The launch area and the N + In the region between the base regions, the laser power is 10~15W and the etching speed is 50~80mm / s.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: The back contact battery of the present invention achieves reduced carrier transport loss, reduced metal cost, balanced heat dissipation, improved reliability and adaptability to multiple scenarios through the coordinated design of a three-dimensional stepped interdigitated structure, a P / N differentiated metallization structure, a laser stealth isolation structure and a segmented micro grid. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a planar line drawing of the three-dimensional stepped interdigital structure of the present invention.

[0026] Figure 2 This is a line drawing of the laser stealth isolation groove of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0028] In some embodiments of the present invention, a back-contact battery is provided, comprising: an N-type silicon substrate, a front anti-reflection layer; a three-dimensional stepped interdigitated structure, a laser stealth isolation structure, a partitioned metallization structure, and a segmented micro grid structure; The anti-reflection layer is disposed on the front side of the N-type silicon substrate; A three-dimensional stepped interdigitated structure is disposed on the back side of an N-type silicon substrate, comprising alternating P-type interdigitated structures. + Launch area and N + base region, P + The launch zone is higher than N + The height of the base region; Laser stealth isolation structure set at P + The emission area and the N + Between the base regions, the depth of the laser stealth isolation structure is less than P. + The thickness of the emission region; the laser stealth isolation structure is filled with a SiO2 insulating layer; The partitioned metallization structure includes those set in P + The silver grid on the emitter and the setting at N + Copper grid on the base region; The segmented microgateway includes a section located at P + The silver microgate on the emitter and the N-type + The base region contains copper microgates; silver microgates intersect perpendicularly with silver fine gates; copper microgates intersect perpendicularly with copper fine gates; both silver and copper microgates include several gate segments.

[0029] The back contact battery of the present invention, featuring three-dimensional stepped interdigitated and partitioned metallization, solves the problems of high carrier transport loss, high metallization cost, uneven heat dissipation, poor stability, and poor structural adaptability in the prior art through the synergistic design of a three-dimensional stepped interdigitated structure, a P / N partitioned differentiated metallization structure, a laser stealth isolation structure, and a segmented micro grid structure. It can meet the industrial demand for mass production, low cost, high reliability, and multi-scenario adaptability of back contact batteries.

[0030] The back-contact battery of this invention features a three-dimensional stepped interdigitated structure design. By spatially layering, it shortens the lateral transport distance of charge carriers, reduces carrier recombination losses, improves the fill factor, and drives the conversion efficiency of the back-contact battery to exceed 26.5%, fully leveraging the high current advantage of the back-contact battery. This solves the problems of long carrier transport paths, high losses, and difficulty in achieving a conversion efficiency of over 26%.

[0031] The back contact battery of the present invention adopts a differentiated metallization scheme for the P-region and the N-region. The P-region uses a silver electrode and the N-region uses a copper electrode. While ensuring conductivity, the amount of silver used is greatly reduced, the metallization cost is lowered, and the cost bottleneck of large-scale promotion of back contact batteries is broken. This echoes the current development trend of silver-free back contact batteries and solves the problems of high metallization cost and large amount of silver paste used.

[0032] The back-contact battery of this invention, through a three-dimensional stepped spatial layering design and thermal conductivity difference adaptation of partitioned metallization, achieves directional heat dissipation from the P-region and N-region, reduces local temperature, suppresses hot spot effect, improves long-term outdoor reliability of the battery, and extends service life; it solves the problems of uneven heat dissipation and obvious hot spot effect.

[0033] The back contact battery of the present invention improves contact uniformity and reduces contact resistance by optimizing the contact method between the metal electrode and the P-region and N-region, and combining the bonding advantages of the three-dimensional stepped structure. At the same time, it selects a suitable metal material to reduce the difference in thermal expansion coefficient with the silicon wafer and improve the mass production yield. It solves the problems of poor contact stability between the metal electrode and the P-region and N-region, easy detachment, and easy microcracks in the silicon wafer.

[0034] The back-contact battery of this invention, through optimized three-dimensional stepped structure and flexible metal interconnect design, is adapted to thin silicon wafer and flexible module scenarios. At the same time, it optimizes front light management, reduces reflectivity, and improves bifaciality, adapting to the application needs of multiple scenarios such as residential and BIPV, and conforming to the development trend of thinner back-contact batteries and high bifaciality. It solves the problem of poor adaptability of back-contact structure and inability to meet the needs of multiple scenarios.

[0035] In some embodiments of the present invention, the N-type silicon substrate includes an N-type monocrystalline silicon substrate; the thickness of the N-type monocrystalline silicon substrate is 130~150μm, for example, 130μm, 140μm or 150μm, etc.; the resistivity of the N-type monocrystalline silicon substrate is 1.8~2.2Ω·cm, for example, 1.8Ω·cm, 2Ω·cm or 2.2Ω·cm, etc.

[0036] The N-type silicon substrate adopts a thin silicon wafer design, which balances mechanical strength and light absorption efficiency and is compatible with existing mass-produced silicon wafer specifications. The back side is polished to provide a flat substrate for subsequent polycrystalline silicon deposition, doping and structural shaping. As the mainstream substrate choice for back contact batteries, it has a mature mass production foundation and fits the industry's trend towards thinner wafers.

[0037] In some embodiments of the present invention, P + Launch area and N + The height difference of the base region is 3~8μm; for example, 3μm, 5μm or 8μm, etc.

[0038] In some embodiments of the present invention, P + Launch area and N + The interdigitation width of the base region is 200~300μm, for example, 200μm, 250μm or 300μm, etc.; P + Launch area and N + The spacing between the base regions is 150~200μm, for example, 150μm, 180μm or 200μm.

[0039] In some embodiments of the present invention, P + The emitter region is a boron-doped polycrystalline silicon layer; P + The thickness of the emitter region is 60~80nm, for example, 60nm, 70nm or 80nm, etc.; P + The boron doping concentration in the emitter region is 7.5 × 10⁻⁶. 19 ~8×10 19 cm -3 Preferably 8×10 19 cm -3 .

[0040] In some embodiments of the present invention, N + The base region is a phosphorus-doped polycrystalline silicon layer; N + The thickness of the base region is 60~80nm, for example, 60nm, 70nm or 80nm, etc.; N + The phosphorus doping concentration in the base region is 3.5 × 10⁻⁶. 19 ~4×10 19 cm -3 The preferred size is 4×10. 19 cm -3 .

[0041] See Figure 1 Three-dimensional stepped interdigitated structure on the back: P + Launch area and N + The base region employs an alternating interdigitated structure, and P + The launch area is higher than N + The base region forms a height difference, creating a three-dimensional stepped structure with a high P-region and a low N-region. This structure, through spatial layering, shortens the lateral transport distance of charge carriers by more than 40%, reduces carrier recombination losses, conforms to the theoretical laws of charge carrier transport, and optimizes the heat dissipation path, solving the problem of uneven heat dissipation in existing planar structures.

[0042] Parameter matching design of three-dimensional stepped interdigital structure: P + The launch area is higher than N + The 3-8μm height difference design of the base region precisely matches the optimization requirements of the carrier transport path, which shortens the transmission distance without affecting the electrode bonding and heat dissipation. At the same time, the parameter design of the interdigital width (200-300μm) and spacing (150-200μm) takes into account the effective power generation area and structural stability, which is the core key to improving conversion efficiency and conforms to the theoretical law of carrier transport.

[0043] In some embodiments of the present invention, the laser stealth isolation structure includes a laser stealth isolation groove.

[0044] In some embodiments of the present invention, the width of the laser stealth isolation structure is 18~25μm, for example, 18μm, 20μm or 25μm.

[0045] In some embodiments of the present invention, the depth of the laser stealth isolation structure and P + The thickness difference of the emission region is 5~10nm, for example, 5nm, 8nm or 10nm; that is, the bottom of the laser stealth isolation structure retains a silicon thin layer with a thickness of 5~10nm.

[0046] In some embodiments of the present invention, the thickness of the SiO2 insulating layer filled in the laser stealth isolation structure is 10~15nm, for example, 10nm, 12nm or 15nm.

[0047] See Figure 1 and Figure 2 The laser stealth isolation structure is located in P + Launch area and N + Between base regions, the depth does not penetrate P + Launch area and N +The base region does not cut into the N-type silicon substrate; a thin silicon layer is retained at the bottom of the trench to prevent exposure of the N-type silicon substrate. The trench is filled with a SiO2 insulating layer to achieve precise electrical isolation between the P-region and the N-region, while suppressing edge leakage and metal creep. Unlike the existing isolation trench design that directly penetrates the silicon substrate, this design ensures isolation while avoiding damage to the silicon substrate, has clear theoretical support and mass production feasibility, and meets the requirements of the patterning process on the back of the back contact battery.

[0048] Precise control of laser stealth isolation structure: The depth of the isolation trench is only etched into the polysilicon layer (60~80nm) without cutting into the silicon substrate. At the same time, a 5~10nm silicon thin layer is retained at the bottom of the trench, and the trench is filled with a SiO2 insulating layer. This achieves precise isolation of the P / N region and avoids leakage and metal creep caused by exposed silicon substrate.

[0049] In some embodiments of the present invention, the silver gate is located at P + On the emitter region, the linewidth of the silver grid is 12~18μm, for example, 12μm, 15μm or 18μm; the height of the silver grid is 10~15μm, for example, 10μm, 12μm or 15μm.

[0050] In some embodiments of the present invention, the copper fine gate is located at N. + On the base region, the linewidth of the copper fine gate is 20~28μm, for example, 20μm, 25μm or 28μm; the height of the copper fine gate is 5~8μm, for example, 5μm, 6μm or 8μm.

[0051] Differentiated metallization structure for P-region and N-region: Addressing the differences in carrier transport characteristics between the P-region and N-region, a differentiated metal electrode design is employed. The P-region uses a silver electrode, while the N-region uses a copper electrode, achieving a balance between high conductivity and low cost, echoing the current trend of de-silvering in back-contact batteries. + The emitter region uses silver electrodes, which have excellent conductivity and can reduce the contact resistance of the P-region (where contact resistance requirements are higher). At the same time, compared to existing technologies with integral silver grids, the amount of silver used is reduced by more than 70%. + The base region uses copper electrodes. Copper has conductivity close to that of silver (only 5% lower) and costs only about 1 / 10 of silver, which can significantly reduce metallization costs. At the same time, copper electrodes have excellent thermal conductivity, which can help dissipate heat from the N region. The low-temperature curing copper paste has its own antioxidant components. Combined with the SiO2 insulating layer in the laser stealth isolation structure, it blocks the lateral creep diffusion of metal plating, solving the problems of easy oxidation and diffusion of existing copper pastes, and adapting to the characteristics of back contact battery structure.

[0052] Material and parameter optimization for P / N zone metallization: targeting P + Zone (high contact resistance required) and N +Due to the differences in characteristics of the cost-sensitive region, a silver and copper metal system was selected; the parameter ratio of silver fine gate (12~18μm wide, 10~15μm high) and copper fine gate (20~28μm wide, 5~8μm high) was matched to achieve a balance between high conductivity and low cost.

[0053] In some embodiments of the present invention, the segmented microgate includes a silver microgate and a copper microgate; the silver microgate is located at P + Above the emitter area, and perpendicular to the silver microgate; the copper microgate is located at N. + It is located above the base region and intersects perpendicularly with the copper grid.

[0054] In some embodiments of the present invention, the length of a single main gate segment of the segmented micro main gate is 2-5 mm, for example, 2 mm, 3 mm or 5 mm; the spacing between adjacent main gate segments is 8-12 mm, for example, 8 mm, 10 mm or 12 mm; both the silver micro main gate and the copper micro main gate include several main gate segments with a length of 2-5 mm, the spacing between adjacent main gate segments of the silver micro main gate is 8-12 mm, and the spacing between adjacent main gate segments of the copper micro main gate is 8-12 mm.

[0055] Segmented micro-busbar structure: Replacing the traditional long busbar, it adopts a segmented design, with the P-region and N-region busbars made of the same material as the corresponding fine grids, intersecting perpendicularly with the fine grids. This structure reduces the shading of the effective power generation area on the back side by the busbar, while dispersing mechanical stress, reducing the risk of microcracks in the silicon wafer, improving the cell's resistance to microcracks, and adapting to thin silicon wafers and flexible module scenarios, further reducing the amount of silver and copper used and lowering costs.

[0056] The segmented micro-busbar structure design features segments with a length of 2-5mm and a spacing of 8-12mm. This design reduces the shading of the effective power generation area by the busbar and disperses mechanical stress, making it compatible with thin silicon wafers and flexible modules. At the same time, the busbar material is consistent with the corresponding fine busbar, ensuring the continuity of current transmission and reducing current transmission loss. This is the core key to improving reliability and adaptability.

[0057] In some embodiments of the present invention, the front antireflection layer includes SiN. x Anti-reflection layer; SiN x The thickness of the antireflection layer is 70~90nm, for example, 70nm, 80nm or 90nm.

[0058] The anti-reflection layer on the front side uses a single layer of SiN. x The anti-reflective layer is used to reduce front light reflection and improve light absorption efficiency. It fits the existing back contact battery front basic structure without increasing process complexity.

[0059] In some embodiments of the present invention, a method for preparing the above-mentioned back contact battery is also provided, comprising the following steps: S1. Pre-treat the N-type single crystal silicon wafer to obtain an N-type silicon substrate; S2. Deposit an intrinsic polycrystalline silicon layer on the back side of an N-type silicon substrate; S3. Boron ion implantation is performed on the P-region and phosphorus ion implantation is performed on the N-region on the intrinsic polycrystalline silicon layer, followed by annealing to form P... + Launch area and N + Base region; S4. Wet etching is used for N + The base region is etched down, so that P + The launch zone is higher than N + The height of the base region; S5, Etching P + Launch area and N + A laser stealth isolation structure is formed in the region between the base regions; then a SiO2 insulating layer is deposited within the laser stealth isolation structure. S6. Screen printing is used on P + The emitter region is printed with a fine silver grid, in N + Base region printed copper grid; S7. Screen printing is used on P + Printed silver microgate in the emitter region, in N + Copper microgates are printed in the base area and then dried after printing. S8. Deposit a front antireflection layer on the front side of an N-type silicon substrate; S9. Perform sintering.

[0060] The method for preparing the back contact battery of the present invention optimizes the structural deposition, etching and metallization steps based on the existing back contact battery mass production line, without the need for additional special equipment, and can directly achieve mass production.

[0061] In some embodiments of the present invention, in step S1, the pretreatment includes sequentially performing cleaning, front texturing, and back polishing; preferably, the front texturing includes alkali texturing.

[0062] N-type monocrystalline silicon wafer pretreatment: N-type monocrystalline silicon wafers are selected and sequentially cleaned, texturized on the front side, and polished on the back side. The front side texturing adopts an alkaline texturing process to form a pyramid textured surface, reducing light reflection (reflectivity ≤12%). The back side polishing removes surface impurities and damaged layers, providing a flat substrate for subsequent polycrystalline silicon deposition and doping, conforming to the existing back contact cell pretreatment process, and optimizing parameters to adapt to the subsequent structure.

[0063] In some embodiments of the present invention, in step S2, the intrinsic polycrystalline silicon layer deposition method includes LPCVD; preferably, LPCVD is used to deposit an intrinsic polycrystalline silicon layer with a thickness of 60~80nm on the back side of an N-type silicon substrate, the deposition temperature is 650~700℃ (e.g., 650℃, 680℃ or 700℃, etc.), and the deposition time is 30~40min (e.g., 30min, 35min or 40min, etc.).

[0064] Deposition of intrinsic polysilicon layer on the back: Using LPCVD process, an intrinsic polysilicon layer with a thickness of 60~80nm is deposited on the back of the silicon wafer at a deposition temperature of 650~700℃ and a deposition time of 30~40min. This ensures that the intrinsic polysilicon layer is tightly bonded to the N-type silicon substrate without gaps, laying the foundation for subsequent selective doping. It is a pre-process for back doping of back contact cells and is compatible with existing equipment.

[0065] In some embodiments of the present invention, in step S3, boron ion implantation is performed in the P-region and phosphorus ion implantation is performed in the N-region on the intrinsic polysilicon layer using photolithography and ion implantation processes. The implantation energy is 50-80 keV (e.g., 50 keV, 60 keV, or 80 keV, etc.). After implantation, the layer is annealed at 840-850°C (e.g., 850°C, etc.) for 15-20 min (e.g., 20 min, etc.) to form P. + Launch area and N + Base region.

[0066] P-region and N-region ion implantation doping and annealing activation: Boron ions were implanted into the P-region and phosphorus ions were implanted into the N-region using photolithography and ion implantation processes. After implantation, annealing was performed to activate the dopant ions and form P-region dopants. + Launch area and N + Base region. Compared with traditional diffusion processes, ion implantation can precisely control the doping concentration and area, reduce process complexity, and align with the development trend of selective doping in back contact batteries.

[0067] In some embodiments of the present invention, in step S4, the depth of the etching is 3~8μm (e.g., 3μm, 5μm or 8μm, etc.); the etching solution for wet etching includes a mixed solution of hydrofluoric acid and nitric acid; the temperature of wet etching is 25~30°C (e.g., 25°C, 28°C or 30°C, etc.), and the time is 5~8min (5min, 6min or 8min, etc.).

[0068] Wet etching to form a three-dimensional stepped structure: A photolithographic mask and anisotropic wet etching process are used, with a mixed solution of hydrofluoric acid and nitric acid as the etching solution, to form N... +The polysilicon layer in the base region is selectively etched down at an etching temperature of 25–30°C, an etching time of 5–8 min, and a etch depth of 3–8 μm. + The polysilicon layer in the emitter region is retained, forming a three-dimensional stepped interdigitated structure with high P-regions and low N-regions. The above etching parameters can precisely control the step height difference and avoid excessive etching that could damage the silicon substrate.

[0069] In some embodiments of the present invention, in step S5, picosecond laser etching is used to etch P. + Launch area and N + In the region between the base regions, the laser power is 10~15W (e.g., 10W, 12W or 15W, etc.), and the etching rate is 50~80mm / s (e.g., 50mm / s, 70mm / s or 80mm / s, etc.); preferably, the wavelength of the picosecond laser is 532nm.

[0070] In some embodiments of the present invention, in step S5, the method for depositing the SiO2 insulating layer includes PECVD.

[0071] Fabrication of laser-guided stealth isolation structure: P is etched using a picosecond laser (wavelength 532nm). + Launch area and N + In the region between the base regions, a laser power of 10-15W and an etching speed of 50-80mm / s are used, with the etching depth precisely controlled at 60-80nm. Only the polysilicon layer is etched without penetrating the silicon substrate, forming isolation trenches with a width of 18-25μm. Subsequently, a PECVD process is used to deposit a 10-15nm thick SiO2 insulating layer within the trench, filling the trench and covering the trench walls to achieve electrical isolation between the P and N regions. Simultaneously, a 5-10nm thick silicon layer is retained at the bottom of the trench to prevent silicon substrate exposure. The laser etching process is compatible with existing back-contact battery patterning equipment, requiring no additional equipment.

[0072] Precise control of laser etching parameters (power, speed) is crucial for ensuring isolation and structural integrity, and is essential for guaranteeing the electrical stability of the battery, meeting the requirements of the patterning process on the back of the battery.

[0073] In some embodiments of the present invention, in step S6, screen printing is used on P + The silver paste is printed in the launch area to form a silver grid, N + The base area is printed with copper paste to form a copper grid; the printing pressure is 0.3~0.5MPa (e.g., 0.3MPa, 0.4MPa or 0.5MPa, etc.), and the printing speed is 100~120mm / s (e.g., 100mm / s, 110mm / s or 120mm / s, etc.); preferably, the silver content in the silver paste is 85wt%~90wt%; the copper content in the copper paste is 90%~95%, and the copper paste includes an antioxidant; the curing temperature of the copper paste is 300℃.

[0074] Zoned metallization printing: Employing screen printing technology, different metal pastes are printed in different areas, adaptable to existing printing equipment, and meeting the mass production needs of metallization for back contact batteries. + Emitter region: Printed silver paste to form a fine grid with a linewidth of 12~18μm and a height of 10~15μm. N + Base area: Printed copper paste to form a fine grid with a line width of 20~28μm and a height of 5~8μm. The copper paste is low-temperature curing type (curing temperature is 300℃), which can be sintered in air without nitrogen protection, reducing process costs and solving the industry pain point of easy oxidation of copper paste.

[0075] The use of low-temperature curing copper paste solves the problem of copper's easy oxidation, which is the core key to reducing costs and echoes the current trend of silver removal in BC batteries.

[0076] In some embodiments of the present invention, in step S7, screen printing is used on P + Printed silver microgate in the emitter region, in N + Print copper microgates in the base area; after printing, dry at 180~200℃ (e.g., 180℃, 190℃ or 200℃, etc.) for 8~10 min (e.g., 8 min, 9 min or 10 min, etc.).

[0077] Segmented micro-gate printing: Using screen printing technology, silver micro-gates are printed in the P area and copper micro-gates are printed in the N area. The length of a single segment of the gate is 2~5mm and the spacing is 8~12mm, which intersects perpendicularly with the fine gate. After printing, it is dried to ensure that the metal paste adheres tightly to the polycrystalline silicon layer.

[0078] In some embodiments of the present invention, in step S8, the deposition method of the front antireflection layer is PECVD; preferably, the deposition method of the front antireflection layer includes: depositing the front antireflection layer on the front side of an N-type silicon substrate using PECVD, with a deposition temperature of 300~350℃ (e.g., 300℃, 320℃ or 350℃, etc.) and a deposition time of 15~20min (e.g., 15min, 18min or 20min, etc.).

[0079] Front-side anti-reflection layer deposition: Using PECVD process, a SiN layer with a thickness of 70~90nm is deposited on the front side of an N-type silicon substrate. x An antireflective layer reduces frontal light reflection and improves light absorption efficiency. It is deposited using a PECVD process and is compatible with existing mass production equipment.

[0080] In some embodiments of the present invention, step S9 includes sintering at 730~750°C for 5~8 minutes; preferably, sintering includes sintering at 750°C for 5 minutes.

[0081] Sintering: Sintering the solar cells strengthens the bond between the metal electrodes and the polycrystalline silicon layer, ensuring stable electrical performance.

[0082] The preparation steps of this invention are all compatible with existing back contact battery mass production equipment (LPCVD, PECVD, screen printing, picosecond laser etching equipment), without the need for additional special equipment. Only the parameters of etching, printing, and sintering are optimized to achieve seamless connection between structural optimization and mass production processes, reduce process upgrade costs, and are the core key to industrial application, meeting the needs of back contact battery mass production development.

[0083] Example 1 The back contact battery provided in this embodiment includes: an N-type silicon substrate, a front anti-reflection layer; a three-dimensional stepped interdigitated structure, a laser stealth isolation structure, a partitioned metallization structure, and a segmented micro grid structure; The N-type silicon substrate is an N-type single-crystal silicon substrate with a thickness of 140 μm and a resistivity of 2 Ω·cm; The front antireflection layer is an 80nm thick SiN layer. x An anti-reflection layer is disposed on the front side of an N-type silicon substrate; A three-dimensional stepped interdigitated structure is disposed on the back side of an N-type silicon substrate; the three-dimensional stepped interdigitated structure includes alternating P-type interdigitated structures. + Launch area and N + Base region; P + The emitter region is a boron-doped polycrystalline silicon layer with a thickness of 70 nm and a boron doping concentration of 8 × 10⁻⁶. 19 cm -3 N + The base region is a phosphorus-doped polycrystalline silicon layer with a thickness of 65 nm and a phosphorus doping concentration of 4 × 10⁻⁶. 19 cm -3 ;P + The launch zone is higher than N + The base region height is 5 μm; P + Launch area and N + The interdigitation width of the base region is 250 μm, and the spacing is 180 μm. The laser stealth isolation structure is set in P + Launch area and N + Laser cloaking isolation trench between base regions; the depth of the laser cloaking isolation trench is less than P. + The thickness of the emission region is 8nm (with an 8nm thick silicon layer retained at the bottom of the trench); the width of the laser stealth isolation trench is 20μm; the laser stealth isolation structure is filled with a 12nm thick SiO2 insulating layer; The partitioned metallization structure includes those set in P + The silver grid on the emitter and the setting at N +The base region has a copper fine gate; the silver fine gate has a linewidth of 15 μm and a height of 12 μm; the copper fine gate has a linewidth of 25 μm and a height of 6 μm. The segmented microgateway includes a section located at P + The silver microgate on the emitter and the N-type + The base region contains copper microgates; silver microgates intersect with silver fine gates perpendicularly; copper microgates intersect with copper fine gates perpendicularly; both silver and copper microgates include several gate segments with a length of 3mm, and the spacing between adjacent gate segments is 10mm.

[0084] The method for preparing a back contact battery provided in this embodiment includes the following steps: S1. The N-type monocrystalline silicon wafer is sequentially cleaned, the front side is alkaline texturing is performed and the back side is polished to obtain an N-type silicon substrate; S2. An intrinsic polycrystalline silicon layer with a thickness of 70 nm was deposited on the back side of an N-type silicon substrate using LPCVD at a deposition temperature of 680℃ and a deposition time of 35 min. S3. Using photolithography and ion implantation, boron ions are implanted into the P-region and phosphorus ions are implanted into the N-region on the intrinsic polysilicon layer, with an implantation energy of 50-80 keV. After implantation, the layer is annealed at 850℃ for 20 min to form P-type polysilicon. + Launch area and N + Base region; S4. Using photolithography and anisotropic wet etching processes, with a mixed solution of hydrofluoric acid and nitric acid as the etching solution, N... + The polysilicon layer in the base region was selectively etched at an etching temperature of 28°C for 7 minutes to a depth of 5 μm. + The polysilicon layer in the emitter region is retained, allowing P + The launch zone is higher than N + The base region has a height of 5μm, forming a three-dimensional stepped interdigitated structure; S5. P is etched using a picosecond laser (wavelength 532nm). + Launch area and N + In the region between the base regions, the laser power is 12W, the etching rate is 70mm / s, and the etching depth is 62nm to form a laser stealth isolation trench; then, a SiO2 insulating layer is deposited in the laser stealth isolation trench using PECVD. S6. Screen printing is used on P + The silver paste is printed in the launch area to form a silver grid, N + The base area is printed with copper paste to form a copper grid; the printing pressure is 0.4 MPa and the printing speed is 110 mm / s; the silver content in the silver paste is 88 wt%; the copper content in the copper paste is 92% and includes antioxidants; the curing temperature of the copper paste is 300℃. S7. Screen printing is used on P + Printed silver microgate in the emitter region, in N + Print copper microgates in the base area; after printing, dry at 200℃ for 10 min; S8. A front antireflection layer is deposited on the front side of an N-type silicon substrate using PECVD at a temperature of 320°C for 18 minutes. S9. Sinter at 750℃ for 5 minutes.

[0085] Example 2 The back contact battery provided in this embodiment is similar to that in Embodiment 1, except that P + The thickness of the emitter region is 63 nm, N + The thickness of the base region is 60 nm; P + The launch zone is higher than N + The base region height is 3 μm; P + Launch area and N + The interdigitation width of the base region is 200 μm, and the spacing is 150 μm; the depth of the laser stealth isolation trench is less than P. + The emitter region has a thickness of 5nm (with a 5nm thick silicon layer retained at the bottom of the trench); the laser stealth isolation trench has a width of 18μm; the SiO2 insulating layer has a thickness of 10nm; the silver microgate has a linewidth of 12μm and a height of 10μm; the copper microgate has a linewidth of 20μm and a height of 5μm; both the silver and copper microgates consist of several 2mm long gate segments, with an 8mm spacing between adjacent gate segments.

[0086] The back-contact battery fabrication method provided in this embodiment is the same as in Embodiment 1, except that in step S2, an intrinsic polycrystalline silicon layer with a thickness of 63 nm is deposited on the back side of an N-type silicon substrate using LPCVD at a deposition temperature of 650°C for 30 min; and in step S4, the etching temperature is 25°C, the etching time is 5 min, and the etching depth is 3 μm. + The polysilicon layer in the emitter region is retained, allowing P + The launch zone is higher than N + The height of the base region is 3μm; in step S5, the laser power is 10W, the etching rate is 50mm / s, and the etching depth is 58nm.

[0087] Example 3 The back contact battery provided in this embodiment is similar to that in Embodiment 1, except that P + The thickness of the emitter region is 80 nm, N + The thickness of the base region is 72 nm; P + The launch zone is higher than N + The base region height is 8 μm; P +Launch area and N + The interdigitation width of the base region is 300 μm, and the spacing is 200 μm; the depth of the laser stealth isolation trench is less than P. + The emitter region is 10 nm thick (with a 10 nm thick silicon layer retained at the bottom of the trench); the laser stealth isolation trench is 25 μm wide; the SiO2 insulating layer is 15 nm thick; the silver microgate has a linewidth of 18 μm and a height of 15 μm; the copper microgate has a linewidth of 28 μm and a height of 8 μm; both the silver and copper microgates consist of several 5 mm long gate segments, with a 12 mm spacing between adjacent gate segments.

[0088] The back-contact battery fabrication method provided in this embodiment is the same as in Embodiment 1, except that in step S2, an intrinsic polycrystalline silicon layer with a thickness of 80 nm is deposited on the back side of an N-type silicon substrate using LPCVD at a deposition temperature of 700°C for 40 min; and in step S4, the etching temperature is 30°C, the etching time is 8 min, and the etching depth is 8 μm. + The polysilicon layer in the emitter region is retained, allowing P + The launch zone is higher than N + The height of the base region is 8 μm; in step S5, the laser power is 15 W, the etching rate is 80 mm / s, and the etching depth is 70 nm.

[0089] Comparative Example 1 The back contact cell provided in this comparative example includes: an N-type silicon substrate, a P-type silicon substrate, and a P-type silicon substrate. + Launch area, N + Base region, isolation groove and integral silver grid structure; The N-type silicon substrate is an N-type single-crystal silicon substrate with a thickness of 140 μm and a resistivity of 2 Ω·cm; The front antireflection layer is an 80nm thick SiN layer. x An anti-reflection layer is disposed on the front side of an N-type silicon substrate; Alternating P atoms are disposed on the back side of the N-type silicon substrate. + Launch area and N + The base region and the two are distributed in a planar interdigitated pattern; P + The emitter region is a boron-doped polycrystalline silicon layer with a thickness of 70 nm and a boron doping concentration of 8 × 10⁻⁶. 19 cm -3 N + The base region is a phosphorus-doped polycrystalline silicon layer with a thickness of 70 nm and a phosphorus doping concentration of 4 × 10⁻⁶. 19 cm -3 ;P + Launch area and N + The interdigitation width of the base region is 200~300μm, and the spacing is 150~200μm; P +Launch area and N + An isolation trench with a depth of 70nm and a width of 20μm (i.e., penetrating the polysilicon layer to the surface of the silicon substrate) is provided between the base regions, and the isolation trench is filled with a SiO2 insulating layer with a thickness of 12nm. P + On the launch area and N + Each base region is equipped with a silver grid and a silver main grid; the silver grid fully covers P + Launch area and N + In the base region, the silver main grid and the silver fine grid intersect perpendicularly; the linewidth of the silver fine grid is 12~18μm and the height is 10~15μm; the silver main grid is a continuous silver main grid, which perpendicularly crosses and covers all the fine grids, running through the entire back P region and N region. The P region and N region share the same continuous silver main grid, without partitioned differentiated materials or segmented cutouts. The method for preparing the back contact battery provided in this comparative example includes the following steps: S1. The N-type monocrystalline silicon wafer is sequentially cleaned, the front side is alkaline texturing is performed and the back side is polished to obtain an N-type silicon substrate; S2. An intrinsic polycrystalline silicon layer with a thickness of 70 nm was deposited on the back side of an N-type silicon substrate using LPCVD at a deposition temperature of 680℃ and a deposition time of 35 min. S3. Using photolithography and ion implantation, boron ions are implanted into the P-region and phosphorus ions are implanted into the N-region on the intrinsic polysilicon layer, with an implantation energy of 50-80 keV. After implantation, the layer is annealed at 850℃ for 20 min to form P-type polysilicon. + Launch area and N + Base region; S4. P is etched using a picosecond laser (wavelength 532nm). + Launch area and N + In the region between the base regions, the laser power is 15W, the etching rate is 80mm / s, and the etching depth is 70nm to form an isolation trench; then, a SiO2 insulating layer is deposited in the isolation structure using PECVD. S5, using screen printing on P + Launch area and N + The base area is printed with silver paste to form a silver grid; S6. Screen printing is used on P + Launch area and N + Silver main grid printed in base area; S7. A front antireflection layer is deposited on the front side of an N-type silicon substrate using PECVD at a temperature of 320°C for 18 minutes. S8. Sinter at 750℃ for 5 minutes.

[0090] Test case The back contact batteries prepared in Examples 1-3 and Comparative Example 1 were tested for electrical performance, metallization cost, heat dissipation performance, contact resistance and mass production yield. The results are shown in Figure 1.

[0091] In Table 1, the silver usage and metallization cost are based on Comparative Example 1. The contact resistance is the contact resistance between the metal electrode and the P / N region.

[0092] Table 1

[0093] Carrier transport losses are significantly reduced and conversion efficiency is significantly improved: The three-dimensional stepped interdigitated structure shortens the lateral transport distance of carriers by more than 40% through spatial layering, reducing carrier recombination losses; Compared with Comparative Example 1, the fill factor of the back contact battery in Examples 1-3 is increased by 2.0% to more than 82.8%, and the conversion efficiency exceeds 26.5%, giving full play to the high current advantage of the back contact battery, which is in line with the current industry trend of back contact battery efficiency exceeding 27%, while the optimization of the front anti-reflection layer further improves the light absorption efficiency.

[0094] Significantly reduced metallization costs drive large-scale adoption: A differentiated metallization scheme is adopted for P / N regions, using silver in the P region (reducing the amount used) and copper in the N region instead of silver. This reduces the amount of silver used in the back contact cells of Examples 1-3 by more than 70% compared to Comparative Example 1, lowers the metallization cost by 30%-40%, and reduces the proportion of metallization cost to non-silicon cost to below 30%. This breaks through the cost bottleneck for the large-scale promotion of back contact cells, responds to the photovoltaic industry's demand for cost reduction and efficiency improvement, and at the same time, the application of copper paste solves the pain point of the high cost of existing silver paste, demonstrating significant economic benefits for mass production.

[0095] Improved heat dissipation uniformity and complete suppression of hot spot effect: The spatial layering design of the three-dimensional stepped structure, combined with the differentiated thermal conductivity of copper electrodes (high thermal conductivity) and silver electrodes (suitable for P-area heat dissipation), achieves P-area heat dissipation uniformity. + N + The directional heat dissipation in the area reduces the local temperature of the back contact battery in Examples 1-3 by more than 25°C, suppresses the hot spot effect by ≥90%, improves temperature stability, extends battery life by 5-8 years, enhances long-term outdoor reliability, and solves the aging problem caused by the hot spot effect of existing back contact batteries.

[0096] Improved contact stability and significantly increased mass production yield: The three-dimensional stepped structure makes the contact between the metal electrode and the P / N region more uniform. The contact resistance of Examples 1-3 is 0.69-0.78 mΩ, which is more than 37% lower than the 1.25 mΩ of Comparative Example 1, avoiding problems such as poor contact and cold solder joints; at the same time, the thermal expansion coefficient of the copper electrode (16.5 × 10⁻⁶) is also improved. -6The temperature (°C) is closer to that of a silicon wafer. Combined with a segmented micro grid to disperse mechanical stress, the occurrence of silver grid shedding and silicon wafer microcracks is reduced by more than 90%. The mass production yield of the cells in Examples 1 to 3 is 95.7% to 96.5%, which is 5.8% to 6.6% higher than that of Comparative Example 1 (89.9%). This reduces mass production costs and after-sales risks, and solves the pain point of low mass production yield of existing back contact cells.

[0097] With strong structural adaptability, it meets the needs of multiple application scenarios: The flexible design of the three-dimensional stepped structure and segmented micro grid can be adapted to thin silicon wafers and flexible modules below 130μm; at the same time, it reduces grid shading, increases the effective power generation area on the back, reduces back reflectivity by more than 8%, and increases bifaciality to more than 75%, making it suitable for multiple application scenarios such as residential rooftops, BIPV, and portable photovoltaic equipment. It fits the development trend of thinner back contact batteries and high bifaciality, and broadens the application range of back contact batteries.

[0098] Although the present invention has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, without departing from the spirit and scope of the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention; therefore, this means that all such substitutions and modifications that fall within the scope of the present invention are included in the appended claims.

Claims

1. A back-contact battery, characterized in that, Including: N-type silicon substrate, front anti-reflection layer, three-dimensional stepped interdigitated structure, laser stealth isolation structure, partitioned metallization structure and segmented micro gate structure; The front antireflection layer is disposed on the front side of the N-type silicon substrate; The three-dimensional stepped interdigitated structure is disposed on the back side of the N-type silicon substrate, comprising alternating P-type interdigitated structures. + Launch area and N + The base region, the P + The height of the launch area is higher than that of N. + The height of the base region; The laser stealth isolation structure is disposed on P + The emission area and the N + Between the base regions, the depth of the laser stealth isolation structure is less than that of P. + The thickness of the emission region; the laser stealth isolation structure is filled with a SiO2 insulating layer; The partitioned metallization structure includes a component disposed in the P + The silver grid on the emission region and the N + Copper grid on the base region; The segmented micro gate includes components disposed on the P + The silver microgate on the emitter and the N-type + The base region contains a copper micro-gate; the silver micro-gate intersects perpendicularly with the silver fine gate; the copper micro-gate intersects perpendicularly with the copper fine gate; both the silver micro-gate and the copper micro-gate include several gate segments.

2. The back contact battery according to claim 1, characterized in that, The P + The launch area and the N + The height difference of the base region is 3~8μm; And / or, the P + The emission area and the N + The interdigitation width of the base region is 200~300μm, and the spacing is 150~200μm.

3. The back contact battery according to claim 1, characterized in that, The P + The emitter region is a boron-doped polycrystalline silicon layer with a thickness of 60-80 nm and a boron doping concentration of 7.5 × 10⁻⁶. 19 ~8×10 19 cm -3 ; And / or, the N + The base region is a phosphorus-doped polycrystalline silicon layer with a thickness of 60-80 nm and a phosphorus doping concentration of 3.5 × 10⁻⁶ nm. 19 ~4×10 19 cm -3 .

4. The back contact battery according to claim 1, characterized in that, Includes at least one of the following features (1) to (3); (1) The width of the laser stealth isolation structure is 18~25μm; (2) The depth of the laser stealth isolation structure and the P + The difference in thickness of the emission region is 5~10nm; (3) The thickness of the SiO2 insulating layer is 10~15nm.

5. The back contact battery according to claim 1, characterized in that, The linewidth of the silver grid is 12~18μm, and the height is 10~15μm; And / or, the linewidth of the copper fine gate is 20~28μm and the height is 5~8μm.

6. The back contact battery according to claim 1, characterized in that, The segmented micro grid has a single grid segment length of 2-5 mm and a spacing of 8-12 mm between adjacent grid segments.

7. The back contact battery according to claim 1, characterized in that, The front antireflection layer includes SiN. x Anti-reflection layer; the SiN x The thickness of the antireflection layer is 70~90nm.

8. The method for preparing the back contact battery according to any one of claims 1 to 7, characterized in that, Includes the following steps: S1. Pre-treat the N-type single crystal silicon wafer to obtain an N-type silicon substrate; S2. Deposit an intrinsic polycrystalline silicon layer on the back side of the N-type silicon substrate; S3. Boron ion implantation is performed on the P-region and phosphorus ion implantation is performed on the N-region of the intrinsic polycrystalline silicon layer, followed by annealing to form P... + Launch area and N + Base region; S4. Wet etching is used to etch the N... + The base region is etched down, so that the P + The height of the launch area is higher than that of N. + The height of the base region; S5, Etching the P + The launch area and the N + The region between the base regions forms a laser stealth isolation structure; Then, a SiO2 insulating layer is deposited within the laser stealth isolation structure; S6. Screen printing is used on P + The emitter region is printed with a fine silver grid, in the N + Base region printed copper grid; S7, screen printing is used on P + The emitter region is printed with a silver microgate, in the N + Copper microgates are printed in the base area and then dried after printing. S8. Deposit a front antireflection layer on the front side of the N-type silicon substrate; S9. Perform sintering.

9. The method for preparing a back contact battery according to claim 8, characterized in that, Step S4 includes at least one of the following features (1) to (3); (1) The depth of the inscription is 3~8μm; (2) The etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid and nitric acid; (3) The temperature of the wet etching is 25~30℃ and the time is 5~8min.

10. The method for preparing a back contact battery according to claim 8, characterized in that, In step S5, picosecond laser is used to etch the P + The launch area and the N + In the region between the base regions, the laser power is 10~15W and the etching speed is 50~80mm / s.

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