Back contact solar cell, method of manufacturing the same and photovoltaic system

Abstract

The application provides a back contact solar cell, a preparation method thereof and a photovoltaic system, and relates to the technical field of back contact solar cells. The back contact solar cell comprises a silicon substrate, a positive electrode and a negative electrode. The back surface of the silicon substrate is based on an isolation region, and a P region and an N region are formed at intervals. A first silicon oxide isolation film is arranged on the isolation region. A second silicon oxide isolation film is arranged on one side of a first doped layer close to the isolation region. A third silicon oxide isolation film is arranged on one side of a second doped layer close to the isolation region. The positive electrode forms ohmic contact with the first doped layer. The negative electrode forms ohmic contact with the second doped layer. The technical scheme provided by the application can greatly improve the isolation effect between the P region and the N region, effectively reduce the risk of electric leakage of the back contact solar cell, and does not need to etch the silicon substrate when forming the isolation region, thereby not increasing the risk of mechanical load failure of the back contact solar cell.

Description

Technical Field

[0001] This application relates to the field of back-contact solar cell technology, specifically to a back-contact solar cell, its fabrication method, and a photovoltaic system. Background Technology

[0002] Back-contact solar cells are a type of solar cell where all metal contacts are located on the back of the cell. The main advantage of back-contact solar cells is that they maximize the light-receiving area on the front of the cell, thereby improving photoelectric conversion efficiency. In back-contact solar cells, the PN junction and metal contacts are all located on the back of the cell. The P-doped and N-doped regions are arranged in an alternating forked pattern. To prevent leakage caused by contact between the P-doped and N-doped regions, isolation trenches are typically placed between them.

[0003] Currently, the silicon wafer thickness for back-contact solar cells is trending towards thinner wafers. Thinner wafers help reduce production costs, but as the wafer thickness decreases, the risk of mechanical failure in solar cell modules increases significantly. For back-contact solar cells with isolation trenches to separate P-doped and N-doped regions, as the trench depth increases, the risk of leakage due to contact between the P-doped and N-doped regions decreases. However, the substrate silicon is more prone to microcracks, and the bending resistance of the solar cell module decreases, resulting in a higher risk of mechanical failure.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a back-contact solar cell, its fabrication method, and a photovoltaic system. The P-region and N-region are isolated by an isolation region. The first doped layer and the second doped layer are isolated by a second silicon oxide isolation film and a third silicon oxide isolation film. The isolation region is also provided with a first silicon oxide isolation film, which can significantly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back-contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate, and it will not increase the risk of mechanical load failure of the back-contact solar cell.

[0006] To achieve the above objectives, this application adopts the following technical solution: A back-contact solar cell includes a silicon substrate, a positive electrode, and a negative electrode; The back side of the silicon substrate includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; a first silicon oxide isolation film is disposed on the isolation region; The P-region includes a first doped layer, and a second silicon oxide isolation film is disposed on the side of the first doped layer near the isolation region, and the second silicon oxide isolation film is located within the P-region. The N-region includes a second doped layer, and a third silicon oxide isolation film is disposed on the side of the second doped layer near the isolation region, and the third silicon oxide isolation film is located within the N-region; The positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

[0007] In some embodiments, the thickness of the first silicon oxide separator is 2 nm to 20 nm; and / or The width of the second silicon oxide separator is 2nm~20nm; and / or The width of the third silicon oxide separator is 2nm~20nm.

[0008] In some embodiments, the material further includes a first alumina layer, a first antireflective layer, a first tunneling silicon oxide layer, a second alumina layer, a second antireflective layer, a second tunneling silicon oxide layer, a third alumina layer, and a third antireflective layer. The front side of the silicon substrate includes a first aluminum oxide layer and a first antireflection layer stacked sequentially. The P region includes a first tunneling silicon oxide layer, a first doped layer, a second aluminum oxide layer, and a second antireflection layer stacked sequentially. The N region includes a second tunneling silicon oxide layer, a second doped layer, a third aluminum oxide layer, and a third antireflection layer stacked sequentially.

[0009] In some embodiments, the thickness of the first tunneling silicon oxide layer is 1 nm to 2 nm; and / or The thickness of the second tunneling silicon oxide layer is 1 nm to 2 nm; and / or The thickness of the first doped layer is 70 nm to 300 nm; and / or The thickness of the second doped layer is 70nm~300nm.

[0010] In some embodiments, the first antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the first antireflection layer is 50 nm to 100 nm; and / or The second antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the second antireflection layer is 50 nm to 100 nm; and / or The third antireflection layer includes at least one of silicon nitride antireflection layer and silicon carbide antireflection layer; the thickness of the third antireflection layer is 50nm~100nm.

[0011] This application also provides a method for fabricating a back-contact solar cell, comprising: A tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially fabricated on the back side of a silicon substrate to obtain the first target silicon wafer. An isolation region is formed by etching on the back side of the first target silicon wafer, with P-regions and N-regions spaced apart; The isolation region is wet-oxidized to form a first silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the N region near the isolation region is wet-oxidized to form a third silicon oxide isolation film, thereby obtaining the second target silicon wafer; Remove the mask layer on the second target silicon wafer to obtain the third target silicon wafer; The intrinsic amorphous silicon layer on the P region of the third target silicon wafer is subjected to high-temperature boron diffusion treatment to form a first doped layer and a BSG layer; the intrinsic amorphous silicon layer on the N region of the third target silicon wafer is subjected to high-temperature phosphorus diffusion treatment to form a second doped layer and a PSG layer, thus obtaining a fourth target silicon wafer. Remove the BSG layer and the PSG layer from the back side of the fourth target silicon wafer; The front and back sides of the fourth target silicon wafer are passivated, and then a positive electrode and a negative electrode are fabricated; the positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

[0012] In some embodiments, before forming the tunneling silicon oxide layer on the back side of the silicon substrate, the method further includes polishing the silicon substrate; the polishing method includes immersing the silicon substrate in an alkaline solution with a mass concentration of 2wt% to 4wt% and polishing it at 60°C to 80°C for 150s to 400s.

[0013] In some embodiments, the mask layer is a silicon oxide layer, and the thickness of the mask layer is 50nm~60nm.

[0014] In some embodiments, during the wet oxidation of the isolation area, the temperature is controlled at 60°C to 65°C, the relative humidity is controlled at 45% to 55%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt% to 12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P-region near the isolation region, the temperature is controlled at 50°C to 55°C, the relative humidity is controlled at 60% to 65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt% to 12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 50℃~55℃, the relative humidity of the air is controlled at 60%~65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%~12wt%.

[0015] This application also provides a photovoltaic system, including: The aforementioned back-contact solar cell; or The back-contact solar cell prepared by the above method.

[0016] In the technical solution of this application, the P-region and the N-region are isolated by an isolation region. The first doped layer and the second doped layer are isolated by a second silicon oxide isolation film and a third silicon oxide isolation film. The isolation region is also provided with a first silicon oxide isolation film, which can greatly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate, and it will not increase the risk of mechanical load failure of the back contact solar cell. Attached Figure Description

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application. Figure 1 This is a schematic diagram of the structure of a back-contact solar cell according to this application.

[0018] Figure 2 This is an intermediate state diagram of a back-contact solar cell according to this application.

[0019] In the figure, the following labels are used: 100, silicon substrate; 101, first alumina layer; 102, first antireflective layer; 201, first tunneling silicon oxide layer; 301, first doped layer; 401, second silicon oxide isolation film; 501, second alumina layer; 601, second antireflective layer; 202, second tunneling silicon oxide layer; 302, second doped layer; 402, third silicon oxide isolation film; 502, third alumina layer; 602, third antireflective layer; 701, first silicon oxide isolation film; 901, positive electrode; 902, negative electrode. Detailed Implementation

[0020] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0022] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0025] This application aims to provide a back-contact solar cell, its fabrication method, and a photovoltaic system. The P-region and N-region are isolated by an isolation region. The first doped layer and the second doped layer are isolated by a second silicon oxide isolation film and a third silicon oxide isolation film. The isolation region is also provided with a first silicon oxide isolation film, which can significantly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back-contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate, which will not increase the risk of mechanical load failure of the back-contact solar cell.

[0026] This application provides a back-contact solar cell, including a silicon substrate, a positive electrode, and a negative electrode; The back side of the silicon substrate includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; a first silicon oxide isolation film is disposed on the isolation region; The P-region includes a first doped layer, and a second silicon oxide isolation film is disposed on the side of the first doped layer near the isolation region, and the second silicon oxide isolation film is located within the P-region. The N-region includes a second doped layer, and a third silicon oxide isolation film is disposed on the side of the second doped layer near the isolation region, and the third silicon oxide isolation film is located within the N-region; The positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

[0027] In this embodiment, the width of the isolation region can be 10~90μm (e.g., 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm). The thickness of the first doped layer can be 50~500nm (e.g., 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm); the thickness of the second doped layer can be 50~500nm (e.g., 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm); the thickness of the first silicon oxide isolation film can be 1~50nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, 300nm, 300nm, 400nm, 450nm, 500nm); The width of the first silicon oxide isolation film can be 1~50nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm); the width of the third silicon oxide isolation film can also be 1~50nm (e.g., 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm). It should be noted that the thickness of each layer can be set according to actual needs, and the width of the isolation region can also be set according to actual needs. Specifically, the width of the first silicon oxide isolation film is the same as the width of the isolation region, the thickness of the second silicon oxide isolation film is the same as the thickness of the first doped layer, and the thickness of the third silicon oxide isolation film is the same as the thickness of the second doped layer.

[0028] In this embodiment, the preparation methods of the first silicon oxide isolation film, the second silicon oxide isolation film, and the third silicon oxide isolation film can all be selected from one or more of wet oxidation, plasma-enhanced chemical vapor deposition, and electrochemical anodic oxidation. The preparation methods of the first doped layer and the second doped layer can all be selected from one or more of plasma-enhanced chemical vapor deposition, chemical vapor deposition, low-pressure chemical vapor deposition, and physical vapor deposition. It should be noted that the first silicon oxide isolation film, the second silicon oxide isolation film, and the third silicon oxide isolation film can be formed by wet oxidation of the isolation region, the sides of the first doped layer, and the second doped layer. Alternatively, a silicon oxide layer can be redeposited on the isolation region, the sides of the first doped layer, and the second doped layer to form the first silicon oxide isolation film, the second silicon oxide isolation film, and the third silicon oxide isolation film.

[0029] In this embodiment, the P-region and N-region are isolated by an isolation region. The first doped layer and the second doped layer are isolated by a second silicon oxide isolation film and a third silicon oxide isolation film. The isolation region is also provided with a first silicon oxide isolation film, which can greatly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate, and it will not increase the risk of mechanical load failure of the back contact solar cell.

[0030] In optional embodiments, the thickness of the first silicon oxide separator is 2nm~20nm (e.g., 2mm, 4mm, 6mm, 8mm, 10mm, 12mm, 14mm, 16mm, 18mm, 20mm); and / or The width of the second silicon oxide separator is 2nm~20nm (e.g., 2mm, 4mm, 6mm, 8mm, 10mm, 12mm, 14mm, 16mm, 18mm, 20mm); and / or The width of the third silicon oxide separator is 2nm to 20nm (e.g., 2mm, 4mm, 6mm, 8mm, 10mm, 12mm, 14mm, 16mm, 18mm, 20mm).

[0031] In this embodiment, optimizing the thickness of the first silicon oxide separator and the widths of the second and third silicon oxide separators can significantly improve the isolation effect between the P-region and the N-region, thereby further reducing the leakage risk of the back-contact solar cell. On the other hand, controlling the thickness of the first silicon oxide separator improves the passivation effect of the silicon substrate, while controlling the widths of the second and third silicon oxide separators helps to improve the bonding strength between the doped layer and other functional layers, enhance the passivation effect, achieve a high open-circuit voltage, and thus improve the overall stability and photoelectric conversion efficiency of the solar cell.

[0032] In optional embodiments, it further includes a first alumina layer, a first antireflection layer, a first tunneling silicon oxide layer, a second alumina layer, a second antireflection layer, a second tunneling silicon oxide layer, a third alumina layer, and a third antireflection layer. The front side of the silicon substrate includes a first aluminum oxide layer and a first antireflection layer stacked sequentially. The P region includes a first tunneling silicon oxide layer, a first doped layer, a second aluminum oxide layer, and a second antireflection layer stacked sequentially. The N region includes a second tunneling silicon oxide layer, a second doped layer, a third aluminum oxide layer, and a third antireflection layer stacked sequentially.

[0033] In this embodiment, the thickness of the first tunneling silicon oxide layer can be 1~10nm (e.g., 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm), and the thickness of the second tunneling silicon oxide layer can be 1~10nm (e.g., 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm); the thickness of the first alumina layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the second alumina layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the third alumina layer can be... The thickness of the first antireflective layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the second antireflective layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the third antireflective layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm); the thickness of the third antireflective layer can be 10~200nm (e.g., 10nm, 30nm, 50nm, 70nm, 90nm, 120nm, 140nm, 160nm, 180nm, 200nm).

[0034] In this embodiment, aluminum oxide layers are respectively provided on the first doped layer and the second doped layer for passivation, resulting in better passivation effect, achieving high open-circuit voltage, and further improving the photoelectric conversion efficiency of the solar cell.

[0035] In optional embodiments, the thickness of the first tunneling silicon oxide layer is 1 nm to 2 nm (e.g., 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm); and / or The thickness of the second tunneling silicon oxide layer is 1 nm to 2 nm (e.g., 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm); and / or The thickness of the first doped layer is 70 nm to 300 nm (e.g., 70 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm); and / or The thickness of the second doped layer is 70nm~300nm (e.g., 70nm, 100nm, 150nm, 200nm, 250nm, 300nm).

[0036] In this embodiment, optimizing the thickness of the first tunneling silicon oxide layer, the second tunneling silicon oxide layer, the first doped layer, and the second doped layer can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0037] In optional embodiments, the first antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the first antireflection layer is 50nm~100nm (e.g., 50nm, 60nm, 70nm, 80nm, 90nm, 100nm); and / or The second antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the second antireflection layer is 50 nm to 100 nm (e.g., 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm); and / or The third antireflection layer includes at least one of silicon nitride antireflection layer and silicon carbide antireflection layer; the thickness of the third antireflection layer is 50nm~100nm (e.g., 50nm, 60nm, 70nm, 80nm, 90nm, 100nm).

[0038] In this embodiment, optimizing the type and thickness of the antireflective layer helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.

[0039] This application also provides a method for fabricating a back-contact solar cell, comprising: A tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially fabricated on the back side of a silicon substrate to obtain the first target silicon wafer. An isolation region is formed by etching on the back side of the first target silicon wafer, with P-regions and N-regions spaced apart; The isolation region is wet-oxidized to form a first silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the N region near the isolation region is wet-oxidized to form a third silicon oxide isolation film, thereby obtaining the second target silicon wafer; Remove the mask layer on the second target silicon wafer to obtain the third target silicon wafer; The intrinsic amorphous silicon layer on the P region of the third target silicon wafer is subjected to high-temperature boron diffusion treatment to form a first doped layer and a BSG layer; the intrinsic amorphous silicon layer on the N region of the third target silicon wafer is subjected to high-temperature phosphorus diffusion treatment to form a second doped layer and a PSG layer, thus obtaining a fourth target silicon wafer. Remove the BSG layer and the PSG layer from the back side of the fourth target silicon wafer; The front and back sides of the fourth target silicon wafer are passivated, and then a positive electrode and a negative electrode are fabricated; the positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

[0040] In this embodiment, a first silicon oxide isolation film, a second silicon oxide isolation film, and a third silicon oxide isolation film are formed on the sides of the wet oxidation isolation region, the first doped layer, and the second doped layer. Compared with redepositing silicon oxide layers at corresponding positions to form the first silicon oxide isolation film, the isolation film obtained by wet oxidation has a tighter connection with each layer, a better effect in improving leakage current micro-short circuit phenomenon, and is also beneficial to enhancing the passivation effect of the passivation layer, which can improve the open circuit voltage and further improve the photoelectric conversion efficiency of the solar cell.

[0041] In an optional embodiment, before forming the tunneling silicon oxide layer on the back side of the silicon substrate, the method further includes polishing the silicon substrate; the polishing method may be: placing the silicon substrate in an alkaline solution with a mass concentration of 2wt%~4wt% and polishing it for 150s~400s at 60℃~80℃.

[0042] In this embodiment, the silicon substrate polishing process is optimized, resulting in better polishing effect. This reduces defects on the silicon substrate surface, thereby reducing the surface recombination rate of photogenerated carriers and further improving the photoelectric conversion efficiency of the battery.

[0043] In an optional embodiment, the mask layer is a silicon oxide layer with a thickness of 50-60 nm. In this embodiment, optimizing the mask layer as a silicon oxide layer while controlling its thickness helps protect the intrinsic amorphous silicon layer from damage during subsequent etching or cleaning processes, maintaining its surface properties and passivation effect, thereby further improving the photoelectric conversion efficiency of the battery.

[0044] In an optional embodiment, during the wet oxidation of the isolation area, the temperature is controlled at 60°C to 65°C, the relative humidity is controlled at 45% to 55%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt% to 12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P-region near the isolation region, the temperature is controlled at 50°C to 55°C, the relative humidity is controlled at 60% to 65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt% to 12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 50℃~55℃, the relative humidity of the air is controlled at 60%~65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%~12wt%.

[0045] In this embodiment, a first silicon oxide isolation film, a second silicon oxide isolation film, and a third silicon oxide isolation film are formed on the sides of the wet oxidation isolation region, the first doped layer, and the second doped layer. At the same time, the process parameters of each region of wet oxidation are optimized to improve the connection effect between the isolation film and each layer, which improves the leakage current micro-short circuit phenomenon and enhances the passivation effect of the passivation layer, thereby increasing the open circuit voltage and further improving the photoelectric conversion efficiency of the solar cell.

[0046] The following specific embodiments provide a more detailed description of this application, but should not be construed as limiting the application. Any modifications or substitutions made to the methods, steps, or conditions of this application without departing from the spirit and substance of this application are within the scope of this application.

[0047] Example 1 A type of back-contact solar cell, such as Figure 1 As shown, it includes a silicon substrate 100, a positive electrode 901, and a negative electrode 902; The front side of the silicon substrate 100 includes a first aluminum oxide layer 101 and a first antireflection layer 102 stacked sequentially; the thickness of the first aluminum oxide layer 101 is 10 nm, and the thickness of the first antireflection layer 102 is 10 nm. The back side of the silicon substrate 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 10 μm; a first silicon oxide isolation film 701 is disposed on the isolation region; the thickness of the first silicon oxide isolation film 701 is 1 nm. The P-region includes a first tunneling silicon oxide layer 201, a first doped layer 301, a second aluminum oxide layer 501, and a second antireflection layer 601 stacked sequentially. A second silicon oxide isolation film 401 is disposed on the side of the first doped layer 301 near the isolation region, and the second silicon oxide isolation film 401 is located within the P-region. The thickness of the first tunneling silicon oxide layer 201 is 1 nm, the thickness of the first doped layer 301 is 50 nm, the thickness of the second aluminum oxide layer 501 is 10 nm, the thickness of the second antireflection layer 601 is 10 nm, and the thickness of the second silicon oxide isolation film 401 is 1 nm. The N-region comprises a second tunneling silicon oxide layer 202, a second doped layer 302, a third aluminum oxide layer 502, and a third antireflection layer 602 stacked sequentially. A third silicon oxide isolation film 402 is disposed on the side of the second doped layer 302 near the isolation region, and the third silicon oxide isolation film 402 is located within the N-region. The thickness of the second tunneling silicon oxide layer 202 is 1 nm. The thickness of the second doped layer 302 is 50 nm. The thickness of the third aluminum oxide layer 502 is 10 nm. The thickness of the third antireflection layer 602 is 10 nm. The thickness of the third silicon oxide isolation film 402 is 1 nm. The positive electrode 901 forms an ohmic contact with the first doped layer 301; the negative electrode 902 forms an ohmic contact with the second doped layer 302.

[0048] A method for fabricating a back-contact solar cell, comprising: (1) First, the silicon substrate 100 is polished. The polishing method is as follows: the silicon substrate 100 is placed in an alkaline solution with a mass concentration of 2wt% and polished for 150s at 60°C. Then, a tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially prepared on the back side of the silicon substrate 100 by plasma-enhanced chemical vapor deposition (PECVD) to obtain the first target silicon wafer. The mask layer is a silicon oxide layer and the thickness of the mask layer is 50nm.

[0049] (2) The mask layer is melted by green picosecond laser, and the intrinsic amorphous silicon layer and tunneling silicon oxide layer of the isolation area are removed by alkaline etching. The isolation area is formed on the back side of the first target silicon wafer, and P-region and N-region are formed at intervals. (3) The isolation area is wet-oxidized to form a first silicon oxide isolation film 701; during the wet oxidation of the isolation area, the temperature is controlled at 60°C, the relative humidity of the air is controlled at 45%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%. The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film 401. During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P region near the isolation region, the temperature is controlled at 50°C, the relative humidity of the air is controlled at 60%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%. The intrinsic amorphous silicon layer on the side of the N-region closest to the isolation region is wet-oxidized to form a third silicon oxide isolation film 402, resulting in a second target silicon wafer, as shown below. Figure 2 As shown; during the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 50°C, the relative humidity of the air is controlled at 60%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%. (4) The mask layer on the second target silicon wafer is removed by melting and etching with a green picosecond laser to obtain the third target silicon wafer; (5) A boron-containing paste is printed on the P region of the third target silicon wafer by screen printing, and the intrinsic amorphous silicon layer on the P region of the third target silicon wafer is subjected to high-temperature boron diffusion treatment to form a first doped layer 301 and a BSG layer; a phosphorus-containing paste is printed on the N region of the third target silicon wafer by screen printing, and the intrinsic amorphous silicon layer on the N region of the third target silicon wafer is subjected to high-temperature phosphorus diffusion treatment to form a second doped layer 302 and a PSG layer to obtain a fourth target silicon wafer; (6) Polishing and texturing are performed using a green picosecond laser, a single-sided chain machine, and a tank cleaning machine to remove the BSG layer and the PSG layer on the back of the fourth target silicon wafer; (7) A first alumina layer 101 and a first antireflection layer 102 are sequentially prepared on the front side of the fourth target silicon wafer by plasma enhanced chemical vapor deposition (PECVD). A second alumina layer 501 and a second antireflection layer 601 are sequentially prepared on the first doped layer 301. A third alumina layer 502 and a third antireflection layer 602 are sequentially prepared on the second doped layer 302 to passivate the front and back sides of the fourth target silicon wafer. Then, a positive electrode 901 and a negative electrode 902 are prepared. The positive electrode 901 forms an ohmic contact with the first doped layer 301. The negative electrode 902 forms an ohmic contact with the second doped layer 302.

[0050] Example 2 A type of back-contact solar cell, such as Figure 1 As shown, it includes a silicon substrate 100, a positive electrode 901, and a negative electrode 902; The front side of the silicon substrate 100 includes a first aluminum oxide layer 101 and a first antireflection layer 102 stacked sequentially; the thickness of the first aluminum oxide layer 101 is 200 nm, and the thickness of the first antireflection layer 102 is 200 nm. The back side of the silicon substrate 100 includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; the width of the isolation region is 90 μm; a first silicon oxide isolation film 701 is disposed on the isolation region; the thickness of the first silicon oxide isolation film 701 is 50 nm. The P-region includes a first tunneling silicon oxide layer 201, a first doped layer 301, a second aluminum oxide layer 501, and a second antireflection layer 601 stacked sequentially. A second silicon oxide isolation film 401 is disposed on the side of the first doped layer 301 near the isolation region, and the second silicon oxide isolation film 401 is located within the P-region. The thickness of the first tunneling silicon oxide layer 201 is 2 nm, the thickness of the first doped layer 301 is 500 nm, the thickness of the second aluminum oxide layer 501 is 200 nm, the thickness of the second antireflection layer 601 is 200 nm, and the thickness of the second silicon oxide isolation film 401 is 50 nm. The N-region comprises a second tunneling silicon oxide layer 202, a second doped layer 302, a third aluminum oxide layer 502, and a third antireflection layer 602 stacked sequentially. A third silicon oxide isolation film 402 is disposed on the side of the second doped layer 302 near the isolation region, and the third silicon oxide isolation film 402 is located within the N-region. The thickness of the second tunneling silicon oxide layer 202 is 2 nm. The thickness of the second doped layer 302 is 500 nm. The thickness of the third aluminum oxide layer 502 is 200 nm, the thickness of the third antireflection layer 602 is 200 nm, and the thickness of the third silicon oxide isolation film 402 is 50 nm. The positive electrode 901 forms an ohmic contact with the first doped layer 301; the negative electrode 902 forms an ohmic contact with the second doped layer 302.

[0051] A method for fabricating a back-contact solar cell, comprising: (1) First, the silicon substrate 100 is polished. The polishing method is as follows: the silicon substrate 100 is placed in an alkaline solution with a mass concentration of 4wt% and polished for 400s at 80°C. Then, a tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially prepared on the back side of the silicon substrate 100 by plasma-enhanced chemical vapor deposition (PECVD) to obtain the first target silicon wafer. The mask layer is a silicon oxide layer and the thickness of the mask layer is 60nm.

[0052] (2) The mask layer is melted by green picosecond laser, and the intrinsic amorphous silicon layer and tunneling silicon oxide layer of the isolation area are removed by alkaline etching. The isolation area is formed on the back side of the first target silicon wafer, and P-region and N-region are formed at intervals. (3) The isolation area is wet-oxidized to form a first silicon oxide isolation film 701; during the wet oxidation of the isolation area, the temperature is controlled at 65°C, the relative humidity of the air is controlled at 55%, and the oxidant is hydrogen peroxide with a mass concentration of 12wt%. The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film 401. During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P region near the isolation region, the temperature is controlled at 55°C, the relative humidity of the air is controlled at 65%, and the oxidant is hydrogen peroxide with a mass concentration of 12wt%. The intrinsic amorphous silicon layer on the side of the N-region closest to the isolation region is wet-oxidized to form a third silicon oxide isolation film 402, resulting in a second target silicon wafer, as shown below. Figure 2 As shown; during the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 55°C, the relative humidity of the air is controlled at 65%, and the oxidant is hydrogen peroxide with a mass concentration of 12wt%. (4) The mask layer on the second target silicon wafer is removed by melting and etching with a green picosecond laser to obtain the third target silicon wafer; (5) A boron-containing paste is printed on the P region of the third target silicon wafer by screen printing, and the intrinsic amorphous silicon layer on the P region of the third target silicon wafer is subjected to high-temperature boron diffusion treatment to form a first doped layer 301 and a BSG layer; a phosphorus-containing paste is printed on the N region of the third target silicon wafer by screen printing, and the intrinsic amorphous silicon layer on the N region of the third target silicon wafer is subjected to high-temperature phosphorus diffusion treatment to form a second doped layer 302 and a PSG layer to obtain a fourth target silicon wafer; (6) Polishing and texturing are performed using a green picosecond laser, a single-sided chain machine, and a tank cleaning machine to remove the BSG layer and the PSG layer on the back of the fourth target silicon wafer; (7) A first alumina layer 101 and a first antireflection layer 102 are sequentially prepared on the front side of the fourth target silicon wafer by plasma enhanced chemical vapor deposition (PECVD). A second alumina layer 501 and a second antireflection layer 601 are sequentially prepared on the first doped layer 301. A third alumina layer 502 and a third antireflection layer 602 are sequentially prepared on the second doped layer 302 to passivate the front and back sides of the fourth target silicon wafer. Then, a positive electrode 901 and a negative electrode 902 are prepared. The positive electrode 901 forms an ohmic contact with the first doped layer 301. The negative electrode 902 forms an ohmic contact with the second doped layer 302.

[0053] Example 3 The back-contact solar cell of Example 3 was prepared according to the preparation method of Example 1, except that: Step (1) in Example 3 is as follows: First, the silicon substrate 100 is polished; the polishing method is as follows: the silicon substrate 100 is placed in an alkaline solution with a mass concentration of 2wt% and polished for 150s at 60°C; then, a tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially prepared on the back side of the silicon substrate 100 by plasma-enhanced chemical vapor deposition (PECVD) to obtain the first target silicon wafer; the mask layer is a silicon oxide layer and the thickness of the mask layer is 40nm.

[0054] Example 4 The back-contact solar cell of Example 4 was prepared according to the preparation method of Example 1, except that: Step (1) in Example 4 is as follows: First, the silicon substrate 100 is polished; the polishing method is as follows: the silicon substrate 100 is placed in an alkaline solution with a mass concentration of 2wt% and polished for 150s at 60°C; then, a tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially prepared on the back side of the silicon substrate 100 by plasma-enhanced chemical vapor deposition (PECVD) to obtain the first target silicon wafer; the mask layer is a silicon oxide layer and the thickness of the mask layer is 70nm.

[0055] Example 5 The back-contact solar cell of Example 5 was prepared according to the preparation method of Example 1, except that: Step (3) in Example 5 is as follows: a silicon oxide layer is redeposited at the corresponding position by plasma enhanced chemical vapor deposition (PECVD) to form a first silicon oxide isolation film 701, a second silicon oxide isolation film 401, and a third silicon oxide isolation film 402.

[0056] Example 6 The back-contact solar cell of Example 6 was prepared according to the preparation method of Example 2, except that: Step (3) in Example 6 is: to redeposit silicon oxide layers at the corresponding positions to form a first silicon oxide isolation film 701, a second silicon oxide isolation film 401, and a third silicon oxide isolation film 402 by plasma enhanced chemical vapor deposition (PECVD).

[0057] Example 7 The back-contact solar cell of Example 7 was prepared according to the preparation method of Example 1, except that: Step (3) in Example 7 is: wet oxidation of the isolation area to form a first silicon oxide isolation film 701; during the wet oxidation of the isolation area, the temperature is controlled at 50°C, the relative humidity of the air is controlled at 40%, and the oxidant is hydrogen peroxide with a mass concentration of 7wt%. The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film 401; during the wet oxidation of the intrinsic amorphous silicon layer on the side of the P region near the isolation region, the temperature is controlled at 45°C, the relative humidity of the air is controlled at 55%, and the oxidant is hydrogen peroxide with a mass concentration of 7wt%. The intrinsic amorphous silicon layer on the side of the N-region closest to the isolation region is wet-oxidized to form a third silicon oxide isolation film 402, resulting in a second target silicon wafer, as shown below. Figure 2 As shown, during the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 45°C, the relative humidity of the air is controlled at 55%, and the oxidant is hydrogen peroxide with a mass concentration of 7wt%.

[0058] Example 8 The back-contact solar cell of Example 8 was prepared according to the preparation method of Example 1, except that: Step (3) in Example 8 is: wet oxidation of the isolation area to form a first silicon oxide isolation film 701; during the wet oxidation of the isolation area, the temperature is controlled at 70°C, the relative humidity of the air is controlled at 60%, and the oxidant is hydrogen peroxide with a mass concentration of 14wt%. The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film 401. During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P region near the isolation region, the temperature is controlled at 60°C, the relative humidity of the air is controlled at 70%, and the oxidant is hydrogen peroxide with a mass concentration of 15wt%. The intrinsic amorphous silicon layer on the side of the N-region closest to the isolation region is wet-oxidized to form a third silicon oxide isolation film 402, resulting in a second target silicon wafer, as shown below. Figure 2 As shown, during the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 60°C, the relative humidity of the air is controlled at 70%, and the oxidant is hydrogen peroxide with a mass concentration of 15wt%.

[0059] Example 9 The back-contact solar cell of Example 9 was prepared according to the preparation method of Example 1, except that: Step (3) in Example 9 is: wet oxidation of the isolation area to form a first silicon oxide isolation film 701; during the wet oxidation of the isolation area, the temperature is controlled at 60°C and the oxidant is hydrogen peroxide with a mass concentration of 8wt%. The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film 401; during the wet oxidation of the intrinsic amorphous silicon layer on the side of the P region near the isolation region, the temperature is controlled at 50°C, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%. The intrinsic amorphous silicon layer on the side of the N-region closest to the isolation region is wet-oxidized to form a third silicon oxide isolation film 402, resulting in a second target silicon wafer, as shown below. Figure 2 As shown, during the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 50°C, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%.

[0060] Example 10 The back-contact solar cell of Example 10 was prepared according to the preparation method of Example 1, except that: In Example 10, the thickness of the first silicon oxide separator 701 of the back contact solar cell is 2 nm, the width of the second silicon oxide separator 401 is 2 nm, and the width of the third silicon oxide separator 402 is 2 nm.

[0061] Example 11 The back-contact solar cell of Example 11 was prepared according to the preparation method of Example 1, except that: In Example 11, the thickness of the first silicon oxide separator 701 of the back contact solar cell is 20 nm, the width of the second silicon oxide separator 401 is 20 nm, and the width of the third silicon oxide separator 402 is 20 nm.

[0062] Example 12 The back-contact solar cell of Example 12 was prepared according to the preparation method of Example 1, except that: In Example 12, the thickness of the first doped layer 301 of the back contact solar cell is 70 nm, and the thickness of the second doped layer 302 is 70 nm.

[0063] Example 13 The back-contact solar cell of Example 13 was prepared according to the preparation method of Example 1, except that: In Example 13, the thickness of the first doped layer 301 of the back contact solar cell is 300 nm, and the thickness of the second doped layer 302 is 300 nm.

[0064] Example 14 The back-contact solar cell of Example 14 was prepared according to the preparation method of Example 1, except that: In Example 14, the thickness of the first antireflection layer 102 of the back-contact solar cell is 50 nm, the thickness of the second antireflection layer 601 is 50 nm, and the thickness of the third antireflection layer 602 is 50 nm.

[0065] Example 15 The back-contact solar cell of Example 15 was prepared according to the preparation method of Example 1, except that: In Example 15, the thickness of the first antireflection layer 102 of the back-contact solar cell is 100 nm, the thickness of the second antireflection layer 601 is 100 nm, and the thickness of the third antireflection layer 602 is 100 nm.

[0066] Comparative Example 1 The back-contact solar cell of Comparative Example 1 was prepared according to the preparation method of Example 1, except that: The relevant operations of step (3) were not performed in Comparative Example 1; that is, the back contact solar cell prepared in Comparative Example 1 was not provided with the first silicon oxide separator 701, the second silicon oxide separator 401, and the third silicon oxide separator 402.

[0067] In the above embodiments and comparative examples, all antireflection layers are silicon nitride antireflection layers. It should be noted that other suitable antireflection layers can also be selected in the above embodiments. Photoelectric testing was performed on the back-contact solar cells prepared in the above embodiments and comparative examples, and the test results are shown in Table 1 below.

[0068] Table 1

[0069] Referring to the detection data of Examples 1-15 and Comparative Example 1 above, it can be seen that the P-region and the N-region are isolated by an isolation region. The first doped layer 301 and the second doped layer 302 are isolated by a second silicon oxide isolation film 401 and a third silicon oxide isolation film 402. A first silicon oxide isolation film 701 is also provided on the isolation region, which can greatly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate 100, and it will not increase the risk of mechanical load failure of the back contact solar cell.

[0070] Referring to the detection data of Examples 1 and 3-4 above, it can be seen that optimizing the mask layer to be a silicon oxide layer and controlling the thickness of the mask layer is beneficial to protecting the intrinsic amorphous silicon layer from damage during subsequent etching or cleaning processes, maintaining its surface characteristics and passivation effect, thereby further improving the photoelectric conversion efficiency of the battery.

[0071] Referring to the test data of Examples 1 and 5-6 above, it can be seen that, compared with redepositing silicon oxide layers at corresponding positions to form the first silicon oxide separator 701, the second silicon oxide separator 401, and the third silicon oxide separator 402, the separator obtained by wet oxidation has a higher degree of connection with each layer, a better effect in improving leakage current micro-short circuit phenomenon, and is also beneficial to enhancing the passivation effect of the passivation layer, which can increase the open circuit voltage and further improve the photoelectric conversion efficiency of the solar cell.

[0072] Referring to the detection data of Examples 1 and 7-9 above, it can be seen that simultaneously optimizing the process parameters of each region of wet oxidation, optimizing the connection effect between the separator and each layer, and improving the leakage current micro-short circuit phenomenon are more effective. At the same time, it is beneficial to enhance the passivation effect of the passivation layer, which can increase the open circuit voltage and further improve the photoelectric conversion efficiency of the solar cell.

[0073] Referring to the detection data of Examples 1 and 10-11 above, it can be seen that optimizing the thickness of the first silicon oxide separator 701 and optimizing the width of the second silicon oxide separator 401 and the third silicon oxide separator 402 can significantly improve the isolation effect between the P-region and the N-region, thereby further reducing the leakage risk of the back contact solar cell. On the other hand, controlling the thickness of the first silicon oxide separator 701 results in better passivation of the silicon substrate 100, and controlling the width of the second silicon oxide separator 401 and the third silicon oxide separator 402 is beneficial to improving the bonding strength between the doped layer and other functional layers, improving the passivation effect, achieving a high open-circuit voltage, and thus improving the overall stability and photoelectric conversion efficiency of the solar cell.

[0074] Referring to the detection data of Examples 1 and 12-13 above, it can be seen that optimizing the thickness of the first doped layer 301 and the second doped layer 302 can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0075] Referring to the detection data of Examples 1 and 14-15 above, it can be seen that optimizing the type and thickness of the antireflection layer helps to reduce the reflectivity of the battery and improve the photoelectric conversion efficiency.

[0076] In summary, the P-region and N-region of this application are isolated by an isolation region. The first doped layer 301 and the second doped layer 302 are isolated by a second silicon oxide isolation film 401 and a third silicon oxide isolation film 402. The isolation region is also provided with a first silicon oxide isolation film 701, which can significantly improve the isolation effect between the P-region and the N-region, thereby effectively reducing the leakage risk of the back contact solar cell. When forming the isolation region, it is not necessary to etch the silicon substrate 100, and it will not increase the risk of mechanical load failure of the back contact solar cell.

[0077] This application may provide a back-contact solar cell (not shown) comprising a silicon wafer having its (surface) BSG and / or PSG removed by the method described above.

[0078] This application provides a photovoltaic system, including: a back-contact solar cell as described in any of the above embodiments; or a back-contact solar cell prepared by the preparation method described in any of the above embodiments. The advantages of the aforementioned back-contact solar cell are also present in this photovoltaic system, and will not be elaborated further here. The application fields of the aforementioned photovoltaic system are wide, not limited to photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, but also including various devices and apparatuses that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is to say, the photovoltaic system can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0079] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0080] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A back-contact solar cell, characterized in that, Includes silicon substrate, positive electrode, and negative electrode; The back side of the silicon substrate includes a P-region, an N-region, and an isolation region, wherein the isolation region is used to separate the P-region and the N-region; a first silicon oxide isolation film is disposed on the isolation region; The P-region includes a first doped layer, and a second silicon oxide isolation film is disposed on the side of the first doped layer near the isolation region, and the second silicon oxide isolation film is located within the P-region. The N-region includes a second doped layer, and a third silicon oxide isolation film is disposed on the side of the second doped layer near the isolation region, and the third silicon oxide isolation film is located within the N-region; The positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

2. The back-contact solar cell according to claim 1, characterized in that, The thickness of the first silicon oxide separator is 2nm~20nm; and / or The width of the second silicon oxide separator is 2nm~20nm; and / or The width of the third silicon oxide separator is 2nm~20nm.

3. The back-contact solar cell according to claim 1, characterized in that, It also includes a first alumina layer, a first antireflective layer, a first tunneling silicon oxide layer, a second alumina layer, a second antireflective layer, a second tunneling silicon oxide layer, a third alumina layer, and a third antireflective layer; The front side of the silicon substrate includes a first aluminum oxide layer and a first antireflection layer stacked sequentially. The P region includes a first tunneling silicon oxide layer, a first doped layer, a second aluminum oxide layer, and a second antireflection layer stacked sequentially. The N region includes a second tunneling silicon oxide layer, a second doped layer, a third aluminum oxide layer, and a third antireflection layer stacked sequentially.

4. The back-contact solar cell according to claim 3, characterized in that, The thickness of the first tunneling silicon oxide layer is 1 nm to 2 nm; and / or The thickness of the second tunneling silicon oxide layer is 1 nm to 2 nm; and / or The thickness of the first doped layer is 70 nm to 300 nm; and / or The thickness of the second doped layer is 70nm~300nm.

5. The back-contact solar cell according to claim 3, characterized in that, The first antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the first antireflection layer is 50 nm to 100 nm; and / or The second antireflection layer includes at least one of a silicon nitride antireflection layer and a silicon carbide antireflection layer; the thickness of the second antireflection layer is 50 nm to 100 nm; and / or The third antireflection layer includes at least one of silicon nitride antireflection layer and silicon carbide antireflection layer; the thickness of the third antireflection layer is 50nm~100nm.

6. A method for fabricating a back-contact solar cell, characterized in that, include: A tunneling silicon oxide layer, an intrinsic amorphous silicon layer, and a mask layer are sequentially fabricated on the back side of a silicon substrate to obtain the first target silicon wafer. An isolation region is formed by etching on the back side of the first target silicon wafer, with P-regions and N-regions spaced apart; The isolation region is wet-oxidized to form a first silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the P region near the isolation region is wet-oxidized to form a second silicon oxide isolation film; The intrinsic amorphous silicon layer on the side of the N region near the isolation region is wet-oxidized to form a third silicon oxide isolation film, thereby obtaining the second target silicon wafer; Remove the mask layer on the second target silicon wafer to obtain the third target silicon wafer; The intrinsic amorphous silicon layer on the P region of the third target silicon wafer is subjected to high-temperature boron diffusion treatment to form a first doped layer and a BSG layer; the intrinsic amorphous silicon layer on the N region of the third target silicon wafer is subjected to high-temperature phosphorus diffusion treatment to form a second doped layer and a PSG layer, thus obtaining a fourth target silicon wafer. Remove the BSG layer and the PSG layer from the back side of the fourth target silicon wafer; The front and back sides of the fourth target silicon wafer are passivated, and then a positive electrode and a negative electrode are fabricated; the positive electrode forms an ohmic contact with the first doped layer; the negative electrode forms an ohmic contact with the second doped layer.

7. The method according to claim 6, characterized in that, Before preparing the tunneling silicon oxide layer on the back side of the silicon substrate, the method further includes polishing the silicon substrate; the polishing method includes immersing the silicon substrate in an alkaline solution with a mass concentration of 2wt% to 4wt% and polishing it for 150s to 400s at a temperature of 60℃ to 80℃.

8. The method according to claim 6, characterized in that, The mask layer is a silicon oxide layer, and the thickness of the mask layer is 50nm~60nm.

9. The method according to claim 6, characterized in that, During the wet oxidation process of the isolation area, the temperature is controlled at 60℃~65℃, the relative humidity is controlled at 45%~55%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%~12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the P-region near the isolation region, the temperature is controlled at 50°C to 55°C, the relative humidity is controlled at 60% to 65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt% to 12wt%; and / or During the wet oxidation of the intrinsic amorphous silicon layer on the side of the N region near the isolation region, the temperature is controlled at 50℃~55℃, the relative humidity of the air is controlled at 60%~65%, and the oxidant is hydrogen peroxide with a mass concentration of 8wt%~12wt%.

10. A photovoltaic system, characterized in that, include: Back-contact solar cell as described in any one of claims 1-5; or The back-contact solar cell prepared by the preparation method according to any one of claims 6-9.

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