Back contact crystalline silicon solar cell structure and method of manufacturing the same

Abstract

The application discloses a back contact crystalline silicon solar cell structure and a preparation method thereof, relates to the technical field of back contact crystalline silicon solar cell passivation, and the cell structure comprises an N-type silicon base, has a textured structure, an aluminum oxide passivation layer and a silicon nitride anti-reflection layer on the front surface; the back surface has a silicon oxide tunnel layer, an N-poly, a boron diffusion P emission region, a gap between the P region and the N-poly and a textured surface, and the outer part has an aluminum oxide passivation layer and a silicon nitride anti-reflection layer; an N electrode contacts the N-poly, and a P electrode contacts the P region. The preparation method comprises the following steps: double-sided texturing, mask plating, boron diffusion, laser patterning, alkali polishing, deposition of a tunnel layer and an N-poly, phosphorus diffusion, laser slotting, alkali etching, film removal, deposition of a passivation / anti-reflection layer and metallization. The P region structure without a P-poly is adopted in combination with the back surface texture, so that the double-sided rate is improved and the process is simplified.

Description

Technical Field

[0001] This invention relates to the field of passivation technology for back-contact crystalline silicon solar cells, and specifically to a back-contact crystalline silicon solar cell structure and its fabrication method. Background Technology

[0002] Currently, crystalline silicon solar cell technology is gradually transitioning to TBC (Tunneling oxide passivated contact structure) structure. As the mainstream representative of full back contact solar technology, this structure has entered the stage of large-scale mass production.

[0003] The back contact structure of a conventional TBC battery is as follows: Figure 13 As shown, the back surface of the N-type silicon substrate 1 is sequentially covered with a silicon oxide layer, an N-type doped polysilicon layer 5 / P-type doped polysilicon layer, an aluminum oxide layer, a silicon nitride layer, and an N-type metal electrode 6 and / or a P-type metal electrode 8, with a pyramid-shaped textured structure formed in the gap region on the back surface. Multiple composite films are deposited on the back surface of the silicon substrate 1. The N-type metal electrode 6 penetrates the silicon nitride layer and the aluminum oxide layer through high-temperature sintering to form an ohmic contact with the N-type doped polysilicon layer 5; the P-type metal electrode 8 penetrates the silicon nitride layer and the aluminum oxide layer through high-temperature sintering to form an ohmic contact with the P-type doped polysilicon layer.

[0004] The TBC battery uses a pyramid-shaped textured surface on the front and back gap areas (e.g., ...). Figure 13 As shown in the figure, this structure has a significant light-trapping effect, greatly reducing the reflectivity of the front and back gap areas, significantly increasing the battery's light utilization rate, and significantly increasing the battery's short-circuit current. This technology is relatively mature and is widely used in various battery technologies.

[0005] However, the aforementioned conventional TBC batteries still have the following technical problems: First, the pyramidal textured surface structure has already reached its physical limit in reducing reflectivity (typically, the lowest reflectivity can only be reduced to about 8%-10%), making it difficult to further reduce the reflection loss of incident light, which restricts the further improvement of short-circuit current.

[0006] Second, the P-poly (P-type doped polycrystalline silicon layer) layer on the back side has strong parasitic absorption of long-wavelength light (especially near-infrared light), which causes a large amount of light incident from the back side to be absorbed by the P-poly layer and unable to reach the interior of the silicon substrate, severely limiting the bifaciality of the battery (usually only about 70%-75%) and reducing the total power generation in bifacial power generation scenarios.

[0007] Therefore, there is an urgent need to develop a back-contact crystalline silicon solar cell structure and its fabrication method to further reduce the front reflectivity and increase the bifaciality of the cell, thereby breaking through the performance bottleneck of existing TBC cells. Summary of the Invention

[0008] The purpose of this invention is to provide a back-contact crystalline silicon solar cell structure and its fabrication method, which solves the problems that the existing pyramid textured structure is difficult to further reduce the reflection loss of incident light, which restricts the further improvement of short-circuit current and the strong parasitic absorption of the P-poly on the back side, which seriously limits the bifaciality of the cell.

[0009] The objective of this invention can be achieved through the following technical solutions: A back-contact crystalline silicon solar cell structure includes a silicon substrate; A textured structure 1 is formed on the front side of the silicon substrate, and a passivation layer 1 and an antireflection layer 1 are sequentially disposed on the outside of the textured structure 1 from the inside to the outside. A tunneling layer is formed on the back side of the silicon substrate, and an N-type doped polycrystalline silicon layer is disposed on the outside of the tunneling layer; A P-emitter region is formed on the back side of the silicon substrate, and a gap region is formed between the P-emitter region and the N-type doped polysilicon layer; A textured structure formed on the gap region on the back of the silicon substrate and outside the P-emitter region; Passivation layer two and antireflection layer two are disposed outside the textured structure two and the N-type doped polycrystalline silicon layer; and An N-type metal electrode and a P-type metal electrode are provided. The N-type metal electrode passes through the second passivation layer and the second antireflection layer to form an ohmic contact with the N-type doped polysilicon layer, and the P-type metal electrode passes through the second passivation layer and the second antireflection layer to form an ohmic contact with the P emitter region.

[0010] The back-contact crystalline silicon solar cell structure provided by this invention has, but is not limited to, the following beneficial effects compared to existing technologies: The P-emitter region is a boron diffusion layer formed by boron diffusion, without a poly structure. Compared with the P-type doped polycrystalline silicon layer in the traditional TBC battery structure, the P-emitter region of this structure does not require additional deposition of doped polycrystalline silicon, eliminating the parasitic absorption problem of long-wavelength light by the P-type doped polycrystalline silicon layer. This allows more long-wavelength light incident from the back to reach the silicon substrate and be effectively utilized, thereby significantly improving the bifaciality of the battery and increasing the total power generation in bifacial power generation scenarios.

[0011] An additional textured structure is formed outside the P-emitter region. By increasing the textured structure outside the P-emitter region, the reflectivity of back-incident light is further reduced, the propagation path of light inside the silicon is increased, and more long-wavelength light is absorbed by the silicon substrate and converted into electrical energy. This significantly improves the utilization rate of back-incident light, thereby significantly improving the bifaciality of the cell.

[0012] As a further aspect of the present invention: the velvet structure is in the shape of an inverted pyramid, and the reflectivity of the velvet structure is ≤5%; The first velvet structure has the same structure as the second velvet structure.

[0013] As a further aspect of the present invention: multiple sets of the N-type doped polysilicon layer and the P-emitter region are provided, and the multiple sets of the N-type doped polysilicon layer and the P-emitter region are alternately arranged.

[0014] As a further aspect of the present invention: the silicon substrate is an N-type single-crystal silicon substrate; Both the first passivation layer and the second passivation layer are aluminum oxide layers, and both the first antireflection layer and the second antireflection layer are silicon nitride layers; The tunneling layer is a silicon oxide layer.

[0015] As a further aspect of the present invention: a method for fabricating a back-contact crystalline silicon solar cell structure, comprising the following steps: The silicon substrate is cleaned, and after cleaning, it is textured on both sides to obtain textured structure one and textured structure two. A silicon nitride mask is deposited on the outside of the textured structure on the front side of the silicon substrate; Boron diffusion is performed on the back side of the silicon substrate to form a PN junction and a BSG layer; The back area of ​​the silicon substrate is marked by laser, and the boron doped layer in the laser-affected area is removed by alkaline etching to form a planar silicon substrate; Oxidation forms a tunneling layer, polycrystalline silicon is deposited, and then phosphorus diffusion is performed to form an N-type doped polycrystalline silicon layer and a PSG layer. Laser marking was used to mark the back area of ​​the silicon substrate, chain acid etching was used to remove the front PSG layer, followed by alkaline etching to complete the etching of the laser-acted area and form a textured structure II in the gap area. Acid washing is performed to remove the PSG and BSG layers on the back of the silicon substrate and the silicon nitride mask on the front of the silicon substrate; A passivation layer is deposited on both sides of a silicon substrate by atomic deposition, followed by an antireflection layer deposited by plasma-chemical vapor deposition. Metallize the N-type and P-type metal electrodes at corresponding positions on the back side of the silicon substrate to obtain a back-contact crystalline silicon solar cell structure.

[0016] As a further aspect of the present invention, the BSG layer is controlled to be 80-100 nm thick.

[0017] As a further aspect of the present invention, polycrystalline silicon deposition on the back surface of a silicon substrate is performed using low-pressure chemical vapor deposition and a dual-intercalation method.

[0018] As a further aspect of the present invention, the tunneling layer is controlled to be 1-2 nm thick.

[0019] As a further aspect of the present invention: the N-type doped polycrystalline silicon layer is 150-350nm, and the PSG layer is 20-60nm.

[0020] As a further aspect of the present invention, the width of the gap region is 40-150nm.

[0021] The present invention provides a method for fabricating a back-contact crystalline silicon solar cell structure, which, compared with the prior art, has, but is not limited to, the following beneficial effects: Compared with the traditional BC process, the above-mentioned preparation process of the present invention eliminates a series of complex steps required for the preparation of P-poly, such as PECVD / LPCVD deposition, annealing, boron diffusion, laser doping, etching and cleaning. This simplifies the preparation process, reduces the process difficulty and production cost, significantly increases production capacity, and is more conducive to large-scale mass production and promotion. Attached Figure Description

[0022] The invention will now be further described with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the process flow of the present invention. Figure 1 ; Figure 3 This is a schematic diagram of the process flow of the present invention. Figure 2 ; Figure 4 This is a schematic diagram of the process flow of the present invention. Figure 3 ; Figure 5 This is a schematic diagram of the process flow of the present invention. Figure 4 ; Figure 6 This is a schematic diagram of the process flow of the present invention. Figure 5 ; Figure 7 This is a schematic diagram of the process flow of the present invention. Figure 6 ; Figure 8 This is a schematic diagram of the process flow of the present invention. Figure 7 ; Figure 9 This is a schematic diagram of the process flow of the present invention. Figure 8 ; Figure 10 This is a schematic diagram of the process flow of the present invention. Figure 9 ; Figure 11 This is a schematic diagram of the process flow of the present invention. Figure 10 ; Figure 12This is a schematic diagram of the process flow of the present invention. Figure 10 one; Figure 13 This is a schematic diagram of the TBC battery structure in the existing technology; Figure 14 These are SEM images of the first and second velvet structures of this invention.

[0024] In the figure: 1. Silicon substrate; 2. Tunneling layer; 3. Passivation layer 1; 31. Passivation layer 2; 4. Antireflection layer 1; 41. Antireflection layer 2; 5. N-type doped polycrystalline silicon layer; 6. N-type metal electrode; 7. P-emitter region; 8. P-type metal electrode; 9. Textured structure 1; 91. Textured structure 2. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0026] like Figure 1 As shown, an embodiment of the present invention provides a back-contact crystalline silicon solar cell structure, including a silicon substrate 1; A textured structure 9 is formed on the front side of the silicon substrate 1. A passivation layer 3 and an anti-reflection layer 4 are sequentially disposed on the outside of the textured structure 9 from the inside to the outside. A tunneling layer 2 is formed on the back side of the silicon substrate 1, and an N-type doped polycrystalline silicon layer 5 is disposed on the outside of the tunneling layer 2; A P-emitter region 7 is formed on the back side of the silicon substrate 1, and a gap region is formed between the P-emitter region 7 and the N-type doped polysilicon layer 5. Textured structure 91 formed on the gap region on the back of the silicon substrate 1 and outside the P emitter region 7; Passivation layer 31 and antireflection layer 41 are disposed outside the textured structure 91 and the N-type doped polysilicon layer 5; and An N-type metal electrode 6 and a P-type metal electrode 8 are provided. The N-type metal electrode 6 passes through the passivation layer 31 and the anti-reflection layer 41 to form an ohmic contact with the N-type doped polysilicon layer 5. The P-type metal electrode 8 passes through the passivation layer 31 and the anti-reflection layer 41 to form an ohmic contact with the P-emitter region 7.

[0027] It should be noted that in this embodiment, the silicon substrate 1 is an N-type monocrystalline silicon substrate. Compared with the P-type silicon substrate, the N-type silicon substrate is less sensitive to boron and oxygen impurities, has a longer minority carrier lifetime, and has no light-induced degradation problem, making it more suitable for fabricating high-efficiency back-contact solar cells.

[0028] It should be understood that in this embodiment, "the front side of the silicon substrate 1" refers to the side of the silicon substrate 1 facing the light-receiving surface, and "the back side of the silicon substrate 1" refers to the side away from the light-receiving surface. The structure of the present invention places both the positive and negative electrodes on the back of the battery, and there is no light-shielding structure on the front, which can effectively reduce light-shielding loss and improve the photoelectric conversion efficiency of the battery.

[0029] In this embodiment, the P-emitter region 7 is a boron diffusion layer formed by boron diffusion, without a poly structure. Compared with the P-type doped polycrystalline silicon layer (P-poly) in the traditional TBC battery structure, the P-emitter region 7 of this structure does not require additional deposition of doped polycrystalline silicon, eliminating the parasitic absorption problem of long-wavelength light by the P-type doped polycrystalline silicon layer. This allows more long-wavelength light incident from the back side to reach the interior of the silicon substrate and be effectively utilized, thereby significantly improving the bifaciality of the battery and increasing the total power generation in bifacial power generation scenarios.

[0030] In this embodiment, an additional textured structure 91 is formed outside the P-emitter region 7. By increasing the textured structure outside the P-emitter region 7, the reflectivity of back-incident light is further reduced, the propagation path of light inside the silicon is increased (light trapping effect), and more long-wavelength light is absorbed by the silicon substrate and converted into electrical energy. This significantly improves the utilization rate of back-incident light, thereby significantly improving the bifaciality of the battery.

[0031] In this embodiment, the back side of the silicon substrate 1 has no P-type doped polycrystalline silicon layer, which eliminates a series of complex steps required for the preparation of P-poly, such as PECVD / LPCVD deposition, annealing, boron diffusion, laser doping, etching and cleaning. This simplifies the preparation process, reduces the process difficulty and production cost, and is more conducive to large-scale mass production and promotion.

[0032] Preferably, such as Figure 14 As shown, the first suede structure 9 is in the shape of an inverted pyramid, and the reflectivity of the first suede structure 9 is ≤5%; the first suede structure 9 has the same structure as the second suede structure 91.

[0033] In this embodiment, the front and back gap areas and the P emitter area are all set as inverted pyramid suede surfaces. Compared with the traditional upright pyramid suede surface, the inverted pyramid suede surface can further reduce the light reflectivity of the front and back sides, breaking through the physical limit of reflectivity of the traditional pyramid suede surface structure, further reducing the reflection loss of incident light, effectively improving the short-circuit current of the battery, and promoting the further improvement of the battery photoelectric conversion efficiency.

[0034] Preferably, such as Figure 1 As shown, multiple sets of the N-type doped polysilicon layer 5 and the P-emitter region 7 are provided, and the multiple sets of the N-type doped polysilicon layer 5 and the P-emitter region 7 are alternately arranged.

[0035] It should be understood that in a full back contact (BC) cell, all electrodes are located on the back side. Therefore, the P-region and N-region must be fabricated simultaneously on the back side of the cell, and they need to be arranged alternately to collect electrons and holes respectively. By setting multiple sets of alternating structures, the width of each P-region / N-region can be shortened, so that photogenerated carriers only need to travel a short lateral distance to reach the corresponding electrode, thereby reducing resistance loss.

[0036] Preferably, in this embodiment, the silicon substrate 1 is an N-type single crystal silicon substrate; the passivation layer 1 3 and the passivation layer 2 31 are both aluminum oxide layers, the antireflection layer 1 4 and the antireflection layer 2 41 are both silicon nitride layers; and the tunneling layer 2 is a silicon oxide layer.

[0037] In this embodiment, aluminum oxide is used as a passivation layer, which significantly reduces the surface recombination rate, increases the open circuit voltage (Voc), and has an excellent passivation effect on the P emitter region 7, making up for the passivation loss that may be caused by the absence of P-poly in this solution.

[0038] In this embodiment, silicon nitride is used as an antireflection layer to reduce frontal reflectivity, increase light absorption, and protect the underlying alumina layer and silicon surface, thereby improving process reliability.

[0039] In this embodiment, silicon oxide is used as the tunneling layer, which together with N-poly forms the TOPCon passivated contact structure to achieve an extremely low dark saturation current density.

[0040] Preferably, such as Figures 2-12 As shown, the present invention also provides a method for fabricating a back-contact crystalline silicon solar cell structure, comprising the following steps: like Figure 2 As shown, the silicon substrate 1 is cleaned, and then double-sided texturing is performed to obtain textured structure 1 9 and textured structure 2 91. The double-sided texturing is achieved through a grooved alkaline texturing process, simultaneously fabricating micron-scale inverted pyramid textured structures (with reflectivity as low as 5%) on both the front and back sides of the N-type single-crystal silicon wafer. This provides efficient light trapping for the front side and a high bifaciality foundation for the P-region on the back side. The back-side textured surface will selectively retain the P-region in subsequent processes, enabling on-demand optical design.

[0041] like Figure 3 As shown, a silicon nitride mask is deposited on the outside of the textured structure 9 on the front side of the silicon substrate 1 to protect the textured structure on the front side from being damaged by subsequent processes.

[0042] like Figure 4 As shown, boron diffusion is performed on the back side of silicon substrate 1 to form a PN junction and a BSG layer. The BSG layer is formed during boron diffusion when the silicon wafer surface is exposed to an oxygen-containing atmosphere, resulting in an oxidation reaction that creates a glassy thin film primarily composed of silicon dioxide and borosilicate. The thickness of this layer can be controlled by adjusting the oxidation time and oxygen flow rate.

[0043] Furthermore, the BSG layer acts as a protective mask throughout the subsequent processes: during subsequent alkaline polishing, cleaning, and other processes, the BSG layer can withstand the corrosion of alkaline solutions, protecting the boron-doped P-regions already formed beneath it from being damaged.

[0044] like Figure 5 and Figure 6 As shown, the back area of ​​silicon substrate 1 is marked with a laser, and after alkaline polishing (etching), the boron doped layer in the laser-affected area is removed to form a planar silicon substrate; In this step, only the P-region is retained on the back side of silicon substrate 1, while the rest is washed into a plane to lay a good foundation for subsequent polycrystalline silicon deposition.

[0045] like Figure 7 and Figure 8 As shown, oxidation is performed to form a tunneling layer 2. Polycrystalline silicon is deposited by LPCVD, followed by phosphorus diffusion to form an N-type doped polycrystalline silicon layer 5 and a PSG layer, wherein the N-type doped polycrystalline silicon layer is 150-350nm and the PSG layer is 20-60nm. It is important to note in this step that a double-insertion method is used for intrinsic poly deposition on the back side. Specifically, the silicon substrate 1 is inserted into the quartz boat in a "back-to-back" manner, and the quartz boat is placed in a tube furnace. Silane and other gases are introduced and decomposed at high temperature. Because the silicon substrate 1 is placed back-to-back, the silane gas can fully contact the back side of the silicon substrate 1, depositing a layer of intrinsic polysilicon on it. However, the front side is blocked by the other silicon wafer, resulting in very little deposition.

[0046] like Figure 9 and Figure 10 As shown, the back area of ​​the silicon substrate 1 is marked with a laser, and the front PSG layer (not shown in the figure) is removed by chain acid etching. Then, alkaline etching is performed to complete the etching of the laser-acted area and form a textured structure 91 in the gap area. The gap area is 40-150nm wide. Since the tunneling layer 2 is very thin, only 1-2nm, it is not enough to withstand the alkaline texturing operation.

[0047] like Figure 11 As shown, acid washing is performed to remove the PSG and BSG layers on the back of the silicon substrate 1 and the silicon nitride mask on the front of the silicon substrate 1. It should be noted that the PSG in the P region on the back is removed by alkaline etching after laser treatment, and the PSG in the N region on the back is removed by HF in an acid bath after the alkaline etching step.

[0048] like Figure 12 and Figure 1 As shown, a passivation layer is atomically deposited on both sides of the silicon substrate 1, and an antireflection layer is deposited by plasma chemical vapor deposition; N-type metal electrode 6 and P-type metal electrode 8 are metallized at corresponding positions on the back side of the silicon substrate 1 to obtain a back-contact crystalline silicon solar cell structure.

[0049] Preferably, the BSG layer is controlled to be 80-100 nm thick.

[0050] The processes in this invention, such as double-sided texturing, boron diffusion, laser marking, alkaline polishing, LPCVD deposition, phosphorus diffusion, chain acid etching, acid washing, atomic deposition, plasma chemical vapor deposition, and metallization, are all mature technologies in the prior art. The specific process steps and equipment are not described in detail here. The process parameters can be reasonably adjusted according to actual needs.

[0051] Compared with the traditional BC process, the above-mentioned process of the present invention eliminates a series of complex steps required for the preparation of P-poly, such as PECVD / LPCVD deposition, annealing, boron diffusion, laser doping, etching and cleaning. This simplifies the preparation process, reduces the process difficulty and production cost, significantly increases production capacity, and is more conducive to large-scale mass production and promotion.

[0052] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the description, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0053] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0054] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0055] It should be emphasized that when the term "comprising / including" is used in this specification, it is used to explicitly indicate the presence of the stated feature, integer, step, or component, but does not exclude the presence or addition of one or more other features, integers, steps, parts, or groups of features, integers, steps, or parts.

[0056] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0057] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A back-contact crystalline silicon solar cell structure, characterized in that, Including silicon substrate (1); A textured structure (9) is formed on the front side of the silicon substrate (1). A passivation layer (3) and an antireflection layer (4) are sequentially disposed on the outside of the textured structure (9) from the inside to the outside. A tunneling layer (2) is formed on the back side of the silicon substrate (1), and an N-type doped polycrystalline silicon layer (5) is disposed on the outside of the tunneling layer (2). A P-emitter region (7) is formed on the back side of the silicon substrate (1), and a gap region is formed between the P-emitter region (7) and the N-type doped polycrystalline silicon layer (5); Textured structure 2 (91) formed on the gap region on the back of the silicon substrate (1) and outside the P emitter region (7). Passivation layer two (31) and antireflection layer two (41) disposed outside the textured structure two (91) and the N-type doped polycrystalline silicon layer (5); and The N-type metal electrode (6) and the P-type metal electrode (8) are connected. The N-type metal electrode (6) passes through the second passivation layer (31) and the second antireflection layer (41) to form an ohmic contact with the N-type doped polysilicon layer (5). The P-type metal electrode (8) passes through the second passivation layer (31) and the second antireflection layer (41) to form an ohmic contact with the P emitter region (7).

2. The back-contact crystalline silicon solar cell structure according to claim 1, characterized in that, The velvet structure one (9) is in the shape of an inverted pyramid, and the reflectivity of the velvet structure one (9) is ≤5%; The first velvet structure (9) has the same structure as the second velvet structure (91).

3. The back-contact crystalline silicon solar cell structure according to claim 1, characterized in that, Multiple sets of the N-type doped polysilicon layer (5) and the P-emitter region (7) are provided, and the multiple sets of the N-type doped polysilicon layer (5) and the P-emitter region (7) are alternately provided.

4. A back-contact crystalline silicon solar cell structure according to any one of claims 1-3, characterized in that, The silicon substrate (1) is an N-type single crystal silicon substrate; The first passivation layer (3) and the second passivation layer (31) are both aluminum oxide layers, and the first antireflection layer (4) and the second antireflection layer (41) are both silicon nitride layers; The tunneling layer (2) is a silicon oxide layer.

5. A method for fabricating a back-contact crystalline silicon solar cell structure, characterized in that, Includes the following steps: The silicon substrate (1) is cleaned, and after cleaning, it is textured on both sides to obtain textured structure one (9) and textured structure two (91). A silicon nitride mask is deposited on the outside of the textured structure (9) on the front side of the silicon substrate (1); Boron diffusion is performed on the back side of the silicon substrate (1) to form a PN junction and a BSG layer; The back area of ​​the silicon substrate (1) is marked by laser, and the boron doped layer in the laser-acted area is removed by alkaline etching to form a planar silicon substrate; Oxidation forms a tunneling layer (2), polycrystalline silicon is deposited, and then phosphorus diffusion is performed to form an N-type doped polycrystalline silicon layer (5) and a PSG layer; Laser marking was used to mark the back area of ​​the silicon substrate (1), the front PSG layer was removed by chain acid etching, and then alkaline etching was performed to complete the etching of the laser-acted area and form a textured structure II (91) in the gap area. Acid washing was performed to remove the PSG layer and BSG layer on the back of the silicon substrate (1) and the silicon nitride mask on the front of the silicon substrate (1); A passivation layer is deposited on both sides of a silicon substrate (1), followed by a plasma chemical vapor deposition antireflection layer; The N-type metal electrode (6) and the P-type metal electrode (8) are metallized at corresponding positions on the back side of the silicon substrate (1) to obtain a back-contact crystalline silicon solar cell structure.

6. The method for fabricating a back-contact crystalline silicon solar cell structure according to claim 5, characterized in that, The BSG layer is controlled to be 80-100nm thick.

7. The method for fabricating a back-contact crystalline silicon solar cell structure according to claim 5, characterized in that, Polycrystalline silicon was deposited on the back surface of the silicon substrate (1) using low-pressure chemical vapor deposition and a dual-intercalation method.

8. The method for fabricating a back-contact crystalline silicon solar cell structure according to claim 5, characterized in that, The tunneling layer (2) is controlled to be 1-2 nm thick.

9. The method for fabricating a back-contact crystalline silicon solar cell structure according to claim 5, characterized in that, The N-type doped polycrystalline silicon layer (5) is 150-350nm, and the PSG layer is 20-60nm.

10. The method for fabricating a back-contact crystalline silicon solar cell structure according to claim 5, characterized in that, The width of the gap region is 40-150nm.

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