A photoelectric detector and a preparation method thereof

CN122803455APending Publication Date: 2026-09-22BEIJING YANDONG MICROELECTRONICS
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202610964284.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-30
Publication Date
2026-09-22

AI Technical Summary

Technical Problem

在高输入光功率下,探测器会出现热失效、界面反射、空间电荷效应,这些因素会导致探测器的光电流饱和,并且导致探测器的损坏和光学特性的变化,劣化器件的响应度和带宽

Benefits of technology

1、优化光场分布,突破响应度与带宽的制约瓶颈:通过设置锥形渐变波导和弯曲波导,并且设置波导与Ge吸收区域的结构,形成双侧模式演化耦合,有效克服了传统对接耦合和倏逝耦合中光吸收仅集中在极短接触区域的局限性。通过使光场在整个锗(Ge)吸收层长度范围内实现均匀、长距离的分布,大幅提升了器件对入射光的有效吸收率。这种均匀的光场分布直接打破了传统光电探测器中“响应度与带宽相互制约”的物理瓶颈,在显著提升器件响应度(R值)的同时,保障了优异的高频响应带宽。

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122803455A_ABST
    Figure CN122803455A_ABST
Patent Text Reader

Abstract

The application relates to the technical field of semiconductor photoelectric communication, and discloses a photoelectric detector and a preparation method thereof, which comprise a photoelectric conversion structure and an electrode in communication with the photoelectric conversion structure; the photoelectric conversion structure comprises a silicon waveguide and a Ge absorption region, and two silicon waveguides are arranged on the two sides of the Ge absorption region; the silicon waveguide comprises a bending region and a taper region which are sequentially connected, and the width of the taper region linearly decreases along the light propagation direction; the small end of the taper region of the two silicon waveguides is flush with one end of the Ge absorption region and is arranged on the two sides of the Ge absorption region. The preparation method comprises the steps of waveguide etching, top layer silicon doping, Ge absorption region preparation and electrode preparation, and a double-side mode evolution coupled photoelectric detector is obtained. The double-side mode evolution coupled photoelectric detector can improve light field uniformity, increase coupling efficiency, and prepare a photoelectric detector with a larger bandwidth and higher linearity.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This invention relates to the field of semiconductor optical communication technology, specifically to a photodetector and its fabrication method. Background Technology

[0002] The statements in this section provide only background information relevant to the disclosure of this application and may not constitute prior art.

[0003] Photodetectors convert optical signals into electrical signals and are key components of monolithically integrated silicon photonics. With the rapid development of big data and cloud computing, communication networks face the challenge of surging capacity and increased load. Optical communication systems, as the primary carrier of over 90% of global data traffic, play a crucial role in coping with future traffic explosions due to their high transmission rates and high reliability. An optical communication system consists of three parts: an optical transmitter, a transmission channel, and an optical receiver. Among these, the photodetector, as the core component of the optical receiver, directly affects the overall system performance due to its photoelectric conversion performance.

[0004] There are three important parameters characterizing the performance of photodetectors: the first is dark current, which refers to the current in the detector when there is no incident light power. High dark current can have an adverse noise effect on the detector. The second parameter is responsivity, which measures the current generated per unit of light power incident on the detector. Responsivity is a key parameter for converting light power into current. It is wavelength-dependent and is expressed by the formula R=I / P, where I is the current and P is the incident light power. The third parameter is bandwidth, which represents the detector's response rate to different levels of light signals.

[0005] The structural optimization of waveguide-integrated silicon-based germanium detectors involves both optical and electrical structure optimization. The former relates to light absorption and electron-hole pair generation, while the latter relates to the collection of photogenerated electron-hole pairs. Under high input optical power, detectors can experience thermal failure, interface reflection, and space charge effects. These factors can lead to photocurrent saturation, detector damage, and changes in optical properties, degrading the device's responsivity and bandwidth. Optimizing the optical structure to address photocurrent saturation and degradation under high input optical power, and improving the bandwidth and linearity of the photodetector, is a pressing issue that needs to be addressed.

[0006] The germanium detector involved in this patent has an optimized design for the light incident mode. This structure can improve the uniformity of the light field and increase the coupling efficiency, providing a new approach for the design of photodetectors with large bandwidth and high linearity. Summary of the Invention

[0007] The purpose of this invention is to address the degradation and nonlinearity issues of germanium detectors under high input optical power by providing a photodetector and its fabrication method, which optimizes the waveguide and detector structures and significantly improves the performance of the germanium detector under high input optical power.

[0008] The technical solution of the present invention is as follows: The present invention provides a photodetector, comprising a photoelectric conversion structure and an electrode connected to the photoelectric conversion structure; The photoelectric conversion structure includes a silicon waveguide and a Ge absorption region (germanium absorption region), with two silicon waveguides symmetrically arranged on both sides of the Ge absorption region; The Ge absorption region has a length of L2 and a width of W1. The silicon waveguide includes a curved region and a tapered region connected in sequence. The width of the tapered region decreases linearly along the direction of light propagation and decreases uniformly from both sides towards the central axis. The wider end of the tapered region has a width of W3, and the narrower end has a width of W4. The curved region includes an outer arc segment and an inner arc segment connected to each other. The outer arc segment connects to one end of the tapered region to form a funnel-shaped waveguide structure. The optical signal input end is located at the top of the curved region away from the tapered region. Preferably, the outer and inner circular arc segments are 1 / 4 circular arcs, and the radii of the two arcs are equal; the radius of the arc is L1. The smaller ends of the two silicon waveguide tapered regions are flush with one end of the Ge absorption region and are located on both sides of the Ge absorption region. The central axes of the two tapered regions are parallel to the central axis of the Ge absorption region. The length of the two tapered regions is L2 minus L1. The top surfaces of the silicon waveguide and the Ge absorbing region are located at different heights, with the top surface of the Ge absorbing region being higher than the top surface of the silicon waveguide. The top surface of the Ge absorbing region is 200-400 nm higher than the top surface of the silicon waveguide.

[0009] According to a preferred embodiment, the value of L2 is 20-50 µm.

[0010] According to a preferred embodiment, the value of W3 is 200-500 nm; the value of W4 is 100-200 nm.

[0011] According to a preferred embodiment, L1 is 10-20 µm, and W1 is 500-1000 nm.

[0012] According to a preferred embodiment, the distance between the axis of the tapered region of the two silicon waveguides and the edge of the Ge absorption region is W2. The value of W2 is 50-200 nm.

[0013] According to a preferred embodiment, the thickness of the silicon waveguide is H1. The thickness of the Ge absorption region is H2; H1 is 110-190 nm and H2 is 200-1000 nm.

[0014] According to a preferred embodiment, the photoelectric conversion structure further includes an SOI substrate carrying the Ge absorption region, wherein the SOI substrate comprises, from bottom to top, a silicon substrate layer, a buried oxide layer (BOX layer) disposed above the silicon substrate layer, and a 220 nm top silicon layer. The buried oxide layer is provided with a top silicon layer, with the intrinsic region in the middle and N-type and P-type regions on both sides; the N-type region includes N+ doped region and N++ doped region from the inside to the outside, and the P-type region includes P+ doped region and P++ doped region from the inside to the outside. The Ge absorption region is located above the intrinsic region in the middle of the top silicon layer.

[0015] The silicon waveguide is symmetrically disposed in the N+ doped region and the P+ doped region; the Ge absorption region (9) is embedded in the intrinsic region of the top silicon (30) and epitaxially extended, with an embedding depth of H3, where H3 is 110-190 nm.

[0016] According to a preferred embodiment, the width of the top silicon layer is 10-50 µm, the width of the N+ doped region is 3-10 µm, the width of the N++ doped region is 2-10 µm, the width of the P+ doped region is 3-10 µm, and the width of the P++ doped region is 2-10 µm.

[0017] According to a preferred embodiment, the electrode is connected to the P++ doped region and the N++ doped region and then electrically connected to the photoelectric conversion structure. The electrode, from bottom to top, includes a first tungsten plug layer, a first metal layer, a second tungsten plug layer, and a second metal layer.

[0018] According to a preferred embodiment, the first metal layer is AlCu.

[0019] According to a preferred embodiment, the second metal layer is AlCu.

[0020] Another aspect of the present invention provides a method for fabricating a photodetector as described above, comprising the following steps: S1: Waveguide Etching: A substrate with a top silicon layer is provided, and the top silicon layer is patterned and etched to form a grating structure, a strip waveguide, and two symmetrically arranged silicon waveguides, wherein the silicon waveguides include a curved region and a tapered region connected in sequence; after etching, a layer of SiO2 is deposited to protect the surface of the silicon material. S2: Top silicon doping: Ion implantation is performed on the material after S1 etching to form P-type and N-type regions on both sides of the intrinsic region in the center of the top silicon. N+ doping regions and N++ doping regions are set from the inside to the outside of the N-type region, and P+ doping regions and P++ doping regions are set from the inside to the outside of the P-type region. Then, a layer of SiO2 is deposited to protect the surface of the silicon material. S3: Ge absorption region fabrication: A pattern of Ge absorption region is etched on the intrinsic region. A Ge absorption region is formed by epitaxial growth at the location where the pattern of Ge absorption region is etched on the intrinsic region between the two silicon waveguides. The top surface of the Ge absorption region is higher than the top surface of the silicon waveguide, with a height difference of 200-400 nm. S4: Electrode Fabrication: After depositing and planarizing the dielectric layer, two electrodes are fabricated sequentially. From bottom to top, the electrodes consist of a first tungsten plug layer, a first metal layer, a second tungsten plug layer, and a second metal layer. A first through-hole and a second through-hole are fabricated through the N++ doped region and the P++ doped region, respectively, connecting to the N++ doped region and the P++ doped region. Conductive material is filled into the first and second through-holes until it is flush with the upper surface of the through-holes, forming a first conductive plug and a second conductive plug. A metal thin film is further deposited on top of the first and second conductive plugs to form a first contact electrode and a second contact electrode.

[0021] According to a preferred embodiment, the substrate in S1 is an SOI substrate, which includes a silicon substrate layer, a silicon oxide buried oxide layer and a top silicon layer arranged sequentially from bottom to top.

[0022] Compared with existing technologies, the advantages of this invention are: 1. Optimizing the light field distribution to overcome the bottlenecks of responsivity and bandwidth: By setting up tapered and curved waveguides, and configuring the structure between the waveguides and the Ge absorption region, a two-sided mode evolution coupling is formed, effectively overcoming the limitation of traditional docking and evanescent coupling where light absorption is concentrated only in a very short contact area. By achieving a uniform, long-distance distribution of the light field across the entire length of the germanium (Ge) absorption layer, the effective absorption rate of the device for incident light is significantly improved. This uniform light field distribution directly breaks through the physical bottleneck of "mutual constraint between responsivity and bandwidth" in traditional photodetectors, significantly improving the device's responsivity (R-value) while ensuring excellent high-frequency response bandwidth.

[0023] 2. Suppressing space charge and thermal effects to improve device performance at high power: By achieving a uniform distribution of carrier generation rate within the Ge layer, this design fundamentally avoids excessive accumulation of photogenerated carrier concentration in localized areas. This physical mechanism effectively alleviates the space charge effect (i.e., bandwidth reduction caused by carrier shielding electric field) and localized thermal effects that are prone to occur in traditional devices at high optical power. Therefore, the device not only maintains stable high bandwidth and linearity under high power input conditions, but also significantly improves the overall photocurrent generation capability and operational reliability. Attached Figure Description

[0024] Figure 1 This is a top view of the waveguide and Ge absorption region of the photodetector. Figure 2 This is a cross-sectional view of the complete structure of the photodetector along section A-A'. Figure 3 This is a flowchart illustrating the fabrication method of the silicon-based germanium photodetector of this application.

[0025] Figure reference numerals: 1-Silicon substrate, 10-Waveguide, 11-Grate, 2-Buried oxide layer, 30-Top silicon layer, 31, 32-Silicon waveguide, 33-P+ doped region, 34-N+ doped region, 40-N++ doped region, 41-P++ doped region, 5-First tungsten plug, 6-First metal layer, 7-Second tungsten plug, 8-Second metal layer, 9-Ge absorption region. Detailed Implementation

[0026] The specific embodiments listed in this invention are merely examples, and the invention is not limited to the specific embodiments described below. For those skilled in the art, any equivalent modifications and substitutions to the embodiments described below are also within the scope of this invention. Therefore, all equivalent transformations and modifications made without departing from the spirit and scope of this invention should be covered within its scope. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. All reagents or instruments whose manufacturers are not specified are commercially available conventional products. To better illustrate this invention, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this invention can be practiced even without certain specific details. In other embodiments, methods, means, equipment, and steps well known to those skilled in the art are not described in detail in order to highlight the main points of this invention.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art. Unless otherwise specified, all units used in this specification are International Standard Units (SI), and all numerical values ​​and ranges appearing in this invention should be understood to include systematic errors unavoidable in industrial production.

[0028] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0029] Example 1 This embodiment provides a dual-mode evolution coupled photodetector, including a photoelectric conversion structure and electrodes connected to the photoelectric conversion structure. The photodetector primarily receives light from a grating into a silicon waveguide. Figure 1 As shown, the photoelectric conversion structure includes silicon waveguides 31 and 32 and a Ge absorption region 9. Two silicon waveguides 31 and 32 are respectively disposed on both sides of the Ge absorption region 9. The length of the Ge absorption region 9 is L2, and its width is W1. Silicon waveguides 31 and 32 include a curved region and a tapered region connected in sequence. The width of the tapered region linearly decreases from both sides towards the central axis, with a width of W3 at the larger end and W4 at the smaller end. The curved region includes a 1 / 4 outer arc and a 1 / 4 inner arc connected to each other. The 1 / 4 outer arc connects to the wider end of the tapered region, forming a funnel-shaped waveguide structure. The radii of the 1 / 4 outer arc and the 1 / 4 inner arc are equal; the radius of the arc is L1. The smaller ends of the tapered regions of the two silicon waveguides 31 and 32 are flush with one end of the Ge absorption region on both sides of the Ge absorption region. The central axes of the two tapered regions are parallel to the central axis of the Ge absorption region 9. The lengths of the two tapered regions are L2 minus L1, respectively.

[0030] The distance between the central axis of the two silicon waveguide tapered regions and the edge of the Ge absorption region 9 is W2, which gradually increases from the larger end of the tapered region to the smaller end. The value of W2 ranges from 50 to 200 nm.

[0031] The advantage of this structural design is that it results in better uniformity of incident light, thereby increasing the bandwidth of the device.

[0032] According to a preferred embodiment, such as Figure 2As shown, the photoelectric conversion structure also includes an SOI substrate carrying the Ge absorption region, which, from bottom to top, includes a silicon substrate layer 1 and a BOX layer (buried oxide layer) 2 disposed above the silicon substrate layer; a top silicon layer 30 is disposed above the BOX layer, with an intrinsic region in the middle of the top silicon layer 30 and N-type and P-type regions on both sides; the N-type region includes an N+ doped region 34 and an N++ doped region 40 from the inside to the outside, and the P-type region includes a P+ doped region 33 and a P++ doped region 41 from the inside to the outside; the Ge absorption region 9 is disposed above the intrinsic region in the middle of the top silicon layer 30. The Ge absorption region (9) is embedded in the intrinsic region of the top silicon layer (30) and epitaxially extended, with an embedding depth of 110-190 nm and an epitaxial height of 200-400 nm.

[0033] The N+ doped region 34 and the P+ doped region 33 are symmetrically etched with silicon waveguides 31 and 32 as described above; the height of the silicon waveguide is H1, and the value of H1 is 110-190 nm; the thickness of the Ge absorption region is H2, and the value of H2 is 200-1000 nm.

[0034] The top surfaces of the silicon waveguide and the Ge absorption region are located at different heights, with the top surface of the Ge absorption region higher than the top surface of the silicon waveguide; the top surface of the Ge absorption region is 200–400 nm higher than the top surface of the silicon waveguide. This configuration significantly improves the detector's responsivity under high optical power conditions.

[0035] According to a preferred embodiment, the width of the top silicon 30 is 10-50 µm, the width of the N+ doped region is 3-10 µm, the width of the N++ doped region is 2-10 µm, the width of the P+ doped region is 3-10 µm, and the width of the P++ doped region is 2-10 µm.

[0036] According to a preferred embodiment, the electrode connected to the photoelectric conversion structure is connected to the P++ doped region and the N++ doped region, and the electrode includes, from bottom to top, a first tungsten plug 5, a first metal layer 6, a second tungsten plug 7, and a second metal layer 8.

[0037] According to a preferred embodiment, the first metal layer 7 is AlCu.

[0038] According to a preferred embodiment, the second metal layer 8 is AlCu.

[0039] According to coupled-mode theory, to avoid localized carrier accumulation in the absorption region, the power conversion of Si waveguides to Ge-on-Si structures should be slow and gradual. Therefore, the structural transition needs to be as gentle as possible, requiring both the radius of the curved waveguide and the length of the tapered waveguide to be as long as possible.

[0040] From the perspective of optical absorption, a longer tapered waveguide means a longer Ge absorption region, allowing light to be fully absorbed over a longer propagation distance, thus contributing to improved detector responsivity. However, from the perspective of electrical bandwidth, a longer Ge absorption region results in a larger top and bottom surface area, leading to increased junction capacitance. This increased capacitance degrades the device's RC bandwidth, limiting the overall length and performance of the device.

[0041] Therefore, in device design, a trade-off and optimization is needed between "improving responsivity by extending the absorption region" and "controlling the capacitance to maintain the RC bandwidth".

[0042] After weighing bandwidth against coupling efficiency and responsivity, the following parameters are determined to be preferred in this application: L1 is 5-20 µm, L2 is 20-50 µm, W1 is 500-1000 nm, W2 is 100 nm, W3 is 200-500 nm; W4 is 100-200 nm; H4 is 220 nm; H5 is 70 nm; H3 is 110 nm. The thickness of the inner arc at the end away from the conical region is W5, and W5 is greater than W3. The thickness of the arc gradually decreases uniformly towards the conical region.

[0043] According to the technical solution provided by the present invention, when light enters the silicon waveguides 31 and 32 on both sides, the light is absorbed by the Ge layer in a mode evolution incident manner. Compared with the traditional docking coupling and evanescent coupling, where the Ge layer absorption is only strong at a very short distance between the Ge and the waveguide, the carrier generation rate of the Ge layer is uniformly distributed, achieving longer absorption over the length of the Ge layer. Therefore, the incident light of the Ge layer is increased, preventing the accumulation of local high-concentration carriers. This design physically suppresses the thermal effect and space charge effect of photogenerated carriers, increases the responsivity R value, and increases the bandwidth.

[0044] Example 2: Fabrication of a Two-Sided Mode Evolution Coupled Photodetector According to such Figure 3 Preparation steps shown: S1: Waveguide Etching: Patterned etching is performed on the 220 nm top silicon layer 30 to form a grating structure 11, a strip waveguide 10, and two symmetrically arranged silicon waveguides 31 and 32. The silicon waveguides 31 and 32 include sequentially connected curved and tapered regions. The etching depth of the grating structure 11 is 70 nm, the etching depth of the strip waveguide 10 is 220 nm, and the etching depth of the silicon waveguides 31 and 32 is 110-190 nm. After etching, a thin layer of SiO2 is deposited to protect the surface of the silicon material. Preferably, the substrate is an SOI substrate, which includes a silicon substrate layer, a buried silicon oxide layer, and a top silicon layer arranged sequentially from bottom to top. Standard SOI substrates are commercially available.

[0045] S2: Top silicon doping: After etching in S1, the material is implanted with ions of different concentrations in four separate stages to form an intrinsic region in the middle of the top silicon 30. N-type and P-type regions are formed on both sides of the intrinsic region. N+ doped regions 34 and N++ doped regions 40 are formed from the inside to the outside of the N-type region, and P+ doped regions 33 and P++ doped regions 41 are formed from the inside to the outside of the P-type region. Then, a layer of SiO2 is deposited to protect the surface of the silicon material. CMP is then performed to form a flat surface. S3: Ge Absorption Region Fabrication: A pattern of Ge absorption regions, i.e., Ge-accommodating regions, is etched into the intrinsic region using photolithography and etching. At the location where the Ge absorption region pattern is etched in the intrinsic region between the two silicon waveguides 31 and 32, Ge is selectively epitaxially filled into the Ge-accommodating regions to form Ge absorption region 9. The top surface of Ge absorption region 9 is higher than the top surfaces of the silicon waveguides 31 and 32, with a height difference of 200–400 nm. After epitaxy, a SiO2 cladding layer is deposited.

[0046] S4: The next step is the back-end metal interconnect process. First, the silicon surface is etched to form the first and second vias, exposing the P++ and N++ interfaces. Then, W is used to fill them. Subsequently, the first metal layer, the second tungsten plug, and the second metal layer are filled. The double metal layer is completed, forming a testable structure.

[0047] The values ​​of L1 are 5µm, L2 are 20µm-50µm, W1 is 500-1000 nm, W2 is 100 nm, W3 is 300 nm, and W4 is 100 nm.

[0048] According to a preferred embodiment, the height H1 of the silicon waveguide is 110-190 nm and the thickness H2 of the Ge absorption region is 380 nm.

[0049] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

Claims

1. A photodetector, characterized in that, Includes a photoelectric conversion structure and electrodes electrically connected to the photoelectric conversion structure; The photoelectric conversion structure includes silicon waveguides (31, 32) and a Ge absorption region (9), with the two silicon waveguides (31, 32) symmetrically arranged on both sides of the Ge absorption region (9); The silicon waveguides (31, 32) include a curved region and a tapered region connected in sequence. The width of the tapered region decreases linearly along the direction of light propagation. The curved region includes an outer arc segment and an inner arc segment connected to each other. The outer arc segment is connected to the wider end of the tapered region, forming a funnel-shaped waveguide (31, 32) structure. The curved region is the optical signal input end. The smaller end of the tapered region of the two silicon waveguides (31, 32) is flush with one end of the Ge absorption region (9) and is located on both sides of the Ge absorption region (9). The central axis of the two tapered regions is parallel to the central axis of the Ge absorption region (9). The top surfaces of the silicon waveguides (31, 32) and the Ge absorption region (9) are located at different height layers, with the top surface of the Ge absorption region (9) being higher than the top surface of the silicon waveguides (31, 32).

2. The photodetector according to claim 1, characterized in that, The distance between the central axis of the tapered region of the two silicon waveguides (31, 32) and the edge of the Ge absorption region (9) is W2, where W2 is 50-200 nm.

3. The photodetector according to claim 2, characterized in that, The top surface of the Ge absorption region (9) is 200-400 nm higher than the top surface of the silicon waveguide (31, 32).

4. The photodetector according to claim 2, characterized in that, The radius of the outer and inner circular arc segments is L1, the width of the larger end of the conical region is W3, and the width of the smaller end is W4; W3 is 200-500 nm; W4 is 100-200 nm; and L1 is 10-20 µm.

5. The photodetector according to claim 4, characterized in that, The height of the silicon waveguides (31, 32) is H1, and the value of H1 is 110-190 nm.

6. The photodetector according to claim 1, characterized in that, The thickness of the Ge absorption region (9) is H2, the length is L2, and the width is W1; the value of H2 is 200-1000 nm, the value of L2 is 20 µm-50 µm, and the value of W1 is 500-1000 nm.

7. The photodetector according to claim 1, characterized in that, The photoelectric conversion structure also includes an SOI substrate that carries the Ge absorption region (9). The SOI substrate includes, from bottom to top, a silicon substrate layer (1) and a buried oxide layer (2) disposed above the silicon substrate layer (1). A top silicon layer (30) is provided above the buried oxide layer (2). The top silicon layer (30) is provided with an intrinsic region in the middle and N-type and P-type regions on both sides. The N-type region includes an N+ doped region (34) and an N++ doped region (40) from the inside to the outside. The P-type region includes a P+ doped region (33) and a P++ doped region (41) from the inside to the outside. The Ge absorption region (9) is located above the intrinsic region in the middle of the top silicon layer (30).

8. The photodetector according to claim 7, characterized in that, The N+ doped region (34) and P+ doped region (33) are respectively symmetrically provided with silicon waveguides (31, 32); the Ge absorption region (9) is embedded in the intrinsic region of the top silicon (30) and epitaxially extended, with an embedding depth of H3, where H3 is 110-190 nm.

9. The photodetector according to claim 7, characterized in that, The electrode is connected to the N-type region and P-type region of the SOI substrate and then electrically connected to the photoelectric conversion structure. The electrode includes, from bottom to top, a first tungsten plug (5), a first metal layer (6), a second tungsten plug (7), and a second metal layer (8).

10. A method for fabricating a photodetector, characterized in that, The The steps include the following: S1: Waveguide etching: A substrate with a top silicon layer (30) is provided, and the top silicon layer (30) is patterned and etched to form a grating structure (11), a strip waveguide (10) and two symmetrically arranged silicon waveguides (31, 32), wherein the silicon waveguides (31, 32) include a curved region and a tapered region connected in sequence; S2: Top silicon doping: Ion implantation is performed on the material after S1 etching to form P-type and N-type regions on both sides of the intrinsic region in the center of the top silicon (30); S3: Ge absorption region preparation: A pattern of Ge absorption region (9) is etched on the intrinsic region. Ge absorption region (9) is formed by epitaxial growth at the location where the pattern of Ge absorption region is etched on the intrinsic region between the two silicon waveguides (31, 32). The top surface of the Ge absorption region (9) is higher than the top surface of the silicon waveguides (31, 32), and the height difference is 200-400 nm. S4: Electrode preparation: After depositing and planarizing the dielectric layer, two electrodes are prepared in sequence. The electrodes, from bottom to top, include a first tungsten plug (5), a first metal layer (6), a second tungsten plug (7), and a second metal layer (8). The two first tungsten plugs form ohmic contacts with the N-type region and the P-type region, respectively, to complete the preparation of the electrodes.