Light emitting diode, manufacturing method and light emitting device

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides a light-emitting diode, a manufacturing method and a light-emitting device. The light-emitting diode comprises a substrate, a semiconductor stack and a contact electrode layer which are sequentially arranged on the substrate, and further comprises: an insulating structure covering the surface of the contact electrode layer, the insulating structure comprising a passivation layer located on part of the surface of the contact electrode layer and a first insulating layer located on part of the surface of the passivation layer, wherein the passivation layer has a first opening part; a pad electrode arranged above the passivation layer, the pad electrode being electrically connected with the contact electrode layer through the first opening part; and the projection area of the first opening part on the contact electrode layer is located in the projection area of the pad electrode on the contact electrode layer. According to the application, the insulating structure and the opening morphology design are utilized, the edge gap of the insulating layer is eliminated, water vapor leakage and metal diffusion are effectively blocked, and the reliability of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode, a manufacturing method thereon, and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device whose basic structure consists of a PN junction between a P-type semiconductor and an N-type semiconductor. When a forward voltage is applied to the LED, electrons and holes recombine at the junction of the PN junction, releasing energy. This energy is emitted in the form of photons, forming light radiation.

[0003] In conventional flip-chip LEDs, the contact electrode layer (PAD1) and the pad electrode (PAD2) need to be locally electrically isolated by an insulating layer, with electrical connection only achieved in the bonding area. Traditional processes typically use a single layer of silicon dioxide (SiO2) as a passivation layer, and then create windows in the bonding area through wet etching before depositing pad metal. This process has at least the following problems:

[0004] First, the gaps result in poor sealing. Wet etching is an isotropic process that creates tiny gaps at the edges of openings in the insulating layer. When the solder pad metal is deposited, it is difficult to completely fill these gaps, allowing moisture to seep in along the interface, corroding the internal metal layer and causing device failure.

[0005] Second, intermetallic diffusion leads to structural damage. High thermal conductivity gold (Au) or gold-tin (AuSn) eutectic materials are commonly used for pad electrodes, while the contact electrode layer often contains an aluminum (Al) layer for stress balancing. These gaps provide diffusion paths for gold atoms. Under high-temperature packaging or long-term operating conditions, Au diffuses downwards through these gaps, reacting with Al in the underlying electrode layer to form intermetallic compounds such as AuAl2. This leads to volume expansion and film rupture, severely impacting device performance and lifespan. Summary of the Invention

[0006] In view of the defects and deficiencies existing in the prior art, this application provides a light-emitting diode, a manufacturing method and a light-emitting device, which utilizes a stacked insulating structure and optimizes its opening structure, thereby solving the problems of water vapor leakage and metal diffusion.

[0007] In a first aspect, this application provides a light-emitting diode, including a substrate and a semiconductor stack and a contact electrode layer sequentially disposed on the substrate, and further comprising:

[0008] An insulating structure covering the surface of the contact electrode layer;

[0009] The insulating structure includes a passivation layer located on a portion of the surface of the contact electrode layer, and a first insulating layer located on a portion of the surface of the passivation layer; wherein the passivation layer has a first opening;

[0010] A pad electrode is disposed above the passivation layer and electrically connected to the contact electrode layer through a first opening;

[0011] In the top view of the light-emitting diode, the projection area of ​​the first opening on the contact electrode layer is located within the projection area of ​​the pad electrode on the contact electrode layer.

[0012] Secondly, this application provides a method for manufacturing a light-emitting diode, comprising the following steps:

[0013] S1: Provides a semiconductor structure including a semiconductor stack and a contact electrode layer having a circuit pattern formed thereon;

[0014] S2: A passivation layer covering the contact electrode layer and the chip surface and a first insulating layer located on the passivation layer are formed sequentially to obtain an insulating structure;

[0015] S3: Photoresist is coated and patterned on the insulating structure corresponding to the bonding region to form an opening;

[0016] S4: A dry etching process is used to etch the first insulating layer and the passivation layer in sequence. The etching rate of the first insulating layer is greater than the etching rate of the passivation layer. As a result, when etching to the surface of the contact electrode layer, the degree of lateral over-etching of the first insulating layer is greater than the degree of lateral over-etching of the passivation layer.

[0017] S5: Remove the photoresist, deposit a pad electrode in the bonding area, fill the first opening of the passivation layer and cover the sidewalls and part of the surface of the passivation layer.

[0018] Thirdly, this application provides a light-emitting device, comprising: an encapsulation substrate; at least one light-emitting diode disposed on the surface of the encapsulation substrate, wherein the encapsulation substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is any of the light-emitting diodes described above, or a light-emitting diode manufactured using any of the methods described above.

[0019] Compared with the prior art, the technical solution provided in this application has at least the following beneficial effects:

[0020] The technical solution provided in this application utilizes a multilayered insulation structure design, employing a highly dense aluminum oxide layer as a passivation layer. Combined with a stepped opening structure formed by dry etching, this allows the pad electrodes to directly cover the surface and sidewalls of the dense passivation layer, eliminating the edge gaps generated in traditional wet processes and cutting off the channels for moisture penetration. Simultaneously, the contact electrode layer includes a diffusion barrier layer, which effectively prevents gold atoms in the pad electrodes from diffusing into the aluminum layer in the contact electrode layer. This fundamentally avoids the formation of brittle intermetallic compounds such as AuAl2, eliminates the risk of film rupture caused by volume expansion, and significantly improves the long-term reliability and lifespan of the device under harsh environments such as high temperature and high humidity. Attached Figure Description

[0021] Figure 1 A schematic diagram of the planar structure of the light-emitting diode provided in Embodiment 1;

[0022] Figure 2 A partially enlarged schematic diagram of the pad electrode and insulating structure provided for one embodiment;

[0023] Figure 3 A partially enlarged schematic diagram of the pad electrode and insulation structure provided for another embodiment;

[0024] Figure 4 A flowchart of the method for manufacturing a light-emitting diode provided in Example 2;

[0025] Figure 5 This is a schematic diagram of the light-emitting device provided in Embodiment 3.

[0026] List of reference numerals in the attached diagram:

[0027] 100, Substrate; 200, Semiconductor stack; 210, First semiconductor layer; 220, Active layer; 230, Second semiconductor layer; 201, First mesa; 202, Second mesa; 300, Transparent conductive layer; 400, Current blocking layer; 500, Reflective structure; 510, DBR structure layer; 520, Specular reflection layer; 600, Second insulating layer; 700, Contact electrode layer; 710, First contact layer; 720, Second contact layer; 800, Insulating structure; 810, Passivation layer; 820, First insulating layer; 910, First pad; 920, Second pad; OP1, First opening; OP2, Second opening;

[0028] 10. Light-emitting device; 101. Packaging substrate; 102. Light-emitting element. Detailed Implementation

[0029] In view of the drawbacks of the prior art mentioned in the background section, this application provides a light-emitting diode, including a substrate and a semiconductor stack and a contact electrode layer sequentially disposed on the substrate, and further comprising:

[0030] An insulating structure covering the surface of the contact electrode layer;

[0031] The insulating structure includes a passivation layer located on a portion of the surface of the contact electrode layer, and a first insulating layer located on a portion of the surface of the passivation layer; wherein the passivation layer has a first opening;

[0032] A pad electrode is disposed above the passivation layer and electrically connected to the contact electrode layer through a first opening;

[0033] In the top view of the light-emitting diode, the projection area of ​​the first opening on the contact electrode layer is located within the projection area of ​​the pad electrode on the contact electrode layer.

[0034] By adopting the above technical solution, a stacked structure including a passivation layer and a first insulating layer is set on the contact electrode layer, and the edge projection of the first opening is controlled to be within the edge projection range of the pad electrode, so that the pad electrode can completely cover the opening of the passivation layer. The pad metal and the upper surface of the passivation layer form a continuous and uninterrupted contact interface, eliminating the gaps caused by the isotropic wet corrosion in the prior art, effectively blocking water vapor from penetrating into the interior of the structure along the sidewall, and improving the reliability of the device.

[0035] In one embodiment, the first insulating layer has a second opening, and the projection of the pad electrode on the contact electrode layer is located within the projection area of ​​the second opening on the contact electrode layer. In this way, the pad electrode will not contact the sidewall of the first insulating layer during deposition, thus avoiding breakage or poor coverage of the pad metal at the step.

[0036] In one implementation, the sidewall slope of the passivation layer at the first opening is greater than the sidewall slope of the first insulating layer at the second opening. This achieves a good balance between the quality of the insulation structure and its fabrication feasibility.

[0037] In one embodiment, the passivation layer is made of aluminum oxide, and the thickness of the passivation layer is from 0.03 μm to 0.2 μm. The use of alumina, with its good density, as the passivation layer material effectively blocks the diffusion of moisture and metal ions. The aforementioned thickness range ensures the blocking effect while avoiding increased thermal resistance or excessive stress due to excessive film thickness.

[0038] In one embodiment, the material of the first insulating layer includes silicon dioxide, and the thickness of the first insulating layer is 0.5 μm to 1.5 μm. Selecting silicon dioxide of a suitable thickness as the first insulating layer, forming a composite insulating structure with the alumina layer, improves the overall insulation reliability.

[0039] In one implementation, the thickness of the passivation layer is less than the thickness of the first insulating layer. The passivation layer is less likely to form excessively high steps at the edge of the pad electrode, reducing the risk of breakage of the pad electrode. At the same time, the thinner passivation layer will not increase additional thermal resistance or deformation, and has less impact on the bonding process, ensuring bonding reliability.

[0040] In one implementation, there is a distance D1 between the edge projection of the first opening and the edge projection of the pad electrode, where 0 μm < D1 ≤ 10 μm. This further ensures that the pad electrode completely covers the edge of the passivation layer opening, achieving a good seal, and also guarantees sufficient electrical contact area between the pad electrode and the underlying contact electrode layer, while avoiding increasing the cost of metal materials.

[0041] In one implementation, there is a distance D2 between the edge projection of the pad electrode and the edge projection of the second opening, where 0μm < D2 ≤ 2μm, so that the coverage area of ​​the first insulating layer is large enough to optimize the layout space of the insulating layer and the electrode.

[0042] In one embodiment, the contact electrode layer includes a stress balancing layer and a diffusion barrier layer; wherein the stress balancing layer comprises an aluminum material layer. By providing a diffusion barrier layer in the contact electrode layer, gold atoms can be effectively prevented from diffusing into the aluminum layer, thus suppressing the formation of brittle compounds such as AuAl2 at the source.

[0043] In one embodiment, the diffusion barrier layer is made of one or more of platinum, titanium, chromium, or nickel.

[0044] In one embodiment, the material of the pad electrode is gold or gold-tin eutectic material.

[0045] This application also provides a method for fabricating a light-emitting diode, comprising the following steps: S1: providing a semiconductor structure, including a semiconductor stack and a contact electrode layer with a circuit pattern formed thereon; S2: sequentially forming a passivation layer covering the contact electrode layer and the chip surface and a first insulating layer located on the passivation layer to obtain an insulating structure; S3: coating photoresist on the insulating structure corresponding to the bonding region and patterning it to form an opening; S4: using a dry etching process to sequentially etch the first insulating layer and the passivation layer, wherein the etching rate of the first insulating layer is greater than the etching rate of the passivation layer, so that when etching to the surface of the contact electrode layer, the lateral over-etching degree of the first insulating layer is greater than the lateral over-etching degree of the passivation layer; S5: removing the photoresist, depositing a pad electrode in the bonding region to fill the first opening of the passivation layer and cover the sidewall and part of the surface of the passivation layer.

[0046] By adopting the above technical solution, a passivation layer is deposited first, followed by a first insulating layer. Then, through a single photolithography and sequential dry etching, the difference in etching rates between the two materials is utilized to make the lateral over-etching degree of the first insulating layer greater than that of the passivation layer, thereby naturally forming a stepped opening structure that is wider at the top and narrower at the bottom. Only one photolithography is required, and no complex additional processes are needed to achieve good coverage of the passivation layer edge by the pad electrode.

[0047] In one embodiment, the passivation layer is made of aluminum oxide and is prepared by atomic layer deposition or plasma-enhanced chemical vapor deposition; the first insulating layer is made of silicon dioxide and is prepared by plasma-enhanced chemical vapor deposition.

[0048] In one implementation, the dry etching process uses a mixed gas containing fluorocarbon and chlorine-based gases. By adjusting the ratio of the mixed gas, the etching selectivity ratio between the first insulating layer and the passivation layer is made greater than 1. By adjusting the composition of the etching gas, the difference in etching rates between the two insulating layers can be precisely controlled. The higher the selectivity ratio, the more obvious the difference in lateral over-etching, thereby precisely controlling the morphology of the opening and obtaining a predetermined stepped structure.

[0049] This application also provides a light-emitting device, comprising: a packaging substrate; at least one light-emitting diode (LED) disposed on the surface of the packaging substrate, wherein the packaging substrate and the electrode structure of the LED are electrically connected; the LED is any of the LEDs described above, or an LED manufactured using any of the methods described above. The light-emitting device configured with the aforementioned LED also exhibits excellent moisture resistance and resistance to metal diffusion, significantly improving product performance and lifespan.

[0050] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0051] The composition and dopants of each layer of the light-emitting diode in this application can be analyzed by any suitable method, such as secondary ion mass spectrometry (SIMS). The thickness of each layer of the light-emitting diode in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM), in conjunction with, for example, the depth positions of each layer on a SIMS spectrum.

[0052] Example 1:

[0053] This embodiment provides a light-emitting diode (LED), see [link]. Figures 1 to 3 The light-emitting diode includes a substrate 100, a semiconductor stack 200, a transparent conductive layer 300, a current blocking layer 400, a reflective structure 500, a second insulating layer 600, a contact electrode layer 700, an insulating structure 800, and pad electrodes, etc. The projection of the light-emitting diode along its top view direction is a horizontal projection. The specific structure and technical solution of the light-emitting diode provided in this embodiment will be described in detail below.

[0054] See Figure 1 The substrate 100, as the epitaxial growth substrate, can be a conductive material, insulating material, or light-transmitting material with excellent thermal conductivity, such as a sapphire substrate, silicon carbide substrate, gallium nitride substrate, zinc oxide substrate, gallium arsenide substrate, or silicon substrate.

[0055] See also Figure 1A semiconductor stack 200 is disposed on a substrate 100. The semiconductor stack 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230 stacked sequentially. Each material layer can be formed by methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, hydride vapor deposition, physical vapor deposition, or ion plating. In this embodiment, the first semiconductor layer 210 is an electron-providing layer and can be formed by implanting n-type dopants, such as Si, Ge, Se, Te, and C. The second semiconductor layer 230 is a hole-providing layer and can be formed by implanting p-type dopants, such as Mg, Zn, Be, Ca, Sr, and Ba. The active layer 220 is a layer that outputs light of a predetermined wavelength by combining electrons and holes. It can be a single-layer or multi-layer quantum well structure with alternating stacked potential well layers and barrier layers, such as one of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs(InGaAs) / AlGaAs, or GaP(InGaP) / AlGaP. The semiconductor stack 200 is etched to expose a first mesa 201 on the upper surface of the first semiconductor layer 210 and a second mesa 202 on the upper surface of the second semiconductor layer 230.

[0056] See also Figure 1 A transparent conductive layer 300 is formed on the semiconductor stack 200, and the transparent conductive layer 300 is located above the second mesa 202 to achieve higher current injection efficiency. The transparent conductive layer 300 can be one or a combination of ITO, InO, SnO, CTO, AZO, ATO, GZO, ZnO, and GaP. Further, the thickness of the transparent conductive layer 300 is between 5 nm and 50 nm.

[0057] See also Figure 1 A current blocking layer 400 and a DBR structure layer 510 are formed on the transparent conductive layer 300 using physical vapor deposition or chemical vapor deposition. The current blocking layer 400 and the DBR structure layer 510 are located on the upper surface and sidewalls of the transparent conductive layer 300, the upper surface and sidewalls of the second mesa 202, and extend to a portion of the upper surface of the first mesa 201. They are then patterned using photolithography and etching to create multiple openings that expose the surface of the transparent conductive layer 300. The current blocking layer 400 can spread the current throughout the entire light-emitting area, preventing current accumulation below the electrodes, resulting in more uniform light emission in different areas of the active layer 220, effectively improving the internal quantum efficiency and light emission brightness. Its materials include SiO2, SiN, and SiO2. x N yThe material is selected from at least one of the following: TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, and MgF2. The DBR structure layer 510 is a stack of two materials with different refractive indices stacked alternately, used to reflect a portion of the light from the light-emitting structure towards the substrate and then emit it. For example, the first material layer is a SiO2 layer, and the second material layer is a TiO2 layer. The mirror reflection layer 520 forms an ohmic contact with the transparent conductive layer 300 through the openings in the current blocking layer 400 and the DBR structure layer 510. It can be made of one or more materials and alloys of Ag, Al, Ti, Ni, Pt, Au, Rh, TiW, TiN, etc.

[0058] See also Figure 1 A second insulating layer 600 is formed on the specular reflective layer 520. The edge of the second insulating layer 600 extends to cover the sidewalls of the specular reflective layer 520 and the DBR structure layer 510. The second insulating layer 600 has electrode holes, through which the upper electrode structure makes ohmic contact with the first semiconductor layer 210 and the second semiconductor layer 230, respectively. The material of the second insulating layer 600 can be SiO2. x SiN x TiO2, Al x O y or MgF y It can also be a multilayer structure, such as a DBR structure layer. The second insulating layer 600 not only provides mechanical protection and electrical insulation, but its laterally extended coverage structure also helps to isolate the edges of the underlying film layer, improving the reliability of the device structure.

[0059] See Figures 1 to 3 A contact electrode layer 700 is formed on the second insulating layer 600. The contact electrode layer 700 includes a first contact layer 710 that is in contact with the first semiconductor layer 210 ohms and a second contact layer 720 that is in contact with the second semiconductor layer 230 ohms.

[0060] The contact electrode layer 700 comprises, from bottom to top, a reflective layer, a protective layer, a stress balancing layer, a diffusion barrier layer, and an adhesion layer. The stress balancing layer contains at least one aluminum material layer. The diffusion barrier layer is located above the contact electrode layer and serves to achieve ohmic contact with the subsequently deposited pad electrodes, while also acting as a barrier to prevent the downward diffusion of atoms such as gold and tin.

[0061] As an example, the reflective layer is located at the bottom of the contact electrode layer. Its main function is to reflect light emitted from the active area, reduce light absorption, and improve the light extraction efficiency of the chip. The reflective layer can be made of aluminum (Al), silver (Ag), or chromium (Cr), as well as their alloys or stacks, and the thickness of the reflective layer can be from 100 nm to 500 nm.

[0062] As an example, the protective layer can be made of titanium (Ti), nickel (Ni), or a combination of both, to effectively block oxygen, water vapor, and corrosive gases. The thickness of the protective layer can be from 10 nm to 100 nm.

[0063] As an example, the stress regulation layer sits above the protective layer, primarily serving the dual functions of thermal stress buffering and lateral current propagation. The stress regulation layer can be a stacked structure of Ti and Al layers, with the Ti layer at the bottom, having a thickness of 5nm to 50nm, forming a smooth transition with the protective layer. Simultaneously, the Ti layer acts as the adhesion substrate for the Al layer, which sits above the Ti layer, with a thickness of 200nm to 800nm, forming the main layer for stress regulation. It is understood that aluminum has a low Young's modulus and high plastic deformation capacity, enabling it to undergo plastic flow during the high-temperature processes of chip manufacturing and subsequent packaging bonding, absorbing and dissipating thermal stress, and preventing chip warping or passivation layer cracking.

[0064] As an example, the barrier layer is located above the stress regulation layer. Although the aluminum layer in the stress regulation layer provides stress balance, Au in the pad electrodes easily reacts with Al to form brittle AuAl2, which poses a risk of intermetallic diffusion. The barrier layer can be a single layer or a stack of one or more of chromium (Cr), platinum (Pt), titanium (Ti), and nickel (Ni), with a thickness ranging from 30 nm to 200 nm. It effectively prevents gold or gold-tin alloys in the pad electrodes from diffusing downwards to the aluminum layer at high temperatures, thereby avoiding the formation of harmful intermetallic compounds.

[0065] See also Figures 1 to 3 The insulating structure 800 includes a passivation layer 810 located on a portion of the surface of the contact electrode layer 700, and a first insulating layer 820 located on a portion of the surface of the passivation layer 810. The insulating structure 800 provides electrical isolation and physical protection. The passivation layer 810 directly covers the surface of the contact electrode layer 700, and its material is typically a highly dense dielectric material, such as an alumina layer, which effectively prevents moisture penetration. The first insulating layer 820 is located above the passivation layer 810, and its material can be a material with good insulating properties, such as silicon dioxide. Its thickness is typically greater than that of the passivation layer 810, and it primarily serves as insulation and withstand voltage.

[0066] In the bonding region, the passivation layer 810 has a first opening OP1, and the first insulating layer 820 has a second opening OP2. In a top view, the edge projection of the first opening OP1 lies within the edge projection range of the upper pad electrode. Specifically, the pad electrode includes a first pad 910 in direct contact with the first contact layer 710, and a second pad 920 in direct contact with the second contact layer 720. The first opening OP1 of the passivation layer 810 exposes the surface of the underlying contact electrode layer 700. The pad electrode fills the opening and covers the sidewalls and part of the upper surface of the passivation layer 810. Because the edge of the first opening OP1, i.e., the edge of the sidewall of the passivation layer 810, is completely and seamlessly covered by the pad electrode, the metal of the pad electrode can directly and tightly adhere to the dense upper surface of the passivation layer 810, thereby forming a structure similar to a sealed cap. The edge projection of the pad electrode is located outside the edge projection of the first opening OP1. This means that the edge projections of both the first pad 910 and the second pad 920 are located outside the edge projection of the first opening OP1. The following description of the pad electrode includes both the first pad 910 and the second pad 920, and no further distinction will be made.

[0067] It should be understood that if the edge of the first opening OP1 is not completely covered by the pad electrode, i.e., there is an exposed step or gap between the sidewall of the passivation layer 810 and the pad electrode, moisture in the environment can easily seep in along this step or gap during subsequent packaging or use, corroding the underlying contact electrode layer 700, especially the aluminum layer therein, leading to device failure. The pad electrode extends outward beyond the opening edge of the passivation layer 810, completely eliminating the seepage path of moisture along the insulating structure and the gap in the sidewall of the pad electrode. The pad electrode not only achieves good electrical connection with the contact electrode layer 700, but also acts as a sealing structure for the opening edge of the passivation layer 810, realizing the dual functions of electrical connection and moisture-proof sealing, significantly improving the reliability of the light-emitting diode.

[0068] In an optional implementation, see [link to implementation details]. Figure 2 The edge projection of the first opening OP1 is within the edge projection range of the pad electrode, and the edge projection of the pad electrode is within the edge projection range of the second opening OP2. That is, the pad electrode only covers the edge of the passivation layer 810 to ensure a basic sealing effect, but the edge of the first insulating layer 820 is not covered by the pad electrode, and the sidewall portion of the first insulating layer 820 is exposed to the environment.

[0069] In an optional implementation, see [link to implementation details]. Figure 3The edge projection of the first opening OP1 is located within the edge projection range of the pad electrode, and the edge projection of the pad electrode is located within the edge projection range of the second opening OP2. This means that in the top view, the pad electrode not only covers the edge of the passivation layer 810, but also extends outward to cover the edge of the first insulating layer 820, completely cutting off the communication path between the external environment and the internal contact electrode layer 700.

[0070] See Figure 2 and Figure 3 The passivation layer 810 has a steeper sidewall slope at the first opening OP1 than the first insulating layer 820 has at the second opening OP2, resulting in an inverted trapezoidal structure that is wider at the top and narrower at the bottom. Specifically, the steeper sidewall of the passivation layer 810 maximizes the contact area between the pad electrode and the lower contact electrode layer 700; while the gentler sidewall of the first insulating layer 820 results in a wider opening, which facilitates the filling of the pad electrode metal material and reduces the risk of voids or cracks. It is understood that this stepped structure is naturally formed under specific etching processes, and its morphology can be controlled by adjusting process parameters.

[0071] See also Figure 2 and Figure 3 There is a distance D1 between the edge projection of the first opening OP1 and the edge projection of the pad electrode, where 0μm < D1 ≤ 10μm. If D1 is too small, for example, close to 0μm, although theoretical coverage is achieved, gaps in incomplete coverage are easily generated under actual process alignment deviations, leading to a decrease in sealing performance. If D1 is too large, for example, exceeding 10μm, the area of ​​the pad electrode will unnecessarily increase, crowding out the effective light-emitting area of ​​the chip or increasing parasitic capacitance. Furthermore, this distance D1 can be set to 2μm to 6μm, which can ensure the coverage width of the pad electrode on the edge of the passivation layer 810, ensuring sealing reliability, without affecting the contact area of ​​the pad electrode, thus optimizing the chip area utilization. Similarly, see [link to relevant documentation]. Figure 2 and Figure 3 There is a distance D2 between the edge projection of the pad electrode and the edge projection of the second opening OP2, where 0 μm < D2 ≤ 2 μm. For example, the distance D2 can be set to 1 μm.

[0072] See also Figure 2 and Figure 3The passivation layer 810 is an alumina layer. Alumina has extremely high density and is an excellent material for moisture barrier layers, with a thickness of 0.03 μm to 0.2 μm. Understandably, if the alumina layer is too thin, for example, less than 0.03 μm, its pinhole density increases, making it difficult to form a continuous and dense structural layer; if the thickness is too thick, for example, greater than 0.2 μm, although the barrier effect is better, it increases the contact resistance and thermal resistance between the pad electrode and the contact electrode layer 700. Furthermore, the alumina layer itself is relatively brittle, and excessive thickness can easily lead to cracking under thermal stress, introducing new failure risks. Therefore, the passivation layer 810 has a thickness of 0.05 μm to 0.15 μm, ensuring both barrier effect and electrical and thermal performance.

[0073] See also Figure 2 and Figure 3 The first insulating layer 820 is made of silicon dioxide, which has good insulation and withstand voltage properties and a mature deposition process. Its thickness is 0.5μm to 1.5μm. This setting is based on the principle of meeting the overall insulation and withstand voltage requirements of the chip.

[0074] Furthermore, the thickness of the passivation layer 810 is less than the thickness of the first insulating layer 820. Specifically, since the passivation layer 810 is made of dense alumina material, its barrier effect is sufficient even with a relatively thin thickness. Therefore, the aforementioned thickness constraint ensures that the step height formed by the passivation layer 810 at the edge of the pad electrode is low, preventing the pad electrode from breaking due to the raised step. At the same time, the thinner passivation layer 810 has minimal impact on the thermal resistance of the eutectic bonding process, ensuring good thermal conductivity and reliability at the bonding interface. The thicker first insulating layer further ensures its insulation capability and isolation effect against external moisture intrusion.

[0075] See Figures 1 to 3 The pad electrode is made of gold or gold-tin eutectic material. Gold or gold-tin eutectic material has good electrical conductivity, thermal conductivity and excellent bonding performance. It can form a strong ohmic contact with the contact electrode layer 700 below and fit tightly with the edge of the alumina passivation layer 810, realizing the integration of electrical connection and sealing, and facilitating the interconnection of flip chip and external substrate.

[0076] Example 2:

[0077] This embodiment provides a method for fabricating a light-emitting diode (LED), used to prepare the LED as described in Embodiment 1. See also... Figure 1 and Figure 4 The method specifically includes the following steps:

[0078] Step S1: Provide a semiconductor structure, including a semiconductor stack 200 and a contact electrode layer 700 having a circuit pattern formed thereon.

[0079] Specifically, the semiconductor structure can be a semiconductor stack 200 epitaxially grown on a substrate 100, such as a GaN wafer with epitaxial growth and electrode patterning completed. The pattern of the contact electrode layer 700 defines the position of the subsequent bonding region. The contact electrode layer 700 is a multilayer structure including a stress balancing layer and a diffusion barrier layer. The stress balancing layer contains at least one aluminum material layer, and the diffusion barrier layer can effectively prevent gold atoms from diffusing into the aluminum layer, thereby suppressing metal diffusion of the pad electrode and the formation of brittle compounds such as AuAl2 from the source.

[0080] Step S2: A passivation layer 810 covering the contact electrode layer 700 and the chip surface and a first insulating layer 820 located on the passivation layer 810 are formed sequentially to obtain an insulating structure 800.

[0081] Specifically, the passivation layer 810 is made of aluminum oxide and is prepared using atomic layer deposition or plasma-enhanced chemical vapor deposition (PECVD). The first insulating layer 820 is made of silicon dioxide and is prepared using PECVD. In this step, a dense aluminum oxide film is first deposited as the passivation layer 810, with a thickness controlled between 0.03 μm and 0.2 μm to obtain excellent moisture barrier capability. Subsequently, a thicker silicon dioxide layer is deposited as the first insulating layer 820, with a thickness controlled between 0.5 μm and 1.5 μm to provide sufficient insulation withstand voltage capability. When depositing the above insulating structure 800, by controlling the deposition time and process parameters, the thickness of the passivation layer 810 is made smaller than the thickness of the first insulating layer 820. The thinner passivation layer 810 ensures a dense barrier effect while avoiding the formation of excessively high steps at the edge of the pad electrode, thus ensuring the reliability of the device structure.

[0082] Step S3: Coat and pattern photoresist on the insulating structure 800 corresponding to the bonding region to form an opening.

[0083] Specifically, the bonding area window that needs to be exposed in the contact electrode layer 700 is defined by photolithography. In the photoresist patterning stage, by controlling the size of the photoresist opening, it can be made smaller than the width of the final deposited pad electrode. Thus, after etching, a certain coverage distance D1 is naturally formed between the edge of the first opening OP1 of the passivation layer 810 and the edge of the pad electrode. D1≤10μm, which can ensure the sealing coverage effect of the subsequent pad electrode on the edge of the passivation layer opening from the process level.

[0084] Step S4: Using a dry etching process, the first insulating layer 820 and the passivation layer 810 are etched sequentially. The etching rate of the first insulating layer 820 is greater than the etching rate of the passivation layer 810. As a result, when etching to the surface of the contact electrode layer 700, the degree of lateral over-etching of the first insulating layer 820 is greater than the degree of lateral over-etching of the passivation layer 810. A first opening OP1 is formed in the passivation layer 810 and a second opening OP2 is formed in the first insulating layer 820.

[0085] Specifically, the dry etching process uses a mixed gas containing fluorocarbon and chlorine-based gases. By adjusting the ratio of the mixed gases, the etching selectivity ratio for the first insulating layer and the passivation layer is made greater than 1. For example, by adjusting the ratio of fluorocarbon gases such as carbon tetrafluoride (CF4) or trifluoromethane (CHF3) to chlorine gases such as chlorine (Cl2) or boron trichloride (BCl3), the etching rate of silicon dioxide is made significantly faster than that of alumina.

[0086] It should be understood that during the etching of the silicon dioxide layer, the active free radicals generated by the fluorocarbon gas react with the silicon dioxide to produce volatile products. Simultaneously, due to the auxiliary effect of ion bombardment, the etching rate is relatively fast. When etching reaches the underlying alumina passivation layer, the high lattice energy and chemical stability of alumina result in lower reactivity to fluorine-based gases. Furthermore, the etching rate of alumina by chlorine-based gases is also relatively slow, leading to a significant decrease in the etching rate of the alumina layer. This high selectivity causes the etching to eventually stop at the surface of the contact electrode layer, naturally forming a stepped structure with a wide opening in the first insulating layer and a narrow opening in the passivation layer.

[0087] Step S5: Remove the photoresist, deposit pad electrodes in the bonding area, fill the first opening OP1 and cover the sidewalls and part of the surface of the passivation layer 810.

[0088] Specifically, since the stepped opening formed in step S4 has a structure that is wider at the top and narrower at the bottom, it is beneficial for the step coverage during the metal deposition process, reducing the risk of forming voids or open circuits on the sidewalls of the opening. The deposited gold or gold-tin eutectic material pad electrode can smoothly fill the first opening OP1 and extend to cover the upper surface edge of the passivation layer 810.

[0089] By employing the above-described process, a light-emitting diode (LED) with excellent moisture-proof sealing performance and resistance to metal diffusion was obtained. This method utilizes the selectivity characteristics of dry etching to construct a composite insulating layer opening with a specific morphology in a single step, effectively solving the water vapor leakage problem caused by the uncovered edges of the insulating layer opening in existing technologies. It requires no additional complex processes, exhibits good process compatibility, and is suitable for large-scale industrial production.

[0090] Example 3:

[0091] See Figure 5 This embodiment provides a light-emitting device 10, which is a flip-chip LED product, including a packaging substrate 101; at least one light-emitting element 102 disposed on the surface of the packaging substrate 101, and the packaging substrate 101 is electrically connected to the electrode structure of the light-emitting diode. The light-emitting element 102 is the light-emitting diode provided in Embodiment 1 or a light-emitting diode manufactured using the method of Embodiment 2.

[0092] Because this LED employs an optimized insulation structure design—that is, a passivation layer and a first insulating layer are sequentially disposed on the surface of the contact electrode layer, and the edge projection of the first opening is controlled to be within the edge projection range of the pad electrode—the LED already possesses excellent sealing performance before packaging. During the packaging process, when the pad electrode and the packaging substrate undergo eutectic bonding, the contact electrode layer effectively prevents metal atoms in the pad electrode from diffusing into the contact electrode layer, avoiding the formation of harmful intermetallic compounds and thus ensuring the long-term stability of the bonding interface. Furthermore, in traditional LEDs, moisture easily penetrates along the interface between the insulating layer and the electrode during long-term operation. In this embodiment, the LED, with its pad electrode completely covering the opening edge of the passivation layer, physically cuts off the channel for moisture penetration, effectively preventing corrosion of the internal metal layer. The LED-equipped device exhibits good quality reliability and a long service life, better meeting product requirements.

[0093] In summary, the light-emitting diode, manufacturing method, and light-emitting device provided in this application have high industrial application value because they effectively overcome the shortcomings of the prior art.

[0094] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A light-emitting diode, comprising a substrate and a semiconductor stack and a contact electrode layer sequentially disposed on the substrate, characterized in that, Also includes: An insulating structure that covers the surface of the contact electrode layer; The insulating structure includes a passivation layer located on a portion of the surface of the contact electrode layer, and a first insulating layer located on a portion of the surface of the passivation layer; wherein the passivation layer has a first opening; A pad electrode is disposed above the passivation layer and electrically connected to the contact electrode layer through the first opening; In the top view of the light-emitting diode, the projection area of ​​the first opening on the contact electrode layer is located within the projection area of ​​the pad electrode on the contact electrode layer.

2. The light-emitting diode according to claim 1, characterized in that, The first insulating layer has a second opening, and the projection of the pad electrode on the contact electrode layer is located within the projection area of ​​the second opening on the contact electrode layer.

3. The light-emitting diode according to claim 1, characterized in that, The slope of the sidewall of the passivation layer at the first opening is greater than the slope of the sidewall of the first insulating layer at the second opening.

4. The light-emitting diode according to claim 1, characterized in that, The passivation layer is made of aluminum oxide and has a thickness of 0.03 μm to 0.2 μm.

5. The light-emitting diode according to claim 1, characterized in that, The material of the first insulating layer includes silicon dioxide, and the thickness of the first insulating layer is 0.5 μm to 1.5 μm.

6. The light-emitting diode according to claim 1, characterized in that, The thickness of the passivation layer is less than the thickness of the first insulating layer.

7. The light-emitting diode according to claim 1, characterized in that, There is a distance D1 between the edge projection of the first opening and the edge projection of the pad electrode, where 0 μm < D1 ≤ 10 μm.

8. The light-emitting diode according to claim 1, characterized in that, There is a distance D2 between the edge projection of the pad electrode and the edge projection of the second opening, where 0 μm < D2 ≤ 2 μm.

9. The light-emitting diode according to claim 1, characterized in that, The contact electrode layer includes a stress balancing layer and a diffusion barrier layer; wherein the stress balancing layer includes an aluminum material layer.

10. The light-emitting diode according to claim 9, characterized in that, The diffusion barrier layer is made of one or more of platinum, titanium, chromium, or nickel.

11. The light-emitting diode according to claim 1, characterized in that, The material of the pad electrode is gold or gold-tin eutectic material.

12. A method for manufacturing a light-emitting diode, characterized in that, S1: Provides a semiconductor structure including a semiconductor stack and a contact electrode layer having a circuit pattern formed thereon; S2: A passivation layer covering the contact electrode layer and the chip surface and a first insulating layer located on the passivation layer are formed sequentially to obtain an insulating structure; S3: Photoresist is coated and patterned on the insulating structure corresponding to the bonding region to form an opening; S4: A dry etching process is used to etch the first insulating layer and the passivation layer in sequence. The etching rate of the first insulating layer is greater than the etching rate of the passivation layer. As a result, when etching to the surface of the contact electrode layer, the degree of lateral over-etching of the first insulating layer is greater than the degree of lateral over-etching of the passivation layer. S5: Remove the photoresist, deposit a pad electrode in the bonding area, fill the first opening of the passivation layer and cover the sidewalls and part of the surface of the passivation layer.

13. The method for manufacturing a light-emitting diode according to claim 12, characterized in that, The passivation layer is made of aluminum oxide and is prepared by atomic layer deposition or plasma-enhanced chemical vapor deposition. The first insulating layer is made of silicon dioxide and is prepared by plasma-enhanced chemical vapor deposition.

14. The method for manufacturing a light-emitting diode according to claim 12, characterized in that, The dry etching process uses a mixed gas containing fluorocarbon gas and chlorine-based gas. By adjusting the ratio of the mixed gas, the etching selectivity ratio between the first insulating layer and the passivation layer is made greater than 1.

15. A light-emitting device, characterized in that, The light-emitting device includes: Packaging substrate; At least one light-emitting diode is disposed on the surface of the encapsulation substrate, and the encapsulation substrate and the electrode structure of the light-emitting diode are electrically connected; the light-emitting diode is the light-emitting diode according to any one of claims 1 to 11, or is a light-emitting diode manufactured by the method according to any one of claims 12 to 14.

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