Flip-chip light emitting diode chip and method of manufacturing the same

Abstract

The application discloses a flip light-emitting diode chip and a preparation method thereof. The preparation method of the flip light-emitting diode chip comprises the following steps: S1, providing a substrate and preparing an epitaxial layer on the substrate; S2, preparing a connecting metal layer and a second insulating layer on the epitaxial layer, etching a second insulating layer through hole, and preparing a P-type pad and an N-type pad in the second insulating layer through hole; and S3, preparing a reinforcing transition layer on the P-type pad and the N-type pad, wherein the reinforcing transition layer comprises a plurality of silver-palladium alloy reinforcing transition units, each of the reinforcing transition units is located at each corner of the pad, each of the reinforcing transition units comprises at least two reinforcing blocks, each of the reinforcing blocks is arranged in sequence and at intervals in a direction away from the corner and has a decreasing width, and each of the reinforcing blocks comprises a circular arc part and two extension parts extending along two ends of the circular arc part. The application aims at solving the technical problems of insufficient welding strength and poor anti-vibration performance of the flip LED chip pad corners caused by stress concentration in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] Flip-chip LEDs are widely used in backlighting and automotive lighting due to their advantages such as backlight emission, good solderability, high thrust, and high reliability. Currently, automotive LED chips generally use gold-tin pads, bonded to the substrate via eutectic bonding. Automotive lighting applications have stringent requirements for shock resistance, but the stress concentration at the corners of LED chip pads is high. Under long-term vibration, this can easily lead to solder joint cracking or even pad detachment, severely affecting the reliability and lifespan of the automotive lights.

[0003] In existing technologies, improvements to the shock resistance of flip-chip LEDs are mainly achieved through optimizing pad structure design, increasing pad thickness, adjusting pad material systems, or optimizing eutectic bonding process parameters. However, simply increasing pad thickness or adjusting material systems is limited by the compatibility of chip manufacturing processes and cannot effectively solve the corner stress concentration problem without affecting other performance characteristics. Optimizing process parameters is significantly limited by equipment precision and process windows, resulting in limited improvement. Therefore, how to effectively strengthen the stress concentration areas at the corners of flip-chip LED pads, improve the bonding strength at the corners, and thus improve the overall shock resistance of the chip, has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a flip-chip light-emitting diode and its fabrication method, thereby solving the technical problems of insufficient welding strength and poor shock resistance caused by stress concentration at the corners of the flip-chip pads.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: A method for fabricating a flip-chip light-emitting diode includes the following steps: S1, a substrate is provided, and an epitaxial stack is formed on the substrate, the epitaxial stack comprising an N-type GaN layer, an active light-emitting layer, a P-type GaN layer, a current spreading layer, a current blocking layer, a Bragg reflector layer, a metal reflector layer and a first insulating layer stacked sequentially. S2, a connecting metal layer and a second insulating layer are prepared on the side of the epitaxial stack facing away from the substrate, a portion of the second insulating layer is etched to form a second insulating layer via, and a P-type pad and an N-type pad are prepared in the second insulating layer via; S3, a reinforcing transition layer is prepared on the side of the P-type pad and the N-type pad facing away from the substrate. The reinforcing transition layer includes a plurality of reinforcing transition units, each of which is a silver-palladium alloy. Each reinforcing transition unit is located at each corner of the P-type pad and the N-type pad, and each reinforcing transition unit includes at least two reinforcing blocks. The reinforcing blocks are arranged sequentially at intervals along a direction away from the corner. Each reinforcing block includes an arc portion and two extension portions extending from both ends of the arc portion. Wherein, the mass percentage of silver in the silver-palladium alloy is A, the width of the reinforcing block is L, and the width of each reinforcing block decreases in the direction away from the corner, the interval between two adjacent reinforcing blocks is L1, the radius of the arc of the arc portion is R, and the extension width of both extension portions is L2.

[0006] Furthermore, the step of fabricating the epitaxial stack on the substrate is as follows: An N-type GaN layer, an active light-emitting layer, and a P-type GaN layer are sequentially deposited on the substrate; A current spreading layer is prepared on the side of the P-type GaN layer facing away from the substrate. A portion of the current spreading layer, the P-type GaN layer, and the active light-emitting layer are etched until the N-type GaN layer is exposed to form an N-type GaN layer conductive step. A portion of the N-type GaN layer conductive step is etched to form an isolation trench. A current blocking layer and a Bragg reflector layer are fabricated on the side of the current spreading layer, the conductive steps of the N-type GaN layer, and the isolation trench facing away from the substrate. A portion of the Bragg reflector layer is etched until the current blocking layer is exposed to form Bragg reflector vias, which include P-type and N-type Bragg reflector vias. A portion of the current blocking layer is also etched to form current blocking layer vias, which include P-type and N-type current blocking layer vias. A first metal stack is deposited on the side of the Bragg reflector layer and the current blocking layer via facing away from the substrate to form a metal reflector layer, and a first insulating layer is prepared on the side of the metal reflector layer facing away from the substrate. A portion of the first insulating layer is etched until the metal reflector layer is exposed to form a first insulating layer conductive via. The first insulating layer conductive via includes a P-type first insulating layer conductive via and an N-type first insulating layer conductive via to form the epitaxial stack.

[0007] Furthermore, the current spreading layer is an indium tin oxide thin film, the Bragg reflector layer comprises 3 to 10 pairs of TiO2 / SiO2 stacks, and the second insulating layer is a SiO2 thin film.

[0008] Furthermore, the specific steps for fabricating the connecting metal layer and the second insulating layer on the side of the epitaxial stack facing away from the substrate are as follows: A negative photoresist is coated on the side of the first insulating layer and the conductive via of the first insulating layer facing away from the substrate. A patterned P-type connection metal layer region and N-type connection metal layer region are formed by photolithography. A second metal stack is deposited on the side of the first insulating layer and the conductive via of the first insulating layer facing away from the substrate using an electron beam evaporation process. Then, the remaining photoresist and metal on it outside the P-type connection metal layer region and the N-type connection metal layer region are removed by a lift-off process to form the connection metal layer. A SiO2 thin film is deposited on the side of the connection metal layer facing away from the substrate as the second insulating layer.

[0009] Furthermore, the specific steps for preparing P-type and N-type pads within the through-holes of the second insulating layer are as follows: A negative photoresist is coated on the side of the second insulating layer and the via of the second insulating layer facing away from the substrate. Patterned P-type and N-type pad regions are formed by photolithography. A third metal stack is deposited on the side of the second insulating layer and the via of the second insulating layer facing away from the substrate using electron beam evaporation. Then, the remaining photoresist and metal on it outside the P-type and N-type pad regions are removed by a stripping process to form the P-type and N-type pads.

[0010] Furthermore, the specific steps for fabricating the reinforcing transition layer on the side of the P-type pad and the N-type pad facing away from the substrate are as follows: Photoresist is applied to the side of the P-type and N-type pads facing away from the substrate. Patterned reinforcing transition unit regions are formed at each corner of the P-type and N-type pads using a photolithography process. A silver-palladium alloy is deposited on the side of the P-type and N-type pads facing away from the substrate using a magnetron sputtering process. Then, the remaining photoresist and the silver-palladium alloy on it outside the reinforcing transition unit regions are removed using a lift-off process to form the reinforcing transition layer.

[0011] Furthermore, the mass percentage A of silver in the silver-palladium alloy is 75% to 85%, the width L of the reinforcing block is 5 μm to 20 μm, the interval L1 between two adjacent reinforcing blocks is 10 μm to 12 μm, the radius R of the arc portion is not less than 50 μm, and the extension width L2 of the extension portion is 50 μm to 100 μm.

[0012] A flip-chip light-emitting diode (LED) is fabricated using the aforementioned flip-chip light-emitting diode fabrication method.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: By setting a reinforcing transition layer at the stress concentration area of ​​the pad corner, the reinforcing transition layer includes a plurality of reinforcing transition units, each of which includes at least two reinforcing blocks at each corner. The reinforcing blocks are arranged sequentially at intervals along the direction away from the corner, and the width of each reinforcing block decreases along the direction away from the corner. By setting this reinforcing transition layer structure in the stress concentration area at the corner, on the one hand, physical reinforcement of the stress concentration area is achieved; on the other hand, by forming a stepped stress buffer structure through multiple reinforcing blocks with decreasing widths along the direction away from the corner, the stress at the corner is gradually dispersed and transferred, avoiding stress concentration at a single interface. At the same time, the silver-palladium alloy can enhance the wettability of the gold-tin alloy on the top layer of the pad at the corner of the pad, so that the solder does not shrink at the corner during the soldering process, and the solder spreads quickly and evenly, thereby improving the soldering strength at the corner. This effectively solves the problem of cracking at the corner soldering interface caused by stress concentration at the corner in the existing process, and significantly improves the chip's vibration resistance and long-term reliability. In addition, each reinforcing block includes an arc portion and two extension portions extending from both ends of the arc portion. The arc portion is adapted to the curvature of the corner, and the extension portions extend outward along both sides of the corner, which can cover a larger stress-affected area around the corner, further improving the stress concentration dispersion effect of the reinforcing transition layer. Attached Figure Description

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure after the current spreading layer is prepared and the N-type GaN layer conductive steps are etched in the method for preparing a flip-chip light-emitting diode according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure after etching to form an isolation trench in the fabrication method of the flip-chip light-emitting diode according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after depositing a current blocking layer and preparing a Bragg reflector layer in the fabrication method of the flip-chip light-emitting diode according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure after etching to form the Bragg reflector layer via and the current blocking layer via in the fabrication method of the flip-chip light-emitting diode according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the metal reflective layer is prepared in the method for preparing a flip-chip light-emitting diode according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the first insulating layer is prepared and the conductive vias of the first insulating layer are etched in the method for preparing a flip-chip light-emitting diode according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after the interconnecting metal layer is prepared in the method for preparing a flip-chip light-emitting diode according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after the P-type pads, N-type pads, and reinforced transition layer are prepared in the method for fabricating a flip-chip light-emitting diode according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the reinforcing block structure in the method for fabricating a flip-chip light-emitting diode according to an embodiment of the present invention.

[0015] Explanation of key component symbols: 10. Substrate; 114. N-type GaN layer conductive step; 115. Isolation trench; 141. P-type Bragg reflector layer via; 142. N-type Bragg reflector layer via; 131. P-type current blocking layer via; 132. N-type current blocking layer via; 15. Metal reflector layer; 161. P-type first insulating layer conductive via; 162. N-type first insulating layer conductive via; 171. P-type connection metal layer; 172. N-type connection metal layer; 191. P-type pad; 192. N-type pad; 20. Reinforcing transition layer; 201. Reinforcing block; 2011. Arc portion; 2012. Extension portion.

[0016] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0017] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0018] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," "up," "down," and similar expressions used herein are for illustrative purposes only and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0019] In this invention, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0020] Example 1: Please see Figures 1 to 9 A method for fabricating a flip-chip light-emitting diode includes the following steps: S1, a substrate 10 is provided, and an epitaxial stack is formed on the substrate 10. The epitaxial stack includes an N-type GaN layer, an active light-emitting layer, a P-type GaN layer, a current spreading layer, a current blocking layer, a Bragg reflector layer, a metal reflector layer 15, and a first insulating layer stacked sequentially.

[0021] Specifically, an N-type GaN layer, an active light-emitting layer, and a P-type GaN layer are sequentially deposited on the substrate 10 using an MOCVD process; A current spreading layer is prepared on the side of the P-type GaN layer facing away from the substrate 10; Specifically, indium tin oxide (ITO) is deposited as a current spreading layer using magnetron sputtering. Photoresist is then coated onto the surface of the current spreading layer. Exposure and development processes are used to remove a portion of the photoresist, exposing the current spreading layer beneath it. ITO etching solution is then used to remove the exposed current spreading layer, exposing the P-type GaN layer beneath it. Inductively coupled plasma etching is then used to remove the exposed P-type GaN layer and the active light-emitting layer beneath it, until the N-type GaN layer is exposed, forming an N-type GaN layer conductive step 114. The photoresist is then removed. Next, photoresist is coated again, and exposure and development are used to remove a portion of the photoresist, exposing a portion of the N-type GaN layer conductive step 114. Inductively coupled plasma etching is then used to remove the exposed N-type GaN layer conductive step 114, forming an isolation trench 115. Finally, the photoresist is removed. A current blocking layer is deposited on the side of the current spreading layer, the N-type GaN layer conductive step 114, and the isolation trench 115 facing away from the substrate 10. Specifically, a SiO2 thin film is deposited using a PECVD process as a current blocking layer; a Bragg reflector layer is prepared on the side of the current blocking layer facing away from the substrate 10. Specifically, 3 to 10 pairs of TiO2 / SiO2 stacks are deposited as Bragg reflector layers using electron beam evaporation. Photoresist is coated onto the surface of the Bragg reflector layer, and after exposure and development, a portion of the photoresist is removed. Inductively coupled plasma etching is then used to remove the Bragg reflector layer beneath this portion of photoresist, forming vias in the Bragg reflector layer. These vias include P-type Bragg reflector vias 141 and N-type Bragg reflector vias 142. The photoresist is then removed. Finally, the current blocking layer at the bottom of the vias in the Bragg reflector layer is etched. Specifically, the photoresist is continued to be coated, and the photoresist located in the via of the Bragg reflector layer is removed by exposure and development. The current blocking layer under this part of the photoresist is removed by BOE etching solution to form a current blocking layer via. The current blocking layer via includes a P-type current blocking layer via 131 and an N-type current blocking layer via 132. Then the photoresist is removed. A metal layer 15 is formed by depositing the metal layers of the first metal stack on the side of the Bragg reflector layer and the current blocking layer that is opposite to the substrate 10. Specifically, the first metal stack is composed of an Ag metal layer, a first Ti metal layer, a first Ni metal layer, a first Pt metal layer, a second Ti metal layer, a second Ni metal layer, a second Pt metal layer, and a third Ti metal layer stacked sequentially. During fabrication, a negative photoresist is coated, and the photoresist in the area where the metal reflective layer is to be formed is exposed using a photomask. After development, the photoresist in the unexposed areas is removed. Then, the Ag metal layer, the first Ti metal layer, the first Ni metal layer, the first Pt metal layer, the second Ti metal layer, the second Ni metal layer, the second Pt metal layer, and the third Ti metal layer are sequentially deposited using an electron beam evaporation process. The thickness of the Ag metal layer is 1200Å to 2000Å, the thickness of the first Ti metal layer is 1000Å to 2000Å, the thickness of the first Ni metal layer is 1000Å to 2000Å, the thickness of the first Pt metal layer is 1000Å to 2000Å, the thickness of the second Ti metal layer is 1000Å to 2000Å, the thickness of the second Ni metal layer is 1000Å to 2000Å, the thickness of the second Pt metal layer is 2000Å to 3000Å, and the thickness of the third Ti metal layer is 30Å to 50Å. Then, the photoresist and the metal on it are removed using a lift-off process to form a metal reflective layer 15. A first insulating layer is formed on the side of the metal reflective layer 15 that faces away from the substrate 10; Specifically, an Al2O3 film is prepared using the ALD process in the metal reflective layer 15 and the areas not covered by the metal reflective layer 15, and then a SiO2 film is prepared using the PECVD process on the surface of the Al2O3 film. The Al2O3 film and the SiO2 film together constitute the first insulating layer. The first insulating layer is etched; Specifically, photoresist is coated on the surface of the first insulating layer, and a portion of the photoresist is removed by exposure and development to expose the first insulating layer beneath the photoresist. The exposed first insulating layer is then removed using an inductively coupled plasma etching process to form conductive vias in the first insulating layer. These conductive vias include P-type conductive vias 161 and N-type conductive vias 162 to form the epitaxial stack.

[0022] S2, a connecting metal layer and a second insulating layer are prepared on the side of the epitaxial stack facing away from the substrate 10, and a portion of the second insulating layer is etched to form a second insulating layer via, and a P-type pad 191 and an N-type pad 192 are prepared in the second insulating layer via.

[0023] Specifically, a negative photoresist is coated on the side of the first insulating layer and the conductive via of the first insulating layer facing away from the substrate 10. The photoresist in the area to be formed of the connecting metal layer is exposed by a mask. After development, the photoresist in the unexposed area is removed. Each metal layer of the second metal stack is deposited sequentially using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a blue film stripping process to form the connecting metal layer. The connecting metal layer includes a P-type connecting metal layer 171 and an N-type connecting metal layer 172. The second metal stack is composed of a Cr metal layer, an Al metal layer, a fourth Ti metal layer, a third Pt metal layer, a fifth Ti metal layer, a fourth Pt metal layer, a sixth Ti metal layer, an Au metal layer, a fifth Pt metal layer, and a seventh Ti metal layer stacked sequentially. During fabrication, the Cr metal layer, the Al metal layer, the fourth Ti metal layer, the third Pt metal layer, the fifth Ti metal layer, the fourth Pt metal layer, the sixth Ti metal layer, the Au metal layer, the fifth Pt metal layer, and the seventh Ti metal layer are deposited sequentially by vapor deposition. The thickness of the Cr metal layer is 30 Å to 50 Å. The thickness of the first Ti metal layer is 3000 Å to 5000 Å, the thickness of the fourth Ti metal layer is 1000 Å to 2000 Å, the thickness of the third Pt metal layer is 1000 Å to 2000 Å, the thickness of the fifth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fourth Pt metal layer is 1000 Å to 2000 Å, the thickness of the sixth Ti metal layer is 1000 Å to 2000 Å, the thickness of the Au metal layer is 8000 Å to 10000 Å, the thickness of the fifth Pt metal layer is 2000 Å to 3000 Å, and the thickness of the seventh Ti metal layer is 30 Å to 50 Å. A second insulating layer is prepared on the side of the connecting metal layer that faces away from the substrate 10; Specifically, a SiO2 thin film is prepared as a second insulating layer on the surface of the connecting metal layer and the area not covered by the connecting metal layer using a PECVD process, and the thickness of the second insulating layer is 10000 Å. The second insulating layer is etched; Specifically, photoresist is coated on the surface of the second insulating layer, and some of the photoresist is removed by exposure and development. The exposed second insulating layer is removed by inductively coupled plasma etching process to form a through-hole in the second insulating layer. P-type pad 191 and N-type pad 192 are prepared in the through-hole of the second insulating layer; Specifically, negative photoresist is coated on the side of the second insulating layer and the via of the second insulating layer facing away from the substrate 10. The photoresist in the area where P-type and N-type pads are to be formed is exposed by exposure through a mask. After development, the photoresist in the unexposed area is removed. Each layer of the third metal stack is deposited sequentially using an electron beam evaporation process. Then, the photoresist and the metal on it are removed using a lift-off process to form P-type pad 191 and N-type pad 192. The third metal stack is composed of an eighth Ti metal layer, a third Ni metal layer, a ninth Ti metal layer, a fourth Ni metal layer, and an AuSn alloy layer stacked sequentially. During preparation, the eighth Ti metal layer, the third Ni metal layer, the ninth Ti metal layer, the fourth Ni metal layer, and the AuSn alloy layer are deposited sequentially by vapor deposition. The thickness of the eighth Ti metal layer is 1000 Å to 2000 Å, the thickness of the third Ni metal layer is 1000 Å to 2000 Å, the thickness of the ninth Ti metal layer is 1000 Å to 2000 Å, the thickness of the fourth Ni metal layer is 1000 Å to 2000 Å, and the thickness of the AuSn alloy layer is 3 μm to 5 μm.

[0024] S3, a reinforced transition layer 20 is prepared on the side of the P-type pad 191 and the N-type pad 192 facing away from the substrate 10.

[0025] Specifically, photoresist is coated on the side of the P-type pad 191 and the N-type pad 192 facing away from the substrate 10. After exposure and development, part of the photoresist is removed. A silver-palladium alloy is deposited using a magnetron sputtering process with a deposition thickness of 30 Å to 200 Å. Then, the photoresist and the silver-palladium alloy on it are removed using a lift-off process to form the reinforcing transition layer 20. The reinforcing transition layer 20 includes a plurality of reinforcing transition units, each of which is a silver-palladium alloy. Each reinforcing transition unit is located at a corner of the P-type pad 191 and the N-type pad 192, and at each corner, there are at least two reinforcing blocks 201. The reinforcing blocks 201 are arranged sequentially at intervals along the direction away from the corner, and the width of each reinforcing block 201 decreases along the direction away from the corner. Each of the reinforcing blocks 201 includes an arc portion 2011 and two extension portions 2012 extending from both ends of the arc portion 2011; The mass percentage of silver in the silver-palladium alloy is A, the width of the reinforcing block 201 is L, the interval between two adjacent reinforcing blocks 201 is L1, the radius of the arc of the arc portion 2011 is R, and the extension width of the extension portion 2012 is L2. The radius R of the arc refers to the radius of the outer arc of the arc portion 2011 with the center of the arc portion 2011 as a reference.

[0026] In this embodiment, the deposition thickness of the silver-palladium alloy is 100 Å, the mass percentage A of silver in the silver-palladium alloy is 80%, and three reinforcing blocks 201 are included at each corner. The widths L of the three reinforcing blocks 201 are 15 μm, 10 μm and 5 μm respectively along the direction away from the corner. The interval L1 between two adjacent reinforcing blocks 201 is 10 μm. The radius R of the arc portion 2011 is 50 μm, and the extension width L2 of the extension portion 2012 is 100 μm.

[0027] Example 2 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the mass percentage A of silver in the silver-palladium alloy is 75%.

[0028] Example 3 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the mass percentage A of silver in the silver-palladium alloy is 85%.

[0029] Example 4 This embodiment is basically the same as embodiment 1, except that in this embodiment, each corner includes two reinforcing blocks 201, and the widths L of the two reinforcing blocks 201 are 15μm and 5μm respectively along the direction away from the corner.

[0030] Example 5 This embodiment is basically the same as embodiment 1, except that in this embodiment, the interval L1 between two adjacent reinforcing blocks 201 is 11μm.

[0031] Example 6 This embodiment is basically the same as embodiment 1, except that in this embodiment, the interval L1 between two adjacent reinforcing blocks 201 is 12μm.

[0032] Example 7 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the radius R of the arc portion 2011 is 75μm.

[0033] Example 8 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the radius R of the arc portion 2011 is 100μm.

[0034] Example 9 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the extension width L2 of the extension portion 2012 is 75μm.

[0035] Example 10 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the extension width L2 of the extension portion 2012 is 50μm.

[0036] Example 11 This embodiment is basically the same as Embodiment 1, except that in this embodiment, the widths L of the three reinforcing blocks 201 are 20μm, 10μm and 5μm respectively along the direction away from the corner.

[0037] Comparative Example 1 This comparative example is basically the same as Example 1, except that the reinforcing transition layer 20 is not provided in this comparative example.

[0038] Comparative Example 2 This comparative example is basically the same as Example 1, except that in this comparative example, the mass percentage A of silver in the silver-palladium alloy is 70%.

[0039] Comparative Example 3 This comparative example is basically the same as Example 1, except that in this comparative example, the mass percentage A of silver in the silver-palladium alloy is 90%.

[0040] Comparative Example 4 This comparative example is basically the same as Example 1, except that in this comparative example, a reinforcing block 201 is included at each of the corners.

[0041] Comparative Example 5 This comparative example is basically the same as Example 1, except that in this comparative example, each corner includes four reinforcing blocks 201, and the widths L of the four reinforcing blocks 201 are 15μm, 12μm, 8μm and 5μm respectively along the direction away from the corner.

[0042] Comparative Example 6 This comparative example is basically the same as Example 1, except that the interval L1 between two adjacent reinforcing blocks 201 in this comparative example is 5μm.

[0043] Comparative Example 7 This comparative example is basically the same as Example 1, except that the interval L1 between two adjacent reinforcing blocks 201 in this comparative example is 15μm.

[0044] Comparative Example 8 This comparative example is basically the same as Example 1, except that the radius R of the arc portion 2011 in this comparative example is 25μm.

[0045] Comparative Example 9 This comparative example is basically the same as Example 1, except that in this comparative example, the extension width L2 of the extension portion 2012 is 30μm.

[0046] Comparative Example 10 This comparative example is basically the same as Example 1, except that in this comparative example, the extension width L2 of the extension portion 2012 is 150μm.

[0047] Comparative Example 11 This comparative example is basically the same as Example 1, except that in this comparative example, the widths L of the three reinforcing blocks 201 are 6μm, 4μm and 2μm respectively along the direction away from the corner.

[0048] Comparative Example 12 This comparative example is basically the same as Example 1, except that in this comparative example, the widths L of the three reinforcing blocks 201 are 24μm, 18μm and 12μm respectively along the direction away from the corner.

[0049] The present invention also provides a flip-chip light-emitting diode, which is manufactured using the flip-chip light-emitting diode fabrication method described above.

[0050] Furthermore, performance tests were performed on the flip-chip LEDs prepared in all embodiments and comparative examples, as detailed below: Taking the fabrication of a 1400×1400μm flip-chip LED as an example, the flip-chip LED to be tested was soldered onto a ceramic substrate using a eutectic bonding process. The bonding layer was Au metal, and the bonding temperature was 300℃. After soldering, a thrust tester was used to perform a thrust test on the chip. The test speed was 200μm / s, and the test height was 50μm. For each embodiment or comparative example, a batch of chips was prepared according to its respective process parameters. Thirty chips were randomly selected from the batch for testing, and the thrust value of each chip was recorded. The average value of the 30 chips was taken as the thrust test result of that embodiment or comparative example.

[0051] The specific parameters used in Examples 1 to 11 and Comparative Examples 1 to 12 during the manufacturing process of this invention, and the corresponding test results obtained, are shown in Table 1.

[0052] Table 1:

[0053] According to Table 1, the comparison between Examples 1 to 11 and Comparative Examples 1 to 12 shows that: Comparative Example 1, without the reinforcing transition layer 20, had an average thrust of 10.68 kgf. Examples 1 to 11, with the reinforcing transition layer 20, had average thrusts ranging from 15.03 kgf to 17.54 kgf, all significantly higher than Comparative Example 1. This demonstrates that the physical reinforcement of the reinforcing transition layer 20 and the improvement in wettability by the silver-palladium alloy material work synergistically to enhance the weld strength at corners.

[0054] In Example 2, the thrust was 16.40 kgf when A was 75%; in Example 1, the thrust was 17.54 kgf when A was 80%; and in Example 3, the thrust was 16.90 kgf when A was 85%. The thrust showed a trend of first increasing and then decreasing, with the highest thrust occurring when A was 80%. In Comparative Example 2, the thrust was 13.52 kgf when A was 70%; and in Comparative Example 3, the thrust was 12.87 kgf when A was 90%, both significantly lower than in the examples. The silver content A determines the improvement effect of the silver-palladium alloy on the wettability of gold-tin solder. When A is too small, the silver content is insufficient, and the wettability improvement effect is limited; when A is too large, the palladium content is relatively reduced, and the alloy's ability to regulate solder wettability weakens. This indicates that the best wettability improvement effect can be obtained in the range of 75% to 85% A, and the effect is significantly reduced when A is too small or too large.

[0055] In Example 4, the thrust was 15.03 kgf when there were two reinforcing blocks 201; in Example 1, the thrust was 17.54 kgf when there were three reinforcing blocks 201; and in Comparative Example 5, the thrust was 14.68 kgf when there were four reinforcing blocks 201. The thrust showed a trend of first increasing and then decreasing, with the highest thrust observed when there were three reinforcing blocks 201. In Comparative Example 4, the thrust was 11.34 kgf when there was one reinforcing block 201, which was significantly lower than in the other examples. The number of reinforcing blocks 201 determines the number of stages of the stepped stress buffer. If the number is too small, i.e., one block, a stepped buffer effect cannot be formed, and the stress remains concentrated on a single interface. If the number is too large, i.e., four blocks, the spacing between adjacent reinforcing blocks 201 is compressed due to the limited space at the corner of the solder pad, and the filling and wetting effect of the solder between the reinforcing blocks 201 is suppressed, which in turn leads to a decrease in thrust. This indicates that having two or three reinforcement blocks 201 achieves the best balance between stepped buffering and spatial layout, with three being optimal.

[0056] In Example 5, the thrust when L1 is 11 μm is 17.30 kgf; in Example 1, the thrust when L1 is 10 μm is 17.54 kgf; and in Example 6, the thrust when L1 is 12 μm is 17.06 kgf. L1 maintains a high thrust level within the range of 10 μm to 12 μm. In Comparative Example 6, the thrust when L1 is 5 μm is 12.93 kgf; and in Comparative Example 7, the thrust when L1 is 15 μm is 13.86 kgf, both significantly lower than in the examples. The interval L1 determines the stress transfer efficiency between adjacent reinforcing blocks 201. If L1 is too small, the spacing between adjacent reinforcing blocks 201 is too close, causing overlap and mutual interference of the stress fields borne by each reinforcing block 201, failing to achieve the effect of gradually dispersing stress. If L1 is too large, the distance between reinforcing blocks 201 is too far, resulting in a lack of effective support when stress is transferred between adjacent reinforcing blocks 201, weakening the stepped buffering effect. This indicates that the optimal step buffering effect can be obtained when L1 is in the range of 10μm to 12μm, and the effect decreases significantly when L1 is too small or too large.

[0057] In Example 7, the thrust was 17.40 kgf when R was 75 μm; in Example 1, the thrust was 17.54 kgf when R was 50 μm; and in Example 8, the thrust was 17.32 kgf when R was 100 μm. R maintained a high thrust level throughout the range of 50 μm to 100 μm. In Comparative Example 8, the thrust was 12.41 kgf when R was 25 μm, significantly lower than in the other examples. The radius R determines the degree of fit between the arc portion 2011 and the corner curvature of the pad. If R is too small, the curvature of the arc portion 2011 is too large, failing to effectively conform to the geometry of the corner, resulting in poor stress dispersion. When R is 50 μm or more, the arc portion 2011 can adapt well to the corner curvature, and stress is transmitted evenly. This indicates that an effective stress dispersion effect can be achieved when R is not less than 50 μm.

[0058] In Example 9, the thrust when L2 is 75 μm is 17.30 kgf; in Example 1, the thrust when L2 is 100 μm is 17.54 kgf; and in Example 10, the thrust when L2 is 50 μm is 17.14 kgf. L2 maintains a high thrust level within the range of 50 μm to 100 μm. In Comparative Example 9, the thrust when L2 is 30 μm is 13.25 kgf; and in Comparative Example 10, the thrust when L2 is 150 μm is 13.50 kgf, both significantly lower than in the examples. The extension width L2 determines the coverage area of ​​the stress-affected zone on both sides of the corner by the extension 2012. If L2 is too short (30 μm), it cannot fully cover the stress concentration area on both sides of the corner, resulting in limited reinforcement. If L2 is too long (150 μm), the extension 2012 encroaches on the central welding area of ​​the pad, hindering the normal spread of solder in the central area. This indicates that L2 can adequately cover the corner stress-affected area within the range of 50μm to 100μm, and the effect decreases significantly when L2 is too short or too long.

[0059] In Example 11, the thrust was 17.40 kgf when L was distributed as 20, 10, and 5; in Example 1, the thrust was 17.54 kgf when L was distributed as 15, 10, and 5, showing similar thrust levels. In Comparative Example 11, the thrust was 12.80 kgf when L was distributed as 6, 4, and 2 (i.e., generally smaller); in Comparative Example 12, the thrust was 13.10 kgf when L was distributed as 24, 18, and 12 (i.e., generally larger), both significantly lower than in the examples. The width L of the reinforcing block 201 determines the load-bearing cross-sectional area of ​​each reinforcing block 201. When L is generally small, the load-bearing cross-section of each reinforcing block 201 is insufficient, and even with a stepped structure, stress cannot be effectively absorbed and dispersed. When L is generally large, each reinforcing block 201 occupies corner space, narrowing the solder flow path and deteriorating wetting and filling effects. This indicates that L within the range of 5 μm to 20 μm can ensure that each reinforcing block 201 has sufficient load-bearing cross-section and a reasonable spatial layout.

[0060] Furthermore, the wettability in the mechanism of action of this invention refers to the ability of liquid solder to spread on a solid surface, which is determined by the interfacial tension between the solid and liquid phases. The palladium element in the silver-palladium alloy material has a suitable interfacial tension with the gold-tin solder, which can enhance the wettability of the solder at the corners of the solder pads, allowing the solder to spread quickly and evenly during the soldering process without solder shrinkage.

[0061] Meanwhile, multiple reinforcing blocks 201, with their width decreasing away from the corner, form a stepped stress buffer structure. When the chip is subjected to vibration or impact loads, the stress first acts on the widest reinforcing block 201 closest to the corner. After this reinforcing block 201 bears and absorbs part of the stress, the remaining stress is transferred to the next reinforcing block 201, decreasing step by step. This stepped stress transfer mechanism avoids stress concentration on a single interface, allowing the stress to be evenly distributed along multiple reinforcing blocks 201.

[0062] In actual welding, the silver-palladium alloy reinforced transition layer 20 improves wettability, allowing the solder to spread fully at the corners, forming full, void-free weld fillets. Simultaneously, its stepped stress buffer structure gradually disperses mechanical stress during service, preventing stress concentration at the weld interface at the corners. This synergistic effect makes the weld interface at the corners less prone to cracking, thus significantly improving the chip's vibration resistance and long-term reliability.

[0063] In summary, this invention achieves a synergistic effect of physical reinforcement and improved wettability by setting a reinforcing transition layer 20 at the stress concentration point of the pad, and the reinforcing transition layer 20 includes at least two silver-palladium alloy reinforcing blocks 201 whose width decreases away from the corner. When the mass percentage A of silver in the silver-palladium alloy is 75% to 85%, the number of reinforcing blocks 201 is 2 or 3, the width L of the reinforcing blocks 201 is 5 μm to 20 μm, the interval L1 between adjacent reinforcing blocks 201 is 10 μm to 12 μm, the radius R of the arc portion 2011 is not less than 50 μm, and the extension width L2 of the extension portion 2012 is 50 μm to 100 μm, the thrust can be increased from 10.68 kgf without the reinforcing transition layer to 15.03 kgf to 17.54 kgf, with a maximum thrust increase of 64.2%. This invention effectively solves the technical problem of insufficient welding strength and poor shock resistance caused by stress concentration at the corner of the flip-chip light-emitting diode pad.

[0064] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a flip-chip light-emitting diode, characterized in that, The steps include the following: S1, a substrate is provided, and an epitaxial stack is formed on the substrate, the epitaxial stack comprising an N-type GaN layer, an active light-emitting layer, a P-type GaN layer, a current spreading layer, a current blocking layer, a Bragg reflector layer, a metal reflector layer and a first insulating layer stacked sequentially. S2, a connecting metal layer and a second insulating layer are prepared on the side of the epitaxial stack facing away from the substrate, a portion of the second insulating layer is etched to form a second insulating layer via, and a P-type pad and an N-type pad are prepared in the second insulating layer via; S3, a reinforcing transition layer is prepared on the side of the P-type pad and the N-type pad facing away from the substrate. The reinforcing transition layer includes a plurality of reinforcing transition units, each of which is a silver-palladium alloy. Each reinforcing transition unit is located at each corner of the P-type pad and the N-type pad, and each reinforcing transition unit includes at least two reinforcing blocks. The reinforcing blocks are arranged sequentially at intervals along a direction away from the corner. Each reinforcing block includes an arc portion and two extension portions extending from both ends of the arc portion. Wherein, the mass percentage of silver in the silver-palladium alloy is A, the width of the reinforcing block is L, and the width of each reinforcing block decreases in the direction away from the corner, the interval between two adjacent reinforcing blocks is L1, the radius of the arc of the arc portion is R, and the extension width of both extension portions is L2.

2. The method for fabricating a flip-chip light-emitting diode according to claim 1, characterized in that, The step of preparing the epitaxial stack on the substrate is as follows: An N-type GaN layer, an active light-emitting layer, and a P-type GaN layer are sequentially deposited on the substrate; A current spreading layer is prepared on the side of the P-type GaN layer facing away from the substrate. A portion of the current spreading layer, the P-type GaN layer, and the active light-emitting layer are etched until the N-type GaN layer is exposed to form an N-type GaN layer conductive step. A portion of the N-type GaN layer conductive step is etched to form an isolation trench. A current blocking layer and a Bragg reflector layer are fabricated on the side of the current spreading layer, the conductive steps of the N-type GaN layer, and the isolation trench facing away from the substrate. A portion of the Bragg reflector layer is etched until the current blocking layer is exposed to form Bragg reflector vias, which include P-type and N-type Bragg reflector vias. A portion of the current blocking layer is also etched to form current blocking layer vias, which include P-type and N-type current blocking layer vias. A first metal stack is deposited on the side of the Bragg reflector layer and the current blocking layer via facing away from the substrate to form a metal reflector layer, and a first insulating layer is prepared on the side of the metal reflector layer facing away from the substrate. A portion of the first insulating layer is etched until the metal reflector layer is exposed to form a first insulating layer conductive via. The first insulating layer conductive via includes a P-type first insulating layer conductive via and an N-type first insulating layer conductive via to form the epitaxial stack.

3. The method for fabricating a flip-chip light-emitting diode according to claim 2, characterized in that, The current spreading layer is an indium tin oxide thin film, the Bragg reflector layer comprises 3 to 10 pairs of TiO2 / SiO2 stacks, and the second insulating layer is a SiO2 thin film.

4. The method for fabricating a flip-chip light-emitting diode according to claim 2, characterized in that, The specific steps for preparing the connecting metal layer and the second insulating layer on the side of the epitaxial stack facing away from the substrate are as follows: A negative photoresist is coated on the side of the first insulating layer and the conductive via of the first insulating layer facing away from the substrate. A patterned P-type connection metal layer region and N-type connection metal layer region are formed by photolithography. A second metal stack is deposited on the side of the first insulating layer and the conductive via of the first insulating layer facing away from the substrate by electron beam evaporation. Then, the remaining photoresist and metal on it outside the P-type connection metal layer region and the N-type connection metal layer region are removed by a lift-off process to form the connection metal layer. A SiO2 thin film is deposited on the side of the connecting metal layer facing away from the substrate as the second insulating layer.

5. The method for fabricating a flip-chip light-emitting diode according to claim 1, characterized in that, The specific steps for preparing P-type and N-type pads within the through-holes of the second insulating layer are as follows: A negative photoresist is coated on the side of the second insulating layer and the via of the second insulating layer facing away from the substrate. Patterned P-type and N-type pad regions are formed by photolithography. A third metal stack is deposited on the side of the second insulating layer and the via of the second insulating layer facing away from the substrate using electron beam evaporation. Then, the remaining photoresist and metal on it outside the P-type and N-type pad regions are removed by a stripping process to form the P-type and N-type pads.

6. The method for fabricating a flip-chip light-emitting diode according to claim 1, characterized in that, The specific steps for fabricating the reinforcing transition layer on the side of the P-type pad and the N-type pad facing away from the substrate are as follows: Photoresist is applied to the side of the P-type and N-type pads facing away from the substrate. Patterned reinforcing transition unit regions are formed at each corner of the P-type and N-type pads using a photolithography process. A silver-palladium alloy is deposited on the side of the P-type and N-type pads facing away from the substrate using a magnetron sputtering process. Then, the remaining photoresist and the silver-palladium alloy on it outside the reinforcing transition unit regions are removed using a lift-off process to form the reinforcing transition layer.

7. The method for fabricating a flip-chip light-emitting diode according to claim 1, characterized in that, The mass percentage A of silver in the silver-palladium alloy is 75% to 85%, the width L of the reinforcing block is 5 μm to 20 μm, the interval L1 between two adjacent reinforcing blocks is 10 μm to 12 μm, the radius R of the arc portion is not less than 50 μm, and the extension width L2 of the extension portion is 50 μm to 100 μm.

8. A flip-chip light-emitting diode, characterized in that, It is manufactured using the method for fabricating a flip-chip light-emitting diode as described in any one of claims 1 to 7.

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