A preparation method of a vertical structure micro-LED vehicle-mounted matrix headlamp based on DPSS epitaxy

Abstract

The application discloses a preparation method of a vertical structure Micro-LED vehicle-mounted matrix headlamp based on DPSS epitaxy, and belongs to the technical field of Micro-LED vehicle-mounted lighting. 7 cm ‑2 The GaN epitaxial wafer with a dislocation density of less than or equal to 1*10 The vertical structure Micro-LED matrix headlamp is prepared through the processes of mesa etching, grid-shaped N-pole preparation and fluorescent powder conversion after the combination of the epitaxial wafer and the CMOS driving substrate is realized through metal eutectic bonding and the N-face DPSS micro-nano antireflection structure is reserved after the substrate is peeled off. The application reduces the dislocation density and improves the light efficiency through DPSS epitaxy, solves the problems of uneven brightness, low efficiency, difficult heat dissipation and serious light decay under large current of the traditional vehicle-mounted Micro-LED headlamp, and meets the requirements of high reliability and high uniformity of vehicle-grade high-power lighting.

Description

Technical Field

[0001] This invention relates to the fields of Micro-LED lighting and automotive optoelectronics technology, and in particular to a method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy. Background Technology

[0002] With the rapid development of intelligent driving technology, adaptive matrix headlights have become a core configuration for high-end automotive lighting. Micro-LED matrix headlights, with their advantages of micron-level pixel size, high brightness, and independent zone light control, can achieve precise anti-glare high beams, adaptive cornering lights, and sign projection, making them the mainstream technology direction for next-generation automotive lighting.

[0003] Currently, most mainstream Micro-LED automotive headlights use GaN epitaxy on a flat sapphire substrate combined with a lateral chip structure, which has many technical drawbacks that are difficult to overcome in practical applications: First, the crystal quality is inherently flawed, with poor uniformity. When GaN is heteroepitaxially layered on planar sapphire, a large number of penetrating dislocations are generated due to lattice mismatch and thermal mismatch, with a dislocation density as high as 10-1. 8 ~10 9 cm -2 Dislocations, acting as non-radiative recombination centers, directly reduce the quantum efficiency within the chip; furthermore, the random distribution of dislocations leads to extremely poor consistency in brightness and wavelength across different locations on the same epitaxial wafer. For matrix headlights containing tens of thousands of pixels, this defect directly results in low yield and uneven light spots, failing to meet automotive-grade quality requirements.

[0004] Second, the light extraction efficiency is low. The interface between the planar substrate and GaN is flat and lacks micro-nano scattering structures. A large number of photons undergo total internal reflection within the epitaxial layer and cannot escape, further limiting the overall light efficiency.

[0005] Third, lateral structure chips suffer from current congestion and heat dissipation bottlenecks. In lateral structures, current must flow laterally through an extremely thin n-GaN layer to reach the side electrodes. The current density near the electrodes is extremely high, easily forming local hot spots and causing uneven brightness. At the same time, heat must be dissipated downwards through the poorly thermally conductive sapphire substrate, resulting in a long heat dissipation path and high thermal resistance. Combined with the high heat generated by the low efficiency of flat-chip epitaxy, the chip's operating temperature rises significantly, accelerating device aging.

[0006] The triple combination of the aforementioned problems of high dislocation density, current congestion, and heat dissipation obstruction causes a significant drop in the internal quantum efficiency of Micro-LED chips under high current drive, resulting in premature saturation of light output. This makes it difficult to meet the stringent requirements of high power, long lifespan, and high reliability for automotive matrix headlights. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy. By synergistic optimization of DPSS substrate epitaxy and vertical chip architecture, the core pain points of traditional Micro-LED automotive headlights are systematically solved from materials to structure, realizing the fabrication of automotive-grade high-power, high-uniformity, and high-reliability Micro-LED matrix headlights.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy includes the following steps: S1, Epitaxial wafer pretreatment: Take a GaN epitaxial wafer with DPSS, wherein the dislocation density of the GaN epitaxial wafer is ≤1×10 7 cm -2 A P-plane ITO thin film is deposited on the surface of the P-type GaN layer of the GaN epitaxial wafer, and then annealed to form an ohmic contact. S2, Eutectic bonding: Bonding metal layers are deposited on the P-side ITO surface of the GaN epitaxial wafer and the surface of the silicon-based CMOS driving substrate respectively. The GaN epitaxial wafer and the CMOS driving substrate are then bonded face to face and formed into a bond body through high temperature and high pressure eutectic bonding. S3, Substrate stripping and N-side fabrication: Remove the DPSS of the bonded structure, thin the exposed N-type GaN layer, and retain the DPSS micro / nano structure on the surface of the N-type GaN layer; after thinning, deposit a Pre-ITO layer on the N-type GaN surface as the N-side contact layer. S4, Pixel Mesa Film Fabrication: A hard mask layer is deposited on the surface of the Pre-ITO layer, and after photolithography patterning, a periodic island-shaped mask is formed; the Pre-ITO layer, N-type GaN layer, quantum well light-emitting layer and P-type GaN layer between the mesa are removed by ICP dry etching; then the epitaxial residue between the mesa is removed by wet etching and the defects on the mesa sidewalls are repaired; finally, the hard mask is removed to obtain a matrix-arranged Micro-LED pixel mesa. S5, Electrode structure fabrication: A first passivation layer is deposited on the device surface, and the conductive layer between the mesa is broken to the surface of the CMOS driving substrate by ion beam etching; an N-side ITO thin film is deposited on the entire surface, and the ITO outside the light-emitting area is removed by patterning; a grid-like N-polar metal layer is prepared in the channel between the pixel mesa, and the N-polar metal layer forms an electrical connection with the N-side ITO thin film to form a common N-polarity; S6, Functional layer fabrication and white light conversion: A second passivation layer is deposited on the device surface as a refractive index buffer layer and a protective layer, and the electrode pad area is patterned to expose the device. A phosphor layer is filled on the light-emitting side of the pixel mesa, and after curing and thinning, a white light Micro-LED automotive matrix headlight device is obtained.

[0009] In a preferred embodiment, in step S1, the thickness of the P-side ITO film is 150 nm, and it is deposited using an electron beam evaporation process; the annealing temperature is 500~600℃, and the annealing atmosphere is air or nitrogen atmosphere.

[0010] In a preferred embodiment, in step S2, the bonding metal layer is an AuSn eutectic alloy layer or an Au-Au metal layer; the eutectic bonding temperature is 280~350℃, and the bonding pressure is 0.5~2MPa.

[0011] In a preferred embodiment, in step S3, the DPSS is removed by laser lift-off or selective etching lift-off with phosphate-based etchant; the sapphire substrate can be reused after cleaning.

[0012] In a preferred embodiment, in step S3, the height difference of the DPSS micro / nano structure of the thinned N-type GaN layer is 1.2~1.3μm, the thickness of the thinnest part of the N-type GaN layer is 1.2μm, and the thickness of the thickest part is 2.5μm.

[0013] In a preferred embodiment, in step S4, the hard mask layer is a SiO2 layer grown by PECVD process; the wet etching uses KOH alkaline solution to repair the sidewall lattice damage caused by ICP dry etching while etching.

[0014] In a preferred embodiment, in step S4, the diameter of the Micro-LED pixel mesa is 40μm, 50μm, or 60μm, and the pixel mesa are arranged uniformly in a row-column matrix.

[0015] In a preferred embodiment, in step S5, the thickness of the N-side ITO thin film is 300 nm, and it is prepared by electron beam evaporation; the N-polar metal layer is prepared by negative photoresist stripping process, and its thickness is 2~3 μm, forming a continuous and interconnected grid-like common N-polar layer.

[0016] In a preferred embodiment, in step S6, the second passivation layer is a SiO2 dielectric layer, and its refractive index is between that of GaN epitaxial wafer and air.

[0017] In a preferred embodiment, in step S6, the light-emitting surface of the pixel mesa is treated with oxygen plasma before filling with phosphor; the phosphor is filled by spin coating process to convert blue Micro-LED into white light output.

[0018] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows: 1. High crystal quality and high uniformity: The DPSS substrate reduces the dislocation density to 10 through lateral epitaxy. 7 cm-2 The magnitude of the quantum efficiency is increased, and the location of dislocations is constrained, thereby improving the internal quantum efficiency from the root, ensuring the brightness and wavelength consistency of matrix pixels, and significantly improving the yield of automotive-grade products.

[0019] 2. High native light extraction efficiency: The DPSS micro-nano structure retained on the N-side allows photons to undergo multiple scattering, changing the emission angle to break through the limitation of total internal reflection, thus improving light extraction efficiency without additional roughening processes; combined with a refractive index buffer layer, it further reduces interface reflection loss.

[0020] 3. Extreme heat dissipation and uniform current: The vertical structure directly connects the heat-generating core to the high thermal conductivity substrate through metal bonding, creating a low thermal resistance vertical heat dissipation channel; the current flows uniformly through the light-emitting area in the vertical direction, physically eliminating the current congestion effect and avoiding local hot spots.

[0021] 4. Automotive-grade high reliability: Low on-resistance reduces forward voltage and power consumption; the all-metal bonding structure provides strong resistance to thermal and mechanical fatigue; efficient heat dissipation and uniform current work together to support stable high-brightness output under ultra-high current density, meeting the requirements of high-power automotive lighting and long life. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to the present invention; Figure 2 This is a schematic diagram of the structure after steps S1 and S2 in the preparation method of the present invention; Figure 3 This is a schematic diagram of the structure after substrate peeling in step S3 of the preparation method of the present invention; Figure 4 This is a schematic diagram of the structure after thinning treatment in step S3 of the preparation method of the present invention; Figure 5 This is a schematic diagram of the structure after step S4 in the preparation method of the present invention; Figure 6 This is a schematic diagram of the structure after treatment in step S5 of the preparation method of the present invention; Figure 7 This is a schematic diagram of the device structure after step S6 in the preparation method of the present invention; Figure 8This is a SEM image of the Micro-LED pixel mesa obtained by the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0027] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0028] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] All epitaxial growth in all embodiments was performed using a commercial MOCVD system, chip fabrication was carried out using standard semiconductor process line equipment, and performance testing was performed using a probe station, integrating sphere, spectrometer, thermal resistance tester, and high and low temperature test chamber.

[0031] Example 1 See appendix Figure 1-8 As shown, this embodiment provides a method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy (wherein DPSS is: a dielectric patterned sapphire substrate with a periodically distributed dielectric pattern, and a GaN-based epitaxial layer formed on the DPSS substrate using crystal plane-assisted lateral epitaxial growth technology, with a dislocation density ≤1×10⁻⁶). 7 cm -2 ;) The specific preparation process is as follows: S1, Epitaxial wafer pretreatment: A GaN epitaxial wafer with a DPSS substrate was selected as the starting material. The epitaxial layers, from bottom to top, consisted of an N-type GaN layer, an InGaN / GaN multiple quantum well light-emitting layer, and a P-type GaN layer. The epitaxial growth was performed using a crystal plane-assisted lateral epitaxial growth technique, and the overall dislocation density was ≤1×10⁻⁶. 7 cm -2 This is far lower than the level of traditional planar sapphire epitaxy.

[0032] An ITO thin film with a thickness of 150 nm was deposited on the surface of a P-type GaN layer using electron beam evaporation. The sample was then placed in a rapid annealing furnace and annealed at 550 °C in air for 10 min to allow the ITO to form a good ohmic contact with the P-type GaN and reduce the contact resistance.

[0033] S2, eutectic bonding: AuSn eutectic metal layers were deposited on the P-side ITO surface of the epitaxial wafer and the corresponding areas of the silicon-based CMOS driving substrate, with a total metal layer thickness of 3 μm. After precise alignment of the GaN epitaxial wafer and the CMOS driving substrate, they were bonded face-to-face and placed in a vacuum eutectic bonding machine. The bonding was completed by holding the temperature and pressure at 320°C and 1 MPa for 15 minutes in a nitrogen atmosphere, forming a bonded body that has both mechanical and electrical connections.

[0034] S3, Substrate lift-off and N-plane fabrication: Substrate separation is performed using a 248nm excimer laser: the laser is incident from the sapphire side, passes through the sapphire and is absorbed by the GaN layer at the interface, causing the interface GaN to decompose into Ga metal and nitrogen gas, thereby achieving complete separation of the DPSS sapphire substrate and GaN epitaxial wafer.

[0035] After substrate stripping, the exposed N-type GaN layer was thinned as a whole using inductively coupled plasma dry etching. The etching depth was controlled during the etching process to completely preserve the DPSS micro-nano dome structure on the N-type GaN surface. After thinning, the height difference of the DPSS structure was controlled at 1.2~1.3μm, with the thinnest part of the N-type GaN having a remaining thickness of about 1.2μm and the thickest part having a remaining thickness of about 2.5μm, ensuring that the light scattering and anti-reflection effect of the micro-nano structure was not damaged.

[0036] After thinning, a thin Pre-ITO layer is deposited on the N-type GaN surface using electron beam evaporation to serve as the N-side ohmic contact layer.

[0037] As an alternative implementation, a phosphoric acid-based etching solution can be used to selectively etch and remove the substrate: the bond is immersed in the phosphoric acid-based etching solution, and the etching solution penetrates to the interface between the substrate and GaN through the side trenches, selectively etching the low-quality GaN buffer layer at the interface to achieve complete separation of the DPSS substrate; the separated sapphire substrate can be reused after cleaning, reducing production costs.

[0038] S4, Pixel platform film preparation: A 600 nm thick SiO2 layer was grown on the surface of the Pre-ITO layer using plasma-enhanced chemical vapor deposition (PECVD) as a hard mask. After spin-coating positive photoresist, periodic island-shaped photolithographic patterns were formed through exposure and development. The SiO2 layer was then etched using the photoresist as a mask to transfer the pattern onto the hard mask.

[0039] The ICP dry etching process was employed to sequentially etch away the Pre-ITO layer, N-type GaN layer, quantum well light-emitting layer, and P-type GaN layer outside the mesa, down to the surface of the bonding metal layer. Due to the inherent thickness difference in DPSS epitaxy, some epitaxial layer remains between mesa layers after dry etching. Therefore, the sample was immersed in a 20% KOH solution and wet etched at 80°C. This process thoroughly removes the epitaxial residue between mesa layers, ensuring electrical isolation between pixels. Furthermore, KOH wet etching repairs sidewall lattice damage caused by ICP dry etching, reducing non-radiative recombination centers on the sidewalls and improving the device's luminous efficiency and reliability.

[0040] After wet etching, the remaining SiO2 hard mask is removed using BOE buffered oxide etchant, resulting in Micro-LED pixel mesa arranged in a row-column matrix. In this embodiment, the pixel mesa diameter is 50 μm, and the pixel pitch matches the resolution and optical design requirements of the automotive headlight.

[0041] S5, Electrode structure fabrication: A 200nm thick first SiO2 passivation layer is grown on the entire surface of the device using PECVD to protect the sidewalls of the epitaxial layer and the bonding metal layer. Combined with photolithography, ion beam etching (IBE) is used to etch the ITO and bonding metal layers between the mesa down to the surface of the silicon-based CMOS substrate, achieving electrical isolation between adjacent pixels.

[0042] An N-side ITO film with a thickness of 300nm is deposited using electron beam evaporation, enabling electrical connection of the N-side of all pixel mesa through ITO to ensure uniform current distribution. Subsequently, ITO outside the light-emitting area is removed using ITO wet etching solution to avoid short circuits.

[0043] A negative photoresist is spin-coated onto the device surface. After pre-baking, exposure, and development, the channel region between the mesa is exposed. A Cr / Al / Ti / Au stacked N-electrode metal is deposited using an electron beam evaporation process, with a total thickness of 2.5 μm. After the deposition is completed, excess metal and photoresist are removed by a stripping process, forming a continuous and interconnected mesh-like N-electrode metal in the channel between the pixel mesa. This serves as a common N-electrode for the entire surface, further reducing the N-electrode on-resistance and ensuring uniform current distribution under high current.

[0044] S6, Functional layer fabrication and white light conversion: A second SiO2 passivation layer with a thickness of 150 nm was grown on the device surface using PECVD. This layer serves two purposes: firstly, as a physical protective layer to isolate moisture and external forces; and secondly, as a refractive index buffer layer with a refractive index between GaN and air, which reduces total internal reflection at the interface and further improves light extraction efficiency. Subsequently, the second passivation layer was patterned using photolithography and dry etching processes, exposing the electrode pad areas of the N and P electrodes for subsequent wire bonding.

[0045] The light-emitting region is defined using photolithography. Oxygen plasma is used to treat the light-emitting surface of the pixel mesa, increasing the surface hydroxyl density and improving the adhesion of the phosphor layer. Subsequently, yellow phosphor is uniformly filled into the light-emitting region using spin coating. After stepped temperature curing, the surface is thinned and polished to control the phosphor layer thickness uniformity deviation to ≤5%, converting the blue Micro-LED into white light output. Finally, after encapsulation, a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy is obtained.

[0046] Testing showed that the Micro-LED matrix headlight fabricated in this embodiment achieved an 18% improvement in internal quantum efficiency, a 22% improvement in light extraction efficiency, and a 65% reduction in thermal resistance compared to the traditional flat-panel lateral solution, reaching a range of 25 A / cm². 2 It operates stably under ultra-high current density, with pixel brightness uniformity >96%, meeting the lifespan and reliability requirements of automotive-grade high-power lighting.

[0047] Example 2 This embodiment targets the application scenario of high-resolution automotive matrix headlights, employing smaller pixel units and Au-Au metal hot-press bonding technology to further improve pixel integration. The specific fabrication process is as follows: S1, Epitaxial wafer pretreatment: Select dislocation density ≤ 8 × 10 6 cm -2 The DPSS substrate GaN epitaxial wafer has the same epitaxial layer structure as in Example 1. A 150 nm thick ITO film was deposited on the surface of the P-type GaN layer using electron beam evaporation, followed by annealing at 500 °C in a nitrogen atmosphere for 15 min to form a stable P-side ohmic contact.

[0048] S2, eutectic bonding: (Au-Au hot-press bonding) Pure Au metal layers with a thickness of 1.5 μm were deposited on the ITO surface of the P-side of the epitaxial wafer and the surface of the silicon-based CMOS driving substrate as bonding layers. After precise alignment of the epitaxial wafer and the CMOS substrate, they were bonded face-to-face and placed in a vacuum hot press at 280°C and 2 MPa for 20 minutes. The thermal diffusion of Au atoms achieved intermetallic bonding, forming a bonded body. This bonding method eliminates the risk of eutectic liquid phase overflow and is more suitable for the alignment accuracy requirements of small-sized, high-density pixels.

[0049] S3, Substrate lift-off and N-plane fabrication: The DPSS sapphire substrate was removed using a 248nm excimer laser lift-off process, and the exposed N-type GaN layer was then subjected to ICP dry thinning. After thinning, the height difference of the DPSS micro / nano structure was controlled to 1.2 μm, with the thinnest N-type GaN layer measuring 1.2 μm and the thickest 2.4 μm, completely preserving the micro / nano scattering structure. A thin Pre-ITO layer was then deposited as the N-face contact layer after thinning.

[0050] S4, Pixel platform film preparation: A SiO2 hard mask was grown using PECVD and patterned by photolithography to form a periodic island-shaped mask pattern with a diameter of 40 μm. After penetrating the epitaxial layer using ICP dry etching, the sample was immersed in a 15% KOH solution and wet etched at 75°C for 12 min to completely remove epitaxial residues between mesa and repair sidewall damage. After removing the hard mask using BOE, a 40 μm pixel matrix array was obtained, with a pixel pitch adapted to the optical design of high-resolution headlights.

[0051] S5, Electrode structure fabrication: After depositing the first SiO2 passivation layer across the entire surface, IBE etching is used to achieve electrical isolation between pixels. A 300nm thick N-side ITO film is deposited across the entire surface, and the non-emitting ITO areas are removed by wet etching. A 2μm thick mesh-like N-electrode metal is fabricated using a negative resist lift-off process. The metal layer has a Cr / Al / Cu / Au stacked structure, forming a continuous common N-electrode between high-density pixels to ensure uniform current spread under high current.

[0052] S6, Functional layer fabrication and white light conversion: A second SiO2 passivation layer with a thickness of 120 nm was grown as a refractive index buffer and protective layer, and the electrode pads were patterned to expose the surface. After oxygen plasma treatment of the light-emitting surface, yellow phosphor was spin-coated and cured to reduce its thickness. The uniformity deviation of the phosphor layer thickness was controlled to be ≤4%, thus completing the white light conversion.

[0053] Tests showed that the 40μm pixel Micro-LED matrix headlight produced in this embodiment has a pixel density that is 56% higher than that of Embodiment 1, enabling more precise zoned light control and signage projection functions; the internal quantum efficiency is 21% higher than that of the traditional flat lateral solution of the same size, the thermal resistance is reduced by 68%, and the brightness uniformity between pixels is >95%, meeting the requirements for high-resolution vehicle adaptive headlights.

[0054] Example 3 This embodiment targets high-power automotive high-beam lighting scenarios, employing a large-size pixel and wet substrate separation process, combined with mixed phosphors to achieve high color rendering white light output, while simultaneously enabling the recycling and reuse of the sapphire substrate. The specific fabrication process is as follows: S1, Epitaxial wafer pretreatment: Select dislocation density ≤ 1×10 7 cm -2 The DPSS substrate GaN epitaxial wafer was deposited with a 150nm thick ITO film on the surface of the P-type GaN layer using electron beam evaporation, and then annealed at 600℃ in air for 8 minutes to form a low-resistivity P-side ohmic contact.

[0055] S2, eutectic bonding: AuSn eutectic metal layers with a total thickness of 3.5 μm were deposited on the surfaces of the epitaxial wafer and the CMOS substrate, respectively. After precise alignment and bonding, eutectic bonding was carried out for 10 minutes in a nitrogen atmosphere at 350°C and 0.5 MPa pressure to form a high-strength bond, which meets the heat dissipation and mechanical reliability requirements of high-power devices.

[0056] S3, Substrate lift-off and N-plane fabrication: The bond was immersed in an 85°C phosphate-based mixed etching solution. The etching solution penetrated through the device side trenches to the interface between the DPSS substrate and the GaN epitaxial wafer, selectively etching the low-quality GaN buffer layer at the interface. The etching time was controlled at 45 minutes, achieving complete separation of the DPSS sapphire substrate and the epitaxial layer. After separation, the sapphire substrate could be directly recycled and reused for epitaxial growth after being cleaned with deionized water and rinsed with acid, significantly reducing raw material costs.

[0057] After substrate stripping, the N-type GaN layer was thinned by ICP. After thinning, the height difference of the DPSS structure was 1.3 μm. The thinnest part of the N-type GaN was 1.3 μm and the thickest part was 2.5 μm, completely preserving the micro-nano antireflection structure. Subsequently, a Pre-ITO layer was deposited by vapor deposition.

[0058] S4, Pixel platform film preparation: After patterning with a SiO2 hard mask, an island-shaped mask array with a diameter of 60 μm is formed. After ICP dry etching, wet etching is performed at 85°C for 8 min using a 25% KOH solution to remove epitaxial residues and repair sidewall damage. After BOE mask removal, a matrix mesa with 60 μm pixels is obtained.

[0059] S5, Electrode structure fabrication: After depositing the first SiO2 passivation layer and isolating it with IBE etching, a 300nm thick N-side ITO film is deposited and patterned across the entire surface. A 3μm thick Ti / Al / Ti / Au stacked N-polarity metal mesh is prepared using a negative resist lift-off process to further reduce the on-state voltage drop and Joule heating under high current.

[0060] S6, Functional layer fabrication and white light conversion: A second SiO2 passivation layer with a thickness of 180 nm was grown, and the electrode pads were patterned to expose them. After oxygen plasma treatment of the light-emitting surface, a mixed phosphor layer of YAG yellow phosphor and nitride red phosphor was spin-coated. After step curing and thinning polishing, a warm white light output with a color rendering index Ra>90 was achieved, improving the visual comfort and color reproduction of nighttime lighting.

[0061] Testing showed that the 60μm pixel Micro-LED matrix headlight fabricated in this embodiment exhibited a 42% increase in single-pixel light output power, a 17% increase in internal quantum efficiency, a 24% increase in light extraction efficiency, and a 63% reduction in device thermal resistance compared to Embodiment 1; at 30 A / cm 2 It can operate continuously for 1000 hours at ultra-high current density with light decay of less than 3%, meeting the stringent requirements of high power and long life of automotive high beams. Moreover, the sapphire substrate recovery rate can reach more than 95%, significantly reducing mass production costs.

[0062] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy, characterized in that, Includes the following steps: S1, Epitaxial wafer pretreatment: Take a GaN epitaxial wafer with DPSS, wherein the dislocation density of the GaN epitaxial wafer is ≤1×10 7 cm -2 A P-plane ITO thin film is deposited on the surface of the P-type GaN layer of the GaN epitaxial wafer, and then annealed to form an ohmic contact. S2, Eutectic bonding: Bonding metal layers are deposited on the P-side ITO surface of the GaN epitaxial wafer and the surface of the silicon-based CMOS driving substrate respectively. The GaN epitaxial wafer and the CMOS driving substrate are then bonded face to face and formed into a bond body through high temperature and high pressure eutectic bonding. S3, Substrate stripping and N-side fabrication: Remove the DPSS of the bonded structure, thin the exposed N-type GaN layer, and retain the DPSS micro / nano structure on the surface of the N-type GaN layer; After thinning, a Pre-ITO layer is deposited on the N-type GaN surface as the N-side contact layer; S4, Pixel platform mask fabrication: A hard mask layer is deposited on the surface of the Pre-ITO layer, and after photolithography patterning, a periodic island-shaped mask is formed; ICP dry etching is used to remove the Pre-ITO layer, N-type GaN layer, quantum well light-emitting layer and P-type GaN layer between mesa. Then wet etching is used to remove the epitaxial residue between mesa and repair the defects on the mesa sidewalls. Finally, the hard mask is removed to obtain the matrix-arranged Micro-LED pixel mesa. S5, Electrode structure fabrication: Deposit the first passivation layer on the device surface, and use ion beam etching to disconnect the conductive layer between the mesa to the surface of the CMOS driving substrate; An N-sided ITO thin film is deposited by vapor deposition on the entire surface, and the ITO outside the light-emitting area is removed by patterning. A grid-like N-polar metal layer is prepared in the channel between the pixel mesa, and the N-polar metal layer forms an electrical connection with the N-sided ITO thin film to form a common N-polarity. S6, Functional layer fabrication and white light conversion: A second passivation layer is deposited on the device surface as a refractive index buffer layer and a protective layer, and the electrode pad area is patterned to expose the device. A phosphor layer is filled on the light-emitting side of the pixel mesa, and after curing and thinning, a white light Micro-LED automotive matrix headlight device is obtained.

2. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S1, the thickness of the P-side ITO film is 150 nm, and it is deposited using an electron beam evaporation process; the annealing temperature is 500~600℃, and the annealing atmosphere is air or nitrogen atmosphere.

3. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S2, the bonding metal layer is an AuSn eutectic alloy layer or an Au-Au metal layer; the eutectic bonding temperature is 280~350℃, and the bonding pressure is 0.5~2MPa.

4. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S3, the DPSS is removed by laser lift-off process or selective etching lift-off process using phosphate-based etchant; the sapphire substrate can be reused after cleaning.

5. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S3, the height difference of the DPSS micro-nano structure of the thinned N-type GaN layer is 1.2~1.3μm, the thickness of the thinnest part of the N-type GaN layer is 1.2μm, and the thickness of the thickest part is 2.5μm.

6. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S4, the hard mask layer is a SiO2 layer grown by PECVD process; the wet etching uses KOH alkaline solution to repair the sidewall lattice damage caused by ICP dry etching at the same time.

7. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S4, the diameter of the Micro-LED pixel mesa is 40μm, 50μm or 60μm, and each pixel mesa is arranged in a row and column matrix.

8. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S5, the thickness of the N-side ITO thin film is 300 nm, and it is prepared by electron beam evaporation. The N-polar metal layer is prepared by negative photoresist stripping process, and its thickness is 2~3 μm, forming a continuous and interconnected grid-like common N-polar layer.

9. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S6, the second passivation layer is a SiO2 dielectric layer, and its refractive index is between that of GaN epitaxial wafer and air.

10. The method for fabricating a vertical structure Micro-LED automotive matrix headlight based on DPSS epitaxy according to claim 1, characterized in that, In step S6, the light-emitting surface of the pixel mesa is treated with oxygen plasma before the phosphor is filled; the phosphor is filled by spin coating process to convert the blue Micro-LED into white light output.

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