Electronic device

Abstract

An electronic device is provided. The electronic device includes a plurality of first main lines, a plurality of first branch lines, and a first circuit group. The plurality of first main lines extends in a first direction. The plurality of first branch lines is respectively electrically connected to the plurality of first main lines and extends in a second direction perpendicular to the first direction. The first circuit group is disposed at one side of the plurality of first main lines and includes a first circuit and a second circuit. The first circuit is electrically connected to one of the plurality of first branch lines. The second circuit is electrically connected to another of the plurality of first branch lines. The first circuit and the second circuit are arranged in the second direction.

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] For electronic devices with narrow bezels or even no bezels, functional circuits (such as drive circuits, detection circuits, electrostatic discharge (ESD) protection circuits, etc.) need to be integrated into the active region or pixel area. Therefore, the active region or pixel area needs to be rearranged. Summary of the Invention

[0003] This disclosure pertains to an electronic device that facilitates the achievement of narrow bezels or even bezel-less designs.

[0004] According to embodiments of this disclosure, an electronic device includes multiple first main lines, multiple first branch lines, and a first circuit group. The multiple first main lines extend along a first direction. The multiple first branch lines are respectively electrically connected to the multiple first main lines and extend along a second direction perpendicular to the first direction. The first circuit group is disposed on one side of the multiple first main lines and includes a first circuit and a second circuit. The first circuit is electrically connected to one of the multiple first branch lines. The second circuit is electrically connected to the other of the multiple first branch lines. The first circuit and the second circuit are arranged along the second direction.

[0005] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0007] Figure 2 yes Figure 1 A simple circuit diagram of a medium-sized circuit;

[0008] Figure 3 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 4 For the corresponding Figure 3 A magnified view of the four pixels in the image;

[0010] Figure 5 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0011] Figure 6 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0013] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as meaning "containing but not limited to...".

[0014] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of various films, regions, and / or structures may be reduced or enlarged.

[0015] As described in this disclosure, a structure (or layer, element, substrate) located on / above another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate spacer) between the two structures, with the lower surface of one structure adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single or multiple solid or non-solid structure, without limitation.

[0016] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0017] The electrical connection or coupling described in this disclosure can refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable component, or combination of the above components between the endpoints of the components in two circuits, but not limited thereto.

[0018] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), or the thickness or width can be measured from a cross-sectional image in an electron microscope, but are not limited thereto. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0019] Figure 1 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 2 yes Figure 1 A simplified circuit diagram of the circuit. Figure 3 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 4 For the corresponding Figure 3 A magnified view of the four pixels in the image. Figure 5 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 6 This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. In this top view schematic diagram, some components or films are not shown for the sake of simplicity and clarity. However, if desired, the electronic device may include components or films not shown in the top view schematic diagram. It is worth noting that the following embodiments can be replaced, rearranged, and combined with features of several different embodiments without departing from the spirit of the present disclosure to complete other embodiments. Features in various embodiments can be mixed and matched, as long as they do not violate the spirit of the present disclosure or conflict with each other.

[0020] Please refer to Figure 1The electronic device 1 may include multiple first main lines M1, multiple first branch lines B1, and a first circuit group GC1. The multiple first main lines M1 extend along a first direction D1. The multiple first branch lines B1 are electrically connected to the multiple first main lines M1 and extend along a second direction D2 perpendicular to the first direction D1. The first circuit group GC1 is disposed on one side (e.g., the left side) of the multiple first main lines M1 and includes a first circuit (e.g., circuit CK11) and a second circuit (e.g., circuit CK12). The first circuit (circuit CK11) is electrically connected to one of the multiple first branch lines B1 (e.g., first branch line B11). The second circuit (circuit CK12) is electrically connected to the other of the multiple first branch lines B1 (e.g., first branch line B12). The first circuit (circuit CK11) and the second circuit (circuit CK12) are arranged along the second direction D2.

[0021] Specifically, Figure 1 The diagram schematically illustrates a pixel PX and the wiring surrounding it (including multiple first main lines M1 and multiple first branch lines B1). In some embodiments, the electronic device 1 may be a light-emitting device, such as a miniature light-emitting device, but is not limited thereto. For example, the electronic device 1 may further include a first light-emitting unit L1 electrically connected to a first circuit group GC1, wherein the first light-emitting unit L1 is disposed on one side (e.g., the left side) of the multiple first main lines M1, and the first light-emitting unit L1 and the multiple first branch lines B1 may be disposed on opposite sides (e.g., above and below) of the first circuit group GC1. That is, the first circuit group GC1 may be disposed between the first light-emitting unit L1 and the multiple first branch lines B1.

[0022] In some embodiments, the first light-emitting unit L1 may include a first light-emitting element L11 and a second light-emitting element L12, which are respectively electrically connected to the first circuit (circuit CK11) and the second circuit (circuit CK12). Optionally, as Figure 1 As shown, the first light-emitting unit L1 may further include a third light-emitting element L13, and the first circuit group GC1 may further include a circuit CK13 electrically connected to the third light-emitting element L13. In some embodiments, such as Figure 1 As shown, the third light-emitting element L13 can be disposed between the first light-emitting element L11 and the second light-emitting element L12, and the circuit CK13 can be disposed between the circuit CK11 and the circuit CK12, but is not limited thereto. In some alternative embodiments, the first light-emitting element L11, the second light-emitting element L12 and the third light-emitting element L13 can be arranged sequentially along the second direction D2, and the circuits CK11, CK12 and CK13 can be arranged sequentially along the second direction D2.

[0023] The number of multiple first main lines M1 and multiple first branch lines B1 can both be three, and each circuit can be electrically connected to the corresponding first main line through the corresponding first branch line. For example, such as Figure 1 As shown, circuit CK11 can be electrically connected to the first main line M11 through the first branch line B11, circuit CK12 can be electrically connected to the first main line M12 through the first branch line B12, and circuit CK13 can be electrically connected to the first main line M13 through the first branch line B13.

[0024] In some embodiments, the first light-emitting unit L11, the second light-emitting element L12, and the third light-emitting element L13 are respectively red, green, and blue micro-light-emitting elements; circuits CK11, CK12, and CK13 are micro-light-emitting element driving circuits; and multiple first main lines M1 and multiple first branch lines B1 are data lines for transmitting data signals, but are not limited thereto. In some embodiments, multiple first main lines M1 belong to a first patterned conductive layer, and multiple first branch lines B1 belong to a second patterned conductive layer. The second patterned conductive layer overlaps the first patterned conductive layer along a third direction D3 perpendicular to the first direction D1 and the second direction D2. At least one insulating layer ( Figure 1 (Not shown) can be disposed between the first patterned conductive layer and the second patterned conductive layer, and each first main line can be electrically connected to the corresponding first branch line through a through-hole CV penetrating at least one insulating layer.

[0025] In some embodiments, such as Figure 1 As shown, the electronic device 1 may further include multiple auxiliary lines AL, wherein each circuit (including circuit CK11, circuit CK12 and circuit CK13) can be electrically connected to the corresponding first branch line through the corresponding auxiliary line AL. In some embodiments, the multiple auxiliary lines AL belong to a first patterned conductive layer (that is, the multiple auxiliary lines AL and the multiple first main lines M1 can be formed together), and each auxiliary line AL can be electrically connected to the corresponding first branch line through a through-hole CV penetrating at least one insulating layer.

[0026] Each circuit in the first circuit group GC1 (including circuits CK11, CK12, and CK13) may include one or more active components and one or more passive components. For example, such as Figure 2 As shown, each circuit may include six transistors and one capacitor (also referred to as "6T1C"). Specifically, each circuit in the first circuit group GC1 (including circuits CK11, CK12, and CK13) may include transistors T1, T2, T3, T4, T5, T6, and a storage capacitor Cst. Each transistor has a first terminal, a second terminal, and a third terminal, wherein the first terminal is the gate terminal, one of the second and third terminals is the source terminal, and the other of the second and third terminals is the drain terminal.

[0027] like Figure 2As shown, the first terminal of transistor T1 can be electrically connected to one terminal of the storage capacitor Cst, the third terminal of transistor T4, and the second terminal of transistor T6. The second terminal of transistor T1 can be electrically connected to the second terminals of transistors T3 and T4. The third terminal of transistor T1 can be electrically connected to the third terminals of transistors T2 and T5. The first terminal of transistor T2 can be electrically connected to the scan line SL. The second terminal of transistor T2 can be electrically connected to the data line DL (e.g., one of multiple first main lines M1). The first terminal of transistor T3 can be electrically connected to the emitter control line EM. The third terminal of transistor T3 can be electrically connected to the corresponding light-emitting element (e.g., the first light-emitting element L11, the second light-emitting element L12, or the third light-emitting element L13). The first terminal of transistor T4 can be electrically connected to the scan line SL. The first terminal of transistor T5 can be electrically connected to the emitter control line EM. The second terminal of transistor T5 can be electrically connected to the other terminal of the storage capacitor Cst and the power supply line PSL that provides the power supply voltage (e.g., PVDD). The first terminal of transistor T6 can be electrically connected to the reset line RST. The third terminal of transistor T6 can be electrically connected to the power line PL that provides the power supply voltage (e.g., VRST). The corresponding light-emitting element (e.g., the first light-emitting element L11, the second light-emitting element L12, or the third light-emitting element L13) can be electrically connected between the third terminal of transistor T3 and the ground line GL that provides the ground voltage (e.g., PVSS). It should be understood that... Figure 2 This is only a schematic diagram of one embodiment of the circuit; other circuit structures may also be used.

[0028] Please refer to Figure 3 and Figure 4 In addition to the aforementioned multiple first main lines M1, multiple first branch lines B1, first circuit group GC1, and first light-emitting unit L1, the electronic device 1A may also include a second circuit group GC2 disposed on one side (e.g., the left side) of the multiple first main lines M1. The second circuit group GC2 may include a third circuit (e.g., circuit CK21) electrically connected to one of the multiple first branch lines B1 (e.g., first branch line B11) and a fourth circuit (e.g., circuit CK22) electrically connected to another of the multiple first branch lines B1 (e.g., first branch line B12), and the multiple first branch lines B1 may be disposed between the first circuit group GC1 and the second circuit group GC2. For example, as... Figure 3 or Figure 4 As shown, the first circuit group GC1 and the second circuit group GC2 are arranged along the first direction D1. In some embodiments, as Figure 3 or Figure 4As shown, the second circuit group GC2 may further include circuit CK23 electrically connected to the first branch B13 of the plurality of first branches B1. Each circuit in the second circuit group GC2 (including circuits CK21, CK22, and CK23) may include one or more active components and one or more passive components. Please refer to [reference needed] for details. Figure 2 The relevant descriptions will not be repeated here. In some embodiments, such as Figure 3 or Figure 4 As shown, each circuit in the second circuit group GC2 (including circuits CK21, CK22 and CK23) can be electrically connected to the corresponding first branch through the corresponding auxiliary line AL.

[0029] In the embodiment where the first circuit group GC1 and the second circuit group GC2 share multiple first branch lines B1, the wiring space between the first circuit group GC1 and the second circuit group GC2 can be reduced, thereby freeing up more space to arrange other functional circuits.

[0030] In some embodiments, the electronic device 1A may further include a second light-emitting unit L2 electrically connected to the second circuit group GC2, wherein the first light-emitting unit L1 and the second light-emitting unit L2 are disposed on one side (e.g., the left side) of the plurality of first main lines M1, the first light-emitting unit L1 is disposed on the side of the first circuit group GC1 away from the plurality of first branch lines B1 (e.g., the upper side), and the second light-emitting unit L2 is disposed on the side of the second circuit group GC2 away from the plurality of first branch lines B1 (e.g., the lower side). That is, the first circuit group GC1, the plurality of first branch lines B1 and the second circuit group GC2 may be disposed between the first light-emitting unit L1 and the second light-emitting unit L2.

[0031] In some embodiments, the second light-emitting unit L2 may also include three light-emitting elements respectively electrically connected to circuits CK21, CK22 and CK23. Figure 3 or Figure 4 (Not shown in the image). Please refer to the following for details. Figure 1 The relevant descriptions will not be repeated here.

[0032] In some embodiments, the electronic device 1A may further include a plurality of second main lines M2, a plurality of second branch lines B2, and a third circuit group GC3. The plurality of second main lines M2 may extend along a first direction D1. The plurality of second branch lines B2 may be electrically connected to the plurality of second main lines M2 and may extend along a second direction D2. The third circuit group GC3 may be disposed on the side of the plurality of second main lines M2 away from the plurality of first main lines M1 (e.g., the right side). The third circuit group GC3 may include a fifth circuit (e.g., circuit CK31) electrically connected to one of the plurality of second branch lines B2 (e.g., second branch line B21) and a sixth circuit (e.g., circuit CK32) electrically connected to another of the plurality of second branch lines B2 (e.g., second branch line B22). The plurality of first main lines M1 and the plurality of second main lines M2 are disposed between the first circuit group GC1 and the third circuit group GC3. For example, as... Figure 3 or Figure 4 As shown, the first circuit group GC1 and the third circuit group GC3 are arranged along the second direction D2. In some embodiments, as Figure 4 As shown, the third circuit group GC3 may also include circuit CK33 electrically connected to the second branch B23 of the plurality of second branches B2. Each circuit in the third circuit group GC3 (including circuits CK31, CK32, and CK33) may include one or more active components and one or more passive components. Please refer to [reference needed] for details. Figure 2 The relevant descriptions will not be repeated here. In some embodiments, such as Figure 3 or Figure 4 As shown, each circuit in the third circuit group GC3 (including circuits CK31, CK32 and CK33) can be electrically connected to the corresponding second branch through the corresponding auxiliary line AL.

[0033] In some embodiments, multiple second main lines M2 belong to a first patterned conductive layer (i.e., multiple second main lines M2, multiple auxiliary lines AL, and multiple first main lines M1 can be formed together), and multiple second branch lines B2 belong to a second patterned conductive layer (i.e., multiple second branch lines B2 and multiple first branch lines B1 can be formed together). Each of the multiple second main lines M2 (including second main lines M21, second main lines M22, and second main lines M23) can be electrically connected to the corresponding second branch line (e.g., second branch line B21, second branch line B22, and second branch line B23) through a via CV, and each auxiliary line AL can be electrically connected to the corresponding second branch line through a via CV.

[0034] In some embodiments, the electronic device 1A may further include a fourth circuit group GC4 disposed on the side (e.g., the right side) away from the plurality of second main lines M2. The fourth circuit group GC4 may include a seventh circuit (e.g., circuit CK41) electrically connected to one of the plurality of second branches B2 (e.g., second branch B21) and an eighth circuit (e.g., circuit CK42) electrically connected to another of the plurality of second branches B2 (e.g., second branch B22), wherein the plurality of second branches B2 are disposed between the third circuit group GC3 and the fourth circuit group GC4, and the plurality of first main lines M1 and the plurality of second main lines M2 are also disposed between the second circuit group GC2 and the fourth circuit group GC4. For example, as... Figure 4 As shown, the third circuit group GC3 and the fourth circuit group GC4 are arranged along the first direction D1, and the second circuit group GC2 and the fourth circuit group GC4 are arranged along the second direction D2. In some embodiments, as Figure 4 As shown, the fourth circuit group GC4 may also include circuit CK43 electrically connected to the second branch B23 of the plurality of second branches B2. Each circuit in the fourth circuit group GC4 (including circuits CK41, CK42, and CK43) may include one or more active components and one or more passive components. Please refer to [reference needed] for details. Figure 2 The relevant descriptions will not be repeated here. In some embodiments, such as Figure 3 or Figure 4 As shown, each circuit in the fourth circuit group GC4 (including circuits CK41, CK42 and CK43) can be electrically connected to the corresponding second branch through the corresponding auxiliary line AL.

[0035] In the embodiment where the third circuit group GC3 and the fourth circuit group GC4 share multiple second branch lines B2, the wiring space between the third circuit group GC3 and the fourth circuit group GC4 can be reduced, thereby freeing up more space to arrange other functional circuits.

[0036] In some embodiments, the electronic device 1A may further include a third light-emitting unit L3 electrically connected to a third circuit group GC3 and a fourth light-emitting unit L4 electrically connected to a fourth circuit group GC4. The third light-emitting unit L3 and the fourth light-emitting unit L4 are disposed on the side of the plurality of second main lines M2 away from the plurality of first main lines M1 (e.g., the right side), the third light-emitting unit L3 is disposed on the side of the third circuit group GC3 away from the plurality of second branch lines B2 (e.g., the upper side), and the fourth light-emitting unit L4 is disposed on the side of the fourth circuit group GC4 away from the plurality of second branch lines B2 (e.g., the lower side). That is, the third circuit group GC3, the plurality of second branch lines B2, and the fourth circuit group GC4 may be disposed between the third light-emitting unit L3 and the fourth light-emitting unit L4.

[0037] In some embodiments, the third light-emitting unit L3 may further include three light-emitting elements electrically connected to circuits CK31, CK32, and CK33, respectively. Figure 3 or Figure 4 (Not shown in the image), the fourth light-emitting unit L4 may also include three light-emitting elements electrically connected to circuits CK41, CK42, and CK43 respectively. Figure 3 or Figure 4 (Not shown in the image). Please refer to the following for details. Figure 1 The relevant descriptions will not be repeated here.

[0038] In some embodiments, such as Figure 3 As shown, the electronic device 1A may further include a plurality of units U arranged in an array along a first direction D1 and a second direction D2, wherein each of the plurality of units U includes a plurality of first branches B1, a first circuit group GC1, a second circuit group GC2, a plurality of second branches B2, a third circuit group GC3, a fourth circuit group GC4, a first light-emitting unit L1, a second light-emitting unit L2, a third light-emitting unit L3, and a fourth light-emitting unit L4. Figure 3 Four units U are schematically shown, but electronic device 1A may include more than four units U.

[0039] By concentrating the components and / or circuits in four adjacent pixels PX in the central area of ​​the four adjacent pixels PX (e.g., the area enclosed by the thick dashed frame representing unit U), the peripheral areas of the four adjacent pixels PX (e.g., the area outside the thick dashed frame) can be left empty to accommodate functional circuitry. Since the first circuit group GC1 and the second circuit group GC2 share multiple first branches B1, and the third circuit group GC3 and the fourth circuit group GC4 share multiple second branches B2, the width W1 of unit U in the first direction D1 can be reduced. For example, the width W1 of unit U in the first direction D1 can be smaller than the width W2 of unit U in the second direction D2. Therefore, in some embodiments, such as... Figure 3 As shown, the distance DT1 between two adjacent units U arranged along the first direction D1 is greater than the distance DT2 between two adjacent units U arranged along the second direction D2. In some alternative embodiments, although not shown, W1>W2, and DT1 <DT2。

[0040] In some embodiments, such as Figure 3 As shown, the electronic device 1A may further include one or more functional lines FL extending along the second direction D2 and / or the first direction D1. For example, as Figure 4 As shown, the electronic device 1A may also include a series of units U extending along the first direction D1 and across a column of units U (i.e., a plurality of units U arranged along the first direction D1). Figure 4The diagram shows only one unit U, the first power line PL1, and a row of units U that are electrically connected to the first power line PL1 and extend along the second direction D2 and cross the second direction D2. That is, multiple units U are arranged along the second direction D2. Figure 4 The second power line PL2 of only one unit U is shown in the diagram.

[0041] In some embodiments, such as Figure 4 As shown, the first power line PL1 can be disposed between multiple first main lines M1 and multiple second main lines M2. In some embodiments, such as Figure 4 As shown, electronic device 1A may include one or more first power lines PL1 and one or more second power lines PL2. In some embodiments, such as Figure 4 As shown, the second power line PL2 (for example, Figure 4 The second power line PL2 above can cross a row of units U (that is, multiple units U arranged along the second direction D2); Figure 4 Only one unit U is shown in the diagram, along with the first circuit group GC1 and the third circuit group GC3. In some embodiments, such as Figure 4 As shown, the second power line PL2 (for example, Figure 4 The second power line PL2 below can cross a row of units U (that is, multiple units U arranged along the second direction D2); Figure 4 The second circuit group GC2 and the fourth circuit group GC4 (only one unit U) are shown in the figure.

[0042] In some embodiments, such as Figure 4 As shown, the second power line PL2 is broken into multiple parts. For example, the second power line PL2 may include multiple first parts PL21 and multiple second parts PL22 that are not aligned with the multiple first parts PL21 in the second direction D2, wherein the multiple first parts PL21 and multiple second parts PL22 may be arranged alternately along the second direction D2. The first parts PL21 may span multiple first main lines M1, a first circuit group GC1 (or a second circuit group GC2), a third circuit group GC3 (or a fourth circuit group GC4), and multiple second main lines M2 to be electrically connected to two first power lines PL1 spanning two adjacent units U. The second parts PL22 may electrically connect two adjacent first power lines PL1 spanning the same unit U. By electrically connecting multiple power lines (e.g., first power lines PL1 and second power lines PL2) together, a uniform constant potential can be provided and / or the impedance (or load) of the power lines can be reduced.

[0043] In some embodiments, such as Figure 4As shown, the first power line PL1 belongs to the first patterned conductive layer (that is, the first power line PL1, multiple second main lines M2, multiple auxiliary lines AL and multiple first main lines M1 can be formed together), while the second power line PL2 belongs to the second patterned conductive layer (that is, the second power line PL2, multiple second branch lines B2 and multiple first branch lines B1 can be formed together), wherein the second power line PL2 can be electrically connected to the first power line PL1 through multiple vias CV.

[0044] For example, such as Figure 4 As shown, the electronic device 1A may further include multiple transmission control lines EM extending along a second direction D2 and arranged along a first direction D1. Two adjacent transmission control lines EM may cross a row of cells U. For example, multiple first branches B1 and multiple second branches B2 of a row of cells U may be disposed between two adjacent transmission control lines EM, wherein one of the two adjacent transmission control lines EM crosses a first circuit group GC1 and a third circuit group GC3 of the row of cells U, and the other of the two adjacent transmission control lines EM crosses a second circuit group GC2 and a fourth circuit group GC4 of the row of cells U. The multiple transmission control lines EM may belong to a second patterned conductive layer (i.e., the multiple transmission control lines EM, the second power line PL2, the multiple second branches B2, and the multiple first branches B1 may be formed together). In some alternative embodiments, the multiple second branches B2 and the multiple first branches B1 may belong to a second patterned conductive layer, and the multiple transmission control lines EM and the second power line PL2 may belong to a third patterned conductive layer.

[0045] For example, such as Figure 4 As shown, the electronic device 1A may also include multiple scan lines SL and multiple reset lines RST. The details of the multiple scan lines SL and multiple reset lines RST (e.g., architecture, associated film layers, etc.) are similar to those of the multiple emission control lines EM, and will not be repeated here.

[0046] exist Figure 4 In this configuration, the second power line PL2, reset line RST, scan line SL, and transmit control line EM are arranged sequentially in a direction away from the plurality of first branches B1 and the plurality of second branches B2 (e.g., the first direction or its opposite direction), but this disclosure is not limited thereto. Furthermore, Figure 3 The type and / or number of function lines (FLs) are not limited. For example, function lines (FLs) may include more than […]. Figure 4 The number of function lines shown may be more or less.

[0047] Please refer to Figure 5 In addition to the aforementioned multiple first main lines M1, multiple second main lines M2, multiple units U, and function lines FL, the electronic device 1B may also include a detection circuit INP disposed between two adjacent rows of units U. In some embodiments, such as Figure 5 As shown, electronic device 1B may include more than one detection circuit INP. In some alternative embodiments, although Figure 5 Not shown, but other components may be placed between two adjacent rows of cells U. For example, ESD protection diodes or systems; process control marking groups; process inspection / verification patterns; signal fan-out patterns; monitoring lines; GOP control signal lines; power lines; distinguishing marks, text, letters, patterns, etc.; test markings (e.g., test element group (TEG), device under test (DUT), etc.); vias in the substrate (e.g., THV, TGV, etc.); circuit groups; function lines FL; auxiliary lines AL; and / or combinations of at least two of the above may be placed between two adjacent rows of cells U, but are not limited thereto.

[0048] In some embodiments, such as Figure 5 As shown, the electronic device 1B may further include a first power supply line PSL1 disposed between two adjacent column units U and a second power supply line PSL2 electrically connected to the first power supply line PSL1 and disposed between two adjacent row units U. In some embodiments, the electronic device 1B may further include one or more first power supply lines PSL1 (only one is shown) and one or more second power supply lines PSL2. In some embodiments, the first power supply line PSL1 belongs to a first patterned conductive layer, while the second power supply line PSL2 belongs to a second patterned conductive layer, wherein the second power supply line PSL2 can be electrically connected to the first power supply line PSL1 through a plurality of vias CV.

[0049] As described above, the layout space extending along the second direction D2 (e.g., the layout space between two adjacent rows of cells U) can be wider / larger than the layout space extending along the first direction D1 (e.g., the layout space between two adjacent columns of cells U). Therefore, functional circuits or wiring requiring more space can be disposed between two adjacent rows of cells U, while functional circuits or wiring requiring less space can be disposed between two adjacent columns of cells U. For example, although in Figure 5 Not shown, gate drive circuitry (e.g., gate driver on panel (GOP) circuitry), additional power lines, additional power supply lines, ESD protection circuitry, contact pads for side-wiring or bonding to COF (Chip On Film) or FPC (Flexible Printed Circuit), other circuitry and / or wiring may be arranged in the layout space extending along the first direction D1, but are not limited thereto. For example, although in Figure 5Not shown, contact pads for side wiring or for bonding to COF (Chip On Film) or FPC (Flexible Printed Circuit) may be disposed in a layout space extending along a first direction D1 and / or a second direction D2. For example, although in Figure 5 As not shown, through glass vias (TGV) and / or through hole vias (THV) in the substrate (e.g., PI, glass, etc.) may be provided in the layout space extending along the first direction D1, in the layout space extending along the second direction D2, and / or at the corners of the pixel PX.

[0050] Please refer to Figure 6 In addition to the aforementioned multiple first main lines M1, multiple second main lines M2, multiple units U, and function lines FL, the electronic device 1C may further include a gate drive circuit GDC disposed between two adjacent rows of units U, wherein the gate drive circuit GDC is used to provide gate signals to the first circuit group GC1, the second circuit group GC2, the third circuit group GC3, and the fourth circuit group GC4. In some embodiments, such as Figure 6 As shown, the gate drive circuit GDC is located on the side of the second circuit group GC2 away from the first circuit group GC1 (e.g., the lower side).

[0051] In some embodiments, such as Figure 6 As shown, the electronic device 1C may further include a clock signal line CK disposed between two adjacent columns of cells U and electrically connected to the gate drive circuit GDC. In some embodiments, the clock signal line CK is disposed on the side (e.g., the left side) away from the plurality of first main lines M1 in the first circuit group GC1 and the second circuit group GC2. In some embodiments, the electronic device 1C may include a plurality of clock signal lines CK. In some embodiments, the clock signal line CK belongs to the first patterned conductive layer, but is not limited thereto.

[0052] By setting the clock signal line CK away from the data lines (e.g., multiple first main lines M1 and / or multiple second main lines M2), line defects (or grayscale shifts) caused by coupling between the clock signal line CK and the data lines can be reduced, thereby improving display quality.

[0053] In summary, in the embodiments of this disclosure, electronic devices with narrow bezels or even bezel-less designs can be achieved using the proposed layout design.

Claims

1. An electronic device, characterized in that, include: Multiple primary lines extend along the primary direction; Multiple first branch lines are electrically connected to the multiple first main lines and extend along a second direction perpendicular to the first direction; as well as A first circuit group, disposed on one side of the plurality of first main lines, includes: The first circuit is electrically connected to one of the plurality of first branches; as well as The second circuit is electrically connected to another of the plurality of first branches. The first circuit and the second circuit are arranged along the second direction.

2. The electronic device according to claim 1, characterized in that, Also includes: A first light-emitting unit is electrically connected to the first circuit group, wherein the first light-emitting unit is disposed on one side of the plurality of first main lines, and the first light-emitting unit and the plurality of first branch lines are disposed on opposite sides of the first circuit group.

3. The electronic device according to claim 2, characterized in that, The first light-emitting unit includes a first light-emitting element and a second light-emitting element that are electrically connected to the first circuit and the second circuit, respectively.

4. The electronic device according to claim 1, characterized in that, Also includes: The second circuit group is disposed on one side of the plurality of first main lines and includes: The third circuit is electrically connected to one of the plurality of first branches; as well as The fourth circuit is electrically connected to the other of the plurality of first branches. The plurality of first branch lines are arranged between the first circuit group and the second circuit group.

5. The electronic device according to claim 4, characterized in that, Also includes: The first light-emitting unit is electrically connected to the first circuit group; as well as The second light-emitting unit is electrically connected to the second circuit group, wherein: The first light-emitting unit and the second light-emitting unit are disposed on one side of the plurality of first main lines. The first light-emitting unit is disposed on the side of the first circuit group away from the plurality of first branches, and The second light-emitting unit is disposed on the side of the second circuit group away from the plurality of first branches.

6. The electronic device according to claim 4, characterized in that, Also includes: Multiple secondary main lines extend along the first direction; Multiple second branch lines are electrically connected to the multiple second main lines and extend along the second direction; as well as The third circuit group is disposed on the side of the plurality of second main lines away from the plurality of first main lines and includes: The fifth circuit is electrically connected to one of the plurality of second branches; as well as The sixth circuit is electrically connected to another of the plurality of second branches. The plurality of first main lines and the plurality of second main lines are disposed between the first circuit group and the third circuit group.

7. The electronic device according to claim 6, characterized in that, Also includes: A fourth circuit group, disposed on the side of the plurality of second main lines away from the plurality of first main lines, includes: The seventh circuit is electrically connected to one of the plurality of second branches; as well as The eighth circuit is electrically connected to the other of the plurality of second branches. The plurality of second branch lines are disposed between the third circuit group and the fourth circuit group, and the plurality of first main lines and the plurality of second main lines are also disposed between the second circuit group and the fourth circuit group.

8. The electronic device according to claim 7, characterized in that, Also includes: The first light-emitting unit is electrically connected to the first circuit group; The second light-emitting unit is electrically connected to the second circuit group; The third light-emitting unit is electrically connected to the third circuit group; as well as The fourth light-emitting unit is electrically connected to the fourth circuit group, wherein: The first light-emitting unit and the second light-emitting unit are disposed on one side of the plurality of first main lines. The first light-emitting unit is located on the side of the first circuit group away from the plurality of first branches. The second light-emitting unit is disposed on the side of the second circuit group away from the plurality of first branches. The third light-emitting unit and the fourth light-emitting unit are disposed on the side of the plurality of second main lines away from the plurality of first main lines. The third light-emitting unit is disposed on the side of the third circuit group away from the plurality of second branches, and The fourth light-emitting unit is located on the side of the fourth circuit group away from the plurality of second branches.

9. The electronic device according to claim 8, characterized in that, Also includes: Multiple units are arranged in an array along the first direction and the second direction, wherein each of the multiple units includes the multiple first branches, the first circuit group, the second circuit group, the multiple second branches, the third circuit group, the fourth circuit group, the first light-emitting unit, the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit.

10. The electronic device according to claim 9, characterized in that, The distance between two adjacent units arranged along the first direction is greater than the distance between two adjacent units arranged along the second direction.

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