Micro LED structure and preparation method thereof

Abstract

The application provides a Micro LED structure and a preparation method thereof, and relates to the technical field of display chips.The Micro LED structure comprises a plurality of array-distributed light-emitting units and a metal isolation layer.Each light-emitting unit comprises a transparent conductive layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer.The second semiconductor layer, the light-emitting layer and the first semiconductor layer are sequentially stacked.The roughened surface is formed on the side of the first semiconductor layer away from the second semiconductor layer.The transparent conductive layer is located on the roughened surface of the first semiconductor layer.The metal isolation layer is arranged between adjacent light-emitting units and is electrically connected with part or all of the first semiconductor layers of the adjacent light-emitting units.The metal isolation layer is electrically connected with the transparent conductive layer.Compared with the prior art, the application can isolate light crosstalk, improve current expansion and light extraction efficiency, realize uniform light emission and meet the performance requirements of ultra-high-resolution display.

Description

Technical Field

[0001] This invention relates to the field of display chip technology, and more specifically, to a Micro LED structure and its fabrication method. Background Technology

[0002] Micro LED is the core technology for next-generation ultra-high-definition displays, with broad application prospects in fields such as AR / VR and high-end commercial displays. However, the industrialization of micron-level chips is severely restricted by core bottlenecks such as insufficient light output efficiency, pixel crosstalk, and poor current expansion performance.

[0003] Traditional Micro LEDs have low light extraction efficiency. At the same time, they suffer from severe crosstalk between pixels, and insufficient current expansion can lead to uneven light emission and reduced efficiency, further exacerbating crosstalk and failing to meet the performance requirements of ultra-high resolution displays. Summary of the Invention

[0004] The purpose of this invention is to provide a Micro LED structure and its fabrication method, which can effectively isolate light crosstalk between light-emitting units, improve current spread and light extraction efficiency, and achieve uniform light emission, thereby meeting the performance requirements of ultra-high resolution displays.

[0005] The embodiments of the present invention are implemented through the following scheme: This invention provides a Micro LED structure, comprising: In one aspect, embodiments of the present invention provide a Micro LED structure, comprising: Multiple array-distributed light-emitting units, each light-emitting unit includes a transparent conductive layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the second semiconductor layer, the light-emitting layer and the first semiconductor layer are stacked sequentially, the side of the first semiconductor layer away from the second semiconductor layer is roughened to form a roughened surface, and the transparent conductive layer is located on the roughened surface of the first semiconductor layer; A metal isolation layer is disposed between adjacent light-emitting units and electrically connected to part or all of the first semiconductor layer of the adjacent light-emitting units, and the metal isolation layer is electrically connected to the transparent conductive layer.

[0006] In an optional embodiment, a conductive contact layer for forming an ohmic contact and / or reducing contact resistance is formed between the metal isolation layer and the first semiconductor layer.

[0007] In an optional embodiment, the conductive contact layer includes at least one of a metal layer, a conductive oxide layer, a semiconductor contact layer, and a composite conductive layer.

[0008] In an optional embodiment, a reflector cup and a passivation layer are also included, wherein the reflector cup is located between every two adjacent light-emitting units, and the passivation layer is located between the reflector cup and the light-emitting unit and provides electrical isolation between the reflector cup and the light-emitting unit.

[0009] In an optional embodiment, it further includes an ohmic contact layer, a reflective layer, a leveling layer, and an electrode transition layer, wherein the ohmic contact layer, the reflective layer, and the electrode transition layer are sequentially bonded together to form an electrical connection; the leveling layer is used to fill the gap between each two adjacent light-emitting units and to electrically isolate the reflective cup and the electrode transition layer.

[0010] In an optional embodiment, the device further includes a driving wafer and a hybrid bonding layer, the driving wafer having metal contacts, the hybrid bonding layer having conductive pillars, the metal contacts being electrically connected to the conductive pillars, and the conductive pillars being electrically connected to the electrode transition layer.

[0011] In an optional embodiment, the second semiconductor layer comprises P-type doped GaN, and the first semiconductor layer comprises N-type doped GaN.

[0012] In an optional embodiment, the second semiconductor layer comprises N-type doped GaN, and the first semiconductor layer comprises P-type doped GaN.

[0013] In an optional embodiment, the reflective layer and the reflective cup are at least one of Ni, Ag, Ti, and Au.

[0014] In an optional embodiment, the passivation layer comprises a first insulating layer and a second insulating layer deposited sequentially.

[0015] In an optional embodiment, the first insulating layer comprises Al2O3, the second insulating layer comprises SiO2, and the leveling layer comprises SiO2.

[0016] In another aspect, embodiments of the present invention provide a method for fabricating a Micro LED structure, the method comprising: A substrate with an epitaxial layer is provided, wherein the epitaxial layer includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially stacked on the substrate; An ohmic contact layer is formed on the second semiconductor layer, and then the second semiconductor layer is etched to form a trench that penetrates the second semiconductor layer and the light-emitting layer and extends at least partially to the first semiconductor layer. A reflective layer is formed on the ohmic contact layer; A passivation layer is formed on the surface of the second semiconductor layer, wherein the passivation layer covers the sidewalls of the second semiconductor layer and covers the ohmic contact layer; A reflective cup is formed on the passivation layer, and an avoidance opening is formed therein; A leveling layer is formed on the passivation layer, and then CMP is performed on the side of the leveling layer away from the passivation layer; An electrode transition layer is formed by etching and filling the side of the reflective layer away from the ohmic contact layer, wherein the electrode transition layer penetrates the passivation layer and the leveling layer and is electrically connected to the reflective layer. A hybrid bonding layer is formed on one side of the driving wafer with metal contacts, and then a connecting trench is formed on the hybrid bonding layer that penetrates the hybrid bonding layer and reaches the surface of the driving wafer, and then a conductive pillar is filled in the connecting trench; The hybrid bonding layer on the driving wafer is bonded to the side of the leveling layer away from the first semiconductor layer by hybrid bonding, wherein the metal contacts of the driving wafer are electrically connected to the conductive pillars of the hybrid bonding layer, and the conductive pillars are electrically connected to the electrode transition layer. Remove the substrate to expose the first semiconductor layer; The surface of the first semiconductor layer is roughened. An isolation trench is formed by etching the first semiconductor layer, wherein the isolation trench exposes the passivation layer; A transparent conductive layer is formed on the surface of the first semiconductor layer; A metal isolation layer is formed in the isolation trench, wherein the metal isolation layer is bonded to the sidewall of the first semiconductor layer and electrically connected to the transparent conductive layer.

[0017] In an optional embodiment, after the step of roughening the surface of the first semiconductor layer, the method further includes: A transparent conductive layer is formed on the surface of the first semiconductor layer, and then the transparent conductive layer and the first semiconductor layer are etched to form an isolation trench, wherein the isolation trench exposes the passivation layer; A metal isolation layer is formed in the isolation trench, wherein the metal isolation layer is bonded to the sidewall of the first semiconductor layer and electrically connected to the transparent conductive layer. The beneficial effects of this embodiment of the invention include: This invention provides a Micro LED structure and its fabrication method, employing multiple arrayed light-emitting units. In each light-emitting unit, a first semiconductor layer is disposed on a light-emitting layer, the light-emitting layer is disposed on a second semiconductor layer, an ohmic contact layer is located on the bottom side of the second semiconductor layer, and a metal isolation layer is disposed between adjacent light-emitting units and electrically connected to part or all of the first semiconductor layer of the adjacent light-emitting units. The metal isolation layer is also electrically connected to a transparent conductive layer. Furthermore, the side of the first semiconductor layer away from the second semiconductor layer is roughened to form a roughened surface, and the transparent conductive layer is located on the roughened surface of the first semiconductor layer.

[0018] Compared to existing technologies, this invention uses a metal isolation layer to block adjacent light-emitting units, thereby isolating light crosstalk, improving current spread, and achieving uniform light emission, which can meet the performance requirements of ultra-high resolution displays. Furthermore, by roughening the first semiconductor layer to obtain a roughened surface, controllable micro-nano-level bumps or array structures are formed on the surface, breaking the limitations of total internal reflection within the chip and significantly improving light extraction efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a Micro LED structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the method for fabricating the Micro LED structure provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the method for fabricating the Micro LED structure provided in the embodiment of the present invention; Figure 7This is a schematic diagram of the structure corresponding to step S6 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 10 This is a schematic diagram of the structure corresponding to step S9 in the method for fabricating a Micro LED structure provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the structure corresponding to step S10 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 12 This is a schematic diagram of the structure corresponding to step S11 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 13 This is a schematic diagram of the structure corresponding to step S12 in the fabrication method of the Micro LED structure provided in the embodiment of the present invention. Figure 14 This is a schematic diagram of the structure corresponding to step S13 in the method for fabricating a Micro LED structure provided in an embodiment of the present invention.

[0021] Icons: 100 - Micro LED structure; 110 - Light-emitting unit; 111 - First semiconductor layer; 112 - Second semiconductor layer; 113 - Light-emitting layer; 114 - Ohmic contact layer; 115 - Transparent conductive layer; 116 - Roughened surface; 117 - Conductive contact layer; 120 - Leveling layer; 130 - Electrode transition layer; 140 - Driving wafer; 141 - Metal contact; 150 - Metal isolation layer; 151 - Isolation trench; 160 - Hybrid bonding layer; 161 - Conductive pillar; 170 - Reflective layer; 180 - Reflector cup; 181 - Avoidance opening; 190 - Passivation layer; 200 - Substrate. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] As disclosed in the background section, traditional Micro LEDs have low light extraction efficiency, and the lack of individual light-blocking structures between pixels leads to severe crosstalk between pixels. Furthermore, insufficient current spreading easily results in uneven light emission and reduced efficiency, further exacerbating the crosstalk problem and making it impossible to meet the performance requirements of ultra-high resolution displays.

[0028] Furthermore, the light-emitting surface of traditional Micro LEDs is a planar structure, and total internal reflection is prone to occur inside the light-emitting unit 110, causing some light to be reflected back into the light-emitting unit 110, resulting in low light extraction efficiency and thus affecting the light emission efficiency.

[0029] To address the aforementioned issues, this invention provides a Micro LED structure 100 and its fabrication method. It should be noted that, unless otherwise specified, the features in the embodiments of this invention can be combined with each other.

[0030] See Figure 1 This invention provides a Micro LED structure 100 that effectively isolates light crosstalk between light-emitting units 110, improves current spread and light extraction efficiency, and achieves uniform light emission, thus meeting the performance requirements of ultra-high resolution displays. Simultaneously, it significantly improves the light extraction efficiency of the light-emitting surface, thereby enhancing the light extraction efficiency.

[0031] The Micro LED structure 100 provided in this embodiment of the invention includes a plurality of arrayed light-emitting units 110 and a metal isolation layer 150. Each light-emitting unit 110 includes a transparent conductive layer 115, a first semiconductor layer 111, a light-emitting layer 113, and a second semiconductor layer 112. The second semiconductor layer 112, the light-emitting layer 113, and the first semiconductor layer 111 are stacked sequentially. The side of the first semiconductor layer 111 away from the second semiconductor layer 112 is roughened to form a roughened surface 116, and the transparent conductive layer 115 is located on the roughened surface 116 of the first semiconductor layer 111. The metal isolation layer 150 is disposed between adjacent light-emitting units 110 and electrically connected to part or all of the first semiconductor layer 111 of the adjacent light-emitting unit 110, and the metal isolation layer 150 is electrically connected to the transparent conductive layer 115.

[0032] It should be noted that the metal isolation layer 150 is used here to block the light-emitting units 110, thereby isolating light crosstalk, improving current spread, and achieving uniform light emission, which can meet the performance requirements of ultra-high resolution displays. In addition, the surface of the first semiconductor layer 111 can be treated by a roughening process, that is, the surface of the first semiconductor layer 111 can be modified by physical or chemical methods to form a controllable micro-nano-level bump or array structure on the surface, thereby breaking the limitation of total internal reflection inside the chip and significantly improving light extraction efficiency.

[0033] In some embodiments, a conductive contact layer 117 for forming an ohmic contact and / or reducing contact resistance is formed between the metal isolation layer 150 and the first semiconductor layer 111. Specifically, the conductive contact layer 117 includes at least one of a metal layer, a conductive oxide layer, a semiconductor contact layer, and a composite conductive layer.

[0034] In some embodiments, the Micro LED structure 100 further includes a reflector 180 and a passivation layer 190. The reflector 180 is located between every two adjacent light-emitting units 110, and the passivation layer 190 is located between the reflector 180 and the light-emitting units 110 and provides electrical isolation between the reflector 180 and the light-emitting units 110.

[0035] Furthermore, the Micro LED structure 100 also includes an ohmic contact layer 114, a reflective layer 170, a leveling layer 120, and an electrode transition layer 130. The ohmic contact layer 114, the reflective layer 170, and the electrode transition layer 130 are sequentially bonded together to form an electrical connection. The leveling layer 120 is used to fill the gap between each two adjacent light-emitting units 110 and to electrically isolate the reflector cup 180 and the electrode transition layer 130.

[0036] It should be noted that the reflective layer 170 and reflective cup 180 can be arranged around the light-emitting unit 110 to form a cup-shaped structure, and block and reflect the light emitted from the backlight side and the side, so that all light except the light-emitting surface can be reflected inward and finally emitted from the light-emitting surface, which greatly improves the light emission efficiency.

[0037] It is worth noting that the reflector cup 180 has a clearance opening 181. The width of the electrode transition layer 130 is smaller than the width of the clearance opening 181, the width of the clearance opening 181 is smaller than the width of the reflective layer 170, and the width of the reflective layer 170 is smaller than the width of the ohmic contact layer 114. For example, the width of the electrode transition layer 130 can be 0.8 μm, the width of the clearance opening 181 can be 1.2 μm, the width of the reflective layer 170 can be 1.3 μm, and the width of the ohmic contact layer 114 can be 1.7 μm. Of course, the width data of the electrode transition layer 130, the clearance opening 181, the reflective layer 170, and the ohmic contact layer 114 are merely illustrative examples and do not constitute any limitation. The electrode transition layer 130 is located in the clearance opening 181 and can form electrical isolation with the reflector cup 180 by spacing it apart, which can prevent the reflector cup 180 from being affected during the grooving process. The width of the reflective layer 170 is greater than the width of the avoidance opening 181, so that the reflective layer 170 and the reflective cup 180 form a complete cup-shaped structure, preventing light from escaping from the edges and ensuring the reflective effect of the reflective layer 170 and the reflective cup 180.

[0038] The ohmic contact layer 114 and the transparent conductive layer 115 are both transparent conductive films of ITO (Indium Tin Oxide), which can efficiently diffuse current from the metal electrode to the entire chip area, while ensuring that the light emitted by the light-emitting unit 110 is emitted smoothly.

[0039] It should also be noted that the surface of the first semiconductor layer 111 furthest from the second semiconductor layer 112 serves as the light-emitting surface, emitting light outwards. Its light-emitting principle can be referenced from existing Micro LEDs. The metal isolation layer 150 is located between adjacent first semiconductor layers 111 and extends towards the light-emitting direction, effectively achieving a light-blocking effect between adjacent first semiconductor layers 111, thereby effectively isolating light crosstalk between the light-emitting units 110. Furthermore, in conjunction with the ITO layer, it can enhance current diffusion, achieve uniform light emission, and thus meet the performance requirements of ultra-high resolution displays.

[0040] In some embodiments, the Micro LED structure 100 further includes a driving wafer 140 and a hybrid bonding layer 160. The driving wafer 140 has metal contacts 141, and the hybrid bonding layer 160 has conductive pillars 161. The metal contacts 141 are electrically connected to the conductive pillars 161, and the conductive pillars 161 are electrically connected to the electrode transition layer 130. Specifically, both the electrode transition layer 130 and the conductive pillars 161 can be copper layers. Through a hybrid bonding process, a Cu-Cu weld is formed between the electrode transition layer 130 and the conductive pillars 161. Simultaneously, a dielectric bond is achieved between the leveling layer 120 and the hybrid bonding layer 160, providing mechanical support and electrical isolation.

[0041] In some embodiments, the second semiconductor layer 112 comprises P-type doped GaN, and the first semiconductor layer 111 comprises N-type doped GaN. Alternatively, the first semiconductor layer 111 and the second semiconductor layer 112 can also be other types of N-type and P-type semiconductors, such as ZnSe, ZnO, AlN, InN, InGaN, GaP, AlInGaP, or AlGaAs.

[0042] In some embodiments, the reflective layer 170 and the reflector cup 180 are at least one of Ni, Ag, Ti, and Au. The reflective layer 170 is preferably a composite layer of Ni, Ag, and Ti, with thicknesses of 1 nm, 100 nm, and 10 nm for Ni, Ag, and Ti, respectively. The reflective layer 170 reflects light from the backlight side towards the light-emitting side, thereby improving light extraction efficiency. The reflector cup 180 is preferably a composite layer of Ni, Ag, and Ti, with thicknesses of 1 nm, 100 nm, and 10 nm for Ni, Ag, and Ti, respectively. The reflector cup 180 reflects light from the side towards the outside inwards, thereby improving light extraction efficiency.

[0043] In some embodiments, the passivation layer 190 includes a first insulating layer (not shown) and a second insulating layer (not shown) deposited sequentially, wherein the thickness of the first insulating layer is less than the thickness of the second insulating layer. Specifically, both the first and second insulating layers are insulating dielectric materials, such as SiO2, Si3N4, or Al2O3. Preferably, the first insulating layer includes Al2O3, the second insulating layer includes SiO2, and the leveling layer 120 includes SiO2. By using insulating materials, electrical isolation between adjacent light-emitting units 110 can be effectively achieved, avoiding leakage current.

[0044] It should be noted that the first insulating layer (Al2O3) can be deposited using ALD (Atomic Layer Deposition) technology, and the second insulating layer (SiO2) can be deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition) technology. Preferably, the thickness of the first insulating layer can be 40 nm, and the thickness of the second insulating layer can be 200 nm. These two insulating layers further ensure electrical isolation and guarantee the complete coverage of the sidewalls of the second semiconductor layer 112.

[0045] This invention also provides a method for fabricating a Micro LED structure 100, which includes the following steps: S1: Provide a substrate 200 with an epitaxial layer.

[0046] See also Figure 2 The epitaxial layer includes a first semiconductor layer 111, a light-emitting layer 113, and a second semiconductor layer 112, which are sequentially stacked on the substrate 200. The first semiconductor layer 111 is N-GaN, the second semiconductor layer 112 is P-GaN, and the light-emitting layer 113 is located between the first semiconductor layer 111 and the second semiconductor layer 112.

[0047] S2: An ohmic contact layer 114 is formed on the second semiconductor layer 112, and then the second semiconductor layer 112 is etched to form a trench.

[0048] See also Figure 3 The trench penetrates the second semiconductor layer 112 and the light-emitting layer 113, and extends at least partially to the first semiconductor layer 111. Specifically, an ohmic contact layer 114 can be first deposited on the surface of the second semiconductor layer 112 to form a trench. Then, the second semiconductor layer 112 is etched using a MESA (mesa etching) process to form a trench on the second semiconductor layer 112, separating it into multiple trapezoidal steps, while retaining the ohmic contact layer 114 on the second semiconductor layer 112. During etching, the first semiconductor layer 111 can be used as an etching stop layer, and finally, sidewall cleaning is performed.

[0049] S3: A reflective layer 170 is formed on the ohmic contact layer 114.

[0050] See Figure 4Specifically, the reflective layer 170 can be formed by a lift-off process, wherein the reflective layer 170 is a composite layer of Ni, Ag and Ti, and the thicknesses of Ni, Ag and Ti are 1 nm, 100 nm and 10 nm, respectively. Preferably, the width of the ohmic contact layer 114 is 1.7 μm and the width of the reflective layer 170 is 1.3 μm.

[0051] S4: A passivation layer 190 is formed on the surface of the second semiconductor layer 112.

[0052] See also Figure 5 The passivation layer 190 covers the sidewalls of the second semiconductor layer 112 and the ohmic contact layer 114. Specifically, an Al2O3 layer can be deposited first using an ALD process to form a first insulating layer, and then a SiO2 layer can be deposited using a PECVD process to form a second insulating layer. The thickness of the first insulating layer can be 40 nm, and the thickness of the second insulating layer can be 200 nm. Of course, the first and second insulating layers can also be made of the same material.

[0053] S5: A reflective cup 180 is formed on the passivation layer 190, and an avoidance opening 181 is formed thereon.

[0054] See Figure 6 The reflector cup 180 covers the surface of the passivation layer 190 and has an avoidance opening 181. Specifically, the reflector cup 180 is formed by a lift-off process (peeling process). The reflector cup 180 has a cup-shaped structure and has an avoidance opening 181. The width of the avoidance opening 181 is preferably 1.2 μm.

[0055] S6: A leveling layer 120 is formed on the passivation layer 190, and then CMP is performed on the side of the leveling layer 120 away from the passivation layer 190.

[0056] See Figure 7 The leveling layer 120 covers the passivation layer 190. Specifically, a 2μm thick SiO2 layer can be deposited by PECVD process to form the leveling layer 120. Then, the leveling layer 120 is polished by CMP (Chemical Mechanical Planarization) process until the remaining thickness is 0.8μm. At this time, the leveling layer 120 can cover the entire light-emitting unit 110.

[0057] S7: An electrode transition layer 130 is formed on the side of the reflective layer 170 away from the ohmic contact layer 114.

[0058] See Figure 8The electrode transition layer 130 penetrates the passivation layer 190 and the leveling layer 120 and is electrically connected to the reflective layer 170. Specifically, an opening can first be made in the leveling layer 120 using an etching process. This opening is aligned with the reflective layer 170, and the opening width is 0.8 μm. The reflective layer 170 can serve as an etching stop layer. In actual etching, a 1 μm depth of SiO2 can be etched first, followed by a 40 nm depth of Al2O3, until the reflective layer 170 is exposed. Then, the electrode transition layer 130 is formed using an electroplating process or a metal sputtering process. This electrode transition layer 130 can be a copper layer. Finally, the excess copper layer is removed again using a CMP process.

[0059] S8: A hybrid bonding layer 160 is formed on one side of the driving wafer 140 with metal contacts 141, and then a connecting trench is formed on the hybrid bonding layer 160 that penetrates the hybrid bonding layer and reaches the surface of the driving wafer 140, and then conductive pillars 161 are filled in the connecting trench.

[0060] See Figure 9 Specifically, the hybrid bonding layer 160 and conductive pillars 161 can be fabricated in advance on the driving wafer 140, so that the metal contacts 141 are electrically connected to the conductive pillars 161.

[0061] S9: The hybrid bonding layer 160 on the driving wafer 140 is bonded to the side of the leveling layer 120 away from the first semiconductor layer 111 by hybrid bonding.

[0062] See Figure 10 The metal contacts 141 of the driving wafer 140 are electrically connected to the conductive pillars 161 of the hybrid bonding layer 160, and the conductive pillars 161 are electrically connected to the electrode transition layer 130. Specifically, the electrode transition layer 130 and the conductive pillars 161 are connected through the hybrid bonding layer 160 via a hybrid bonding process. Both the electrode transition layer 130 and the conductive pillars 161 can be copper layers, and a Cu-Cu weld is formed between them through the hybrid bonding process. Simultaneously, the leveling layer 120 and the hybrid bonding layer 160 are dielectrically bonded, providing mechanical support and electrical isolation. Of course, in other preferred embodiments of the present invention, the electrode transition layer 130 and the conductive pillars 161 can also be other metallic materials, such as gold or aluminum. Furthermore, the electrode transition layer 130 and the conductive pillars 161 can also be made of different metallic materials.

[0063] S10: Remove substrate 200 and expose first semiconductor layer 111.

[0064] See Figure 11 Specifically, the substrate 200 is peeled off by a debonding process and residual adhesive is removed by a cleaning solution.

[0065] S11: Roughen the surface of the first semiconductor layer 111.

[0066] See Figure 12 Specifically, the surface of the N-type doped GaN semiconductor layer is modified by physical or chemical methods to form a roughened surface 116, and a controllable micro-nano-level concave-nano structure or array structure is formed on the surface to break the limitation of total internal reflection inside the chip and significantly improve the light extraction efficiency.

[0067] S12: Isolation trench 151 is formed by etching the first semiconductor layer 111.

[0068] See Figure 13 The isolation trench 151 exposes the passivation layer 190. Specifically, the isolation trench 151 is formed by etching the first semiconductor layer 111. The isolation trench 151 corresponds to the gap of the adjacent second semiconductor layer 112, thereby separating the first semiconductor layer 111 and forming the light-emitting unit 110 corresponding to the first semiconductor layer 111 and the second semiconductor layer 112. During etching, the passivation layer 190 can be used as an etching stop layer, and the isolation trench 151 can expose the underlying passivation layer 190 and the reflector cup 180.

[0069] S13: A transparent conductive layer 115 is formed on the surface of the first semiconductor layer 111.

[0070] See Figure 14 Specifically, a transparent conductive layer 115 can be formed on the surface of the roughened first semiconductor layer 111 through a coating process.

[0071] In other preferred embodiments of the present invention, a transparent conductive layer 115 may be formed first on the surface of the first semiconductor layer 111, and then an isolation trench 151 may be formed by etching the transparent conductive layer 115 and the first semiconductor layer 111, wherein the isolation trench 151 exposes the passivation layer 190, and finally a metal isolation layer 150 is formed in the isolation trench 151, wherein the metal isolation layer 150 is bonded to the sidewall of the first semiconductor layer 111 and electrically connected to the transparent conductive layer 115.

[0072] S14: A metal isolation layer 150 is formed in the isolation groove 151.

[0073] Please continue reading Figure 1The metal isolation layer 150 is bonded to the sidewall of the first semiconductor layer 111 and electrically connected to the transparent conductive layer 115. The metal isolation layer 150 is bonded to the passivation layer 190, and the sidewall of the metal isolation layer 150 is bonded to the sidewall of the first semiconductor layer 111 to isolate optical crosstalk between adjacent light-emitting units 110. Specifically, the metal isolation layer 150 can be a copper layer, formed by electroplating or sputtering processes. Furthermore, the bonding of the metal isolation layer 150 to the sidewall of the first semiconductor layer 111 allows the transparent conductive layer 115 to contact the metal isolation layer 150, achieving external electrical connection.

[0074] In summary, this invention provides a Micro LED structure 100 and its fabrication method, employing multiple arrayed light-emitting units 110. In each light-emitting unit 110, a first semiconductor layer 111 is disposed on a light-emitting layer 113, the light-emitting layer 113 is disposed on a second semiconductor layer 112, an ohmic contact layer 114 is located on the bottom side of the second semiconductor layer 112, and a metal isolation layer 150 is disposed between adjacent light-emitting units 110 and electrically connected to part or all of the first semiconductor layer 111 of the adjacent light-emitting units 110. The metal isolation layer 150 is also electrically connected to a transparent conductive layer 115. Furthermore, the side of the first semiconductor layer 111 away from the second semiconductor layer 112 is roughened to form a roughened surface 116, and the transparent conductive layer 115 is located on the roughened surface 116 of the first semiconductor layer 111. Compared to the prior art, this invention uses the metal isolation layer 150 to achieve shielding between adjacent light-emitting units 110, thereby isolating light crosstalk, improving current spread, and achieving uniform light emission, which can meet the performance requirements of ultra-high resolution displays. Furthermore, by roughening the first semiconductor layer 111 to obtain a roughened surface 116, a controllable micro-nano level concave-nano structure or array structure is formed on the surface, thereby breaking the limitation of total internal reflection inside the chip and significantly improving the light extraction efficiency.

[0075] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A Micro LED structure, characterized in that, include: Multiple array-distributed light-emitting units, each light-emitting unit includes a transparent conductive layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer, the second semiconductor layer, the light-emitting layer and the first semiconductor layer are stacked sequentially, the side of the first semiconductor layer away from the second semiconductor layer is roughened to form a roughened surface, and the transparent conductive layer is located on the roughened surface of the first semiconductor layer; A metal isolation layer is disposed between adjacent light-emitting units and electrically connected to part or all of the first semiconductor layer of the adjacent light-emitting units, and the metal isolation layer is electrically connected to the transparent conductive layer.

2. The Micro LED structure according to claim 1, characterized in that, A conductive contact layer is formed between the metal isolation layer and the first semiconductor layer to form an ohmic contact and / or reduce contact resistance.

3. The Micro LED structure according to claim 2, characterized in that, The conductive contact layer includes at least one of a metal layer, a conductive oxide layer, a semiconductor contact layer, and a composite conductive layer.

4. The Micro LED structure according to claim 1, characterized in that, It also includes a reflector cup and a passivation layer, wherein the reflector cup is located between every two adjacent light-emitting units, and the passivation layer is located between the reflector cup and the light-emitting unit and provides electrical isolation between the reflector cup and the light-emitting unit.

5. The Micro LED structure according to claim 4, characterized in that, It also includes an ohmic contact layer, a reflective layer, a leveling layer, and an electrode transition layer, wherein the ohmic contact layer, the reflective layer, and the electrode transition layer are sequentially bonded together to form an electrical connection; the leveling layer is used to fill the gap between each two adjacent light-emitting units and to electrically isolate the reflective cup and the electrode transition layer.

6. The Micro LED structure according to claim 5, characterized in that, It also includes a driving wafer and a hybrid bonding layer, the driving wafer having metal contacts, the hybrid bonding layer having conductive pillars, the metal contacts being electrically connected to the conductive pillars, and the conductive pillars being electrically connected to the electrode transition layer.

7. The Micro LED structure according to claim 6, characterized in that, The second semiconductor layer comprises P-type doped GaN, and the first semiconductor layer comprises N-type doped GaN.

8. The Micro LED structure according to claim 6, characterized in that, The second semiconductor layer comprises N-type doped GaN, and the first semiconductor layer comprises P-type doped GaN.

9. The Micro LED structure according to claim 8, characterized in that, The reflective layer and the reflective cup are at least one of Ni, Ag, Ti, and Au.

10. The Micro LED structure according to claim 5, characterized in that, The passivation layer comprises a first insulating layer and a second insulating layer deposited sequentially.

11. The Micro LED structure according to claim 10, characterized in that, The first insulating layer comprises Al2O3, the second insulating layer comprises SiO2, and the leveling layer comprises SiO2.

12. A method for fabricating a Micro LED structure, used to fabricate the Micro LED structure as described in claim 1, characterized in that, The method includes: A substrate with an epitaxial layer is provided, wherein the epitaxial layer includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially stacked on the substrate; An ohmic contact layer is formed on the second semiconductor layer, and then the second semiconductor layer is etched to form a trench. The trench penetrates the second semiconductor layer and the light-emitting layer, and extends at least partially to the first semiconductor layer. A reflective layer is formed on the ohmic contact layer; A passivation layer is formed on the surface of the second semiconductor layer, wherein the passivation layer covers the sidewalls of the second semiconductor layer and covers the ohmic contact layer; A reflective cup is formed on the passivation layer, and an avoidance opening is formed therein; A leveling layer is formed on the passivation layer, and then CMP is performed on the side of the leveling layer away from the passivation layer; An electrode transition layer is formed by etching and filling the side of the reflective layer away from the ohmic contact layer, wherein the electrode transition layer penetrates the passivation layer and the leveling layer and forms an electrical connection with the reflective layer. A hybrid bonding layer is formed on the side of the driver wafer with metal contacts, and then a connecting trench is formed on the hybrid bonding layer that penetrates the hybrid bonding layer and reaches the driver wafer. Then, conductive pillars are filled in the connecting trench. The hybrid bonding layer on the driving wafer is bonded to the side of the leveling layer away from the first semiconductor layer by hybrid bonding, wherein the metal contacts of the driving wafer are electrically connected to the conductive pillars of the hybrid bonding layer, and the conductive pillars are electrically connected to the electrode transition layer. Remove the substrate to expose the first semiconductor layer; The surface of the first semiconductor layer is roughened. An isolation trench is formed by etching the first semiconductor layer, wherein the isolation trench exposes the passivation layer; A transparent conductive layer is formed on the surface of the first semiconductor layer; A metal isolation layer is formed in the isolation trench, wherein the metal isolation layer is bonded to the sidewall of the first semiconductor layer and electrically connected to the transparent conductive layer.

13. The method for fabricating a Micro LED structure according to claim 11, characterized in that, After the roughening process of the surface of the first semiconductor layer, the method further includes: A transparent conductive layer is formed on the surface of the first semiconductor layer, and then the transparent conductive layer and the first semiconductor layer are etched to form an isolation trench, wherein the isolation trench exposes the passivation layer; A metal isolation layer is formed in the isolation trench, wherein the metal isolation layer is bonded to the sidewall of the first semiconductor layer and electrically connected to the transparent conductive layer.

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