Display panel and electronic device

Abstract

Embodiments of the present application provide a display panel and an electronic device, and relate to the technical field of display. In the display panel, the over-etching can be blocked by the protection layer arranged below the pixel definition layer, so as to avoid forming an excessively high step at the edge position of the pixel definition layer. Even if the touch wiring passes through the edge position of the pixel definition layer, the adjacent touch wirings cannot be disconnected due to the excessively high step at the edge position, and the short circuit situation does not occur. That is, the above-mentioned scheme provided by the embodiments can insulate the adjacent touch wirings from each other, so as to ensure that the display panel has good touch performance.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and an electronic device. Background Technology

[0002] Organic Light Emitting Diode (OLED) is considered the next-generation display technology after liquid crystal display (LCD). Due to its superior color and image quality, it is widely used in various consumer electronics products such as smartphones, televisions, laptops, desktop computers, automotive displays, and wearable devices, becoming the mainstream technology in display panels. In traditional display panel manufacturing, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision, high development costs, and long development cycles. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance aspects, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN 118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A describe relevant content on the technology of non-fine metal mask, for reference.

[0003] However, the current manufacturing process of OLED display products still needs further improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a display panel and an electronic device.

[0005] A first aspect of this application provides a display panel having a display area and a non-display area surrounding the display area, the non-display area including a border area and a bonding area located on the side of the border area away from the display area, the display panel comprising:

[0006] substrate;

[0007] A protective layer is located on the display area and the border area on the substrate;

[0008] A pixel defining layer is located on the side of the protective layer away from the substrate, and in the display area, the pixel defining layer includes pixel openings;

[0009] An isolation structure is located on the side of the pixel defining layer away from the substrate. In the display area, the isolation structure includes an isolation opening, wherein the isolation opening communicates with the pixel opening.

[0010] The light-emitting device is at least partially located within the pixel opening;

[0011] The touch trace is located on the side of the light-emitting device away from the substrate, and extends from the display area and the border area to the bonding area;

[0012] In the border area near the bonding area, the display panel includes bonding traces located at least in the bonding area, the touch traces are electrically connected to the bonding traces, and the orthographic projection outline of the pixel defining layer on the substrate is located within the orthographic projection of the protective layer on the substrate.

[0013] In one possible implementation of this application, the material of the protective layer includes an etching-resistant inorganic material;

[0014] Preferably, the material of the protective layer includes at least one of silicon nitride and silicon oxide.

[0015] In one possible implementation of this application, the thickness of the protective layer is 100 angstroms to 20,000 angstroms in a plane perpendicular to the substrate.

[0016] In one possible implementation of this application, in the border area near the bonding area, the orthographic projection of the touch trace on the substrate is located within the orthographic projection of the pixel defining layer on the substrate;

[0017] Preferably, an insulating structure layer is provided between the touch trace and the bonding trace, and the touch trace is connected to the bonding trace through a film via located in the insulating structure layer, wherein the orthographic projection of the film via on the substrate is located within the orthographic projection of the pixel defining layer on the substrate.

[0018] In one possible implementation of this application, the membrane via is located at the intersection of the touch trace and the bonding trace;

[0019] The substrate includes a substrate, a plurality of stacked conductive layers on the substrate, and an insulating layer between adjacent conductive layers. The bonding traces are formed by conductive layers on the side of the substrate away from the substrate. The insulating structure layer includes a planarization layer and a pixel delimitation layer between the bonding traces and the touch traces.

[0020] The vias in the film layer include interconnected planarization layer vias and pixel defining layer vias, and the touch traces are connected to the bonding traces through the pixel defining layer vias and the planarization layer vias.

[0021] Preferably, the planarization layer is an organic planarization layer.

[0022] In one possible implementation of this application, in the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate overlaps with the orthographic projection of the bonding trace on the substrate.

[0023] In one possible implementation of this application, the substrate includes a dam surrounding the periphery of the display area and located in the border area;

[0024] In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate lies within the orthographic projection of the dam on the substrate.

[0025] In one possible implementation of this application, the substrate includes a plurality of dikes, and the plurality of dikes are arranged sequentially in the border area along a direction away from the display area;

[0026] The orthographic projection outline of the pixel defining layer on the substrate is located within the orthographic projection of the dam on the substrate on the side closer to the bonding area.

[0027] Preferably, the angle between the side of the cofferdam closest to the bonding area and the bottom surface of the cofferdam is an acute angle.

[0028] In one possible embodiment of this application, the touch trace and the bonding trace are located in different film layers, and the touch trace is connected to the bonding trace via a film layer via, wherein the orthographic projection of the film layer via on the substrate is outside the orthographic projection of the pixel defining layer on the substrate.

[0029] In one possible implementation of this application, the substrate includes a substrate, a plurality of stacked conductive layers on the substrate, and an insulating layer between adjacent conductive layers. The bonding traces are formed by conductive layers on the side of the substrate away from the substrate. The substrate further includes a planarization layer between the bonding traces and the touch traces.

[0030] The membrane perforation includes planarization layer perforations, and the cofferdam is formed at least by the planarization layer.

[0031] In one possible implementation of this application, in the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate does not overlap with the orthographic projection of the bonding trace on the substrate.

[0032] In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate overlaps with the orthographic projection of the touch trace on the substrate.

[0033] In one possible implementation of this application, the pixel defining layer is an inorganic pixel defining layer;

[0034] Preferably, the pixel defining layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride;

[0035] Preferably, in the display area, the protective layer further includes a protective layer opening, the orthographic projection of the protective layer opening on the substrate being located within the orthographic projection of the pixel opening on the substrate;

[0036] Preferably, in the direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode stacked together; wherein the second electrode is connected to the isolation structure;

[0037] The first electrode is disposed on the side of the pixel defining layer near the substrate, and at least a portion of the first electrode is exposed through the opening in the protective layer and the pixel opening.

[0038] In one possible implementation of this application, the display panel further includes a thin-film encapsulation layer, which is located on the light-emitting side of the light-emitting device;

[0039] The thin-film encapsulation layer includes a first encapsulation layer, which includes a plurality of encapsulation units. The encapsulation units are used to encapsulate the light-emitting device within the isolation opening.

[0040] Preferably, the thin-film encapsulation layer further includes a second encapsulation layer, the second encapsulation layer being located on the side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covering the encapsulation unit;

[0041] Preferably, the second encapsulation layer fills the isolation opening, and the second encapsulation layer includes a flat surface on the side away from the substrate;

[0042] Preferably, the thin-film encapsulation layer further includes a third encapsulation layer, which is located on the side of the second encapsulation layer away from the substrate;

[0043] Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

[0044] In one possible implementation of this application, the display panel further includes a touch function layer, which is located on the side of the third encapsulation layer away from the substrate;

[0045] The touch function layer includes the touch routing;

[0046] Preferably, in the display area, the orthographic projection of the touch trace on the substrate does not overlap with the orthographic projection of the light-emitting device on the substrate;

[0047] Preferably, in the border area, the pixel defining layer is located on the substrate, the first encapsulation layer and the third encapsulation layer are located on the side of the pixel defining layer away from the substrate, and the touch trace is located on the side of the third encapsulation layer away from the substrate;

[0048] Preferably, the vias for connecting the touch trace and the bonding trace include vias in the third encapsulation layer, the first encapsulation layer, the pixel boundary layer, the protective layer, and the planarization layer. The touch trace is connected to the bonding trace sequentially via the vias in the third encapsulation layer, the first encapsulation layer, the pixel boundary layer, the protective layer, and the planarization layer; or,

[0049] The vias used to connect the touch traces and the bonding traces include vias in the third encapsulation layer, vias in the first encapsulation layer, and vias in the planarization layer. The touch traces are connected to the bonding traces sequentially vias in the third encapsulation layer, vias in the first encapsulation layer, and vias in the planarization layer.

[0050] A second aspect of this application also provides an electronic device, which includes a display panel as described in any possible implementation of the first aspect. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 One example is a schematic diagram illustrating the area distribution of the display panel;

[0053] Figure 2 Example Figure 1 One of the schematic diagrams of the film layer in the central display area;

[0054] Figure 3 The example demonstrates the touch wiring in Figure 1 One of the schematic diagrams showing the distribution of the display area in Central Africa;

[0055] Figure 4 Example Figure 1 Schematic diagram of the film layer in the central display area (Part 2);

[0056] Figure 5The example demonstrates the touch wiring in Figure 1 The second schematic diagram of the distribution of the display area in Central Africa;

[0057] Figure 6 Example Figure 5 One of the schematic diagrams of the cross-section at the DD position;

[0058] Figure 7 Example 2: A schematic diagram illustrating the area distribution of the display panel;

[0059] Figure 8 The example demonstrates the touch wiring in Figure 7 One of the schematic diagrams showing the distribution of the display area in Central Africa;

[0060] Figure 9 Example Figure 8 One of the schematic diagrams of the cross-section at the EE location;

[0061] Figure 10 Example Figure 1 Schematic diagram of the film layer in the central display area (Part 3);

[0062] Figure 11 Example Figure 5 Schematic diagram of the cross section at position DD (second part);

[0063] Figure 12 Example Figure 8 Schematic diagram of the cross section at the EE location (Part 2);

[0064] Figure 13 A schematic diagram of one possible structure for an isolation structure is shown;

[0065] Figure 14 This example illustrates another possible structural diagram of the isolation structure. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0067] In the description of this application, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product is usually placed when in use. They are only used to facilitate the description of this application and to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0068] Increasing the density of light-emitting devices (i.e., pixel density) in a display panel is a crucial way to improve display quality. However, current display panels manufactured using fine metal vapor deposition mask (FMM) technology are limited by technological constraints that prevent further increases in light-emitting device density. Through long-term research, the inventors discovered that to address this technical challenge, some display panels incorporate isolation structures. During the full-layer vapor deposition of the light-emitting material layer and electrodes, these layers can be separated at the isolation structure locations. By employing multiple vapor deposition and etching processes, light-emitting devices of different colors can be formed within different isolation openings. This process is also known as light-emitting device patterning. After the light-emitting devices are fabricated, a touch-sensitive layer is placed on the light-emitting side of the devices to enable touch functionality in the display panel, enhancing the interactive experience between users and electronic devices equipped with the display panel.

[0069] The aforementioned display panel suffers from a malfunction in touch functionality. To address this issue, the inventors have innovatively designed the following technical solution, the specific implementation of which will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions described above are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below are contributions made by the inventors to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0070] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 A schematic diagram illustrating the area distribution of the display panel is provided. Figure 2 Example Figure 1 A schematic diagram of the film layer in area AA of the display panel. Figure 3 A schematic diagram illustrating the distribution of touch traces is provided. In this embodiment, the display panel 1 includes a display area AA and a non-display area AB surrounding the display area AA. The non-display area AB includes a border area AB1 and a bonding area AB2 located on the side of the border area AB1 away from the display area AA. Exemplarily, the display area AA can be a rectangular area, and the border area AB1 can be an annular area surrounding the display area AA. The border area AB1 can include an upper border area, a lower border area, a left border area, and a right border area. The bonding area AB2 can be located on the side of the lower border area away from the display area AA. The display panel 1 includes a substrate 11, a protective layer 17, an isolation structure 12, a light-emitting device 13, a pixel defining layer 14, and touch traces 151. Pixel circuits for driving the light-emitting device 13 are formed in the substrate 11.

[0071] A protective layer 17 is located on the display area AA and the border area AB1 on the substrate 11. The protective layer 17 has etching resistance and can protect the underlying film layer from over-etching. A pixel defining layer 14 is located on the side of the protective layer 17 away from the substrate 11. In the display area AA, the pixel defining layer 14 includes pixel openings 1401, which can be arranged in an array on the display area AA. An isolation structure 12 is located on the side of the pixel defining layer 14 away from the substrate 11. In the display area AA, the isolation structure 12 includes an isolation opening 1201. The orthographic projection of the isolation opening 1201 on the substrate 11 covers the orthographic projection of the pixel opening 1401 on the substrate 11, that is, the isolation opening 1201 and the pixel opening 1401 are connected.

[0072] The light-emitting device 13 is at least partially located within the pixel opening 1401. In the display area AA, the touch trace 151 is located on the side of the light-emitting device 13 away from the substrate 11. The touch trace 151 extends from the display area AA and the border area AB1 towards the bonding area AB2. At least a portion of the touch trace 151 is located in the border area AB1 between the display area AA and the bonding area AB2, that is, at least a portion of the touch trace 151 is located in the border area AB1 near the bonding area AB2. For example, the border area AB1 can be... Figure 1 The bottom border area in the middle.

[0073] In the border area AB1 near the bonding area AB2, the display panel 1 includes at least a bonding trace 201 located in the bonding area AB1. The touch trace 151 is electrically connected to the bonding trace 201. The orthographic projection outline of the pixel defining layer 14 on the substrate 11 is located within the orthographic projection of the protective layer 17 on the substrate 11, that is, the orthographic projection of the edge of the pixel defining layer 14 on the substrate 11 is located within the orthographic projection of the protective layer 17 on the substrate 11.

[0074] The inventors discovered that the main cause of the poor touch function of the display panel 1 is a short circuit in the touch trace 151, and the short circuit is generally located at the edge of the pixel defining layer 14 in the bezel area AB1. Analysis revealed that the main reason for this problem is that the etching process of the pixel defining layer 14 may over-etch the film layer below it. Additionally, over-etching of the film layer below the pixel defining layer 14 is also possible during the patterning process of the light-emitting device 13. This results in a higher step at the edge of the pixel defining layer 14, making it easy for insufficient exposure to occur at this location during the patterning process of depositing the metal film to form the touch trace 151. This leads to residual photoresist, which in turn causes etching residue in the metal layer, resulting in a short circuit between adjacent touch traces 151. The solution provided in this embodiment places the edge of the pixel defining layer 14 within the protective layer 17. Even if over-etching occurs during the etching process of the pixel defining layer 14 and / or over-etching occurs in the film layer below the edge of the pixel defining layer 14 during the patterning process of the light-emitting device 13, the protective layer 17 below the pixel defining layer 14 can block the over-etching, thereby preventing the formation of an excessively high step at the edge of the pixel defining layer 14. Even if the touch trace 151 passes through the edge of the pixel defining layer 14, the adjacent touch trace 151 will not be unable to disconnect due to an excessively high step at the edge, thus preventing a short circuit. In other words, the solution provided in this embodiment can insulate adjacent touch traces 151 from each other, thereby ensuring that the display panel 1 has good touch performance.

[0075] In this embodiment, the material of the protective layer 17 includes an etching-resistant inorganic material, specifically, an inorganic material resistant to etching gases. Exemplarily, the material of the protective layer 17 may include at least one of silicon nitride (SiNx) and silicon oxide (SiOx). For example, the protective layer 17 may be a single-layer structure of silicon oxide or silicon nitride, or a stacked structure of silicon oxide and silicon nitride.

[0076] Furthermore, please refer to again Figure 2 In this embodiment, the thickness d of the protective layer 17 in the plane direction perpendicular to the substrate 11 is 100 angstroms to 20000 angstroms. For example, the thickness d of the protective layer 17 includes 100 angstroms, 500 angstroms, 1000 angstroms, 1580 angstroms, 2475 angstroms, 3850 angstroms, 5000 angstroms, 6750 angstroms, 7580 angstroms, 8525 angstroms, 9520 angstroms, 10000 angstroms, 12500 angstroms, 14580 angstroms, 16580 angstroms, 18750 angstroms, or 20000 angstroms.

[0077] Furthermore, in this embodiment, the pixel defining layer 14 is an inorganic pixel defining layer. The pixel defining layer 14 can be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed by alternating layers of silicon oxide and silicon nitride.

[0078] Furthermore, please refer to again Figure 2 In the display area AA, the protective layer 17 also includes a protective layer opening 1701, which is connected to the pixel defining layer opening 1401, wherein the orthographic projection of the protective layer opening 1701 on the substrate 11 is located within the orthographic projection of the pixel opening 1401 on the substrate 11.

[0079] Please refer to Figure 4 In the direction away from the substrate 11 (Z direction in the figure), the light-emitting device 13 includes a first electrode 131, a light-emitting material layer 132, and a second electrode 133 stacked together. The first electrode 131 is located on the side of the pixel defining layer 14 facing the substrate 11, and at least a portion of the first electrode 131 is exposed through a protective layer opening 1701 and a pixel opening 1401. The second electrode 133 is connected to the isolation structure 12. Exemplarily, the second electrode 133 and the isolation structure 12 are connected by an overlapping manner. The first electrode 131 can be connected to a thin-film transistor formed in the substrate 11. In this embodiment, the first electrode 131 can be the anode of the light-emitting device 13, and the second electrode 133 can be the cathode of the light-emitting device 13.

[0080] In one possible implementation of this embodiment, please refer to Figure 5 In the border area AB1 near the bonding area AB2, the orthographic projection of the touch trace 151 on the substrate 11 lies within the orthographic projection of the pixel defining layer 14 on the substrate 11. That is, in this embodiment, the touch trace 151 does not pass through the edge of the pixel defining layer 14. This design ensures that the touch trace 151 is not affected by the edge step of the pixel defining layer 14 during the patterning process, and allows adjacent touch traces 151 to be insulated from each other.

[0081] Furthermore, in this embodiment, please refer to Figure 5 and Figure 6 Touch trace 151 and bonding trace 201 are located in different film layers. An insulating structure layer can be provided between touch trace 151 and bonding trace 201. Touch trace 151 is connected to bonding trace 201 through film layer via 301 located in the insulating structure layer. The orthographic projection of film layer via 301 on substrate 11 is located within the orthographic projection of pixel defining layer 14 on substrate 11.

[0082] In this embodiment, the via 301 is located at the intersection of the touch trace 151 and the bonding trace 201. The substrate 11 includes a substrate 110, a plurality of stacked conductive layers on the substrate 110, and an insulating layer between adjacent conductive layers. The bonding trace 201 is formed by the conductive layers in the substrate 11. For example, the bonding trace 201 can be formed by the conductive layer on the side of the substrate 11 away from the substrate 11. For instance, when the substrate 11 includes four sequentially stacked metal layers, the bonding trace 201 can be formed by the fourth metal layer. This reduces the vertical distance between the touch trace 151 and the bonding trace 201, facilitating the formation of the via 301 between them. The insulating structure layer may include a planarization layer 111 and a pixel defining layer 14 located between the bonding trace 201 and the touch trace 151, wherein the planarization layer 111 is an organic planarization layer. The film layer via 301 includes a planarization layer via and a pixel defining layer via connected to each other. The touch trace 151 is connected to the bonding trace 201 through the pixel defining layer via and the planarization layer via. The orthographic projection of the planarization layer via on the substrate 11 and the orthographic projection of the pixel defining layer via on the substrate 11 overlap.

[0083] In this embodiment, in the border area AB1 near the bonding area AB2, the orthographic projection outline of the pixel defining layer 14 on the substrate 11 overlaps with the orthographic projection of the bonding trace 201 on the substrate 11, that is, the edge of the pixel defining layer 14 intersects with the bonding trace 201.

[0084] In another possible implementation of this embodiment, please refer to Figure 7 and Figure 8 The substrate 11 also includes a dam 112 surrounding the display area AA and located in the frame area AB1. The dam 112 has a high protrusion height and can be used to block the organic layer to prevent the organic layer from overflowing and causing the display panel 1 to fail to be packaged.

[0085] In the border area AB1 near the bonding area AB2, the orthographic projection outline of the pixel defining layer 14 on the substrate 11 is located within the orthographic projection of the cofferdam 112 on the substrate 11, wherein the orthographic projection outline of the pixel defining layer 14 on the substrate 11 overlaps with the orthographic projection of the touch trace 151 on the substrate 11.

[0086] In the above design, the edge of the pixel defining layer 14 is set at this position. Even if there is over-etching of the pixel defining layer 14 and the possibility of over-etching of the film layer below the pixel defining layer 14 during the process of patterning to form the light-emitting device 13, since the dike 112 has a relatively high protrusion height (high terrain) and there is a protective layer 17 below the pixel defining layer 14 to block over-etching, during the process of forming the touch trace 151, when the photoresist is exposed and developed, no photoresist residue will appear at this position. This can ensure that the touch trace 151 will not have a short circuit caused by the etching metal residue at this position, and ensure that the display panel 1 has good touch performance.

[0087] In this embodiment, the substrate 11 may include a plurality of dams 112, which are arranged sequentially in the border area AB1 along a direction away from the display area AA. For example, when the display area AA is a rectangular region, the orthographic projection shape of the dams 112 on the substrate 11 can be a rectangular ring. In the border area AB1 near the bonding area AB2, the orthographic projection outline of the pixel defining layer 14 on the substrate 11 is located within the orthographic projection of the dams 112 on the side near the bonding area AB2, that is, the edge of the pixel defining layer 14 is located on the outermost dam 112.

[0088] Optionally, such as Figure 9 As shown, the included angle α between the side of the cofferdam 112 near the bonded area AB2 and the bottom surface of the cofferdam 112 is an acute angle. For example, the included angle α is 30°-70°. More specifically, the included angle α includes 30°, 35°, 45°, 50°, 58°, 66° or 70°, etc. This design facilitates the formation of a continuous trace on the side of the cofferdam 112 for the touch wiring 151.

[0089] Furthermore, in this embodiment, please refer to Figure 9 Touch trace 151 and bonding trace 201 are located in different film layers. Touch trace 151 is connected to bonding trace 201 via film layer via 301 in the film layer between the two. The orthogonal projection of film layer via 301 on substrate 11 is outside the orthogonal projection of pixel defining layer 14 on substrate 11.

[0090] In this embodiment, the via 301 is located at the intersection of the touch trace 151 and the bonding trace 201. The substrate 11 includes a substrate 110, a plurality of stacked conductive layers on the substrate 110, and an insulating layer between adjacent conductive layers. The bonding trace 201 is formed by the conductive layers in the substrate 11. For example, the bonding trace 201 can be formed by a conductive layer on the side of the substrate 11 away from the substrate 11. For instance, when the substrate 11 includes four sequentially stacked metal layers, the bonding trace 201 can be formed by the fourth metal layer. This reduces the vertical distance between the touch trace 151 and the bonding trace 201, facilitating the formation of the via 301 between them. The substrate 11 may also include a planarization layer 111 located between the bonding trace 201 and the touch trace 151, wherein the planarization layer 111 is an organic planarization layer. The membrane via 301 includes the planarization layer via. The touch trace 151 is connected to the bonding trace 201 through the planarization layer via. In this embodiment, the cofferdam 112 can be set in the same layer as the planarization layer 111, that is, the cofferdam 112 and the planarization layer 111 can be made of the same material in the same process.

[0091] In this embodiment, in the border area AB1 near the bonding area AB2, the orthographic projection outline of the pixel defining layer 14 on the substrate 11 does not overlap with the orthographic projection of the bonding trace 201 on the substrate 11, that is, the edge of the pixel defining layer 14 and the bonding trace 201 are misaligned.

[0092] Please refer to Figure 10 In this embodiment, the display panel 1 further includes a thin film encapsulation layer 16, which is located on the light-emitting side of the light-emitting device 13, that is, the thin film encapsulation layer 16 is located on the side of the light-emitting device 13 away from the substrate 11.

[0093] The thin-film encapsulation layer 16 includes a first encapsulation layer 161, which includes a plurality of encapsulation units 1611. Each encapsulation unit 1611 encapsulates a light-emitting device 13 within an isolation opening 1201. The encapsulation unit 1611 extends from the surface of the light-emitting device 13 through the isolation structure 12 toward the sidewall of the isolation opening 1201 to the side of the isolation structure 12 away from the substrate 11. Optionally, two adjacent encapsulation units 1611 for encapsulating light-emitting devices 13 of different colors are disconnected on the side of the isolation structure 12 away from the substrate 11, and a gap exists between the encapsulation unit 1611 on the side of the isolation structure 12 away from the substrate 11 and the isolation structure 12. Two adjacent encapsulation units 1611 for encapsulating light-emitting devices 13 of the same color are connected to each other on the side of the isolation structure 12 away from the substrate 11.

[0094] Furthermore, please refer to again Figure 10The thin-film encapsulation layer 16 further includes a second encapsulation layer 162, which is located on the side of the encapsulation unit 1611 away from the substrate 11. The second encapsulation layer 162 at least covers the encapsulation unit 1611 and fills the isolation opening 1201. Optionally, the second encapsulation layer 162 has a flat surface on the side away from the substrate 11.

[0095] Furthermore, the thin-film encapsulation layer 16 also includes a third encapsulation layer 163, which is located on the side of the second encapsulation layer 162 away from the substrate 11.

[0096] Optionally, the materials of the first encapsulation layer 161 and the third encapsulation layer 163 include inorganic encapsulation materials, and the material of the second encapsulation layer 162 includes organic encapsulation materials. That is, the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic encapsulation layers, and the second encapsulation layer 162 is an organic encapsulation layer. For example, the first encapsulation layer 161 and the third encapsulation layer 163 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 162 can be formed by inkjet printing (IJP).

[0097] In this implementation, please refer again. Figure 10 The display panel 1 also includes a touch function layer 15, which is located on the side of the third encapsulation layer 163 away from the substrate 11. The touch function layer 15 includes touch traces 151, which can form a crisscrossing touch pattern at least in the display area AA. In the display area AA, the orthographic projection of the touch traces 151 on the substrate 11 does not overlap with the orthographic projection of the light-emitting device 13 on the substrate 11. For example, the orthographic projection of the touch traces 151 on the substrate 11 can be located within the orthographic projection of the isolation structure 12 on the substrate 11. With this design, the touch traces 151 will not affect the light emission of the light-emitting device 13.

[0098] Please refer to Figure 11 In one possible implementation of this embodiment, in the border area AB1, the pixel defining layer 14 is located on the substrate 11, the first encapsulation layer 161 and the third encapsulation layer 163 are located on the side of the pixel defining layer 14 away from the substrate 11, and the touch trace 151 is located on the side of the third encapsulation layer 163 away from the substrate 11. In this embodiment, the film layer via 301 also includes a film layer via of the third encapsulation layer, a film layer via of the first encapsulation layer, and a protective layer via, that is, the touch trace 151 is connected to the bonding trace 201 in sequence through the film layer via of the third encapsulation layer, the film layer via of the first encapsulation layer, the pixel defining layer via, the protective layer via, and the planarization layer via.

[0099] Please refer to Figure 12In another possible implementation of this embodiment, in the border area AB1, the pixel defining layer 14 is located on the substrate 11, the first encapsulation layer 161 and the third encapsulation layer 163 are located on the side of the pixel defining layer 14 away from the substrate 11, and the touch trace 151 is located on the side of the third encapsulation layer 163 away from the substrate 11. In this embodiment, the film layer via 301 also includes film layer vias in the third encapsulation layer 163 and the first encapsulation layer. The film layer vias in the third encapsulation layer 163 and the first encapsulation layer 161 are connected to the planarization layer vias, that is, the touch trace 151 is connected to the bonding trace 201 through the film layer vias in the third encapsulation layer 163, the first encapsulation layer 161 and the planarization layer vias.

[0100] Please refer to Figure 13 In this embodiment, the isolation structure 12 includes a first isolation portion 121 and a second isolation portion 122 stacked sequentially. The orthographic projection of the first isolation portion 121 on the substrate 11 lies within the orthographic projection of the second isolation portion 122 on the substrate 11. The second isolation portion 122 extends relative to the first isolation portion 121 toward the corresponding isolation opening 1201. On a cross-section perpendicular to the plane of the substrate 11 and passing through the center of the isolation opening 1201, the cross-section of the isolation structure 12 may be T-shaped. The first isolation portion 121 is a conductive isolation portion, and the second electrode 133 can also be electrically connected to the first isolation portion 121. For example, the second electrode 133 is electrically connected by overlapping with the first isolation portion 121.

[0101] Further, please refer to Figure 14 In this embodiment, the isolation structure 12 further includes a third isolation portion 123. The third isolation portion 123, the first isolation portion 121, and the second isolation portion 122 are sequentially stacked in a direction away from the substrate 11. The orthographic projection of the first isolation portion 121 onto the substrate 11 may lie within the orthographic projection of the third isolation portion 123 onto the substrate 11. The cross-section of the isolation structure 12 may be I-shaped on a cross-section perpendicular to the plane of the substrate 11 and passing through the center of the isolation opening 1201. The third isolation portion 123 is a conductive isolation portion, and the second electrode 133 may also be electrically connected to the third isolation portion 123. For example, the second electrode 133 is electrically connected by overlapping with the third isolation portion 123.

[0102] Optionally, the first isolation part 121 may be made of aluminum, silver or copper, the second isolation part 122 may be made of titanium or molybdenum, and the third isolation part 123 may be made of molybdenum or titanium.

[0103] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the display panel provided in this application. The electronic device may include smartphones, tablets, in-vehicle display devices, smart wearable devices, televisions, laptops, and other devices with display functions.

[0104] This application provides a display panel and an electronic device. In the display panel, a protective layer disposed below the pixel boundary layer can prevent over-etching, thereby avoiding the formation of excessively high steps at the edges of the pixel boundary layer. Even if touch traces pass through the edges of the pixel boundary layer, adjacent touch traces will not be unable to disconnect due to excessively high steps at the edge, thus preventing short circuits. In other words, the above-mentioned solution provided in this embodiment can insulate adjacent touch traces from each other, thereby ensuring that the display panel has good touch performance.

[0105] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area surrounding the display area. The non-display area includes a border area and a bonding area located on the side of the border area away from the display area. The display panel includes: substrate; A protective layer is located on the display area and the border area on the substrate; A pixel defining layer is located on the side of the protective layer away from the substrate, and in the display area, the pixel defining layer includes pixel openings; An isolation structure is located on the side of the pixel defining layer away from the substrate. In the display area, the isolation structure includes an isolation opening, wherein the isolation opening communicates with the pixel opening. The light-emitting device is at least partially located within the pixel opening; The touch trace is located on the side of the light-emitting device away from the substrate, and extends from the display area and the border area to the bonding area; In the border area near the bonding area, the display panel includes bonding traces located at least in the bonding area, the touch traces are electrically connected to the bonding traces, and the orthographic projection outline of the pixel defining layer on the substrate is located within the orthographic projection of the protective layer on the substrate.

2. The display panel as described in claim 1, characterized in that, The protective layer is made of etching-resistant inorganic materials; Preferably, the material of the protective layer includes at least one of silicon nitride and silicon oxide.

3. The display panel as described in claim 2, characterized in that, The thickness of the protective layer is 100 angstroms to 20,000 angstroms in the plane perpendicular to the substrate.

4. The display panel as described in claim 1, characterized in that, In the border area near the bonding area, the orthogonal projection of the touch trace on the substrate is located within the orthogonal projection of the pixel defining layer on the substrate; Preferably, an insulating structure layer is provided between the touch trace and the bonding trace, and the touch trace is connected to the bonding trace through a film via located in the insulating structure layer. The orthographic projection of the film via on the substrate is located within the orthographic projection of the pixel defining layer on the substrate.

5. The display panel as described in claim 4, characterized in that, The via in the film layer is located at the intersection of the touch trace and the bonding trace; The substrate includes a substrate, a plurality of stacked conductive layers on the substrate, and an insulating layer between adjacent conductive layers. The bonding traces are formed by conductive layers on the side of the substrate away from the substrate. The insulating structure layer includes a planarization layer and a pixel delimitation layer between the bonding traces and the touch traces. The vias in the film layer include interconnected planarization layer vias and pixel defining layer vias, and the touch traces are connected to the bonding traces through the pixel defining layer vias and the planarization layer vias. Preferably, the planarization layer is an organic planarization layer.

6. The display panel as described in claim 4, characterized in that, In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate overlaps with the orthographic projection of the bonding trace on the substrate.

7. The display panel as described in claim 1, characterized in that, The substrate includes a dam surrounding the periphery of the display area and located in the border area; In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate lies within the orthographic projection of the dam on the substrate.

8. The display panel as described in claim 7, characterized in that, The substrate includes multiple dams, which are arranged sequentially in the border area along a direction away from the display area. The orthographic projection outline of the pixel defining layer on the substrate is located within the orthographic projection of the dam on the substrate on the side closer to the bonding area. Preferably, the angle between the side of the cofferdam closest to the bonding area and the bottom surface of the cofferdam is an acute angle.

9. The display panel as described in claim 8, characterized in that, The touch trace and the bonding trace are located in different film layers. The touch trace is connected to the bonding trace via a film layer via. The orthographic projection of the film layer via on the substrate is outside the orthographic projection of the pixel defining layer on the substrate.

10. The display panel as claimed in claim 9, characterized in that, The substrate includes a substrate, a plurality of stacked conductive layers on the substrate, and an insulating layer between adjacent conductive layers. The bonding traces are formed by conductive layers on the side of the substrate away from the substrate. The substrate also includes a planarization layer between the bonding traces and the touch traces. The membrane perforation includes planarization layer perforations, and the cofferdam is formed at least by the planarization layer.

11. The display panel as claimed in claim 7, characterized in that, In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate does not overlap with the orthographic projection of the bonding trace on the substrate. In the border area near the bonding area, the orthographic projection outline of the pixel defining layer on the substrate overlaps with the orthographic projection of the touch trace on the substrate.

12. The display panel as described in any one of claims 1-11, characterized in that, The pixel delimiting layer is an inorganic pixel delimiting layer; Preferably, the pixel defining layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride; Preferably, in the display area, the protective layer further includes a protective layer opening, the orthographic projection of the protective layer opening on the substrate being located within the orthographic projection of the pixel opening on the substrate; Preferably, in the direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode stacked together; wherein the second electrode is connected to the isolation structure; The first electrode is disposed on the side of the pixel defining layer near the substrate, and at least a portion of the first electrode is exposed through the opening in the protective layer and the pixel opening.

13. The display panel as claimed in claim 12, characterized in that, The display panel further includes a thin-film encapsulation layer, which is located on the light-emitting side of the light-emitting device; The thin-film encapsulation layer includes a first encapsulation layer, which includes a plurality of encapsulation units. The encapsulation units are used to encapsulate the light-emitting device within the isolation opening. Preferably, the thin-film encapsulation layer further includes a second encapsulation layer, the second encapsulation layer being located on the side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covering the encapsulation unit; Preferably, the second encapsulation layer fills the isolation opening, and the second encapsulation layer includes a flat surface on the side away from the substrate; Preferably, the thin-film encapsulation layer further includes a third encapsulation layer, which is located on the side of the second encapsulation layer away from the substrate; Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

14. The display panel as claimed in claim 13, characterized in that, The display panel further includes a touch function layer, which is located on the side of the third encapsulation layer away from the substrate; The touch function layer includes the touch routing; Preferably, in the display area, the orthographic projection of the touch trace on the substrate does not overlap with the orthographic projection of the light-emitting device on the substrate; Preferably, in the border area, the pixel defining layer is located on the substrate, the first encapsulation layer and the third encapsulation layer are located on the side of the pixel defining layer away from the substrate, and the touch trace is located on the side of the third encapsulation layer away from the substrate; Preferably, the vias for connecting the touch traces and the bonding traces include vias in the third encapsulation layer, vias in the first encapsulation layer, vias in the pixel boundary layer, vias in the protective layer, and vias in the planarization layer. The touch traces are connected to the bonding traces sequentially vias in the third encapsulation layer, vias in the first encapsulation layer, vias in the pixel boundary layer, vias in the protective layer, and vias in the planarization layer. or, The vias include vias in the third encapsulation layer, vias in the first encapsulation layer, and vias in the planarization layer. The touch traces are connected to the bonding traces sequentially vias in the third encapsulation layer, vias in the first encapsulation layer, and vias in the planarization layer.

15. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-14.

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