Display panel, method of manufacturing the same, and electronic device

Abstract

The present disclosure relates to a display panel, a method of manufacturing the same, and an electronic device. The display panel includes a substrate including an opening area, an intermediate area at least partially surrounding the opening area, and a display area at least partially surrounding the intermediate area; a light emitting diode in the display area; a first dam in the intermediate area and having at least one first groove defined in an upper surface of the first dam; and a second dam between the first dam and the display area, the second dam including an organic material portion and a metal portion within the organic material portion and having a portion protruding beyond a side surface of the organic material portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0036214, filed on March 20, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to a display panel, a method of manufacturing the display panel, and an electronic device including the display panel. Background Technology

[0004] Electronic devices can display images and / or video using a display panel provided within the device. In recent years, as the applications of display panels have diversified, various functions that can be embedded in or linked to display panels have been proposed. Various methods have been proposed to ensure the basic functionality of the image display panel is achieved while adding various functions.

[0005] In addition to the display panel, the electronic device may include components for performing other functions. For example, the electronic device may include other components such as a camera or sensor. Components may be disposed on the surface of the display panel (e.g., the rear surface). To enable the components to perform their functions smoothly, an opening area may be defined in the display panel, in the area overlapping with the component. The opening may be defined through the display panel. The opening defined in the display panel can be achieved by forming multiple layers on a substrate, cutting multiple layers and the substrate, and removing the portion corresponding to the opening.

[0006] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] In the process of cutting the substrate and multiple layers on the substrate along the dicing line, and removing portions corresponding to the openings to form openings in the display panel, delamination may occur between some of the multiple layers on the substrate. Therefore, a structure may be desired to prevent or substantially prevent delamination.

[0008] Embodiments of this disclosure may relate to a display panel in which layer delamination can be prevented or substantially prevented, a method of manufacturing the display panel, and an electronic device including the display panel.

[0009] However, this disclosure is not limited to the foregoing aspects and features. The foregoing and other aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing one or more of the embodiments presented in this disclosure.

[0010] According to one or more embodiments of the present disclosure, a display panel includes: a substrate including an opening region, an intermediate region at least partially surrounding the opening region, and a display region at least partially surrounding the intermediate region; a light-emitting diode in the display region; a first dam in the intermediate region and having at least one first groove defined in an upper surface of the first dam; and a second dam between the first dam and the display region, the second dam including: an organic material portion; and a metal portion within the organic material portion and having a portion protruding beyond a side surface of the organic material portion.

[0011] In one embodiment, the display panel may further include an inorganic encapsulation layer on the first and second dams.

[0012] In an embodiment, the inorganic encapsulation layer may include a first portion and a second portion that overlap with a first edge and a second edge defining at least one first groove of the first dam, respectively, and the first portion and the second portion of the inorganic encapsulation layer may contact each other in the region overlapping with at least one first groove.

[0013] In an embodiment, the inorganic encapsulation layer may integrally extend and cover the upper, side, and lower surfaces of the portion of the metal portion that protrudes beyond the side surface of the organic material portion.

[0014] In one embodiment, a portion of the lower surface of the inorganic encapsulation layer located on the first dam may be spaced apart from a portion of the upper surface of the first dam.

[0015] In an embodiment, the first dam may be provided as a plurality of first dams, and the display panel may further include an organic encapsulation layer on an inorganic encapsulation layer having at least a portion located between two adjacent first dams among the plurality of first dams.

[0016] In an embodiment, the width of the first groove of the first dam may be approximately 1.5 to approximately 2 times the thickness of the inorganic encapsulation layer on the first dam.

[0017] In one embodiment, in a plan view, the first dam may surround the opening area.

[0018] In an embodiment, the opening that overlaps with the opening region can be defined in the substrate.

[0019] According to one or more embodiments of the present disclosure, a method of manufacturing a display panel includes: preparing a substrate in which an opening region is defined, an intermediate region at least partially surrounding the opening region, and a display region at least partially surrounding the intermediate region; placing a first dam in the intermediate region, the first dam having at least one first groove defined in an upper surface of the first dam; placing an inorganic encapsulation layer on the first dam, a first portion and a second portion of the inorganic encapsulation layer respectively overlapping a first edge and a second edge of the first dam defining at least one first groove contacting each other in the region overlapping the at least one first groove; and cutting the substrate along the boundary between the intermediate region and the opening region.

[0020] In an embodiment, the method may further include: placing a second barrier between the first barrier and the display area, the second barrier comprising: an organic material portion; and a metal portion disposed within the organic material portion and protruding beyond the side surface of the organic material portion.

[0021] In one embodiment, the inorganic encapsulation layer may be disposed on the second dam and may integrally extend and cover the upper, side, and lower surfaces of the portion of the metal portion that protrudes beyond the side surface of the organic material portion of the second dam.

[0022] In one embodiment, during substrate cutting, a portion of the lower surface of the inorganic encapsulation layer located on the first dam may be spaced apart from a portion of the upper surface of the first dam.

[0023] In an embodiment, the first dam may be provided as a plurality of first dams, and the method may further include placing an organic encapsulation layer on an inorganic encapsulation layer, at least a portion of which is located between two adjacent first dams among the plurality of first dams.

[0024] In an embodiment, the method may further include: placing an internal dam in the opening region, the internal dam having at least one second groove defined in the upper surface of the internal dam.

[0025] In an embodiment, the cross-sectional shape of at least one first groove of the first dam and the cross-sectional shape of at least one second groove of the inner dam may be the same as each other.

[0026] In an embodiment, the inorganic encapsulation layer may be disposed on an inner dam and may include a third portion and a fourth portion that overlap with a first edge and a second edge defining at least one second groove of the inner dam, respectively, and the third portion and the fourth portion of the inorganic encapsulation layer may contact each other in the region overlapping with at least one second groove.

[0027] In an embodiment, the method may further include removing the portion of the substrate corresponding to the opening area together with the internal dam.

[0028] In this embodiment, the inorganic encapsulation layer may extend across the display area, the intermediate area, and the opening area, and the inorganic encapsulation layer may be cut together with the substrate during substrate cutting.

[0029] According to one or more embodiments of this disclosure, an electronic device includes: a display panel; and a processor configured to drive the display panel. The display panel includes: a substrate including an opening region, an intermediate region at least partially surrounding the opening region, and a display region at least partially surrounding the intermediate region; a light-emitting diode (LED) in the display region; a first dam in the intermediate region and having at least one first groove defined in an upper surface of the first dam; and an inorganic encapsulation layer covering the LED and the first dam. The inorganic encapsulation layer includes a first portion and a second portion that overlap with a first edge and a second edge of the first dam defining the at least one first groove, respectively. The first portion and the second portion of the inorganic encapsulation layer are in contact with each other in the region overlapping with the at least one first groove.

[0030] However, this disclosure is not limited to the above aspects and features, and the above and other aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and will be apparent in part from thereto, or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments, with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a block diagram of an electronic device according to an embodiment;

[0033] Figures 2 to 4 These are schematic diagrams of some electronic devices according to some embodiments;

[0034] Figure 5 This is a plan view of the display panel according to an embodiment;

[0035] Figure 6 This is a plan view of the display panel according to an embodiment;

[0036] Figure 7 This is a plan view of the display panel according to an embodiment;

[0037] Figure 8 This is a schematic cross-sectional view of the display panel according to an embodiment;

[0038] Figures 9 to 11 Each is an equivalent circuit diagram of the pixels of the display panel according to an embodiment;

[0039] Figure 12 This is a cross-sectional view of the display area of ​​the display panel according to an embodiment;

[0040] Figure 13 This is a plan view of the display panel according to an embodiment;

[0041] Figure 14 This is a cross-sectional view of the display panel according to an embodiment;

[0042] Figure 15 This is an enlarged cross-sectional view of the display panel according to an embodiment;

[0043] Figure 16 This is a cross-sectional view of the display panel according to an embodiment;

[0044] Figure 17 This is a cross-sectional view of the display panel according to an embodiment; and

[0045] Figures 18A to 18G These are cross-sectional views illustrating various processes of a method for manufacturing a display panel according to some embodiments. Detailed Implementation

[0046] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Accordingly, processes, elements, and techniques that are not necessary for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, redundant descriptions may not be repeated.

[0047] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or in the reverse order of the described sequence.

[0048] Furthermore, as will be understood by those skilled in the art, given that this disclosure is as a whole, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other and may be technically linked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0049] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “on” may be used herein to describe the relationship of one element or feature as illustrated in the figures to another element(s). It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the example terms “below” and “below” can include both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0050] Furthermore, it should be anticipated that the shapes shown in the figures may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Accordingly, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the figures, and should be interpreted in light of possible shape variations, for example, due to manufacturing processes. Therefore, the shapes shown in the figures may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0051] In the various figures, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or they can represent directions that are not perpendicular to each other and are different from each other.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or part described below may be referred to as the second element, component, area, layer, or part.

[0053] It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it can be directly on, directly connected to, or directly attached to the other element or layer, or one or more intermediary elements or layers may exist. Similarly, when a layer, area, or element is referred to as being "electrically connected" to another layer, area, or element, it can be directly electrically connected to the other layer, area, or element, or it can be indirectly electrically connected to the other layer, area, or element with one or more intermediary layers, areas, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between those two elements or layers, or one or more intermediary elements or layers may exist.

[0054] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” and “having,” and variations thereof, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When preceding / following a list of elements, expressions such as “at least one of” modify the entire list of elements without modifying any individual element in the list. For example, the expressions “at least one of a, b, and c” and “at least one selected from the group consisting of a, b, and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, and variations thereof.

[0055] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the terms “use,” “being used,” and “being exploited” can be considered synonymous with the terms “utilize,” “being exploited,” and “being exploited,” respectively.

[0056] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on a single integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors within one or more computing devices, executing computer program instructions, and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices, such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs or flash drives. Moreover, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0058] Figure 1 This is a block diagram of an electronic device according to an embodiment.

[0059] refer to Figure 1 The electronic device 10 may include a display panel 11, a processor 12, a memory 13, and a power module (e.g., a power supply circuit or power supply) 14.

[0060] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In embodiments, from a functional or structural point of view, processor 12 may be provided as two parts. For example, processor 12 may include a main processor in the form of a first driver chip including a CPU and an auxiliary processor in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to match the interface specifications of display panel 11.

[0061] The memory 13 may include at least one of non-volatile memory and volatile memory. The memory 13 may store data information for the operation of the processor 12 or the display panel 11. When an application stored in the memory 13 is executed, the processor 12 may transmit image data signals and / or input control signals to the display panel 11, and may process the signals received by the display panel 11 to output image information through the display screen.

[0062] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power for the operation of the electronic device 10. The power conversion of the power conversion module may include direct current (DC) to DC conversion, alternating current (AC) to DC conversion, and / or DC to AC conversion, but this disclosure is not limited thereto.

[0063] The electronic device 10 may further include an input module 15, a non-video output module 16, and / or a communication module 17.

[0064] Input module 15 can provide input information to processor 12 and / or display panel 11. Input module 15 may include various suitable sensor modules (e.g., sensors) as well as physical buttons, keyboards, and microphones. Examples of sensor modules may include biosensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, or heart rate sensors, as well as touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors, photodetectors, photoelectric conversion sensors, or temperature sensors.

[0065] The non-video output module 16 can receive information other than images from the processor 12 and can provide that information to the user. Examples of the non-video output module 16 may include an audio module, a haptic module, a light-emitting module, and other suitable functional modules specific to electronic devices (e.g., a cooling module for a refrigerator).

[0066] The communication module 17 is responsible for sending and receiving information between the electronic device 10 and external devices, and may include a receiving unit and a sending unit. The communication module 17 may include various suitable wireless communication modules such as mobile communication modules, Wi-Fi modules, or Bluetooth modules, and / or various suitable wired communication modules.

[0067] At least one of the components of the electronic device 10 described above may be included within the display device. Additionally, some modules that are functionally included in a single module may be included within the display device, while other modules may be provided separately from the display device. For example, the display device may include a display panel 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10, rather than as the display device. As another example, the power module 14 may be provided within the display device and may supply power to the processor 12 and memory 13 provided within the electronic device 10, rather than the display device. However, this disclosure is not limited thereto.

[0068] Figures 2 to 4 These are schematic diagrams of some electronic devices according to some embodiments. Figures 2 to 4 Various examples of electronic devices to which a display device, according to some embodiments, can be applied are shown.

[0069] Figure 2 Examples of some electronic devices are shown, such as a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a television (TV) 10_1d, and a desktop monitor 10_1e.

[0070] In addition to the display panel, the smartphone 10_1a may include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received via the communication module or another input module and can display the information via the display panel of the display device.

[0071] Similar to smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, and TVs 10_1d, desktop monitors 10_1e may include a display panel and an input module, and in some cases may further include a communication module.

[0072] Figure 3 An example is shown where an electronic device, including a display panel, is applied to a wearable electronic device. The wearable electronic device may include smart glasses 10_2a, a head-mounted display 10_2b, or a smartwatch 10_2c, etc.

[0073] The smart glasses 10_2a and the head-mounted display 10_2b may include a display panel that emits a display image and a reflector that reflects the emitted display image to provide a reflected display screen to the user's eyes. Accordingly, a virtual reality screen or an augmented reality screen may be provided to the user.

[0074] The smartwatch 10_2c may include a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display screen.

[0075] Figure 4 Examples of electronic devices, including a display panel, being applied to a vehicle are shown. For example, electronic device 10_3 can be applied to the vehicle's dashboard or central instrument panel, or it can be applied to a central information display (CID) located on the vehicle's dashboard or an interior rearview mirror display that replaces the side mirrors.

[0076] In some other embodiments, the electronic devices to which the display device is applied may include not only devices with main display screens such as billboards, electronic boards, or game consoles, but also various suitable household appliances that display information via the display panel, such as refrigerators, washing machines, dryers, air conditioners, or robotic vacuum cleaners. Additionally, when the display panel has the function of transmitting light, it can be applied to various suitable electronic devices such as smart windows or transparent display devices that simultaneously display backgrounds and images. The types of electronic devices are not limited to those described above, and various other suitable applications of electronic devices not described above can also be implemented according to some embodiments of this disclosure.

[0077] Figure 5 This is a plan view of the display panel according to an embodiment. Figure 6 This is a plan view of the display panel according to an embodiment. Figure 7 This is a plan view of the display panel according to an embodiment.

[0078] refer to Figures 5 to 7 The display panel 11 may include a display area DA, a peripheral area PA, an aperture area OA, and a central area IA. The display area DA, peripheral area PA, aperture area OA, and central area IA may be defined on the display panel 11. In other words, the display panel 11 may include a substrate 100 (e.g., see...). Figure 12 Furthermore, the display area DA, the peripheral area PA, the opening area OA, and the intermediate area IA can be defined on the substrate 100 or included in the substrate 100.

[0079] In one embodiment, the peripheral region PA may at least partially or completely surround the display region DA (e.g., around its periphery). In another embodiment, the display region DA may at least partially or completely surround the intermediate region IA (e.g., around its periphery). In yet another embodiment, the intermediate region IA may at least partially or completely surround the opening region OA (e.g., around its periphery). In yet another embodiment, the intermediate region IA may be positioned between the display region DA and the opening region OA.

[0080] In this embodiment, the opening region OA can be located inside the display region DA. In this embodiment, as... Figure 5 and Figure 6 As shown, the opening area OA can be located at the upper center of the display area DA. In an embodiment, as... Figure 6 and Figure 7 As shown, the opening region OA can be provided as multiple. In an embodiment, as... Figure 6 As shown, the shapes of the multiple opening regions OA can be different from each other. In an embodiment, as... Figure 7 As shown, multiple opening regions OA can have the same or substantially the same shape (e.g., circular), but their dimensions (e.g., size) can differ from each other. In embodiments, as... Figure 7 As shown, multiple opening regions OA can be positioned in the central portion of the display area DA. The shape, size, and arrangement of the opening regions OA are not limited to... Figures 5 to 7 The shapes, sizes, and arrangements shown in the diagrams can be modified in various ways as needed or desired.

[0081] In this embodiment, an image can be displayed on the display panel 11 using a plurality of pixels PX disposed in the display area DA. The plurality of pixels PX of the display panel 11 may include light-emitting diodes (LEDs) as display elements for displaying images and pixel circuitry for driving the LEDs.

[0082] In an embodiment, the display panel 11 may have an approximately rectangular shape in a plan view. In an embodiment, such as... Figure 5 As shown, the display panel 11 may have a rectangular planar shape, having a short side extending in the x-direction and a long side extending in the y-direction. The rectangular shape may have rounded corners. In an embodiment, as... Figure 6 and Figure 7As shown, the display panel 11 may have a rectangular planar shape having a long side extending in the x-direction and a short side extending in the y-direction, and the rectangular planar shape may have rounded corners. However, the display panel 11 according to one or more embodiments is not limited to such a shape and may be provided in other suitable polygonal, elliptical, or irregular shapes. In addition, the display panel 11 may also be stretchable, such that the display panel 11 can be bent depending on the shape of the electronic device 10 to which the display panel 11 is applied or the space in which the display panel 11 is disposed.

[0083] In an embodiment, Figure 5 The display panel 11 shown can be applied to devices such as smartphones 10_1a (e.g., see...). Figure 2 The electronic device 10. In an embodiment, Figure 6 The display panel 11 shown can be applied to devices such as tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, or desktop monitor 10_1e (e.g., see...). Figure 2 The electronic device 10. In an embodiment, Figure 7 The display panel 11 shown can be applied to electronic devices 10_3, such as those used in vehicles (e.g., see...). Figure 4 The electronic device 10. In an embodiment, when the display panel 11 is applied to the electronic device 10_3 for a vehicle (e.g., see...), Figure 4 When the display panel 11 is used, it can be connected to, for example, an electronic device 10_3 for a vehicle (see, for example, see...). Figure 4 The curved surface of the display panel 11 is provided in a curved shape corresponding to the curved space (or surface) inside the vehicle in which the display panel 11 is disposed. In an embodiment, when the display panel 11 is applied to an electronic device 10_3 for a vehicle (e.g., see...), the curved surface of the display panel 11 is provided in a curved shape corresponding to the curved space (or surface) inside the vehicle in which the display panel 11 is disposed. Figure 4 When the display panel 11 has an opening area OA, it can be connected to the electronic device 10_3 for the vehicle (for example, see...). Figure 4 The area corresponds to the area of ​​other components (e.g., electronic components).

[0084] Figure 8 This is a schematic cross-sectional view of the display panel according to an embodiment. Figure 8 This is a cross-sectional view taken across the middle area IA and the opening area OA of the display panel 11. For example, Figure 8 It is along Figure 5 The cross-sectional view of the display panel 11 taken by line V-V' in the figure.

[0085] refer to Figure 8 The display panel 11 may include a display element layer DPEL, a thin film encapsulation layer TFEL, a touch sensing layer TSL, and an optical function layer OFL.

[0086] The Display Element Layer (DPEL) may include multiple pixels (PX). Each pixel (PX) may include a light-emitting diode (LED) and a pixel circuitry (PC) for driving the LED. The DPEL may include components disposed in multiple layers, including the LED and / or the pixel circuitry (PC). In one embodiment, the LED may be an organic light-emitting diode (OLED) including an organic emitting layer. In another embodiment, the LED may be an inorganic light-emitting diode comprising inorganic materials. An inorganic light-emitting diode may include a PN junction diode comprising inorganic semiconductor materials. When a voltage is applied to the PN junction diode in the forward direction, holes and electrons can be injected, and the energy generated by the recombination of holes and electrons can be converted into light energy, which can emit light of a desired color (e.g., a specific color or a predetermined color). In another embodiment, the DPEL may include quantum dot LEDs. For example, the DPEL may be an emitting layer and may include organic materials, inorganic materials, quantum dots, organic materials with quantum dots, or inorganic materials with quantum dots.

[0087] A thin-film encapsulation layer (TFEL) can be disposed on the display element layer (DPEL) and can protect the DPEL from external factors such as moisture or foreign matter. The TFEL can completely cover the DPEL. The TFEL can include at least one of an inorganic encapsulation layer containing inorganic insulating material and an organic encapsulation layer containing organic insulating material.

[0088] A touch sensing layer (TSL) can obtain coordinate information based on external inputs such as touch events. The TSL may include touch electrodes (e.g., sensing electrodes or touch electrodes) and traces connected to the touch electrodes. The TSL may be disposed on a thin-film encapsulation layer (TFEL). The TSL can detect external inputs using mutual capacitance and / or self-capacitance methods.

[0089] An optical functional layer (OFL) can be disposed on the touch sensing layer (TSL). The OFL may include a light-shielding layer to block reflections of external light that may occur in the layers beneath it. The OFL may also include color filters that can improve the efficiency of display elements, such as light-emitting diodes, in the display element layer (DPEL).

[0090] In some embodiments, a cover window may be further disposed on the optical functional layer OFL and may cover the display panel 11. The cover window may be bonded to the display panel 11 by optically clear adhesive (OCA).

[0091] Covering windows can be made of glass or plastic. Glass materials can include ultra-thin glass. ®Plastic materials may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc.

[0092] In an embodiment, the adhesive layer may be disposed between two layers selected from the various layers described above.

[0093] To improve the transmittance of the opening region OA, the display panel 11 may include a transmission opening 11OP that passes through some of the layers included in the display panel 11. The transmission opening 11OP may include openings that pass through the display element layer DPEL, the thin film encapsulation layer TFEL, the touch sensing layer TSL, and the optical functional layer OFL, respectively. The openings defined in the display element layer DPEL, the thin film encapsulation layer TFEL, the touch sensing layer TSL, and the optical functional layer OFL may overlap each other and may constitute the transmission opening 11OP defined in the display panel 11.

[0094] refer to Figure 1 as well as Figure 8 Other components of the electronic device 10 (hereinafter, components) may overlap with the opening region OA of the display panel 11. This component may overlap with the transmissive opening 11OP defined in the display panel 11. This component may be disposed below the display panel 11 (e.g., such as below the rear surface of the display panel 11). The opening region OA may be a component region (e.g., a sensor region, camera region, or speaker region, etc.) where components for adding various functions to the electronic device 10 are located. In embodiments, this component may include an input module 15, a non-video output module 16, and / or a communication module 17.

[0095] The component may include electronic elements. For example, the component may be an electronic element that uses light or sound. For example, the electronic element may include an infrared sensor, a light-using sensor, a camera that captures images by receiving light, a sensor that outputs and detects light or sound to measure distance or identify fingerprints, a small light that outputs light, or a speaker that outputs sound. Light-using electronic elements may use light of various suitable wavelength bands, such as visible light, infrared light, or ultraviolet light. The opening region OA may correspond to an area capable of transmitting light and / or sound that is output from the component to the outside or propagates from the outside toward the component (e.g., the electronic element).

[0096] Figures 9 to 11 Each is an equivalent circuit diagram of the pixels of the display panel according to an embodiment.

[0097] refer to Figure 9A light-emitting diode (LED) corresponding to a pixel can be electrically connected to a pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel circuit PC can be electrically connected to traces and voltage lines. The traces may include a scan signal line GWL and a data line DL, and the voltage lines may include a first voltage line VDDL.

[0098] The second transistor T2 is a data write transistor and can be electrically connected to the scan signal line GWL and the data line DL. The scan signal line GWL can provide the scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can transmit the data signal Dm received via the data line DL to the first transistor T1 in response to the scan signal GW received via the scan signal line GWL.

[0099] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can store a voltage corresponding to the voltage difference between the voltage received from the second transistor T2 and the first power supply voltage VDD supplied via the first voltage line VDDL.

[0100] The first transistor T1 is a driving transistor and can control the driving current flowing through the light-emitting diode (LED). The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can control the driving current flowing from the first voltage line VDDL to the LED in response to the value of the voltage stored in the storage capacitor Cst. The LED can emit light with a desired brightness (e.g., a specific brightness or a predetermined brightness) depending on the driving current. The first electrode (e.g., a pixel electrode or anode) of the LED can be electrically connected to the first transistor T1, and the second electrode (e.g., a counter electrode or cathode) can be electrically connected to the second voltage line VSSL, which supplies the second power supply voltage VSS.

[0101] Figure 9 The illustration shows a pixel circuit PC comprising a switching transistor (e.g., a second transistor T2) and a capacitor (e.g., a storage capacitor Cst). However, in another embodiment, the pixel circuit PC may include two or more switching transistors and / or two or more capacitors.

[0102] refer to Figure 10 The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. The first transistor T1 may be a driving transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be switching transistors.

[0103] The pixel circuit PC can be electrically connected to traces and voltage lines. Traces may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and transmit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first voltage line VDDL.

[0104] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint to the pixel circuit PC for initializing the first transistor T1. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, used to initialize the first electrode (e.g., pixel electrode or anode) of the light-emitting diode (LED), to the pixel circuit PC.

[0105] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting diode LED via the sixth transistor T6. The first transistor T1 can act as a driver transistor and can receive the data signal Dm according to the switching operation of the second transistor T2 to supply drive current to the light-emitting diode LED.

[0106] The second transistor T2 is a data write transistor and can be electrically connected to the scan signal line GWL and the data line DL. The second transistor T2 can be electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 can be turned on according to the scan signal GW received via the scan signal line GWL, and can perform a switching operation for transmitting the data signal Dm received via the data line DL to the first node N1.

[0107] The third transistor T3 can be electrically connected to the scan signal line GWL, and can be electrically connected to the light-emitting diode (LED) via the sixth transistor T6. The third transistor T3 can be turned on according to the scan signal GW received via the scan signal line GWL, so that the first transistor T1 can be connected as a diode.

[0108] The fourth transistor T4 is the first initialization transistor and can be electrically connected to the initialization control line GIL and the first initialization voltage line VIL1. The fourth transistor T4 can be turned on according to the initialization control signal GI received via the initialization control line GIL, and can transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate of the first transistor T1, thereby initializing the voltage at the gate of the first transistor T1. The initialization control signal GI can correspond to the scan signal of another pixel circuit in the row preceding the corresponding pixel circuit PC.

[0109] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the emitter control line EML, and can be turned on concurrently (e.g., simultaneously or substantially simultaneously) to form a current path based on the emitter control signal EM received via the emitter control line EML, allowing drive current to flow from the first voltage line VDDL towards the light-emitting diode (LED). The first electrode of the LED can be electrically connected to the first transistor T1 via the sixth transistor T6, and the second electrode can be electrically connected to the second voltage line VSSL, which supplies the second power supply voltage VSS.

[0110] The seventh transistor T7 is the second initialization transistor and can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to the bypass control signal GB received via the bypass control line GBL, and can transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting diode LED, thereby initializing the first electrode of the light-emitting diode LED.

[0111] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the gate of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the first voltage line VDDL. The storage capacitor Cst may store and maintain a voltage corresponding to the difference between the voltage of the first voltage line VDDL and the voltage of the gate of the first transistor T1, thereby maintaining the voltage applied to the gate of the first transistor T1.

[0112] refer to Figure 11 The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an auxiliary capacitor Ca. The first transistor T1 may be a driving transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be switching transistors.

[0113] The pixel circuit PC can be electrically connected to traces and voltage lines. Traces may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and transmit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, a sustaining voltage line VSL, and a first voltage line VDDL.

[0114] The first voltage line VDDL transmits the first power supply voltage VDD to the first transistor T1. The first initialization voltage line VIL1 transmits the first initialization voltage Vint to the pixel circuit PC for initializing the first transistor T1. The second initialization voltage line VIL2 transmits the second initialization voltage Vaint, used to initialize the first electrode of the light-emitting diode (LED), to the pixel circuit PC. During the initialization and data write periods, the sustain voltage line VSL provides the sustain voltage VSUS to the second node N2 (e.g., to the second capacitor electrode CE2, such as that provided to the storage capacitor Cst).

[0115] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light-emitting diode LED via the sixth transistor T6. The first transistor T1 can act as a driver transistor and can receive the data signal Dm according to the switching operation of the second transistor T2 to supply drive current to the light-emitting diode LED.

[0116] The second transistor T2 can be electrically connected to the scan signal line GWL and the data line DL, and can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 can be turned on according to the scan signal GW received via the scan signal line GWL, and can perform a switching operation for transmitting the data signal Dm received via the data line DL to the first node N1.

[0117] The third transistor T3 can be electrically connected to the scan signal line GWL, and can be electrically connected to the light-emitting diode (LED) via the sixth transistor T6. The third transistor T3 can be turned on according to the scan signal GW received via the scan signal line GWL, so that the first transistor T1 is connected by a diode, thereby compensating for the threshold voltage of the first transistor T1.

[0118] The fourth transistor T4 can be electrically connected to the initialization control line GIL and the first initialization voltage line VIL1, and can be turned on according to the initialization control signal GI received via the initialization control line GIL, so that the first initialization voltage Vint can be transmitted from the first initialization voltage line VIL1 to the gate of the first transistor T1, thereby initializing the voltage at the gate of the first transistor T1. The initialization control signal GI can correspond to the scan signal of another pixel circuit in the row preceding the corresponding pixel circuit PC.

[0119] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be electrically connected to the emitter control line EML, and can be turned on concurrently (e.g., simultaneously or substantially simultaneously) to form a current path according to the emitter control signal EM received via the emitter control line EML, allowing drive current to flow from the first voltage line VDDL toward the light-emitting diode LED. The first electrode of the light-emitting diode LED can be electrically connected to the first transistor T1 via the sixth transistor T6, and the second electrode can be electrically connected to the second voltage line VSSL supplying the second power supply voltage VSS.

[0120] The seventh transistor T7 is the second initialization transistor and can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to the bypass control signal GB received via the bypass control line GBL, so that the second initialization voltage Vaint is transmitted from the second initialization voltage line VIL2 to the first electrode of the light-emitting diode LED, thereby initializing the first electrode of the light-emitting diode LED.

[0121] The ninth transistor T9 can be electrically connected to the bypass control line GBL, the second capacitor electrode CE2 of the storage capacitor Cst, and the sustaining voltage line VSL. The ninth transistor T9 can be turned on according to the bypass control signal GB received via the bypass control line GBL, and can transmit the sustaining voltage VSUS to the second node N2 (e.g., to the second capacitor electrode CE2 of the storage capacitor Cst) during the initialization period and the data write period.

[0122] Each of the eighth transistor T8 and the ninth transistor T9 can be electrically connected to the second node N2 (e.g., to the second capacitor electrode CE2, such as being electrically connected to the storage capacitor Cst). In an embodiment, during the initialization period and the data write period, the eighth transistor T8 can be turned off and the ninth transistor T9 can be turned on, and during the transmit period, the eighth transistor T8 can be turned on and the ninth transistor T9 can be turned off.

[0123] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the gate of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0124] An auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSL, and the first electrode of the light-emitting diode (LED). While the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode of the LED and the sustaining voltage line VSL, thereby preventing or substantially preventing an increase in black brightness when the sixth transistor T6 is turned off.

[0125] Figures 9 to 11 An embodiment is shown in which the transistors of the pixel circuit PC are implemented as p-channel metal-oxide-semiconductor field-effect transistors (p-channel MOSFETs or PMOS transistors). However, this disclosure is not limited thereto. In the embodiment, Figure 9 At least one of the transistors in the pixel circuit PC (e.g., such as the first transistor T1 and the second transistor T2) can be implemented as an n-channel MOSFET (NMOS transistor). In an embodiment, Figure 10 At least one of the transistors in the pixel circuit PC (e.g., transistors T1 through T7, such as the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7) can be implemented as an NMOS transistor. For example, Figure 10 In the pixel circuit PC, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be implemented as PMOS transistors, and the third transistor T3 and the fourth transistor T4 can be implemented as NMOS transistors. In the embodiment, Figure 11 At least one of the transistors in the pixel circuit PC (e.g., transistors T1, T2, T3, T4, T5, T6, T7, T8, and T9, such as the first to ninth transistors) can be implemented as an NMOS transistor. For example, Figure 11 The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 in the pixel circuit PC can be implemented as PMOS transistors, and the third transistor T3 and the fourth transistor T4 can be implemented as NMOS transistors.

[0126] Figure 12 This is a cross-sectional view of the display area of ​​the display panel according to an embodiment.

[0127] refer to Figure 12 The display element layer DPEL, the thin film encapsulation layer TFEL, the touch sensing layer TSL, and the optical functional layer OFL can be sequentially disposed on the substrate 100.

[0128] The display element layer (DPEL) may include light-emitting diodes (LEDs) and thin-film transistors (TFTs) connected to the LEDs. For ease of explanation, Figure 12The above reference can be illustrated schematically. Figures 9 to 11 This is a part of any of the pixel circuits PCs described. In an embodiment, the thin-film transistor (TFT) connected to the light-emitting diode (LED) can be... Figures 9 to 11 The transistors shown correspond to those connected to the light-emitting diode (LED) (e.g., such as the first transistor T1 or the sixth transistor T6).

[0129] Substrate 100 may comprise a glass material or a polymer resin. In an embodiment, substrate 100 may comprise a laminated structure comprising a base layer containing a polymer resin and a barrier layer containing an inorganic insulating material. The polymer resin may comprise at least one of various suitable materials such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. The inorganic insulating material may comprise silicon oxide (SiO2) and / or silicon nitride (SiN). x ).

[0130] A first conductive layer 101 may be disposed on a substrate 100. In an embodiment, the first conductive layer 101 may include power lines and / or traces. In an embodiment, the first conductive layer 101 may be disposed beneath a semiconductor layer 103 (e.g., an active pattern ACT) to block radio waves and / or light originating from the lower part of the display panel 11 from being transmitted to the active pattern ACT. In an embodiment, the first conductive layer 101 may include a metal (e.g., a metal with light-shielding properties). In an embodiment, the first conductive layer 101 may include at least one of various suitable materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure.

[0131] A first insulating layer 102 may be disposed on the first conductive layer 101. The first insulating layer 102 may completely cover the first conductive layer 101. The first insulating layer 102 may have a flat or substantially flat upper surface. The first insulating layer 102 may include an inorganic insulating material. In embodiments, the first insulating layer 102 may include materials such as SiO2 and SiN. x The first insulating layer 102 may be at least one of various suitable materials, including silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2), and may have a single-layer or multi-layer structure. In an embodiment, the first insulating layer 102 may be a buffer layer.

[0132] A thin-film transistor (TFT) and an inorganic insulating layer (IIL) can be disposed on the first insulating layer 102. The inorganic insulating layer IIL can include multiple layers, and each element of the TFT can be disposed between corresponding layers of the inorganic insulating layer IIL. The TFT can include an active pattern ACT and a gate electrode GE. The inorganic insulating layer IIL can include a second insulating layer 104, a third insulating layer 106, and a fourth insulating layer 108.

[0133] Semiconductor layer 103 may be disposed on first insulating layer 102. Semiconductor layer 103 may include an active pattern ACT. The active pattern ACT may include a source region overlapping with source electrode SE, a drain region overlapping with drain electrode DE, and a channel region between the source and drain regions. The channel region may overlap with gate electrode GE. The source and drain regions may be doped with impurities (e.g., dopant).

[0134] A second insulating layer 104 may be disposed on the semiconductor layer 103. The second insulating layer 104 may cover the semiconductor layer 103 (e.g., an active pattern ACT). The second insulating layer 104 may include an inorganic insulating material. In embodiments, the second insulating layer 104 may include materials such as SiO2 and SiN. x The second insulating layer 104 may be at least one of various suitable materials, including SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2, and may have a single-layer or multi-layer structure. In an embodiment, the second insulating layer 104 may be the first gate insulating layer.

[0135] A storage capacitor Cst may be disposed on the second insulating layer 104. The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap each other, and the second capacitor electrode CE2 may be disposed on the first capacitor electrode CE1.

[0136] The second conductive layer 105 may be disposed on the second insulating layer 104. The second conductive layer 105 may include the gate electrode GE of the thin-film transistor TFT and the first capacitor electrode CE1 of the storage capacitor Cst. In an embodiment, as... Figure 12 As shown, the gate electrode GE and the first capacitor electrode CE1 can be integrally provided as a single unit. In an embodiment, the gate electrode GE and the first capacitor electrode CE1 can be provided separately from each other. In an embodiment, the second conductive layer 105 may include at least one of various suitable materials such as Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and Cu, and may have a single-layer structure or a multi-layer structure.

[0137] A third insulating layer 106 may be disposed on the second conductive layer 105. The third insulating layer 106 may cover the second conductive layer 105 (e.g., a gate electrode GE and a first capacitor electrode CE1). The third insulating layer 106 may include an inorganic insulating material. In embodiments, the third insulating layer 106 may include materials such as SiO2 and SiN. x The third insulating layer 106 may be at least one of various suitable materials, including SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2, and may have a single-layer or multi-layer structure. In an embodiment, the third insulating layer 106 may be a second gate insulating layer.

[0138] The third conductive layer 107 may be disposed on the third insulating layer 106. The third conductive layer 107 may include a second capacitor electrode CE2. The second capacitor electrode CE2 may overlap with the first capacitor electrode CE1. In embodiments, the third conductive layer 107 may include at least one of various suitable materials such as Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W and Cu, and may have a single-layer structure or a multi-layer structure.

[0139] A fourth insulating layer 108 may be disposed on the third conductive layer 107. The fourth insulating layer 108 may cover the third conductive layer 107 (e.g., such as the second capacitor electrode CE2). The fourth insulating layer 108 may include an inorganic insulating material. In embodiments, the fourth insulating layer 108 may include materials such as SiO2 and SiN. x The fourth insulating layer 108 may be at least one of various suitable materials, including SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2, and may have a single-layer or multi-layer structure. In an embodiment, the fourth insulating layer 108 may be an interlayer insulating layer.

[0140] A fourth conductive layer 109 may be disposed on a fourth insulating layer 108. The fourth conductive layer 109 may include a source electrode SE and a drain electrode DE. The source electrode SE may overlap with the source region of the active pattern ACT. The source electrode SE may be connected to the active pattern ACT (e.g., the source region) through an opening defined in (e.g., penetrating) an inorganic insulating layer IIL (e.g., the second to fourth insulating layers 104, 106, and 108). The drain electrode DE may overlap with the drain region of the active pattern ACT. The drain electrode DE may be connected to the active pattern ACT (e.g., the drain region) through an opening defined in (e.g., penetrating) an inorganic insulating layer IIL (e.g., the second to fourth insulating layers 104, 106, and 108). In embodiments, the fourth conductive layer 109 may include at least one of various suitable materials such as Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and Cu, and may have a single-layer or multi-layer structure.

[0141] Figure 12 An embodiment is shown in which the second to fourth insulating layers 104, 106 and 108 each have a flat or substantially flat upper surface. However, this disclosure is not limited thereto, and the second to fourth insulating layers 104, 106 and 108 may each have an upper surface shape (e.g., unevenness) corresponding to the shape of the layer disposed thereunder.

[0142] A fifth insulating layer 110 may be disposed on the fourth conductive layer 109. The fifth insulating layer 110 may cover the fourth conductive layer 109 (e.g., such as a source electrode SE and a drain electrode DE). The fifth insulating layer 110 may have a flat or substantially flat upper surface. The fifth insulating layer 110 may include an organic insulating material. In embodiments, the fifth insulating layer 110 may include at least one of various suitable materials such as general-purpose polymers (such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and vinyl alcohol polymers, and the fifth insulating layer 110 may have a single-layer or multi-layer structure. In embodiments, the fifth insulating layer 110 may be a first via layer.

[0143] A fifth conductive layer 111 may be disposed on a fifth insulating layer 110. The fifth conductive layer 111 may include a contact metal that connects the fourth conductive layer 109 (e.g., drain electrode DE) to the first electrode 113 of the light-emitting diode (LED). The fifth conductive layer 111 may further include gate electrodes, traces, or power lines of other transistors. In embodiments, the fifth conductive layer 111 may include at least one of various suitable materials such as Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and Cu, and may have a single-layer or multi-layer structure.

[0144] A sixth insulating layer 112 may be disposed on the fifth conductive layer 111. The sixth insulating layer 112 may cover the fifth conductive layer 111. The sixth insulating layer 112 may have a flat or substantially flat upper surface. The sixth insulating layer 112 may include an organic insulating material. In embodiments, the sixth insulating layer 112 may include at least one of various suitable materials such as general-purpose polymers (such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and vinyl alcohol polymers, and the sixth insulating layer 112 may have a single-layer or multi-layer structure. In embodiments, the sixth insulating layer 112 may be a second through-hole layer.

[0145] A light-emitting diode (LED) can be disposed on a sixth insulating layer 112. The LED may include a first electrode 113 and a second electrode 119 opposite to each other, and an intermediate layer 115 between the first electrode 113 and the second electrode 119. In an embodiment, the first electrode 113 of the LED may correspond to the anode, and the second electrode 119 may correspond to the cathode.

[0146] The first electrode 113 of the light-emitting diode (LED) can be disposed on the sixth insulating layer 112. The first electrode 113 can be connected to the fifth conductive layer 111 through an opening defined in (e.g., penetrating) the sixth insulating layer 112. The first electrode 113 can be connected to (e.g., electrically connected to) the thin-film transistor (TFT) through the fifth conductive layer 111 and the drain electrode DE. The first electrode 113 may comprise a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). The first electrode 113 may comprise a reflective film comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or suitable compounds thereof. However, the elements and materials of the first electrode 113 are not limited to those described above and can be modified in various ways as needed or desired.

[0147] A pixel defining layer 114 may be disposed on a sixth insulating layer 112. The pixel defining layer 114 may cover the edge of the first electrode 113. In other words, the pixel defining layer 114 may be open to expose the central portion of the first electrode 113. The size and shape of the emitting region of the light-emitting diode (LED) may be determined (e.g., may be defined by) the opening defined in (e.g., penetrating) the pixel defining layer 114. In embodiments, the pixel defining layer 114 may comprise an organic insulating material. In embodiments, the pixel defining layer 114 may comprise at least one of various suitable materials such as general polymers (e.g., benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and vinyl alcohol polymers, and the pixel defining layer 114 may have a single-layer structure or a multilayer structure.

[0148] An intermediate layer 115 may be disposed on the first electrode 113. The intermediate layer 115 may include a first common layer 116 and a second common layer 118 disposed on the pixel defining layer 114, and an emission layer 117 disposed in an opening defined in (e.g., penetrating) the pixel defining layer 114. The first common layer 116 may be disposed on the second common layer 118. In an embodiment, the first common layer 116 may be disposed on the pixel defining layer 114, the emission layer 117 may be disposed on the first common layer 116 in an opening defined in (e.g., penetrating) the pixel defining layer 114, and the second common layer 118 may be disposed on the first common layer 116 to cover the emission layer 117. In other words, the emission layer 117 may be disposed in an opening defined in (e.g., penetrating) the pixel defining layer 114, and may be disposed between the first common layer 116 and the second common layer 118.

[0149] The emitting layer 117 may comprise a low molecular weight or polymeric material that emits light of a desired color (e.g., a specific or predetermined color) when an electric current flows. The first common layer 116 may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL). The second common layer 118 may comprise a hole transport layer (HTL) and / or a hole injection layer (HIL). In some embodiments, the first common layer 116 or the second common layer 118 may be omitted as needed or desired. In some embodiments, the first common layer 116 and the second common layer 118 may be interchanged.

[0150] The second electrode 119 may be disposed on the intermediate layer 115. For example, the second electrode 119 may be disposed on the second common layer 118. The second electrode 119 may be configured to completely cover the intermediate layer 115. The second electrode 119 may include a conductive material. For example, the second electrode 119 may include a transparent layer (or a translucent layer) comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or suitable alloys thereof. As another example, the second electrode 119 may further include a layer comprising an oxide such as ITO, IZO, ZnO, or In2O3 on a transparent layer (or translucent layer) comprising one or more of the above materials.

[0151] A thin-film encapsulation layer (TFEL) can be disposed on the second electrode 119 and can completely cover the light-emitting diode (LED). The TFEL can include at least one inorganic layer and at least one organic layer. In an embodiment, the TFEL can include a first inorganic encapsulation layer 120, a second inorganic encapsulation layer 122, and an organic encapsulation layer 121 between the first and second inorganic encapsulation layers 120 and 122. In an embodiment, the first and second inorganic encapsulation layers 120 and 122 can each have an upper surface shape (e.g., unevenness) according to the shape of the layer disposed beneath them. In an embodiment, the organic encapsulation layer 121 can have a flat or substantially flat upper surface.

[0152] The first inorganic encapsulation layer 120 and / or the second inorganic encapsulation layer 122 may include materials such as SiO2 and SiN. x The organic encapsulation layer 121 may be at least one of a variety of suitable materials, including SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2, and may have a single-layer or multi-layer structure. The organic encapsulation layer 121 may include a polymeric material. Examples of polymeric materials may include silicone resins, acrylic resins, epoxy resins, polyimide, and polyethylene.

[0153] A touch sensing layer (TSL) may be disposed on a thin-film encapsulation layer (TFEL). The touch sensing layer (TSL) may include touch electrode layers for detecting external inputs (e.g., touch events) and touch insulating layers between the electrode layers. The touch sensing layer (TSL) may include a first touch insulating layer 123, a first touch electrode layer 124, a second touch insulating layer 125, a second touch electrode layer 126, and a third touch insulating layer 127.

[0154] A first touch insulating layer 123 may be disposed on a thin-film encapsulation layer TFEL (e.g., on a second inorganic encapsulation layer 122 such as on the thin-film encapsulation layer TFEL). A first touch electrode layer 124 may be disposed on the first touch insulating layer 123. A second touch insulating layer 125 may be disposed on the first touch electrode layer 124 and may cover the first touch electrode layer 124. A second touch electrode layer 126 may be disposed on the second touch insulating layer 125. A third touch insulating layer 127 may be disposed on the second touch electrode layer 126 and may cover the second touch electrode layer 126. The second touch electrode layer 126 may be connected to the first touch electrode layer 124 through an opening defined in (e.g., penetrating) the second touch insulating layer 125. In an embodiment, the second touch electrode layer 126 may include a sensing electrode, and the first touch electrode layer 124 may include a bridging electrode.

[0155] In one embodiment, the first touch insulating layer 123 may include an inorganic insulating material. In another embodiment, the first touch insulating layer 123 may include materials such as SiO2 or SiN. x It can be at least one of various suitable materials such as SiON, Al2O3, TiO2, Ta2O5, HfO2 and ZnO2, and can have a single-layer structure or a multi-layer structure.

[0156] In an embodiment, the second touch insulating layer 125 and the third touch insulating layer 127 may comprise organic insulating materials. In an embodiment, the second touch insulating layer 125 and / or the third touch insulating layer 127 may comprise acrylic organic insulating materials. In an embodiment, the second touch insulating layer 125 and / or the third touch insulating layer 127 may have a flat or substantially flat upper surface.

[0157] The first touch electrode layer 124 and the second touch electrode layer 126 may not completely overlap with the emitting region of the light-emitting diode (LED). In an embodiment, the first touch electrode layer 124 and the second touch electrode layer 126 may not overlap with the emitting layer 117 of the LED. In other words, the first touch electrode layer 124 and the second touch electrode layer 126 may have openings that overlap with the emitting region of the LED or the emitting layer 117.

[0158] An optical functional layer (OFL) can be disposed on the touch sensing layer (TSL). The optical functional layer (OFL) may include a light-shielding layer 128, a color filter 129, and an outer coating layer 130. The outer coating layer 130 may cover the light-shielding layer 128 and the color filter 129, and may have a flat or substantially flat upper surface.

[0159] A light-shielding layer 128 may be disposed on the touch sensing layer TSL (e.g., on the third touch insulating layer 127). The light-shielding layer 128 may include a light-shielding material and may cover the first touch electrode layer 124 and the second touch electrode layer 126 to prevent or substantially prevent the first touch electrode layer 124 and the second touch electrode layer 126 from reflecting external light and becoming visible to the user. However, the light-shielding layer 128 is not limited thereto. The light-shielding layer 128 may have openings that allow light emitted from the light-emitting diode (LED) to pass through it. The openings of the light-shielding layer 128 may overlap with the LED (e.g., such as the emitting layer 117).

[0160] A color filter 129 may be disposed on a light-shielding layer 128. The color filter 129 may overlap with an opening defined in (e.g., penetrating) the light-shielding layer 128, and a portion of the color filter 129 may be disposed within the opening defined in (e.g., penetrating) the light-shielding layer 128. The color filter 129 may transmit light of a color (e.g., wavelength range) corresponding to the light emitted from the light-emitting diode (LED). For example, when the emitting layer 117 of the LED emits red light, the color filter 129 may transmit light within the red wavelength range.

[0161] Figure 13 This is a plan view of the display panel according to an embodiment.

[0162] refer to Figure 13 The transmission opening 11OP of the display panel 11 can correspond to the opening area OA. In other words, the transmission opening 11OP that overlaps with the opening area OA can be defined in the display panel 11.

[0163] Display panel 11 may include at least one first dam D1 in the intermediate region IA. In an embodiment, the first dam D1 may at least partially or completely surround the opening region OA or the transmission opening 11OP (e.g., around its periphery). In an embodiment, the first dam D1 may have a frame shape or a closed-loop shape. In an embodiment, the first dam D1 may correspond to the shape of the intermediate region IA.

[0164] In one embodiment, the display panel 11 may have a plurality of first dams D1. In another embodiment, the plurality of first dams D1 may be concentrically arranged. In yet another embodiment, one of the plurality of first dams D1 may at least partially or completely surround another of the plurality of first dams D1 (e.g., around its periphery). In yet another embodiment, the plurality of first dams D1 may have a plurality of closed loops having concentric shapes.

[0165] For ease of explanation, Figure 13 The second dam D2, the third dam D3, and the fourth dam D4, which are described in more detail below, are not shown (see, for example, see...). Figure 14However, this disclosure is not limited to or subject to this limitation.

[0166] Figure 14 This is a cross-sectional view of the display panel according to an embodiment. Figure 14 For example, along Figure 13 The cross-sectional view of the display panel is taken by line XIII-XIII'.

[0167] refer to Figure 14 The first insulating layer 102 may be disposed on the substrate 100. In embodiments, the first insulating layer 102 may be omitted as needed or desired. A first dam D1, a second dam D2, a third dam D3, and a fourth dam D4 may be disposed on the first insulating layer 102. In embodiments, a plurality of first dams D1 may be disposed on the first insulating layer 102. Figure 14 Two first dams D1 are shown. However, this disclosure is not limited to the specific number of first dams D1. In an embodiment, one first dam D1 may be provided, or N first dams D1 may be provided (where N is a natural number of 3 or greater).

[0168] At least one first retaining dam D1, a second retaining dam D2, a third retaining dam D3, and a fourth retaining dam D4 can be disposed in the intermediate region IA. In an embodiment, at least one first retaining dam D1, a second retaining dam D2, a third retaining dam D3, and a fourth retaining dam D4 can be sequentially disposed in a direction away from the opening region OA. In an embodiment, reference... Figure 13 as well as Figure 14 The second dam D2 can be disposed between the first dam D1 and the display area DA. In other words, the first dam D1 can be disposed between the second dam D2 and the opening area OA. In an embodiment, the second dam D2 can be disposed between the first dam D1 and the third dam D3. In an embodiment, the third dam D3 can be disposed between the second dam D2 and the fourth dam D4.

[0169] At least one first groove D1G can be confined in the first dam D1. Figure 14 An embodiment in which three first grooves D1G are defined within a first dam D1 is shown, but this disclosure is not limited thereto. The number of first grooves D1G defined within a first dam D1 can be modified in various ways as needed or desired. In an embodiment, the first grooves D1G may be defined in the upper surface of the first dam D1 (e.g., a surface such as one facing the z-direction). In an embodiment, the first grooves D1G may be defined, for example, in the form of blind holes that do not pass through the first dam D1.

[0170] In an embodiment, the first dam D1 may include an organic insulating material.

[0171] In one embodiment, the first dam D1 may comprise the same material as the fifth insulating layer 110. In another embodiment, the first dam D1 may be formed using the same process as the fifth insulating layer 110. In yet another embodiment, the first dam D1 may be considered part of the fifth insulating layer 110.

[0172] In one embodiment, the first dam D1 may comprise the same material as the sixth insulating layer 112. In another embodiment, the first dam D1 may be formed using the same process as the sixth insulating layer 112. In yet another embodiment, the first dam D1 may be considered part of the sixth insulating layer 112.

[0173] In the embodiment, reference Figure 12 as well as Figure 14 The first dam D1 may comprise the same material as the pixel defining layer 114. In an embodiment, the first dam D1 may be formed in the same process as the pixel defining layer 114. In an embodiment, the first dam D1 may be considered as part of the pixel defining layer 114.

[0174] In an embodiment, the first dam D1 may be provided as a separate organic insulating layer (e.g., a spacer layer) distinct from the fifth insulating layer 110, the sixth insulating layer 112, and the pixel defining layer 114. In an embodiment, the spacer layer may comprise an organic insulating material. In an embodiment, the spacer layer may comprise at least one of various suitable materials such as general-purpose polymers (e.g., benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and vinyl alcohol polymers, and the spacer layer may have a single-layer or multi-layer structure.

[0175] The second dam D2 may be disposed on the inorganic insulating layer IIL extending into the intermediate region IA. In an embodiment, the second dam D2 may include a first-first metal portion D2a, a first organic portion D2b, and a first-second metal portion D2c. The first organic portion D2b may include a first-first organic portion D2b1 and a first-second organic portion D2b2.

[0176] The first-first metal portion D2a may be disposed on the inorganic insulating layer IIL. In an embodiment, the first-first metal portion D2a may be connected to the first conductive layer 101 via an opening defined in (e.g., penetrating therethrough) the inorganic insulating layer IIL and the first insulating layer 102. In an embodiment, the first-first metal portion D2a may comprise the same material as the fourth conductive layer 109. In an embodiment, the first-first metal portion D2a and the fourth conductive layer 109 may be formed in the same process as each other. In an embodiment, the first-first metal portion D2a may be considered as part of the fourth conductive layer 109.

[0177] In one embodiment, the first organic portion D2b1 may be disposed on the first metal portion D2a. In another embodiment, the first organic portion D2b1 may completely cover the first metal portion D2a. In yet another embodiment, the first organic portion D2b1 may comprise the same material as the fifth insulating layer 110. In yet another embodiment, the first organic portion D2b1 and the fifth insulating layer 110 may be formed in the same process. In yet another embodiment, the first organic portion D2b1 may be considered part of the fifth insulating layer 110.

[0178] In one embodiment, the first-second organic portion D2b2 may be disposed on the first-second metal portion D2c. In another embodiment, the first-second organic portion D2b2 may partially cover the first-second metal portion D2c. In yet another embodiment, the first-second organic portion D2b2 may comprise the same material as the sixth insulating layer 112. In yet another embodiment, the first-second organic portion D2b2 may be formed in the same process as the sixth insulating layer 112. In yet another embodiment, the first-second organic portion D2b2 may be considered part of the sixth insulating layer 112.

[0179] The first-second metal portion D2c may be disposed within the first organic portion D2b. In an embodiment, the first-second metal portion D2c may be disposed between the first-first organic portion D2b1 and the first-second organic portion D2b2. In an embodiment, the first-second metal portion D2c may protrude beyond the side surface of the first organic portion D2b (e.g., beyond the side surfaces of the first-first organic portion D2b1 and the first-second organic portion D2b2). In other words, the first-second metal portion D2c and the first organic portion D2b may form an undercut (e.g., pointed) structure. In an embodiment, the first-second metal portion D2c may protrude from the side surface of the first organic portion D2b in a direction toward the opening region OA. In an embodiment, the first-second metal portion D2c may protrude from the side surface of the first organic portion D2b in a direction toward the display region DA (e.g., see...). Figure 13It protrudes in the direction of ).

[0180] In one embodiment, the second electrode 119 may extend into the intermediate region IA. In another embodiment, the second electrode 119 may be disconnected by an undercut structure formed by the first-second metal portion D2c and the first organic portion D2b. In another embodiment, the second electrode 119 may be disconnected at the edge of the first-second metal portion D2c that protrudes beyond the side surface of the first organic portion D2b. In yet another embodiment, the second electrode 119 may be in direct contact with the upper surface of the portion of the first-second metal portion D2c that protrudes beyond the side surface of the first organic portion D2b.

[0181] The third dam D3 may be disposed on the inorganic insulating layer IIL extending into the intermediate region IA. In an embodiment, the third dam D3 may include a second-first metal portion D3a, a second organic portion D3b, and a second-second metal portion D3c. The second organic portion D3b may include a second-first organic portion D3b1 and a second-second organic portion D3b2.

[0182] The second-first metal portion D3a may be disposed on the inorganic insulating layer IIL. In an embodiment, the second-first metal portion D3a may comprise the same material as the fourth conductive layer 109. In an embodiment, the second-first metal portion D3a and the fourth conductive layer 109 may be formed in the same process. In an embodiment, the second-first metal portion D3a may be considered as part of the fourth conductive layer 109.

[0183] In one embodiment, the second-first organic portion D3b1 may be disposed on the second-first metal portion D3a. In another embodiment, the second-first organic portion D3b1 may cover the second-first metal portion D3a. In yet another embodiment, the second-first organic portion D3b1 may comprise the same material as the fifth insulating layer 110. In yet another embodiment, the second-first organic portion D3b1 and the fifth insulating layer 110 may be formed in the same process. In yet another embodiment, the second-first organic portion D3b1 may be considered part of the fifth insulating layer 110.

[0184] In an embodiment, the second-second organic portion D3b2 may be disposed on the second-second metal portion D3c. In an embodiment, the second-second organic portion D3b2 may partially cover the second-second metal portion D3c. In an embodiment, the second-second organic portion D3b2 may comprise the same material as the sixth insulating layer 112. In an embodiment, the second-second organic portion D3b2 may be formed in the same process as the sixth insulating layer 112. In an embodiment, the second-second organic portion D3b2 may be considered part of the sixth insulating layer 112.

[0185] The second-second metal portion D3c may be disposed within the second organic portion D3b. In an embodiment, the second-second metal portion D3c may be disposed between the second-first organic portion D3b1 and the second-second organic portion D3b2. In an embodiment, the second-second metal portion D3c may protrude beyond the side surface of the second organic portion D3b (e.g., beyond the side surface of the second-first organic portion D3b1 and the side surface of the second-second organic portion D3b2). In other words, the second-second metal portion D3c and the second organic portion D3b may form an undercut (or tip) structure. In an embodiment, the third dam D3 may include two or more second-second metal portions D3c. In an embodiment, one of the second-second metal portions D3c may protrude from the side surface of the second organic portion D3b in a direction toward the opening region OA. In an embodiment, another of the second-second metal portions D3c may protrude from the side surface of the second organic portion D3b in a direction toward the display region DA (e.g., see...). Figure 13 The second-second metal portion D3c may be connected to the second-first metal portion D3a via an opening defined in (e.g., penetrating) the second-first organic portion D3b1.

[0186] In one embodiment, the second electrode 119 can be disconnected by an undercut structure formed by the second-second metal portion D3c and the second organic portion D3b. In another embodiment, the second electrode 119 can be disconnected at the edge of the second-second metal portion D3c that protrudes beyond the side surface of the second organic portion D3b. In yet another embodiment, the second electrode 119 can be in direct contact with the upper surface of the portion of the second-second metal portion D3c that protrudes beyond the side surface of the second organic portion D3b.

[0187] The fourth dam D4 may be disposed on the inorganic insulating layer IIL extending into the intermediate region IA. In an embodiment, the fourth dam D4 may include a third-first metal portion D4a, a third organic portion D4b, and a third-second metal portion D4c. The third organic portion D4b may include a third-first organic portion D4b1 and a third-second organic portion D4b2.

[0188] The third-first metal portion D4a may be disposed on the inorganic insulating layer IIL. In an embodiment, the third-first metal portion D4a may be connected to the first conductive layer 101 via an opening defined in (e.g., penetrating) the inorganic insulating layer IIL and the first insulating layer 102. In an embodiment, the third-first metal portion D4a may comprise the same material as the fourth conductive layer 109. In an embodiment, the third-first metal portion D4a and the fourth conductive layer 109 may be formed in the same process as each other. In an embodiment, the third-first metal portion D4a may be considered as part of the fourth conductive layer 109.

[0189] In an embodiment, the third-first organic portion D4b1 may be disposed on the third-first metal portion D4a. In an embodiment, the third-first organic portion D4b1 may completely cover the third-first metal portion D4a. In an embodiment, the third-first organic portion D4b1 may comprise the same material as the fifth insulating layer 110. In an embodiment, the third-first organic portion D4b1 and the fifth insulating layer 110 may be formed in the same process. In an embodiment, the third-first organic portion D4b1 may be considered part of the fifth insulating layer 110.

[0190] In an embodiment, the third-second organic portion D4b2 may be disposed on the third-second metal portion D4c. In an embodiment, the third-second organic portion D4b2 may partially cover the third-second metal portion D4c. In an embodiment, the third-second organic portion D4b2 may comprise the same material as the sixth insulating layer 112. In an embodiment, the third-second organic portion D4b2 may be formed in the same process as the sixth insulating layer 112. In an embodiment, the third-second organic portion D4b2 may be considered part of the sixth insulating layer 112.

[0191] The third-second metal portion D4c may be disposed within the third organic portion D4b. In an embodiment, the third-second metal portion D4c may be disposed between the third-first organic portion D4b1 and the third-second organic portion D4b2. In an embodiment, the third-second metal portion D4c may protrude beyond the side surface of the third organic portion D4b (e.g., beyond the side surface of the third-first organic portion D4b1 and the side surface of the third-second organic portion D4b2). In other words, the third-second metal portion D4c and the third organic portion D4b may form an undercut (or tip) structure. In an embodiment, the third-second metal portion D4c may protrude from the side surface of the third organic portion D4b toward the display area DA (e.g., see...). Figure 13In an embodiment, the third-second metal portion D4c may protrude from the side surface of the third organic portion D4b in the direction toward the opening region OA.

[0192] In one embodiment, the second electrode 119 can be disconnected by an undercut structure formed by the third-second metal portion D4c and the third organic portion D4b. In another embodiment, the second electrode 119 can be disconnected at the edge of the third-second metal portion D4c that protrudes beyond the side surface of the third organic portion D4b. In yet another embodiment, the second electrode 119 can be in direct contact with the upper surface of the portion of the third-second metal portion D4c that protrudes beyond the side surface of the third organic portion D4b.

[0193] The first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122 can extend to the intermediate region IA and can cover the first barrier D1, the second barrier D2, the third barrier D3, and the fourth barrier D4. In an embodiment, the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122 can be disconnected by an undercut structure formed by the second-second metal portion D3c and the second organic portion D3b. In an embodiment, the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122 may not be disconnected by the undercut structure formed by the first-second metal portion D2c and the first organic portion D2b. In other words, the first inorganic encapsulation layer 120 can extend integrally and cover the upper, side, and lower surfaces of the portion of the first-second metal portion D2c that protrudes beyond the side surface of the first organic portion D2b. An organic encapsulation layer 121 can be disposed between the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122. In an embodiment, the organic encapsulation layer 121 can be disposed between the fourth barrier D4 and the display area DA (e.g., see...). Figure 13 Between the first inorganic encapsulation layer 120 and / or between the third dam D3 and the fourth dam D4. A portion of the first inorganic encapsulation layer 120 may be disposed within the first groove D1G of the first dam D1.

[0194] Figure 15 This is an enlarged cross-sectional view of the display panel according to an embodiment. For example, Figure 15 This is an enlarged cross-sectional view of the first retaining dam, D1.

[0195] refer to Figure 15 At least one first groove D1G can be defined in the first dam D1, and a portion of the first inorganic encapsulation layer 120 can be disposed within the first groove D1G of the first dam D1.

[0196] In an embodiment, the first dam D1 may include a first edge ED1 and a second edge ED2 defining a first groove D1G. The first edge ED1 and the second edge ED2 may be edges of the first dam D1 located on opposite sides of the first groove D1G. The first edge ED1 and the second edge ED2 may face each other. In an embodiment, the portion of the first inorganic encapsulation layer 120 disposed on and overlapping the first edge ED1 may be defined as a first portion 1201 of the first inorganic encapsulation layer 120. In an embodiment, the portion of the first inorganic encapsulation layer 120 disposed on and overlapping the second edge ED2 may be defined as a second portion 1202 of the first inorganic encapsulation layer 120. In an embodiment, the first portion 1201 and the second portion 1202 of the first inorganic encapsulation layer 120 may face each other. In an embodiment, the first portion 1201 and the second portion 1202 of the first inorganic encapsulation layer 120 may contact each other in the region overlapping with the first groove D1G of the first dam D1. In an embodiment, when the first portion 1201 and the second portion 1202 of the first inorganic encapsulation layer 120 are in contact with each other, the second inorganic encapsulation layer 122 may not be disposed within the first groove D1G of the first dam D1. However, this disclosure is not limited to the case where the second inorganic encapsulation layer 122 is not disposed within the first groove D1G of the first dam D1, and the second inorganic encapsulation layer 122 may be disposed within one of the plurality of first grooves D1G provided in the first dam D1, but not within the other first groove D1G.

[0197] In an embodiment, the thickness of the first inorganic encapsulation layer 120 disposed on the upper surface of the first dam D1 can be defined as a first thickness 120t. In an embodiment, the width of the first groove D1G of the first dam D1 (e.g., the distance between the first edge ED1 and the second edge ED2) can be defined as a first width Gw. In an embodiment, the first width Gw can be approximately 1.5 to 2 times the first thickness 120t.

[0198] Figure 16 This is a cross-sectional view of the display panel according to an embodiment. Figure 16 It can be, for example, along Figure 13 The cross-sectional view of the display panel is taken by line XIII-XIII'.

[0199] refer to Figure 16A portion of the lower surface of the first inorganic encapsulation layer 120 disposed on the first dam D1 can be spaced apart from a portion of the upper surface of the first dam D1. When the portion of the lower surface of the first inorganic encapsulation layer 120 is spaced apart from the portion of the upper surface of the first dam D1, a plurality of first dams D1 are provided, and this portion of the lower surface of the first inorganic encapsulation layer 120 can be spaced apart from the upper surface of one of the plurality of first dams D1, but another portion of the lower surface of the first inorganic encapsulation layer 120 can remain in contact with the upper surface of another of the plurality of first dams D1, or this portion of the lower surface of the first inorganic encapsulation layer 120 can be spaced apart from a portion of the upper surface of one first dam D1, but another portion of the lower surface of the first inorganic encapsulation layer 120 can remain in contact with another portion of the upper surface of the same first dam D1. In other words, a gap can exist between the first dam D1 and the first inorganic encapsulation layer 120. Figure 16 An embodiment is shown in which a gap appears between the first dam D1 adjacent to the second dam D2 and the first inorganic encapsulation layer 120. However, this disclosure is not limited thereto. In the embodiment, the gap may appear between the first dam D1 adjacent to the opening region OA and the first inorganic encapsulation layer 120. In the embodiment, the gap may appear between the first dam D1 adjacent to the second dam D2 and the inorganic encapsulation layer 120, and between the first dam D1 adjacent to the opening region OA and the inorganic encapsulation layer 120.

[0200] The gap may occur due to the laser cutting process and / or the transmission opening 11OP forming process of the method for manufacturing the display panel as described below. The first dam D1 and the first groove D1G can prevent (or at least reduce) the gap from extending into the intermediate region IA, and can prevent (or at least reduce) the occurrence of cracks in the first inorganic encapsulation layer 120 and / or the second inorganic encapsulation layer 122 in the region adjacent to the edge of the inorganic insulating layer 1IL. In this process, the gap may appear partially between the first inorganic encapsulation layer 120 and a portion of the first dam D1, but it is understood that the first dam D1 and the first groove D1G are used to reduce (or minimize) the gap. Figure 14 The embodiments shown can be understood as embodiments in which the gap is prevented (e.g., completely prevented) by the first dam D1 and the first groove D1G, and Figure 15 The embodiments shown are to be understood as embodiments in which the gap is at least reduced, although not completely prevented. Reference is made below. Figures 18A to 18G The principle by which the first dam D1 and the first groove D1G reduce this gap is described in more detail.

[0201] Figure 17 This is a cross-sectional view of the display panel according to an embodiment. Figure 17 It can be, for example, along Figure 13 The cross-sectional view of the display panel is taken by line XIII-XIII'.

[0202] refer to Figure 17 The organic encapsulation layer 121 can be disposed between adjacent first dams D1. In an embodiment, the organic encapsulation layer 121 can be disposed between the first dam D1 and the second dam D2. In an embodiment, in the region between adjacent first dams D1, the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122 can be spaced apart from each other by the organic encapsulation layer 121 disposed therebetween. In an embodiment, in the region overlapping with the first dam D1, the organic encapsulation layer 121 may not be disposed between the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122. In an embodiment, in the region overlapping with the first dam D1, the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122 can be in direct contact with each other.

[0203] An organic encapsulation layer 121 disposed in the region between adjacent first dams D1 can help prevent (or at least reduce) the aforementioned gap.

[0204] Figures 18A to 18G These are cross-sectional views illustrating various processes of a method for manufacturing a display panel according to some embodiments.

[0205] refer to Figure 18A A first insulating layer 102, an inorganic insulating layer 111, a fourth conductive layer 109, a fifth insulating layer 110, a fifth conductive layer 111, a sixth insulating layer 112, and a second electrode 119 can be formed on the substrate 100. In the current stage of the process, a second dam D2, a third dam D3, and a fourth dam D4 can be formed in the intermediate region 1A. A first internal organic portion IDa and a second internal organic portion IDa can be formed in the opening region 0A. The second internal organic portion IDa can be disposed on the first internal organic portion IDa and can cover the first internal organic portion IDa. In an embodiment, the second internal organic portion IDa can cover the upper surface and side surface of the first internal organic portion IDa.

[0206] In one embodiment, the first internal organic portion IDa may comprise the same material as the sixth insulating layer 112. In another embodiment, the first internal organic portion IDa may be formed in the same process as the sixth insulating layer 112. In yet another embodiment, the first internal organic portion IDa may be considered part of the sixth insulating layer 112.

[0207] In the embodiment, reference Figure 12 as well as Figure 18AThe second internal organic portion IDb may include the same material as the pixel defining layer 114. In an embodiment, the second internal organic portion IDb may be formed in the same process as the pixel defining layer 114. In an embodiment, the second internal organic portion IDb may be considered as part of the pixel defining layer 114.

[0208] As referenced above Figure 14 As described above, when the first dam D1 is formed in the same process as the fifth insulating layer 110, the sixth insulating layer 112, or the pixel defining layer 114, the first dam D1 can be formed on the first insulating layer 102 at the current stage of the process. Hereinafter, for ease of explanation, the first dam D1 can be described as being formed on a separate organic insulating layer (e.g., a spacer layer as described above).

[0209] refer to Figure 18B The first dam D1 can be formed in the intermediate region IA and the opening region OA.

[0210] In an embodiment, as described above, the first dam D1 can be formed as part of an organic insulating layer (e.g., a spacer layer). A plurality of first dams D1 can be disposed on the substrate 100, some of which can be disposed within the intermediate region IA, and others within the opening region OA. The plurality of first dams D1 can be spaced apart from each other. Although Figure 18B Three first retaining dams D1 are shown, but this disclosure is not limited to the specific number of first retaining dams D1. Furthermore, although... Figure 18B An embodiment is shown in which two first dams D1 are disposed in the intermediate region IA and one first dam D1 is disposed in the opening region OA; however, this disclosure is not limited to the specific number of first dams D1 disposed in a particular region. In the embodiment, two first dams D1 may be disposed in the intermediate region IA and two first dams D1 may be disposed in the opening region OA. In the embodiment, three first dams D1 may be disposed in the intermediate region IA and one first dam D1 may be disposed in the opening region OA. At the current stage of the process, the upper surface of the first dam D1 may be flat or substantially flat. In other words, the current stage of the process may be to form a first groove D1G in the first dam D1 (e.g., see...). Figure 14 The stage before that.

[0211] An internal dam ID can be formed in the opening region OA. The internal dam ID may include a first internal organic portion IDa, a second internal organic portion IDb, and a third internal organic portion IDc. In an embodiment, the third internal organic portion IDc may be disposed on the second internal organic portion IDb. In an embodiment, the third internal organic portion IDc may cover the upper and side surfaces of the second internal organic portion IDb. In an embodiment, it is understood that the internal dam ID is achieved by forming the third internal organic portion IDc.

[0212] In an embodiment, the third internal organic portion IDc may include the same material as the first dam D1 and may be formed as part of the same layer as the first dam D1 (e.g., the spacer layer described above). In an embodiment, multiple first dams D1 and third internal organic portions IDc may be formed concurrently with each other (e.g., simultaneously or substantially simultaneously). In an embodiment, a first internal organic portion IDa, a second internal organic portion IDb, and a third internal organic portion IDc may be included, such that the internal dam ID is formed thicker than the first dam D1.

[0213] refer to Figure 18C This can form the first groove D1G and the second groove IDG.

[0214] In an embodiment, a first groove D1G may be formed in a first dam D1. In an embodiment, a second groove IDG may be formed in an inner dam ID (e.g., in a third internal organic portion IDc of the inner dam ID). In an embodiment, the first groove D1G and the second groove IDG may be formed concurrently with each other (e.g., simultaneously or substantially simultaneously). In an embodiment, the process for forming the first groove D1G and the second groove IDG may include etching (e.g., dry etching). In an embodiment, the cross-sectional shape of the first groove D1G and the cross-sectional shape of the second groove IDG may be the same as or substantially the same as each other. In other words, grooves having the same or substantially the same cross-sectional shape may be formed in the first dam D1 and the inner dam ID.

[0215] refer to Figure 18D This can form the first inorganic encapsulation layer 120.

[0216] In an embodiment, the process for forming the first inorganic encapsulation layer 120 may include chemical vapor deposition (CVD). In an embodiment, the first inorganic encapsulation layer 120 may cover the first dam D1, the second dam D2, the third dam D3, the fourth dam D4, and the inner dam ID. In an embodiment, the first inorganic encapsulation layer 120 may integrally extend and cover a plurality of first dams D1, second dams D2, and inner dam ID. In an embodiment, the first inorganic encapsulation layer 120 may integrally extend and cover the upper, side, and lower surfaces of the portion of the first-second metal portion D2c that protrudes beyond the side surface of the first organic portion D2b. In an embodiment, the first inorganic encapsulation layer 120 may cover the protruding portion of the first-second metal portion D2c, and may integrally extend and cover the entire side surface of the first-first organic portion D2b1, the side surface of the inorganic insulating layer 1IL, and the upper surface of the first insulating layer 102 located beneath the first-second metal portion D2c.

[0217] In the embodiments, as referenced above Figure 15 As described in the structure, the first inorganic encapsulation layer 120 can be disposed on the first dam D1.

[0218] The above reference Figure 15 The relationship described between the first dam D1 and the first inorganic encapsulation layer 120 can be applied in the same (or at least similarly) manner between the inner dam ID and the first inorganic encapsulation layer 120. In an embodiment, because a second recess IDG having a shape similar to that of the first recess D1G can be defined within the inner dam ID, the first inorganic encapsulation layer 120 can be disposed on the inner dam ID in a manner similar to that of the first inorganic encapsulation layer 120 disposed on the first dam D1. In an embodiment, portions of the first inorganic encapsulation layer 120 that overlap with the edge defining the second recess IDG of the third inner organic portion IDc (e.g., the third and fourth portions) can contact each other in the region overlapping with the second recess IDG.

[0219] refer to Figure 18E This can form an organic encapsulation layer 121 and a second inorganic encapsulation layer 122.

[0220] An organic encapsulation layer 121 may be disposed on the first inorganic encapsulation layer 120, and a second inorganic encapsulation layer 122 may be disposed on the organic encapsulation layer 121. The second inorganic encapsulation layer 122 may completely cover the organic encapsulation layer 121 and the first inorganic encapsulation layer 120. In an embodiment, the process for forming the second inorganic encapsulation layer 122 may include CVD.

[0221] In some embodiments, refer to the above reference Figure 17Similar to the described embodiment, the organic encapsulation layer 121 can be disposed between a plurality of first dams D1. In an embodiment, the organic encapsulation layer 121 can be disposed between two adjacent first dams D1. In an embodiment, within the opening region OA, the organic encapsulation layer 121 can be disposed between a first dam D1 and an inner dam ID.

[0222] refer to Figure 18F The substrate 100 can be cut along the boundary between the opening region OA and the intermediate region IA (e.g., such as along the cutting line CT corresponding to the boundary).

[0223] In one embodiment, the first insulating layer 102, the first inorganic encapsulation layer 120, and the second inorganic encapsulation layer 122 may be cut together with the substrate 100. In another embodiment, the cutting may include laser cutting.

[0224] refer to Figure 18F and Figure 18G It can remove components located within the opening area OA.

[0225] In this embodiment, the portion of substrate 100 corresponding to the opening region OA can be removed. In this embodiment, the portions of the first insulating layer 102, the first inorganic encapsulation layer 120, and the second inorganic encapsulation layer 122 corresponding to the opening region OA can be removed. In this embodiment, the first barrier D1 disposed within the opening region OA can be removed. In this embodiment, internal barriers ID (e.g., such as the first internal organic portion IDa, the second internal organic portion IDb, and the third internal organic portion IDc) can be removed. Because the components are removed, a transmission opening 11OP overlapping the opening region OA can be formed.

[0226] Refer to the above Figure 18F and Figure 18G During the described cutting and removal processes, delamination may occur between the first inorganic encapsulation layer 120 and the first insulating layer 102 (e.g., due to lack of adhesion). Delamination may cause gaps between the first inorganic encapsulation layer 120 and the second inorganic encapsulation layer 122.

[0227] This gap is particularly likely caused by residual stress remaining in the first inorganic encapsulation layer 120 after its formation. In an embodiment, when the first inorganic encapsulation layer 120 is cut along the cutting line CT, expansion may occur in the first inorganic encapsulation layer 120 due to residual stress. Because the first inorganic encapsulation layer 120 is covered by the second inorganic encapsulation layer 122, the expansion can typically occur in the horizontal direction (e.g., in a direction perpendicular to or substantially perpendicular to the z-axis). The expansion may generate stress in the first inorganic encapsulation layer 120 toward the location where the cut occurs (e.g., toward the cutting line CT). The expansion and stress may cause the first inorganic encapsulation layer 120 to be delaminated from the layer disposed thereunder (e.g., from the first insulating layer 102). Accordingly, the first inorganic encapsulation layer 120 may be delaminated from the first insulating layer 102, and the gap in the first inorganic encapsulation layer 120 may extend in the horizontal direction (e.g., in a direction perpendicular to or substantially perpendicular to the z-axis). In this case, the expansion of the gap can represent an increase in the area where the first inorganic encapsulation layer 120 is delaminated (or spaced apart from) the first insulating layer 102.

[0228] As the gap in the first inorganic encapsulation layer 120 continues to widen and reaches the second dam D2, stress may be concentrated on the portion of the first inorganic encapsulation layer 120 located below the first-second metal portion D2c of the second dam D2 (e.g., such as on the portion adjacent to the edge of the inorganic insulating layer IIL). This stress concentration may cause cracks in the first inorganic encapsulation layer 120 (and the second inorganic encapsulation layer 122) in this region.

[0229] The structure of the first dam D1 (and similarly, the structure of the internal dam ID) can prevent (or at least reduce) delamination (or gaps) of the first inorganic encapsulation layer 120 as described above. Reference Figure 15 as well as Figure 18F and Figure 18GA portion of the first inorganic encapsulation layer 120 may be disposed within the first groove D1G of the first dam D1, such that the first inorganic encapsulation layer 120 may have portions facing and contacting each other on the first groove D1G (e.g., such as a first portion 1201 and a second portion 1202). When horizontal expansion and stress occur in the first inorganic encapsulation layer 120 (e.g., a direction perpendicular to or substantially perpendicular to the z-axis direction), the first portion 1201 and the second portion 1202 may push against each other while contacting each other. For example, the first portion 1201 may expand in a direction toward the opening region OA, and the second portion 1202 may expand in a direction opposite to that toward the opening region OA. The expansion forces (e.g., stresses) of the first portion 1201 and the second portion 1202 may be opposite to each other in one direction, and therefore may cancel each other out. Thus, the stress formed within the first inorganic encapsulation layer 120 may be at least partially reduced, and the expansion of the first inorganic encapsulation layer 120 (e.g., expansion in the horizontal direction) may be prevented (or at least reduced). Additionally, by applying a force that pushes the first portion 1201 and the second portion 1202 against each other, the first portion 1201 can anchor itself to the first groove D1G of the first dam D1, which can help prevent (or at least reduce) delamination (or gaps) of the first inorganic encapsulation layer 120.

[0230] Figure 14 , Figure 18F and Figure 18G An embodiment is shown in which delamination and gaps in the first inorganic encapsulation layer 120 are completely prevented during the cutting of the structure through the first dam D1 and the first inorganic encapsulation layer 120. However, this disclosure is not limited thereto. References Figure 16 During the cutting process, partial delamination and gaps may occur in the first inorganic encapsulation layer 120. However, the structure of the first dam D1 described above according to one or more embodiments can be used to reduce (or minimize) the occurrence and spread of delamination and gaps. In other words, the structure of the first dam D1 and the first inorganic encapsulation layer 120 of the one or more embodiments described above can prevent (or at least reduce) delamination and gaps in the first inorganic encapsulation layer 120, and can prevent (or at least reduce) the propagation of delamination and gaps that may inevitably occur.

[0231] In an embodiment, this prevention (or at least reduction) can also be achieved through the relationship between the first inorganic encapsulation layer 120 and the internal dam ID.

[0232] According to some embodiments of this disclosure as described above, delamination and gaps between layers (e.g., inorganic encapsulation layers and inorganic insulating layers) on the substrate during the cutting and removal processes used to form openings in the display panel can be prevented (or at least reduced). Preventing (or at least reducing) such delamination and gaps can be achieved through the dam structure and inorganic encapsulation layer structure described above.

[0233] The foregoing is a description of some embodiments of this disclosure and should not be construed as limiting it. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it should be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the claims and their equivalents.

Claims

1. A display panel, comprising: A substrate includes an opening region, a central region at least partially surrounding the opening region, and a display region at least partially surrounding the central region; Light-emitting diodes (LEDs) are located in the display area. A first dam, in the intermediate region, and having at least one first groove defined in the upper surface of the first dam; as well as A second barrier, located between the first barrier and the display area, comprises: Organic materials section; as well as The metal portion is located within the organic material portion and has a portion that protrudes beyond the side surface of the organic material portion.

2. The display panel according to claim 1, further comprising: An inorganic encapsulation layer is applied to the first and second dams.

3. The display panel according to claim 2, wherein, The inorganic encapsulation layer includes a first portion and a second portion that overlap with a first edge and a second edge defining the at least one first groove of the first dam, respectively, and the first portion and the second portion of the inorganic encapsulation layer are in contact with each other in the region overlapping with the at least one first groove.

4. The display panel according to claim 2, wherein, The inorganic encapsulation layer extends integrally and covers the upper, side, and lower surfaces of the portion of the metal portion that protrudes beyond the side surface of the organic material portion.

5. The display panel according to claim 2, wherein, A portion of the lower surface of the inorganic encapsulation layer located on the first dam is spaced apart from a portion of the upper surface of the first dam.

6. The display panel according to claim 2, wherein, The first dam is provided as a plurality to include a plurality of first dams, and The display panel further includes an organic encapsulation layer on the inorganic encapsulation layer, the organic encapsulation layer having at least a portion located between two adjacent first dams among the plurality of first dams.

7. The display panel according to claim 2, wherein, The width of the first groove of the first dam is 1.5 to 2 times the thickness of the inorganic encapsulation layer on the first dam.

8. The display panel according to claim 1, wherein, In the plan view, the first retaining dam surrounds the opening area.

9. The display panel according to claim 1, wherein, An opening that overlaps with the opening region is defined in the substrate.

10. A method for manufacturing a display panel, the method comprising: A substrate is prepared therein defining an opening region, an intermediate region at least partially surrounding the opening region, and a display region at least partially surrounding the intermediate region; A first dam is placed in the intermediate region, the first dam having at least one first groove defined in the upper surface of the first dam; An inorganic encapsulation layer is placed on the first dam, and a first portion and a second portion of the inorganic encapsulation layer that overlap with a first edge and a second edge of the first dam defining at least one first groove respectively are in contact with each other in the region overlapping with the at least one first groove. as well as The substrate is cut along the boundary between the intermediate region and the opening region.

11. The method of claim 10, further comprising: A second barrier is placed between the first barrier and the display area, the second barrier comprising: Organic materials section; and The metal portion is disposed within the organic material portion and protrudes beyond the side surface of the organic material portion.

12. The method according to claim 11, wherein, The inorganic encapsulation layer is disposed on the second dam and integrally extends to cover the upper, side, and lower surfaces of the portion of the metal portion that protrudes beyond the side surface of the organic material portion of the second dam.

13. The method according to claim 10, wherein, During the cutting of the substrate, a portion of the lower surface of the inorganic encapsulation layer located on the first dam is spaced apart from a portion of the upper surface of the first dam.

14. The method of claim 10, wherein, The first dam is provided as a plurality to include a plurality of first dams, and The method further includes placing an organic encapsulation layer on the inorganic encapsulation layer, at least a portion of which is located between two adjacent first dams among the plurality of first dams.

15. The method of claim 10, further comprising: An internal dam is placed in the opening area, the internal dam having at least one second groove defined in the upper surface of the internal dam.

16. The method according to claim 15, wherein, The cross-sectional shape of the at least one first groove of the first dam and the cross-sectional shape of the at least one second groove of the inner dam are the same as each other.

17. The method according to claim 15, wherein, The inorganic encapsulation layer is disposed on the inner dam and includes a third portion and a fourth portion that overlap with a first edge and a second edge defining the at least one second groove of the inner dam, respectively, and the third portion and the fourth portion of the inorganic encapsulation layer are in contact with each other in the region overlapping with the at least one second groove.

18. The method of claim 15, further comprising: Remove the portion of the substrate corresponding to the opening area and the internal dam together.

19. The method according to claim 10, wherein, The inorganic encapsulation layer extends across the display area, the intermediate area, and the opening area, and during the cutting of the substrate, the inorganic encapsulation layer is cut together with the substrate.

20. An electronic device comprising: Display panel according to any one of claims 1 to 9; as well as The processor is configured to drive the display panel.

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