Display module, preparation method thereof and display device

Abstract

A display module, a preparation method thereof and a display device, wherein the display module comprises a display substrate and an external circuit assembly, the display substrate comprises a plurality of signal lines and a plurality of pins, the plurality of pins are electrically connected with the plurality of signal lines, the substrate is provided with a plurality of through holes, the external circuit assembly is electrically connected with the plurality of pins through the plurality of through holes, the plurality of pins are divided into a first pin group and a second pin group, the first pin group and the second pin group each comprise at least one pin, the first pin group is located in one of a plurality of straight frame regions, and the second pin group is located in at least one region of the remaining straight frame regions and a rounded corner region except for a straight frame region where a first power pin is located.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display module and its manufacturing method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display module, its manufacturing method, and a display device.

[0005] In a first aspect, this disclosure provides a display module, including: a display substrate and an external circuit assembly located on the backlight side of the display substrate and electrically connected to the display substrate. The display substrate includes: a base and a plurality of signal lines and a plurality of pins disposed on the base. The plurality of pins are electrically connected to the plurality of signal lines. The base is provided with a plurality of vias. The external circuit assembly is electrically connected to the plurality of pins through the plurality of vias and is configured to provide signals to the plurality of signal lines connected to the plurality of pins. The display substrate has a display area and a non-display area located on at least one side of the display area. The boundary of the display area includes: a plurality of rounded corner boundaries and a plurality of straight line boundaries. The non-display area includes: a plurality of straight border areas and a plurality of rounded corner areas. The straight border areas are the areas outside the straight line boundaries, and the rounded corner areas are the areas outside the rounded corner boundaries. The plurality of pins are divided into a first pin group and a second pin group, each of which includes at least one pin; the first pin group is located in one of the plurality of straight border regions, and the second pin group is located in at least one of the remaining straight border regions other than the straight border region where the first pin group is located and a plurality of rounded corner regions.

[0006] In an exemplary embodiment, the display module includes: a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer sequentially stacked on a substrate; The orthographic projections of the plurality of pins and the plurality of vias on the substrate do not overlap with the orthographic projection of the package layer on the substrate.

[0007] In an exemplary embodiment, the pins include: a first power supply pin and a second power supply pin, and the plurality of signal lines include: a plurality of first power supply lines, a plurality of second power supply lines, a first main power supply connection line and a second main power supply connection line, wherein the first power supply lines and the second power supply lines extend at least partially along a second direction, and the first main power supply connection line and the second main power supply connection line extend at least partially along a first direction, wherein the first direction intersects the second direction; The first power line and the second power line are located in the display area. The first power main connection line and the second power main connection line are at least partially located in the first straight frame area. The first straight frame area is the straight frame area where the first power pin is located. The portion of the orthographic projection of the first power main connection line on the substrate extending along the first direction is located on the side of the portion of the orthographic projection of the second power main connection line on the substrate extending along the first direction that is close to the display area. The first power main connection line is electrically connected to multiple first power lines and the first power pin respectively, and the second power main connection line is electrically connected to the second power line and the second power pin respectively. The number of the first power supply pins is multiple, and the multiple first power supply pins extend along a first direction; The number of second power supply pins is multiple, and the second power supply pins are located in the first straight frame area, or in the rounded corner area adjacent to the first straight frame area along the first direction.

[0008] In an exemplary embodiment, when the second power pin is located in the rounded corner area adjacent to the first straight frame area along the first direction, the second power main connection line includes: a first main connection line and a second main connection line that are interconnected, the first main connection line being connected to the second power line, the second main connection line being electrically connected to the second power pin, the first main connection line extending at least partially along the first direction, and the second main connection line extending at least partially along the second direction. The first main connection line is at least partially located in the first straight frame area, the second main connection line is at least partially located in the rounded corner area adjacent to the first straight frame area along the first direction, and the second power pin is located in the same rounded corner area as the second main connection line.

[0009] In an exemplary embodiment, a plurality of second power pins connected to the second power main connection line extend along a second direction.

[0010] In an exemplary embodiment, the second main connection line includes: a power connection segment and a plurality of power connection branches, wherein the power connection segment extends at least partially along a second direction and the power connection branches extend at least partially along a first direction; The power connection segment is electrically connected to the first main connection line and multiple power connection branches respectively. The multiple power connection branches correspond one-to-one with multiple second power pins, and at least one power connection branch is electrically connected to the corresponding second power pin.

[0011] In an exemplary embodiment, the pin further includes a driving pin, and the display module further includes a gate driving circuit and a gate driving trace, at least a portion of the gate driving trace extending along a second direction; The gate drive circuit and the gate drive trace are at least partially located in at least one of the straight frame regions of the third straight frame region and the fourth straight frame region, as well as the rounded corner regions adjacent to the straight frame regions along the second direction. The rounded corner regions adjacent to the first straight frame region include: a first adjacent rounded corner region and a second adjacent rounded corner region. The third straight frame region is adjacent to the first adjacent rounded corner region, and the fourth straight frame region is adjacent to the second adjacent rounded corner region. The third straight frame region and the fourth straight frame region are arranged opposite to each other along the first direction. The gate drive trace is electrically connected to the gate drive circuit and the drive pin, respectively. The number of driving pins is multiple, and the multiple driving pins are located in at least one of the first straight border area, at least one rounded corner area of ​​the multiple rounded corner areas, and at least one straight border area other than the first straight border area.

[0012] In an exemplary embodiment, when the plurality of driving pins are located in at least one rounded corner region among the plurality of rounded corner regions and at least one straight border region other than the first straight border region, the plurality of driving pins are located in at least one straight border region among the third or fourth straight border regions and the straight border region in which they are located has at least one adjacent rounded corner region along the second direction, and at least two of the plurality of driving pins extend along the second direction.

[0013] In an exemplary embodiment, when the plurality of driving pins are located in at least one straight border region other than the first straight border region, the plurality of driving pins are located in at least one straight border region among the third and fourth straight border regions, and the plurality of driving pins extend along the second direction.

[0014] In an exemplary embodiment, the pin includes a data pin, and the display module further includes a plurality of data signal lines and a plurality of data traces, wherein at least a portion of at least one of the data signal lines and the data traces extends along a second direction; The data signal line is located in the display area, and at least a portion of the data trace is located in the first straight border area; The data traces are electrically connected to the data signal lines and data pins, respectively. The number of data pins is multiple, and the multiple data pins are located in the first straight border area, or at least a portion of the multiple data pins are located in at least one rounded corner area and at least one straight border area other than the first straight border area, and another portion of the multiple data pins are located in the first straight border area.

[0015] In an exemplary embodiment, the display module further includes: a gate driving circuit, wherein when at least a portion of the plurality of data pins is located in at least one rounded corner region of the plurality of rounded corner regions, the data pins include: a first data pin and a second data pin, wherein the first data pin is located in the first straight frame region, the second data pin is located in the rounded corner region, and at least two of the plurality of second data pins are arranged at least partially along a second direction; The orthographic projection of the data trace connected to the second data pin on the substrate does not overlap with the orthographic projection of the gate drive circuit on the substrate.

[0016] In an exemplary embodiment, the display module further includes: a gate driving circuit, wherein at least a portion of the plurality of data pins are located in at least one straight border region other than the first straight border region, and when they are located in at least one region of the third straight border region and the fourth straight border region, the data pins include: a first data pin and a third data pin, wherein the first data pin is located in the first straight border region, and the third data pin is located in at least one region of the third straight border region and the fourth straight border region, and the plurality of third data pins are arranged along the second direction; The orthographic projection of the data trace connected to the third data pin on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate.

[0017] In an exemplary embodiment, the portion of the data trace connected to the third data pin extending along the first direction includes: a first data connection line and a second data connection line; The orthographic projection of the first data connection line on the substrate at least partially overlaps with the orthographic projection of the gate driving circuit on the substrate, while the orthographic projection of the second data connection line on the substrate does not overlap with the orthographic projection of the gate driving circuit on the substrate. The film layer containing the first data connection line is different from the film layer containing the gate drive circuit structure that overlaps with the orthographic projection on the substrate.

[0018] In an exemplary embodiment, the adjacent data pins located in the first straight border area are connected to data traces in different film layers, and the adjacent data pins located in the rounded corner area or other straight border areas other than the first straight border area are connected to data traces in different film layers.

[0019] In an exemplary embodiment, the pins further include: touch pins; the display substrate further includes: multiple touch traces located in the non-display area, and the number of touch pins is two; The touch trace is electrically connected to the touch pin, and the touch pin is located in the first straight edge area.

[0020] In an exemplary embodiment, a plurality of pins located in the first pin group extend along a first direction.

[0021] In an exemplary embodiment, the distance between adjacent pins along a first direction or a second direction is in the range of 10 micrometers to 100 micrometers.

[0022] In an exemplary embodiment, the display substrate further includes: multiple signal leads, and the external circuit assembly includes: a flexible circuit board, a driver chip, and a printed circuit board; The multiple signal leads are electrically connected to multiple pins through multiple vias, the flexible circuit board is electrically connected to the multiple signal leads, and the driver chip is disposed on the printed circuit board and electrically connected to the flexible circuit board.

[0023] In an exemplary embodiment, the plurality of signal leads are located on the side of the substrate closer to the external circuitry assembly.

[0024] In an exemplary embodiment, the plurality of signal leads are disposed within the substrate.

[0025] In an exemplary embodiment, the orthographic projection of the external connection component onto the substrate lies within the display area.

[0026] In an exemplary embodiment, the orthographic projection of the at least one via on the substrate is within the range of the orthographic projection of the at least one pin on the substrate, and the area of ​​the at least one pin is greater than three times the area of ​​the at least one via.

[0027] Secondly, this disclosure also provides a display device, including the aforementioned display module.

[0028] Thirdly, this disclosure also provides a method for manufacturing a display module, configured to manufacture the above-mentioned display module, the method comprising: A display substrate is formed, wherein the display substrate includes: a substrate and a plurality of signal lines and a plurality of pins disposed on the substrate, the plurality of pins being electrically connected to the plurality of signal lines; Vias are formed on the substrate of the display substrate; An external circuit assembly is formed on the backlight side of the display substrate. The external circuit assembly is electrically connected to a plurality of pins through the plurality of vias and is configured to provide signals to the plurality of signal lines connected to the plurality of pins.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0031] Figure 1 This is a schematic diagram of the structure of a display device; Figure 2A A schematic diagram of a planar structure of a display substrate. Figure 1 ; Figure 2B Schematic diagram 2 of a planar structure of a display substrate; Figure 2C A schematic diagram of a planar structure of a display substrate. Figure 3 ; Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate; Figure 4 A schematic diagram of the structure of the display module provided in the embodiments of this disclosure. Figure 1 ; Figure 5 for Figure 4 Partial cross-sectional schematic diagram; Figure 6 A partial frontal view of a display module provided as an exemplary embodiment. Figure 1 ; Figure 7 for Figure 6 A schematic diagram of the provided display module; Figure 8 for Figure 6 A schematic diagram of the structure of the second power main connection line in the provided display module; Figure 9A second partial frontal view of a display module provided as an exemplary embodiment; Figure 10 for Figure 9 A schematic diagram of the provided display module; Figure 11 A partial frontal view of a display module provided as an exemplary embodiment. Figure 3 ; Figure 12 for Figure 11 A schematic diagram of the provided display module; Figure 13 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 1 ; Figure 14 Schematic diagram 2 showing the overlap of data traces connecting the gate drive circuit and the third data pin; Figure 15 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 3 ; Figure 16 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 4 ; Figure 17 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 5 ; Figure 18 A partial frontal view of a display module provided as an exemplary embodiment. Figure 4 ; Figure 19 for Figure 9 A schematic diagram of the provided display module; Figure 20 A reverse schematic diagram of a display module provided for an exemplary embodiment.

[0032] Figure 21 A diagram showing pins and vias. Figure 1 ; Figure 22 Schematic diagram 2 showing pins and vias; Figure 23 A diagram showing pins and vias. Figure 3 . Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs. The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0034] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0035] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0036] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0037] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0039] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0040] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0041] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0042] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0043] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0044] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0045] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0046] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0047] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include: a timing controller 11, a data driving circuit 12, a scan driving circuit 13, a light-emitting driving circuit 14, and a pixel array 15. The timing controller 11 is connected to the data driving circuit 12, the scan driving circuit 13, and the light-emitting driving circuit 14. The data driving circuit 12 is connected to multiple data signal lines (D1 to Dn), the scan driving circuit 13 is connected to multiple scan signal lines (G1 to Gm), and the light-emitting driving circuit 14 is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array 15 may include multiple sub-pixels PX. At least one sub-pixel PX may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.

[0048] In an exemplary embodiment, the timing controller 11 can provide grayscale values ​​and control signals of specifications suitable for the data driving circuit 12 to the data driving circuit 12, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit 13 to the scan driving circuit 13, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit 14 to the light-emitting driving circuit 14.

[0049] In an exemplary embodiment, the data driving circuit 12 can use the grayscale values ​​and control signals received from the timing controller 11 to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driving circuit 12 can sample the grayscale values ​​using a clock signal and apply the data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number.

[0050] In an exemplary embodiment, the scan drive circuit 13 can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller 11. For example, the scan drive circuit 13 can sequentially provide scan signals with on-level pulses to scan signal lines G1 to Gm. For example, the scan drive circuit 13 can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0051] In an exemplary embodiment, the light-emitting driving circuit 14 can generate transmission signals to be provided to the light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmission start signals, etc., from the timing controller 11. For example, the light-emitting driving circuit 14 can sequentially provide transmission signals with on-level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driving circuit 14 can be configured as a shift register and can generate transmission signals by sequentially transmitting transmission start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0052] In an exemplary embodiment, the display device may include a display substrate. The scanning driving circuit and the light-emitting driving circuit may be directly disposed on the display substrate. For example, the scanning driving circuit may be disposed on the left frame of the display substrate, and the light-emitting driving circuit may be disposed on the right frame of the display substrate; alternatively, both the left and right frames of the display substrate may contain the scanning driving circuit and the light-emitting driving circuit. In an exemplary embodiment, the scanning driving circuit and the light-emitting driving circuit may be formed together with the sub-pixels during the sub-pixel formation process.

[0053] In an exemplary embodiment, the data driving circuit can be disposed on a separate chip or printed circuit board to connect to sub-pixels via signals on the display substrate. For example, the data driving circuit can be formed on the bezel of the display substrate using a chip-on-glass, chip-on-plastic, or chip-on-film method. The timing controller can be disposed separately from or integrated with the data driving circuit. However, this embodiment is not limited in this respect.

[0054] Figure 2A A schematic diagram of a planar structure of a display substrate. Figure 1 , Figure 2B This is a schematic diagram of a planar structure of a display substrate. Figure 2C A schematic diagram of a planar structure of a display substrate. Figure 3 .like Figures 2A to 2C As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light; or it may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light. Each of the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, and fourth sub-pixel P4 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0055] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0056] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel that emits red (R) light, the second sub-pixel P2 may be a blue sub-pixel that emits blue (B) light, the third sub-pixel P3 may be a green sub-pixel that emits green (G) light, and the fourth sub-pixel P4 may be a white sub-pixel that emits white (W) light.

[0057] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal.

[0058] In an exemplary embodiment, when a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, and this disclosure does not limit this arrangement. Figure 2A This explanation uses an example where a pixel unit comprises three sub-pixels, and these three sub-pixels are arranged horizontally side by side. Figure 2B This explanation is based on the example of a pixel unit comprising three sub-pixels, arranged in a triangular pattern.

[0059] In an exemplary embodiment, when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal, vertical, diamond, or square manner, and this disclosure is not limited thereto. Figure 2C This explanation is based on the example of a pixel unit comprising four sub-pixels arranged in a square.

[0060] In an exemplary embodiment, the pixel driving circuit may include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, and this disclosure is not limited thereto.

[0061] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0062] In an exemplary embodiment, the light-emitting device can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The color of the light emitted by the light-emitting device can be determined as needed. In an exemplary embodiment, the light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited in this respect.

[0063] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels. For example... Figure 3As shown, on a plane perpendicular to the display substrate, the display substrate may include a circuit structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the circuit structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, touch structure layers, etc., which are not limited herein.

[0064] In an exemplary embodiment, the substrate 101 can be a rigid substrate, such as a glass substrate, or the substrate 101 can be a flexible substrate, such as one made of an insulating material like resin; this embodiment is not limited to either. The substrate 101 can be a single-layer structure or a multi-layer structure. When the substrate 101 is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be placed in single or multiple layers between the layers.

[0065] In an exemplary embodiment, the substrate may include: a first flexible layer, a barrier layer, a substrate conductive layer, and a second flexible layer stacked sequentially. In an exemplary embodiment, the substrate conductive layer may be referred to as the 0th source / drain metal (SD0) layer.

[0066] In an exemplary embodiment, forming the substrate includes: firstly, coating a first flexible material onto a glass substrate, curing it to form a first flexible layer; then, sequentially depositing a barrier film and a substrate conductive film on the first flexible layer; and patterning the substrate conductive film using a patterning process to form a barrier layer covering the first flexible layer and a substrate conductive layer pattern disposed on the barrier layer; and finally, coating a second flexible material, curing it to form a second flexible layer covering the substrate conductive layer pattern.

[0067] In an exemplary embodiment, the circuit structure layer 102 may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3This example uses only one transistor 210 and one storage capacitor 211. In some possible implementations, the circuit structure layer 102 of each sub-pixel may include: a semiconductor layer disposed on a substrate 101, the semiconductor layer including: an active pattern; a first insulating layer (or first gate insulating layer) covering the active layer; a first gate metal layer disposed on the first insulating layer (e.g., including the gate electrode of the transistor and the first capacitor electrode); a second insulating layer (or second gate insulating layer) covering the first gate metal layer; a second gate metal layer disposed on the second insulating layer (e.g., including the second capacitor electrode); a third insulating layer (or interlayer insulating layer) covering the second gate metal layer, wherein multiple vias are formed on the first, second, and third insulating layers, and the multiple vias can expose the semiconductor layer; and a source / drain metal layer disposed on the third insulating layer (e.g., including the source electrode and drain electrode of the transistor), the source electrode and drain electrode can be connected to the semiconductor layer through the vias respectively. The active pattern, gate electrode, source electrode, and drain electrode can form the transistor 210, and the first capacitor electrode and the second capacitor electrode can form the storage capacitor 211.

[0068] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0069] In an exemplary embodiment, at least one of the conductive layers in the first gate metal layer, the second gate metal layer, and the source / drain metal layer can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0070] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0071] In an exemplary embodiment, the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together. The light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0072] In an exemplary embodiment, the light-emitting structure layer may include: a fourth conductive layer, a pixel definition layer, an organic structure layer, and a fifth conductive layer.

[0073] In an exemplary embodiment, the fourth conductive layer may include at least the anodes of multiple light-emitting devices. The fourth conductive layer may be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO.

[0074] In an exemplary embodiment, the organic structure layer may include at least: an organic light-emitting layer of multiple light-emitting devices.

[0075] In an exemplary embodiment, the fifth conductive layer may include at least the cathodes of multiple light-emitting devices. The fifth conductive layer may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fifth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0076] In an exemplary embodiment, the encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0077] In an exemplary embodiment, the touch structure layer, in a direction perpendicular to the display substrate, may include: a touch buffer layer (TBL), a first touch conductive layer, a touch interlayer insulating layer (TLD), a second touch conductive layer, and a touch protective layer (TOC) sequentially disposed. The touch buffer layer and the touch interlayer insulating layer may be inorganic insulating layers, while the touch protective layer may be an organic insulating layer. For example, the first touch conductive layer may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions. The first touch electrodes and the first connecting portions may be an integrally connected structure. The second touch conductive layer may include multiple second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: multiple first touch electrodes, multiple second touch electrodes, and multiple second connecting portions, where the second touch electrodes and second connecting portions may be an integrally connected structure; the second touch conductive layer may include multiple first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the touch interlayer insulating layer. In an exemplary embodiment, the first touch electrode may be a driving (Tx) electrode, and the second touch electrode may be a sensing (Rx) electrode. Alternatively, the first touch electrode may be a sensing (Rx) electrode, and the second touch electrode may be a driving (Tx) electrode. This embodiment is not limited in this respect.

[0078] In an exemplary embodiment, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of the following shapes: triangle, square, trapezoid, parallelogram, pentagon, hexagon, and other polygons, which are not limited to the embodiments disclosed herein.

[0079] In an exemplary embodiment, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by interlacing multiple metal wires. The metal mesh can include multiple mesh patterns, and the mesh patterns can be polygons composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0080] The display substrate includes a display area and a non-display area. The non-display area includes a bottom bezel area. The bottom bezel area of ​​the display substrate contains a large number of pins, which makes it impossible to display the narrow bezel of the substrate.

[0081] Therefore, this disclosure provides a display module, a method for manufacturing the same, and a display device.

[0082] Figure 4 A schematic diagram of the structure of the display module provided in the embodiments of this disclosure. Figure 1 , Figure 5 for Figure 4 A partial cross-sectional schematic diagram. Figure 4 This is a frontal view of the module. (Example) Figure 4 and Figure 5 As shown, the display module provided in this embodiment may include: a display substrate 100 and an external circuit assembly 300 located on the backlight side of the display substrate 100 and electrically connected to the display substrate 100. The display substrate 100 includes: a base 101 and multiple signal lines and multiple pins 20 disposed on the base 101. The multiple pins 20 are electrically connected to the multiple signal lines. The base 101 is provided with multiple vias V. The external circuit assembly 300 is electrically connected to the multiple pins 20 through the multiple vias V and is configured to provide signals to the multiple signal lines connected to the multiple pins 20. Figure 4 As shown, the multiple signal lines may include: a data signal line Data, a first power supply line VDD, a second power supply line VSS, a touch control trace TL, a first power main connection line VL1, a second power main connection line VL2, and a gate drive trace GL.

[0083] like Figure 4 As shown, the display substrate has a display area AA and a non-display area BB located on at least one side of the display area AA. The boundary of the display area AA includes a plurality of rounded corner boundaries CR and a plurality of straight line boundaries LR. In an exemplary embodiment, the plurality of straight line boundaries LB and the plurality of rounded corner boundaries CB are alternately connected. Figure 4 This explanation uses four straight-line boundaries and four rounded-corner boundaries as examples.

[0084] like Figure 4 As shown, the non-display area BB includes: multiple straight-line border areas and multiple rounded corner areas. The straight-line border areas are the areas outside the straight-line boundary LR, and the rounded corner areas are the areas outside the rounded corner boundary CR. For example, as... Figure 4As shown, the multiple straight-line border regions include: a first straight-line border region BR1, a second straight-line border region BR2, a third straight-line border region BR3, and a fourth straight-line border region BR4; and the multiple rounded corner regions include: a first rounded corner region CR1, a second rounded corner region CR2, a third rounded corner region CR3, and a fourth rounded corner region CR4. The first straight-line border region BR1 and the second straight-line border region BR2 are positioned opposite each other along a second direction D2; the third straight-line border region BR3 and the fourth straight-line border region BR4 are positioned opposite each other along a first direction D1; the first rounded corner region CR1 is located between the first straight-line border region BR1 and the third straight-line border region BR3; the second rounded corner region CR2 is located between the first straight-line border region BR1 and the fourth straight-line border region BR4; the third rounded corner region CR3 is located between the second straight-line border region BR2 and the third straight-line border region BR3; and the fourth rounded corner region CR4 is located between the second straight-line border region BR2 and the fourth straight-line border region BR4.

[0085] like Figure 4 As shown, the rounded corner regions adjacent to the first straight-line border region include: a first adjacent rounded corner region and a second adjacent rounded corner region. The first adjacent rounded corner region is the first rounded corner region CR1, and the second adjacent rounded corner region is the second rounded corner region CR2.

[0086] In an exemplary implementation, such as Figure 4 As shown, the multiple pins 20 are divided into a first pin group 210 and a second pin group 220. Both the first pin group 210 and the second pin group 220 include at least one pin 20. The first pin group 210 is located in one of the multiple straight border regions, and the second pin group 220 is located in at least one of the remaining straight border regions other than the straight border region where the first pin group 210 is located and multiple rounded corner regions. Figure 4 The illustration is based on the example of the first pin group 210 being located in the first straight edge region BR1 and the second pin group 220 being located in the first rounded corner region CR1. This disclosure does not impose any limitations on this.

[0087] In an exemplary embodiment, at least one pin is located on at least one metal layer. The circuit structure layer may further include a connecting metal layer, which may be located on the side of the semiconductor layer closer to the substrate. The connecting metal layer may serve as a barrier layer for etching vias, preventing etching damage to other film layers on the display module, and may also lead out signals from multiple signal lines.

[0088] In an exemplary embodiment, the non-display area may include a circuit area, a power line area, a crack dam area, and a cutting area arranged sequentially along a direction away from the display area AA. The circuit area may be connected to the display area AA and may include at least a gate driving circuit electrically connected to multiple gate lines in the display area. The power line area is connected to the circuit area and may include at least power lines extending parallel to the edge of the display area and connected to the cathode of the display area. The crack dam area may be connected to the power line area and may include at least multiple cracks formed on an insulating layer group. The cutting area is connected to the crack dam area and may include at least cutting grooves formed on the insulating layer group. The cutting grooves may be configured such that, after all film layers of the display substrate have been prepared, the cutting setup can cut along the cutting grooves respectively. Here, the insulating layer group refers to a combination of insulating layers disposed on the substrate.

[0089] In an exemplary embodiment, the display substrate may also be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area AA. The edge of the display area is the edge of the display area AA near the frame area.

[0090] In an exemplary embodiment, the gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The gate driving trace GL may include signal lines connected to the gate driving circuit, such as clock signal lines or initial signal lines.

[0091] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: multiple first power lines VDD and a first power main connection line VL1. The first power main connection line VL1 is electrically connected to the multiple first power lines VDD. The first power lines VDD extend at least partially along a second direction D2, and the first power main connection line VL1 extends at least partially along a first direction D1, where the first direction D1 intersects the second direction D2.

[0092] In an exemplary implementation, such as Figure 4 As shown, the first power line VDD is at least partially located in the display area AA, and the first main power connection line VL1 is at least partially located in the first straight border area BR1.

[0093] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: multiple second power lines VSS and a second main power connection line VL2. The second main power connection line VL2 is electrically connected to the second power lines VSS. The second power lines VSS extend at least partially along a second direction D2, and the second main power connection line VL2 extends at least partially along a first direction D1.

[0094] In an exemplary implementation, such as Figure 4 As shown, the second power line VSS is at least partially located in the display area AA, and the second power main connection line VL2 is at least partially located in the first straight frame area BR1.

[0095] In an exemplary implementation, such as Figure 4 As shown, the portion of the orthographic projection of the first power main connection line VL1 on the substrate extending along the first direction D1 is located on the side of the portion of the orthographic projection of the second power main connection line VL2 on the substrate extending along the first direction D1 that is closer to the display area AA.

[0096] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: a first power auxiliary connection line L1 and a second power auxiliary connection line L2, wherein the first power auxiliary connection line L1 and the second power auxiliary connection line L2 extend at least partially along a second direction. At least one of the first power auxiliary connection lines L1 and the second power auxiliary connection line L2 is located in at least one region of a third straight frame region and a fourth straight frame region, and its adjacent rounded corner region. The first power auxiliary connection line L1 is electrically connected to the first main power connection line VL1, and the second power auxiliary connection line L2 is electrically connected to the second main power connection line VL2.

[0097] In an exemplary implementation, such as Figure 4 As shown, the orthographic projection of the first power auxiliary connection line L1 on the substrate is located on the side of the orthographic projection of the second power auxiliary connection line L2 on the substrate that is closer to the display area, and the orthographic projection of the gate drive line GL on the substrate is located on the side of the orthographic projection of the first power auxiliary connection line L1 on the substrate that is closer to the display area.

[0098] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: a gate driving circuit and a gate driving trace GL, at least a portion of which extends along a second direction D2. The gate driving circuit is electrically connected to the gate driving trace GL, and the gate driving circuit and the gate driving trace GL are at least partially located in at least one of the third straight-line frame regions BR3 and the fourth straight-line frame region BR4, as well as an adjacent rounded corner region.

[0099] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: multiple data signal lines Data and multiple data traces FL, the data signal lines Data and data traces FL are electrically connected, and at least a portion of at least one of the data signal lines Data and data traces FL extends along a second direction D2. The data signal lines Data are located in the display area AA, and at least a portion of the data traces FL are located in the first straight-line border area BR1.

[0100] In an exemplary implementation, such as Figure 4 As shown, the display substrate may further include: multiple touch traces TL located in the non-display area BB, and touch pins TL located in at least one of the third straight frame area BR3 and the fourth straight frame area BR4, as well as adjacent rounded corner areas.

[0101] In an exemplary implementation, such as Figure 4 As shown, pin 20 includes: a first power supply pin 21, a second power supply pin 22, a driving cathode 23, a data pin 24, and a touch pin 25. Specifically, the first power supply main connection line VL1 is also electrically connected to the first power supply pin 21, the second power supply main connection line VL2 is also electrically connected to the second power supply pin 22, the driving trace GL is also electrically connected to the driving pin 23, the data trace FL is also electrically connected to the data pin 24, and the touch trace TL is also electrically connected to the touch pin 25.

[0102] This disclosure reduces the number of pins in the straight frame area where the first pin group is located by setting the second pin group in at least one of the remaining straight frame areas and multiple rounded corner areas, excluding the straight frame area where the first power pin is located. This increases the lateral width of multiple data traces and reduces the length of the data traces, thereby achieving a narrow bezel on the display substrate.

[0103] In an exemplary implementation, such as Figure 4 As shown, the display module includes a circuit structure layer 102, a light-emitting structure layer 103, and an encapsulation structure layer 104 sequentially stacked on a substrate 101. The orthographic projections of the plurality of pins 20 and the plurality of vias V on the substrate do not overlap with the orthographic projection of the encapsulation layer 104 on the substrate.

[0104] The orthographic projections of the plurality of pins 20 and the plurality of vias V on the substrate in this disclosure do not overlap with the orthographic projections of the encapsulation layer 104 on the substrate. This can reduce the risk of the display module and improve its reliability without affecting the design of the display module.

[0105] In an exemplary implementation, such as Figure 4 As shown, multiple pins located in the first pin group 210 extend along the first direction D1.

[0106] like Figure 4 As shown, the first straight-line border area BR1 is the straight-line border area where the first power supply pin 21 is located. There are multiple first power supply pins 21, and the multiple first power supply pins 21 extend along the first direction D1.

[0107] In an exemplary embodiment, there are multiple second power supply pins 22. The second power supply pins 22 may be located in the first straight frame area BR1, or may be located in the rounded corner area adjacent to the first straight frame area BR1 along the first direction D1, such as the first rounded corner area CR1 and the second rounded corner area CR2.

[0108] In an exemplary embodiment, there are multiple driving pins 23, which can be located in at least one of the first straight-line border region BR1, at least one rounded corner region among multiple rounded corner regions, and at least one straight-line border region other than the first straight-line border region BR1. When the multiple driving pins 23 are located in at least one rounded corner region among multiple rounded corner regions and at least one straight-line border region other than the first straight-line border region, the multiple driving pins 23 are located in at least one straight-line border region among the third straight-line border region or the fourth straight-line border region, and the straight-line border region in which they are located has at least one adjacent rounded corner region along the second direction. When the driving pins 23 are located in at least one straight-line border region other than the first straight-line border region, the driving pins 23 are located in at least one straight-line border region among the third straight-line border region BR3 and the fourth straight-line border region BR4, and the multiple driving pins 23 extend along the second direction D2.

[0109] In an exemplary embodiment, there are multiple data pins 24, which are located in a first straight border region. Alternatively, a portion of the multiple data pins 24 are located in at least one rounded corner region and at least one straight border region other than the first straight border region BR1, and another portion of the multiple data pins 24 are located in the first straight border region BR1.

[0110] In an exemplary embodiment, there are two touch pins 25, and the touch trace TL is electrically connected to the touch pins 25. The touch pins 25 are located in the first straight frame area BR1.

[0111] Figure 4 The following is an example of a scenario where the driving pin 23 is located in the rounded corner area adjacent to the first straight frame area BR1 along the first direction D1, and the adjacent rounded corner area is the first rounded corner area CR1, and the first power supply pin 21, the second power supply pin 22, the data pin 24, and the touch pin 25 are all located in the first straight frame area BR1.

[0112] Figure 6 A partial frontal view of a display module provided as an exemplary embodiment. Figure 1 , Figure 7 for Figure 6 A schematic diagram of the provided display module. Figure 6 and Figure 7The following is an example of a scenario where the second power supply pin 22 is located in the rounded corner area adjacent to the first straight frame area BR1 along the first direction D1, and the adjacent rounded corner area is the first rounded corner area CR1, and the first power supply pin 21, drive pin 23, data pin 24 and touch pin 25 are all located in the first straight frame area BR1.

[0113] Figure 8 for Figure 6 A schematic diagram of the second main power supply connection line in the provided display module. (Combined with...) Figure 6 and Figure 8 As shown, the second power main connection line VL2 includes: a first main connection line VL21 and a second main connection line VL22 that are interconnected. The first main connection line VL21 is connected to the second power line VSS, and the second main connection line VL22 is electrically connected to the second power pin 22. The first main connection line VL21 extends at least partially along a first direction D1, and the second main connection line VL22 extends at least partially along a second direction D2.

[0114] Combination Figure 6 and Figure 8 As shown, the first main connection line VL21 is at least partially located in the first straight frame area BR1, the second main connection line VL22 is at least partially located in the rounded corner area adjacent to the first straight frame area BR1 along the first direction D1, and the second power supply pin 22 is located in the same rounded corner area as the second main connection line VL22. Figure 6 Therefore, the explanation will be based on the example of the second main connection line VL22 and the second power supply pin 22 being located in the first rounded corner area CR1.

[0115] In an exemplary implementation, such as Figure 6 As shown, multiple second power supply pins 22 connected to the second power supply main connection line VL2 extend along the second direction D2.

[0116] In an exemplary embodiment, combined with Figure 6 and Figure 8 As shown, the second main connection line VL22 includes a power connection segment VL221 and multiple power connection branches VL222. The power connection segment VL221 extends at least partially along the second direction D2, and the power connection branches VL222 extend at least partially along the first direction D1. The power connection segment VL221 is electrically connected to both the first main connection line VL21 and the multiple power connection branches VL222. The multiple power connection branches VL222 correspond one-to-one with multiple second power pins 22, and at least one power connection branch VL222 is electrically connected to its corresponding second power pin 22.

[0117] In this disclosure, the second power supply pin 22 is located in the rounded corner area adjacent to the first straight frame region BR1, which can isolate external interference and crosstalk between signals on the left and right sides of the display substrate, thereby improving the reliability of the display module. In addition, since the second power supply main connection line itself is relatively wide and has a low load, the space benefit brought by the second power supply pin 22 being located in the rounded corner area adjacent to the first straight frame region BR1 is also optimal. It can free up approximately 100 to 200 micrometers of lateral space on each side of the first straight frame region, directly shortening the length of the data trace by 50 to 100 micrometers, and the implementation method is also relatively simple.

[0118] Figure 9 This is a second partial frontal view of a display module provided as an exemplary embodiment. Figure 10 for Figure 9 A schematic diagram of the provided display module. Figure 9 and Figure 10 The following example illustrates the situation: the driving pin 23 is located in the rounded corner area adjacent to the first straight frame area BR1 along the first direction D1, and the adjacent rounded corner area is the first rounded corner area CR1; at least some data pins 24 are located in the third straight frame area BR3; and the first power pin 21, the second power pin 22, at least some data pins 24, and the touch pin 25 are all located in the first straight frame area BR1.

[0119] In an exemplary embodiment, at least two of the plurality of drive pins 23 extend along the second direction D2. The extension of at least two of the plurality of drive pins 23 along the second direction D2 can reduce the width of the display module along the first direction, further enabling a narrow bezel.

[0120] In an exemplary implementation, such as Figure 9 As shown, when at least a portion of the plurality of data pins 24 are located in at least one rounded corner region among the plurality of rounded corner regions, the data pins 24 include: a first data pin 241 and a second data pin 242. The first data pin 241 is located in a first straight frame region BR1, and the second data pin 242 is located in the rounded corner region. At least two of the plurality of second data pins 242 are arranged at least partially along a second direction D2. The orthographic projection of the data trace FL connected to the second data pin 242 on the substrate does not overlap with the orthographic projection of the gate drive circuit on the substrate.

[0121] Figure 11 A partial frontal view of a display module provided as an exemplary embodiment. Figure 3 , Figure 12 for Figure 11 A schematic diagram of the provided display module. Figure 11 and Figure 9The difference lies in that the drive pin 23 is located in the first straight-line border region BR1, and at least a portion of the plurality of data pins 24 are located in at least one straight-line border region other than the first straight-line border BR1, and in at least one of the third straight-line border regions BR3 and the fourth straight-line border region BR4. The data pins 24 include: a first data pin 241 and a third data pin 243, the first data pin 241 being located in the first straight-line border region, and the third data pin 243 being located in at least one of the third straight-line border regions BR3 and the fourth straight-line border region BR4, with the plurality of third data pins 243 arranged along the second direction D2.

[0122] like Figure 11 As shown, the orthographic projection of the data trace FL connected to the third data pin 243 on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate.

[0123] In an exemplary implementation, such as Figure 11 As shown, the portion of the data trace FL connected to the third data pin 243 extending along the first direction D1 includes: a first data connection line FL1 and a second data connection line FL2. The first data connection line FL1 at least partially overlaps with the orthographic projection of the gate driving circuit on the substrate, and the orthographic projection of the second data connection line FL2 on the substrate does not overlap with the orthographic projection of the gate driving circuit on the substrate.

[0124] In an exemplary embodiment, the film layer containing the first data connection line FL1 is different from the film layer containing the gate driving circuit structure whose orthogonal projection on the substrate overlaps. This difference in film layer avoids the influence of the first data connection line FL1 configuration on the structure of the gate driving circuit, thus preserving the structure of the gate driving circuit.

[0125] In an exemplary embodiment, the film layer on which the first data connection line FL1 is located may be the same as or different from the film layer on which the second data connection line FL2 is located.

[0126] In an exemplary embodiment, Figure 13 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 1 , Figure 14 The second diagram shows the overlapping data traces connecting the gate drive circuit and the third data pin. Figure 15 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 3 , Figure 16 Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 4 , Figure 17Schematic diagram of data trace overlap connecting the gate drive circuit and the third data pin Figure 5 . Figure 13 Therefore, this explanation will use the example of the first data connection line FL1 being located on the source / drain metal layer and the second data connection line FL2 being located on the first gate metal layer. Figure 14 This explanation uses the example of the first data connection line FL1 and the second data connection line FL2 being located in the second gate metal layer. Figure 15 This explanation uses the example of the first data connection line FL1 located on the source / drain metal layer, the second data connection line FL2 located on the second gate metal layer and the first gate metal layer, with the second data connection line FL2 closer to the display area located on the first gate metal layer, and the second data connection line FL2 farther from the display area located on the second gate metal layer and the first gate metal layer. Figure 13 Therefore, this explanation will use the example of the first data connection line FL1 being located on the source / drain metal layer and the second data connection line FL2 being located on the second gate metal layer. Figure 17 This explanation uses the example of the first data connection line FL1 located on the source / drain metal layer, the second data connection line FL2 located on both the second and first gate metal layers, with the second data connection line FL2 closer to the display area located on the second gate metal layer and the second data connection line FL2 farther from the display area located on the first gate metal layer. In an exemplary embodiment, the adjacent data pins 24 connected to the data traces FL in the first straight border region BR1 are located on different film layers. The adjacent data pins 24 connected to the data traces FL in the first straight border region BR1 are located on either the first gate metal layer or the second gate metal layer.

[0127] In an exemplary embodiment, the film layers on which the data traces FL connected to adjacent data pins 24 located in the rounded corner region or in the other straight border regions excluding the first straight border region BR1 are located can be the same.

[0128] In an exemplary embodiment, the film layers on which adjacent data pins 24 connected to data traces FL located in the rounded corner region or in other straight border regions besides the first straight border region BR1 are located can be different. Having different film layers on which adjacent data pins 24 connected to data traces FL located in the rounded corner region or in other straight border regions besides the first straight border region BR1 are located can reduce the spacing between adjacent data pins 24 connected to data traces FL, further enabling a narrower border.

[0129] In an exemplary embodiment, the film layer on which the data traces FL connected to the adjacent data pins 24 located in the rounded corner area or the other straight border areas excluding the first straight border area BR1 are located can be the first gate metal layer or the second gate metal layer, and this disclosure does not limit it in any way.

[0130] Figure 18A partial frontal view of a display module provided as an exemplary embodiment. Figure 4 , Figure 19 for Figure 18 A schematic diagram of the provided display module. Figure 18 and Figure 19 The example is as follows: the driving pin 23 is located in the rounded corner area adjacent to the first straight frame area BR1, at least some of the multiple data pins 24 are located in the second straight frame area BR2 and the third rounded corner area CR3 other than the first straight frame area BR1, and the first power pin 21, the second power pin 22, at least some of the data pins 24 and the touch pin 25 are located in the first straight frame area BR1.

[0131] Figure 20 A reverse schematic diagram of a display module provided as an exemplary embodiment. For example... Figure 20 As shown, at least some pins are located in the first straight border region BR1 and the second straight border region BR2.

[0132] In an exemplary embodiment, the distance between adjacent pins along the first direction D1 or along the second direction D2 is in the range of 10 micrometers to 100 micrometers.

[0133] In an exemplary implementation, such as Figure 7 , Figure 10 , Figure 12 , Figure 19 , Figure 20 As shown, the display substrate also includes multiple signal leads 105, and the external circuit assembly 300 includes a flexible circuit board 301, a driver chip 302, and a printed circuit board 303. The multiple signal leads 105 are electrically connected to multiple pins through multiple vias V. The flexible circuit board 301 is electrically connected to the multiple signal leads 105. The driver chip 302 is disposed on the printed circuit board 303 and electrically connected to the flexible circuit board 301.

[0134] In an exemplary implementation, such as Figure 5 As shown, multiple signal leads 105 are located on the side of the substrate 105 near the external circuit assembly 300.

[0135] In an exemplary embodiment, multiple signal leads 105 are disposed within the substrate.

[0136] In an exemplary implementation, such as Figure 5 As shown, the orthographic projection of the external connection component 300 on the substrate is located within the display area AA.

[0137] In an exemplary embodiment, Figure 21 A diagram showing pins and vias. Figure 1 , Figure 22 The second diagram shows the pins and vias. Figure 23A diagram showing pins and vias. Figure 3 .like Figures 21 to 23 As shown, the orthographic projection of at least one via V onto the substrate is within the range of the orthographic projection of at least one pin 20 onto the substrate, and the area of ​​at least one pin 20 is greater than three times the area of ​​at least one via V. Figures 21 to 23 The difference lies in the position of the vias and pins.

[0138] Because the signal leads are located on the back of the display module, this disclosure provides ample space for the signal leads, allowing for more flexible placement of vias and pins.

[0139] The display module disclosed in this embodiment can be applied to display products of any resolution.

[0140] This disclosure also provides a method for manufacturing a display module, configured to manufacture the display module provided in any of the foregoing embodiments. The method for manufacturing a display module provided in this disclosure may include the following steps: Step 100: Forming a display substrate, wherein the display substrate includes: a substrate and multiple signal lines and multiple pins disposed on the substrate, the multiple pins being electrically connected to the multiple signal lines; Step 200: Form vias on the substrate of the display substrate.

[0141] Step 200 may include: forming a via on the backlight side of the substrate by an etching process.

[0142] Step 300: Form an external circuit assembly on the backlight side of the display substrate.

[0143] The external circuitry component is electrically connected to multiple pins via multiple vias and is configured to provide signals to multiple signal lines connected to multiple pins.

[0144] In an exemplary embodiment, the method for fabricating a display module includes: forming a display substrate, forming vias on the back side of the display substrate by an etching process, and setting external connection components on the back side of the display substrate.

[0145] In exemplary embodiments, the display module of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0146] This disclosure also provides a display device, including: the display module provided in any of the foregoing embodiments.

[0147] In an exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0148] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0149] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0150] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display module, characterized in that, include: The display substrate and an external circuit assembly located on the backlight side of the display substrate and electrically connected to the display substrate, the display substrate including: a substrate and a plurality of signal lines and a plurality of pins disposed on the substrate, the plurality of pins being electrically connected to the plurality of signal lines, the substrate being provided with a plurality of vias, the external circuit assembly being electrically connected to the plurality of pins through the plurality of vias, and being configured to provide signals to the plurality of signal lines connected to the plurality of pins; The display substrate has a display area and a non-display area located on at least one side of the display area. The boundary of the display area includes multiple rounded corner boundaries and multiple straight line boundaries. The non-display area includes multiple straight border areas and multiple rounded corner areas. The straight border areas are the areas outside the straight line boundaries, and the rounded corner areas are the areas outside the rounded corner boundaries. The plurality of pins are divided into a first pin group and a second pin group, each of which includes at least one pin; the first pin group is located in one of the plurality of straight border regions, and the second pin group is located in at least one of the remaining straight border regions other than the straight border region where the first pin group is located and a plurality of rounded corner regions.

2. The display module according to claim 1, characterized in that, The display module includes: a circuit structure layer, a light-emitting structure layer, and an encapsulation structure layer stacked sequentially on a substrate; The orthographic projections of the plurality of pins and the plurality of vias on the substrate do not overlap with the orthographic projection of the package layer on the substrate.

3. The display module according to claim 1, characterized in that, The pins include: a first power supply pin and a second power supply pin; the multiple signal lines include: multiple first power supply lines, multiple second power supply lines, a first main power supply connection line and a second main power supply connection line; the first power supply lines and the second power supply lines extend at least partially along a second direction; the first main power supply connection line and the second main power supply connection line extend at least partially along a first direction; the first direction intersects the second direction. The first power line and the second power line are located in the display area. The first power main connection line and the second power main connection line are at least partially located in the first straight frame area. The first straight frame area is the straight frame area where the first power pin is located. The portion of the orthographic projection of the first power main connection line on the substrate extending along the first direction is located on the side of the portion of the orthographic projection of the second power main connection line on the substrate extending along the first direction that is close to the display area. The first main power connection line is electrically connected to multiple first power lines and the first power pin respectively, and the second main power connection line is electrically connected to the second power lines and the second power pin respectively. The number of the first power supply pins is multiple, and the multiple first power supply pins extend along a first direction; The number of second power supply pins is multiple, and the second power supply pins are located in the first straight frame area, or in the rounded corner area adjacent to the first straight frame area along the first direction.

4. The display module according to claim 3, characterized in that, When the second power pin is located in the rounded corner area adjacent to the first straight frame area along the first direction, the second power main connection line includes: a first main connection line and a second main connection line that are connected to each other. The first main connection line is connected to the second power line, and the second main connection line is electrically connected to the second power pin. The first main connection line extends at least partially along the first direction, and the second main connection line extends at least partially along the second direction. The first main connection line is at least partially located in the first straight frame area, the second main connection line is at least partially located in the rounded corner area adjacent to the first straight frame area along the first direction, and the second power pin is located in the same rounded corner area as the second main connection line.

5. The display module according to claim 4, characterized in that, The second power supply main connection line connects to a plurality of second power supply pins that extend along a second direction.

6. The display module according to claim 4, characterized in that, The second main connection line includes: a power connection segment and a plurality of power connection branches, wherein the power connection segment extends at least partially along a second direction and the power connection branches extend at least partially along a first direction; The power connection segment is electrically connected to the first main connection line and multiple power connection branches respectively. The multiple power connection branches correspond one-to-one with multiple second power pins, and at least one power connection branch is electrically connected to the corresponding second power pin.

7. The display module according to claim 3, characterized in that, The pins further include: driving pins; the display module further includes: a gate driving circuit and a gate driving trace, at least a portion of the gate driving trace extending along a second direction. The gate drive circuit and the gate drive trace are at least partially located in at least one of the straight frame regions of the third straight frame region and the fourth straight frame region, as well as the rounded corner regions adjacent to the straight frame regions along the second direction. The rounded corner regions adjacent to the first straight frame region include: a first adjacent rounded corner region and a second adjacent rounded corner region. The third straight frame region is adjacent to the first adjacent rounded corner region, and the fourth straight frame region is adjacent to the second adjacent rounded corner region. The third straight frame region and the fourth straight frame region are arranged opposite to each other along the first direction. The gate drive trace is electrically connected to the gate drive circuit and the drive pin, respectively. The number of driving pins is multiple, and the multiple driving pins are located in at least one of the first straight border area, at least one rounded corner area of ​​the multiple rounded corner areas, and at least one straight border area other than the first straight border area.

8. The display module according to claim 7, characterized in that, When the plurality of driving pins are located in at least one rounded corner region of the plurality of rounded corner regions and at least one straight border region other than the first straight border region, the plurality of driving pins are located in at least one straight border region of the third or fourth straight border region and at least one adjacent rounded corner region of the straight border region where they are located along the second direction, and at least two of the plurality of driving pins extend along the second direction.

9. The display module according to claim 7, characterized in that, When the plurality of driving pins are located in at least one straight border region other than the first straight border region, the plurality of driving pins are located in at least one straight border region among the third and fourth straight border regions, and the plurality of driving pins extend along the second direction.

10. The display module according to claim 3, characterized in that, The pins include: data pins; the display module further includes: multiple data signal lines and multiple data traces, at least a portion of at least one of the data signal lines and data traces extending along a second direction. The data signal line is located in the display area, and at least a portion of the data trace is located in the first straight border area; The data traces are electrically connected to the data signal lines and data pins, respectively. The number of data pins is multiple, and the multiple data pins are located in the first straight border area, or a portion of the multiple data pins are located in at least one rounded corner area and at least one straight border area other than the first straight border area, and another portion of the multiple data pins are located in the first straight border area.

11. The display module according to claim 10, characterized in that, The display module further includes: a gate driving circuit. When at least a portion of the plurality of data pins is located in at least one rounded corner region of the plurality of rounded corner regions, the data pins include: a first data pin and a second data pin. The first data pin is located in the first straight frame region, and the second data pin is located in the rounded corner region. At least two of the plurality of second data pins are arranged at least partially along a second direction. The orthographic projection of the data trace connected to the second data pin on the substrate does not overlap with the orthographic projection of the gate drive circuit on the substrate.

12. The display module according to claim 10, characterized in that, The display module further includes: a gate driving circuit, wherein at least a portion of the plurality of data pins are located in at least one straight border region other than the first straight border region, and when they are located in at least one region of the third straight border region and the fourth straight border region, the data pins include: a first data pin and a third data pin, wherein the first data pin is located in the first straight border region, and the third data pin is located in at least one region of the third straight border region and the fourth straight border region, and the plurality of third data pins are arranged along the second direction; The orthographic projection of the data trace connected to the third data pin on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate.

13. The display module according to claim 12, characterized in that, The portion of the data trace connected to the third data pin extending along the first direction includes: a first data connection line and a second data connection line; The orthographic projection of the first data connection line on the substrate at least partially overlaps with the orthographic projection of the gate driving circuit on the substrate, while the orthographic projection of the second data connection line on the substrate does not overlap with the orthographic projection of the gate driving circuit on the substrate. The film layer containing the first data connection line is different from the film layer containing the gate drive circuit structure that overlaps with the orthographic projection on the substrate.

14. The display module according to claim 10, characterized in that, The adjacent data pins located in the first straight frame area are connected to data traces in different film layers, and the adjacent data pins located in the rounded corner area or other straight frame areas other than the first straight frame area are connected to data traces in different film layers.

15. The display module according to claim 3, characterized in that, The pins also include: touch pins; the display substrate also includes: multiple touch traces located in the non-display area, and the number of touch pins is two; The touch trace is electrically connected to the touch pin, and the touch pin is located in the first straight edge area.

16. The display module according to claim 1, characterized in that, Multiple pins located in the first pin group extend along a first direction.

17. The display module according to claim 1, characterized in that, The distance between adjacent pins along a first direction or a second direction is in the range of 10 micrometers to 100 micrometers.

18. The display module according to claim 1, characterized in that, The display substrate also includes: multiple signal leads, and the external circuit components include: a flexible circuit board, a driver chip, and a printed circuit board; The multiple signal leads are electrically connected to multiple pins through multiple vias, the flexible circuit board is electrically connected to the multiple signal leads, and the driver chip is disposed on the printed circuit board and electrically connected to the flexible circuit board.

19. The display module according to claim 18, characterized in that, The multiple signal leads are located on the side of the substrate closer to the external circuit assembly.

20. The display module according to claim 18, characterized in that, The multiple signal leads are disposed within the substrate.

21. The display module according to claim 1, characterized in that, The orthographic projection of the external connection component onto the substrate lies within the display area.

22. The display module according to claim 1, characterized in that, The orthographic projection of the at least one via on the substrate lies within the range of the orthographic projection of the at least one pin on the substrate, and the area of ​​the at least one pin is greater than three times the area of ​​the at least one via.

23. A display device, characterized in that, include: The display module as described in any one of claims 1 to 22.

24. A method for manufacturing a display module, characterized in that, The method, configured to manufacture a display module as described in any one of claims 1 to 22, comprises: A display substrate is formed, wherein the display substrate includes: a substrate and a plurality of signal lines and a plurality of pins disposed on the substrate, the plurality of pins being electrically connected to the plurality of signal lines; Vias are formed on the substrate of the display substrate; An external circuit assembly is formed on the backlight side of the display substrate. The external circuit assembly is electrically connected to a plurality of pins through the plurality of vias and is configured to provide signals to the plurality of signal lines connected to the plurality of pins.

Images