Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first signal line and a second signal line. The change rate of the line width of the first signal line is less than that of the second signal line. Since the absolute line width fluctuation amplitude experienced by the signal lines in the same layer in the photoetching and etching process is basically consistent, the smaller line width change rate makes the relative amplitude of the actual line width of the first signal line deviating from the design value smaller under the same process fluctuation, the first signal line is less likely to be short-circuited with adjacent lines due to too thick line width, and is also less likely to be open due to too thin line width, so that the short-circuit and open defect rates of the first signal line are effectively reduced, and thus the yield of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rise of near-eye display technologies such as virtual reality and augmented reality, the market has placed comprehensive demands on display devices, including high pixel density, low latency, high contrast, low power consumption, and low cost. Among these, high pixel density is crucial for achieving immersive visuals and eliminating the screen-door effect. Glass-based organic light-emitting diode (OLED) display technology, combining the self-emissive characteristics of OLEDs with the maturity and low cost of glass substrates, is considered an ideal technological path that balances performance and commercialization.

[0003] However, to achieve ultra-high density driving circuits on glass substrates, the metal conductive layer needs to achieve submicron-level linewidth and spacing. Existing exposure equipment and masks, when processing patterns at this scale, are limited by optical diffraction limits, easily resulting in rough edges, bridging, or breakage, leading to short circuits or open circuits in the metal circuitry. Traditional solutions, relying solely on increasing the precision of the exposure machine or using higher-specification masks, are not only limited by physical limitations but also lead to a sharp increase in manufacturing costs, making it difficult to meet the demands of large-scale mass production.

[0004] Therefore, it is necessary to provide a display panel and display device to improve this deficiency. Summary of the Invention

[0005] This application provides a display panel and display device that can reduce the defect rate of metal circuits.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, having a first area and a second area, the display panel comprising: The first signal line includes a first sub-line located in the first region and a second sub-line located in the second region and connected to the first sub-line; The second signal line is disposed on the same layer as the first signal line, and includes a third sub-line located in the first area and a fourth sub-line located in the second area and connected to the third sub-line; Specifically, the ratio of the absolute value of the linewidth difference between the first sub-line and the second sub-line to the linewidth of the first sub-line is set as the first rate of change, and the ratio of the absolute value of the linewidth difference between the third sub-line and the fourth sub-line to the linewidth of the third sub-line is set as the second rate of change, wherein the first rate of change is less than the second rate of change.

[0007] Optionally, the first rate of change is less than or equal to 5%; And / or, the second rate of change is greater than or equal to 15%.

[0008] Optionally, the absolute value of the linewidth difference between the first sub-line and the second sub-line is less than the absolute value of the linewidth difference between the third sub-line and the fourth sub-line.

[0009] Optionally, the width of the first sub-line is less than or equal to the width of the second sub-line, and the width of the third sub-line is less than the width of the fourth sub-line.

[0010] Optionally, the sum of the line width of the first sub-line and the spacing between two adjacent first sub-lines is less than the sum of the line width of the third sub-line and the spacing between two adjacent third sub-lines. And / or, the sum of the line width of the second sub-line and the spacing between two adjacent second sub-lines is less than the sum of the line width of the third sub-line and the spacing between two adjacent third sub-lines.

[0011] Optionally, the sum of the line width of the first sub-line and the spacing between two adjacent first sub-lines is less than the sum of the line width of the second sub-line and the spacing between two adjacent second sub-lines; And / or, the sum of the line width of the third sub-line and the spacing between the two adjacent third sub-lines is less than the sum of the line width of the fourth sub-line and the spacing between the two adjacent fourth sub-lines.

[0012] Optionally, the distance between two adjacent first sub-lines is less than the distance between two adjacent second sub-lines; And / or, the spacing between two adjacent third sub-lines is less than the spacing between two adjacent fourth sub-lines.

[0013] Optionally, the first signal line is selected from at least one of a data line, a scan line, an initialization signal line, a reference voltage signal line, and a clock signal line; And / or, the second signal line is selected from at least one of a power signal line, a shielded signal line, a dummy signal line, and a test signal line.

[0014] Optionally, the display panel includes a display area, a fan-out trace area located on one side of the display area in the column direction of the display panel, and a gate driving circuit area located on at least one side of the display area in the row direction of the display panel. The first region includes the display region, and the second region includes at least one of the fan-out routing region and the gate drive circuit region.

[0015] Optionally, the display panel includes multiple insulating layers, wherein in at least two adjacent insulating layers, the stress type in one insulating layer is compressive stress and the stress type in the other insulating layer is tensile stress.

[0016] Optionally, the display panel further includes at least one transition layer, which is disposed between two adjacent insulating layers; The stress value of the transition layer is between the stress values ​​of the two adjacent insulating layers, and the stress value of the transition layer gradually changes along the thickness direction of the transition layer.

[0017] Optionally, the display panel further includes a conductive layer and at least one transition layer, the transition layer being disposed between the conductive layer and an adjacent insulating layer; The stress value of the transition layer is between the stress value of the conductive layer and the stress value of the adjacent insulating layer, and the stress value of the transition layer gradually changes along the thickness direction of the transition layer.

[0018] Optionally, along the thickness direction of the transition layer, the absolute value of the stress variation gradient of the transition layer is greater than or equal to 5 MPa / nm.

[0019] Optionally, along the thickness direction of the transition layer, among two points in the transition layer that are no more than 10 nm apart, the absolute value of the difference between the stress value of one point and the stress value of the other point is less than or equal to 30% of the stress value of the one point.

[0020] Optionally, the display panel includes an insulating layer and a filling portion, the insulating layer having a first groove, and the filling portion being disposed within the first groove.

[0021] Optionally, the ratio of the depth of the first groove to the thickness of the insulating layer is greater than or equal to 0.8.

[0022] Optionally, the filling portion includes: A filling sub-part is disposed within the first groove; and An extension sub-part is disposed outside the first groove and connected to the filling sub-part; Wherein, the angle between the tangent plane of at least one point on the side of the extended sub-part and the reference plane is greater than or equal to 15 degrees and less than or equal to 30 degrees, and the reference plane is parallel to the light-emitting surface of the display panel.

[0023] According to a second aspect of this application, a display device is provided, including a display panel as described above.

[0024] In the display panel of this application embodiment, by making the linewidth variation rate of the first signal line smaller than that of the second signal line, since the absolute linewidth fluctuation amplitude experienced by the first and second signal lines in the same layer during the photolithography and etching processes is basically the same, the smaller linewidth variation rate makes the relative deviation of the actual linewidth of the first signal line from the design value smaller under the same process fluctuation. The first signal line is less likely to short-circuit with adjacent lines due to excessive linewidth, and is less likely to open-circuit due to excessive linewidth, effectively reducing the short-circuit and open-circuit defect rate of the first signal line, thereby improving the yield of the display panel.

[0025] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0027] Figure 1 A top view of a display panel provided in the first embodiment of this application; Figure 2 A schematic diagram of the first signal line and the second signal line in a display panel provided for the first embodiment of this application; Figure 3 A diagram showing the film structure of a display panel provided in the second embodiment of this application; Figure 4 A diagram showing the film structure of a display panel provided in the third embodiment of this application; Figure 5 A diagram showing the film structure of a display panel provided in the fourth embodiment of this application; Figure 6 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0029] Please see Figure 1 and Figure 2 , Figure 1 A top view of the display panel provided in the first embodiment of this application. Figure 2 This is a schematic diagram of a first signal line and a second signal line in a display panel provided in the first embodiment of this application. The display panel includes a first region A1 and a second region A2. The display panel includes a first signal line 11 and a second signal line 12, which are disposed on the same layer. The first signal line 11 includes a first sub-line 111 located in the first region A1 and a second sub-line 112 located in the second region A2. The second signal line 12 includes a third sub-line 121 located in the first region A1 and a fourth sub-line 122 located in the second region A2.

[0030] Please see Figure 2 The line width of the first sub-line 111 is the first line width W1, and the line width of the second sub-line 112 is the second line width W2. The ratio of the absolute value of the difference between the line widths of the first sub-line 111 and the second sub-line 112 to the line width of the first sub-line 111 is set as the first rate of change, and the first rate of change R1 = |W1-W2|÷W1.

[0031] The line width of the third sub-line 121 is the third line width W3, and the line width of the fourth sub-line 122 is the fourth line width W4. The ratio of the absolute value of the difference between the line widths of the third sub-line 121 and the fourth sub-line 122 to the line width of the third sub-line 121 is the second rate of change. The second rate of change R2 = |W3-W4|÷W3.

[0032] In some embodiments, the first rate of change R1 is less than the second rate of change R2.

[0033] The first rate of change R1 can be considered as the rate of change of the linewidth of the first signal line 11 when crossing the first region A1 and the second region A2, and the second rate of change R2 can be considered as the rate of change of the linewidth of the second signal line 12 when crossing the first region A1 and the second region A2. The first rate of change R1 of the first signal line 11 is smaller than the second rate of change R2 of the second signal line 12. Since the absolute linewidth fluctuation amplitude experienced by the first signal line 11 and the second signal line 12 in the same layer is basically the same during the photolithography and etching processes, the smaller linewidth change rate makes the relative deviation of the actual linewidth of the first signal line 11 from the design value smaller under the same process fluctuation. The first signal line 11 is less likely to short-circuit with adjacent lines due to excessive linewidth, and is less likely to open-circuit due to excessive linewidth. This effectively reduces the short-circuit and open-circuit defect rate of the first signal line 11, thereby improving the yield of the display panel.

[0034] In some embodiments, the first region A1 is a dense region, and the second region A2 includes a semi-dense region and an isolated region. A dense region refers to an area where the conductive pattern occupies more than 60% of the area per unit area, a semi-dense region refers to an area where the conductive pattern occupies between 30% and 60% of the area per unit area, and an isolated region refers to an area where the conductive pattern occupies less than 30% of the area per unit area.

[0035] In some embodiments, please refer to Figure 1 The display panel 100 includes a display area AA and a non-display area NA disposed around the periphery of the display area AA. The display area AA is the area used to display the image, and may contain multiple sub-pixels, pixel driving circuits for driving the sub-pixels to emit light, multiple data lines, and multiple scan lines. The non-display area NA is the area used to house peripheral circuits, and includes a fan-out trace area NA1 located on the Y-axis side of the display area AA in the column direction of the display panel, and a gate driving circuit area NA2 located on at least one side of the display area AA in the X-axis direction of the display panel.

[0036] In some embodiments, the display area AA has gate drive circuit areas NA2 on both sides in the row direction X.

[0037] In some embodiments, the display area AA is a dense area, the gate drive circuit area NA2 is a semi-dense area, and the fan-out trace area is an isolated area.

[0038] In some embodiments, the first region A1 includes a display region AA, and the second region A2 includes at least one of a gate drive circuit region NA2 and a fan-out trace region NA1.

[0039] In some embodiments, the area of ​​the first region A1 is larger than the area of ​​the display region AA. The first region A1 includes not only the display region AA, but also the area in the non-display region NA where the area of ​​the metal pattern accounts for more than 60%, such as the area in the non-display region NA where a data signal bus is provided.

[0040] In some embodiments, the area of ​​the first region A1 is equal to the area of ​​the display region AA, that is, the first region A is the display region AA.

[0041] In some embodiments, the area of ​​the second region A2 is equal to the area of ​​the non-display region NA, that is, the second region A2 is the non-display region NA.

[0042] In some embodiments, the first signal line 11 is a critical signal line, which is a signal line used to carry highly important signals such as gate signals, data signals, and clock signals.

[0043] In some embodiments, the first signal line 11 is selected from at least one of a data line, a scan line, an initialization signal line, a reference voltage signal line, and a clock signal line. For example, the display panel includes multiple first signal lines 11, which may include data lines, scan lines, initialization signal lines, reference voltage signal lines, and clock signal lines.

[0044] In some embodiments, the second signal line 12 is a non-critical signal line, which is a signal line used to carry low-importance signals such as common voltage signals, shielding signals, power signals, and test signals.

[0045] In some embodiments, the second signal line 12 is selected from at least one of a common voltage signal line, a shielded signal line, a power signal line, a dummy signal line, and a test signal line. For example, the display panel includes multiple second signal lines 12, which may include common voltage signal lines, shielded signal lines, power signal lines, dummy signal lines, and test signal lines.

[0046] In the actual fabrication process, based on the electrical importance level of the signal lines and the density distribution of the surrounding patterns, differentiated and asymmetric pre-distortion compensation is applied to the mask pattern. The first signal line carrying the critical timing signal is given a higher compensation weight, so that it can obtain better dimensional accuracy than the second signal line carrying non-critical signals after exposure. This makes the linewidth change rate of the first signal line less than that of the second signal line.

[0047] In some embodiments, assigning a higher compensation weight to the first signal line can be understood as follows: by using the loading effect during the etching process as a feedback variable, the exposure energy and focal length during the photolithography stage are dynamically adjusted so that the critical dimensions of the photoresist pattern are preset with a reverse offset before etching. This automatically compensates for the pattern size offset caused by the micro-loading effect after etching, resulting in higher dimensional accuracy and lower linewidth variation rate of the first signal line. In this way, without replacing the existing exposure equipment, the sum of the linewidth of the first signal line 11 carrying the critical signal and the line spacing of adjacent first signal lines 11 can be limited to within 2.8 micrometers, and the short-circuit defect rate of the first signal line 11 can be reduced to less than one in ten thousand.

[0048] In some embodiments, the first rate of change R1 is less than or equal to 5%. For example, the first rate of change R1 can be 5%, 4.5%, 4%, 3%, 2%, 1%, or 0.5%, etc., which can effectively reduce the risk of short-circuit defects in the first signal line carrying the critical signal, thereby improving the yield of the display panel.

[0049] In some embodiments, the second rate of change R2 is greater than or equal to 15%. For example, the second rate of change R2 can be 15%, 17%, 20%, 25%, or 30%, etc. This relaxes the requirements for the linewidth change rate of the second signal line 12, thereby prioritizing the use of process margin to ensure a smaller linewidth change rate of the first signal line 11, reducing the risk of short-circuit defects in the first signal line carrying critical signals, and thus improving the yield of the display panel.

[0050] In some embodiments, please refer to Figure 2 The absolute value of the line width difference between the first sub-line 111 and the second sub-line 112 is less than the absolute value of the line width difference between the third sub-line 121 and the fourth sub-line 122, that is, |W1-W2| < |W3-W4|.

[0051] When crossing from the sparser region A2 to the denser region A1, the linewidth change of the first signal line 11 is less than that of the second signal line 12. The linewidth change of the first signal line 11 is minimal, less than 5%, while the linewidth change of the second signal line 12 is significant, exceeding 15%. When crossing from region A2 to region A1, the second signal line 12 exhibits a "waist-tightening" shape, and when crossing from region A1 to region A2, the second signal line 12 exhibits an "expanding" shape.

[0052] In some embodiments, please refer to Figure 1 The line width of the first sub-line 111 is smaller than that of the second sub-line 112, i.e., W1 < W2. It should be noted that since the first region is a dense region with more metal patterns and requires higher precision, the line width of different parts of the first signal line 11 is differentiated so that the line width of the first sub-line 111 is smaller than that of the second sub-line 112. This gives the part of the first signal line 11 that carries the critical signal located in the dense region (i.e., the first sub-line 111) a higher compensation weight than the second sub-line 112. This can reduce the risk of short circuit defects in the first signal line in the dense region.

[0053] In some embodiments, the line width of the first sub-line 111 is equal to the line width of the second sub-line 112, i.e., W1 = W2. At this time, the line width change rate of the first signal line 11 is 0 or close to 0. The line width of the portion of the first signal line 11 located in the first region A1 is the same as that of the portion located in the second region A2. This can also reduce the risk of short circuit defects in the first signal line in the dense area.

[0054] In some embodiments, please refer to Figure 1 The line width of the third sub-line 121 is smaller than that of the fourth sub-line 122, i.e. W3 < W4. This makes it easier to assign a higher compensation weight to the first signal line 11 that carries the key signal, which helps to reduce the risk of short circuit defects in the first signal line in dense areas.

[0055] In some embodiments, please refer to Figure 2 The sum of the line width of the first sub-line 111 and the spacing between the two adjacent first sub-lines 111 is less than the sum of the line width of the third sub-line 121 and the spacing between the two adjacent third sub-lines 121, i.e., W1+D1<W3+D3; and / or, the sum of the line width of the second sub-line 112 and the spacing between the two adjacent second sub-lines 112 is less than the sum of the line width of the third sub-line 121 and the spacing between the two adjacent third sub-lines 121, i.e., W2+D2<W4+D4.

[0056] By assigning a higher compensation weight to the first signal line 11, not only can the linewidth change rate of the first signal line 11 be less than that of the second signal line 12, but the sum of the linewidth of the first signal line 11 and the spacing between adjacent first signal lines 11 can also be less than the sum of the linewidth of the second signal line 12 and the spacing between adjacent second signal lines 12. This allows the first signal line 11 to have a smaller linewidth and spacing in both the first region A1 and the second region A2. This reduces the short-circuit failure rate of critical signal lines while increasing the density of the driving circuit, thereby enabling the realization of an ultra-high density driving circuit of over 1500 PPI (Pixels Per Inch) on the glass substrate.

[0057] In some embodiments, the sum of the line width of the first sub-line 111 and the spacing between two adjacent first sub-lines 111 is less than the sum of the line width of the second sub-line 112 and the spacing between two adjacent second sub-lines 112. The sum of the line width of the third sub-line 121 and the spacing between two adjacent third sub-lines 121 is less than the sum of the line width of the fourth sub-line 122 and the spacing between two adjacent fourth sub-lines 122.

[0058] In some embodiments, please refer to Figure 2 The sum of the line width of the first sub-line 111 and the spacing between the two adjacent first sub-lines 111 is less than the sum of the line width of the second sub-line 112 and the spacing between the two adjacent second sub-lines 112, i.e., W1+D1 < W2+D2. The sum of the line width of the third sub-line 121 and the spacing between the two adjacent third sub-lines 121 is less than the sum of the line width of the fourth sub-line 122 and the spacing between the two adjacent fourth sub-lines 122, i.e., W3+D3 < W4+D4.

[0059] It should be noted that, since the first area is a dense area with many metal patterns, higher precision is required. By differentiating the line width and spacing of different parts of the first signal line 11, the sum of the line width of the first sub-line 111 and the spacing of the adjacent first sub-line 111 is less than the sum of the line width of the second sub-line 112 and the spacing of the adjacent second sub-line 112. This gives the part of the first signal line 11 carrying the critical signal located in the dense area (i.e., the first sub-line 111) a higher compensation weight than the second sub-line 112. This can reduce the risk of short circuit defects in the first signal line in the dense area. Similarly, by differentiating the line width and spacing of different parts of the second signal line 12, the sum of the line width of the third sub-line 121 and the spacing of the adjacent third sub-line 121 is less than the sum of the line width of the fourth sub-line 122 and the spacing of the adjacent fourth sub-line 122. This gives the part of the second signal line 12 located in the dense area (i.e., the third sub-line 121) a higher compensation weight than the fourth sub-line 122, thereby reducing the risk of short circuit defects in the second signal line in the dense area.

[0060] In some embodiments, the spacing between two adjacent first sub-lines 111 is less than the spacing between two adjacent second sub-lines 112; and / or, the spacing between two adjacent third sub-lines 121 is less than the spacing between two adjacent fourth sub-lines 122.

[0061] In some embodiments, please refer to Figure 2 The spacing between two adjacent first sub-lines 111 is smaller than the spacing between two adjacent second sub-lines 112, i.e., D1 < D2. The spacing between two adjacent third sub-lines 121 is smaller than the spacing between two adjacent fourth sub-lines 122, i.e., D3 < D4. This not only assigns a higher compensation weight to the portion of the first signal line 11 carrying critical signals located in the dense area (i.e., the first sub-line 111) compared to the second sub-line 112, thereby reducing the risk of short-circuit defects in the first signal line in the dense area, but also assigns a higher compensation weight to the portion of the second signal line 12 located in the dense area (i.e., the third sub-line 121) compared to the fourth sub-line 122, thus reducing the risk of short-circuit defects in the second signal line in the dense area.

[0062] Please see Figure 3 , Figure 3The diagram illustrates the film layer structure of a display panel according to a second embodiment of this application. The display panel 100 includes multiple insulating layers 2. In at least two adjacent insulating layers 2, one insulating layer 2 exhibits compressive stress, while the other insulating layer 2 exhibits tensile stress. By making the stress types of at least two adjacent insulating layers 2 opposite, the stresses of adjacent film layers in the stacked structure of the display panel can cancel each other out, causing the overall net stress of the display panel to approach zero. Even during subsequent high-temperature processes, the thermal expansion differences between the film layers can be absorbed by the stress neutralization structure formed by the insulating layers with opposite stress types, thereby suppressing film bulging and peeling.

[0063] It should be noted that "adjacent" in the context of two adjacent insulating layers refers to the two insulating layers being adjacent in the thickness direction of the display panel. The two insulating layers are stacked along the thickness direction, with one insulating layer placed on top of the other adjacent insulating layer and in direct contact with it. This allows the stress in the two insulating layers to cancel each other out, reducing the risk of film bulging and peeling.

[0064] In some embodiments, at least one insulating layer 2 is made of silicon nitride, and by controlling the bonding ratio of silicon-hydrogen bonds and nitrogen-hydrogen bonds in the insulating layer, the insulating layer 2 formed of silicon nitride material is made to exhibit a compressive stress state.

[0065] In some embodiments, at least one insulating layer 2 is made of silicon oxide. By controlling the ratio of oxidant to silicon source gas, the insulating layer formed of silicon oxide can be made to exhibit a tensile stress state.

[0066] In some embodiments, please refer to Figure 3 The plurality of insulating layers 2 include a plurality of inorganic insulating layers. Specifically, the plurality of inorganic insulating layers include a first inorganic insulating layer 201, a second inorganic insulating layer 202 and a third inorganic insulating layer 203 stacked on the substrate 1 along the thickness direction. The stress type in the first inorganic insulating layer 201 is opposite to the stress type in the second inorganic insulating layer 202, and the stress type in the second inorganic insulating layer 202 is opposite to the stress type in the third inorganic insulating layer 203.

[0067] In some embodiments, please refer to Figure 3 The stress type in the first inorganic insulating layer 201 is compressive stress, the stress type in the second inorganic insulating layer 202 is tensile stress, and the stress type in the third inorganic insulating layer 203 is compressive stress. The stress in the second inorganic insulating layer 202 and the adjacent first inorganic insulating layer 201 and third inorganic insulating layer 203 can cancel each other out, making the overall net stress close to zero, thus suppressing the occurrence of film bulging and peeling. The materials of the first inorganic insulating layer 201 and the third inorganic insulating layer 203 are both silicon nitride, and the material of the second inorganic insulating layer 202 includes silicon oxide.

[0068] In some embodiments, the plurality of inorganic insulating layers comprising the first inorganic insulating layer 201, the second inorganic insulating layer 202, and the third inorganic insulating layer 203 may be selected from the buffer layer, gate insulating layer, interlayer dielectric layer, and passivation layer already present in the display panel. This allows the stress of adjacent film layers in the stacked structure of the display panel to cancel each other out without increasing the film layer structure and related process of the display panel, so that the overall net stress of the display panel tends to be zero, thereby suppressing the occurrence of film layer bulging and peeling.

[0069] In some embodiments, the display panel further includes at least one transition layer disposed between two adjacent insulating layers. The stress value of the transition layer is between the stress values ​​of the two adjacent insulating layers, and the stress value of the transition layer gradually changes along the thickness direction of the transition layer. This can eliminate the stress abrupt interface between two adjacent insulating layers with opposite stress types, disperse the interface peeling driving force into the transition layer, thereby suppressing the occurrence of film peeling.

[0070] In some embodiments, a transition layer may be disposed between two adjacent inorganic insulating layers with opposite stress types. For example, a transition layer may be disposed between a first inorganic insulating layer 201 and a second inorganic insulating layer 202. The stress value of the transition layer is between the stress value of the first inorganic insulating layer 201 and the stress value of the second inorganic insulating layer 202. The stress value of the transition layer changes monotonically and continuously along its thickness direction. The stress type of the portion of the transition layer near the first inorganic insulating layer 201 is the same as the stress type in the first inorganic insulating layer 201, and the stress type of the portion of the transition layer near the second inorganic insulating layer 202 is the same as the stress type in the second inorganic insulating layer 202. This can eliminate the stress abrupt interface between two adjacent insulating layers with opposite stress types, disperse the interface peeling driving force into the transition layer, and thereby suppress the occurrence of film peeling.

[0071] In some embodiments, the plurality of insulating layers 2 include inorganic insulating layers and organic insulating layers, wherein the stress type in at least one inorganic insulating layer is opposite to the stress type in an adjacent organic insulating layer, so that the stresses of the inorganic insulating layer and the adjacent organic insulating layer can cancel each other out.

[0072] In some embodiments, please refer to Figure 3 The plurality of insulating layers 2 include at least one organic insulating layer 203, and an organic insulating layer 204 disposed on the third inorganic insulating layer 203. The stress type in the organic insulating layer 204 is opposite to the stress type in the third inorganic insulating layer 203. The stress type in the third inorganic insulating layer 203 is compressive stress, and the stress type in the organic insulating layer 204 is tensile stress.

[0073] In some embodiments, the organic insulating layer 204 can be any organic insulating layer in an existing display panel. For example, the organic insulating layer 204 can be a planarization layer or a pixel definition layer.

[0074] In some embodiments, please refer to Figure 3 The display panel includes at least one transition layer 205, which is disposed between the third inorganic insulating layer 203 and the organic insulating layer 204. The stress value of the transition layer 205 is between the stress values ​​of the third inorganic insulating layer 203 and the organic insulating layer 204. The stress value of the transition layer 205 gradually changes along its thickness direction, which can eliminate the stress abrupt interface between the third inorganic insulating layer 203 and the organic insulating layer 204 and disperse the interface peeling driving force into the transition layer, thereby suppressing the occurrence of film peeling.

[0075] In some embodiments, the stress value of the transition layer varies monotonically and continuously along its thickness direction. The stress variation gradient value of the transition layer along its thickness direction is greater than or equal to 5 MPa / nm. This can eliminate the stress abrupt interface between the upper and lower membrane layers of the transition layer, disperse the interface peeling driving force into the transition layer, and thus suppress the occurrence of membrane peeling.

[0076] In some embodiments, along the thickness direction of the transition layer 205, the absolute value of the difference between the stress value of one point and the stress value of the other point at two points within the transition layer 205 that are no more than 10 nm apart is less than or equal to 30% of the stress value of the first point.

[0077] by Figure 3 For example, the portion shown by the two dashed lines in the transition layer 205 can be regarded as two points in the transition layer 205 with a distance of no more than 10 nm. The ratio of the absolute value of the difference between the stress value of one point and the stress value of the other point to the stress value of one point is the rate of change of the stress values ​​of the two points. This rate of change can be 30%, 28%, 25%, or 20%, etc. As long as the stress change gradient value is greater than or equal to 5 MPa / nm, and the absolute value of the difference between the stress value of one point and the stress value of the other point is ensured to be less than 30%, the stress of the two adjacent films in the transition layer 205 can be smoothly transitioned at the transition layer without any sudden change in the stress value peak or stress jump, thereby suppressing the occurrence of film bulging and peeling.

[0078] In some embodiments, the material of the transition layer includes any one of silicon oxide, silicon nitride, and silicon oxynitride.

[0079] In practical applications, the transition layer can be deposited by varying the gas flow rate ratio. The stress value of the transition layer is between the stress values ​​of the adjacent films above and below, so as to eliminate the stress abrupt interface and disperse the driving force of interface peeling to the transition layer, thereby suppressing the occurrence of film bulging and peeling.

[0080] In practical applications, a confocal Raman spectrometer can be used to perform line scanning analysis along the thickness direction of the transition layer, with a scan compensation of less than or equal to 10 nm. By measuring the characteristic Raman peak positions of nitrogen-silicon bonds or oxygen-silicon bonds in the transition layer, the local stress value is calculated based on the peak position shift. Compressive stress is defined as positive and tensile stress as negative. From the side of the transition layer near the lower third inorganic insulating layer 203 to the side near the upper organic insulating layer 204, the Raman peak position continuously shifts, corresponding to a monotonically continuous change in stress value with a gradient value greater than or equal to 5 MPa / nm, and there are no abrupt peak position changes or stress jumps.

[0081] In some embodiments, the display panel includes a plurality of insulating layers 2 stacked along the thickness direction, the plurality of insulating layers 2 being stacked along the thickness direction to form a composite insulating layer, wherein at least two adjacent insulating layers in the composite insulating layer have opposite stress types.

[0082] In some embodiments, the display panel includes a plurality of insulating layers 2 stacked along the thickness direction. In any two adjacent insulating layers 2, the stress type in one insulating layer 2 is compressive stress and the stress type in the other insulating layer 2 is tensile stress. This can further cancel out the stress of adjacent film layers in the stacked structure of the display panel, making the overall net stress of the display panel approach zero. Even in subsequent high-temperature processes, the thermal expansion difference of each film layer can be absorbed by the stress neutralization structure formed by the insulating layers with opposite stress types, thereby suppressing the occurrence of film layer bulging and peeling.

[0083] In some embodiments, the display panel further includes a conductive layer and at least one transition layer, the transition layer being disposed between the conductive layer and an adjacent insulating layer, the stress value of the transition layer being between the stress value of the conductive layer and the stress value of the adjacent insulating layer, and the stress value of the transition layer gradually changing along the thickness direction of the transition layer, thereby eliminating the stress abrupt interface between the conductive layer and the adjacent insulating layer and dispersing the interface peeling driving force to the transition layer.

[0084] In some embodiments, the display panel includes at least one gate layer, at least one source-drain layer, and at least one metal overlap layer. The conductive layer may be selected from at least one of the gate layer, the source-drain layer, and the metal overlap layer, and the insulating layer may be an insulating layer adjacent to the gate layer or the source-drain layer.

[0085] In some embodiments, the plurality of inorganic insulating layers including the first inorganic insulating layer 201, the second inorganic insulating layer 202, and the third inorganic insulating layer 203, as well as the buffer layer, can be selected from the buffer layer, gate insulating layer, interlayer dielectric layer, and passivation layer already present in the display panel. In this way, without increasing the film layer structure and related process of the display panel, the stress of adjacent film layers in the stacked structure of the display panel can cancel each other out, so that the overall net stress of the display panel tends to be zero, thereby suppressing the occurrence of film layer bulging and peeling.

[0086] In some embodiments, the display panel includes at least one buffer layer, at least one gate insulating layer, at least one interlayer dielectric layer, at least one passivation layer, at least one planarization layer, and at least one pixel definition layer. The inorganic insulating layer among the plurality of insulating layers 2 may be selected from at least one of the buffer layer, gate insulating layer, interlayer dielectric layer, and passivation layer. The transition layer may be selected from at least one of the gate insulating layer, interlayer dielectric layer, and passivation layer, and is disposed separately from the aforementioned inorganic insulating layer. The organic insulating layer among the plurality of insulating layers 2 may be selected from at least one of the planarization layer and the pixel definition layer.

[0087] like Figure 4 As shown, Figure 4 The third embodiment of this application provides a film layer structure diagram of a display panel. The display panel includes an insulating layer 2 and a filling portion 3. The insulating layer 2 is provided with a first groove 4, and the filling portion 3 is disposed in the first groove 4.

[0088] exist Figure 4 In the third embodiment shown, the display panel includes at least one gate insulating layer, at least one interlayer dielectric layer, at least one passivation layer, at least one planarization layer, and at least one pixel definition layer. The insulating layer 2 with the first groove 4 can be selected from at least one of the interlayer dielectric layer, passivation layer, and planarization layer.

[0089] In some embodiments, such as Figure 4 As shown, the display panel includes a third interlayer dielectric layer ILD3, a second gate layer GE2, a first passivation layer PV1, a first planarization layer PLN1, a third source / drain layer (not shown in the figure), a second passivation layer PV2, a first metal overlap layer M1, a second planarization layer PLN2, a third passivation layer PV3, a fourth source / drain layer SD4, a fourth passivation layer PV4, an anode layer ANO, a pixel definition layer PDL, a light-emitting layer, and a cathode layer (not shown in the figure), stacked along the thickness direction of the display panel.

[0090] In some embodiments, please refer to Figure 4The insulating layer 2 with the first groove 4 can be a second planarization layer PLN2. The second planarization layer PLN2 has the first groove 4, and the filling part 3 is disposed in the first groove 4 to fill the first groove 4, eliminate the depression terrain at the first groove 4, improve the flatness of other film layers subsequently formed above the first groove 4, so that the thickness uniformity fluctuation of the subsequent photoresist above the first groove 4 is less than 5%, fundamentally eliminating the problem of etching residue or over-etching caused by uneven photoresist.

[0091] In some embodiments, the ratio of the depth of the first groove 4 to the thickness of the insulating layer 2 is greater than or equal to 0.8.

[0092] In some embodiments, such as Figure 4 As shown, the insulating layer 2 is the second planarization layer PLN2. The second planarization layer PLN2 may have a first groove 4 and a second groove. The depth of the first groove 4 is greater than the depth of the second groove. The depth of the first groove 4 exceeds a threshold. The filling part 3 fills the first groove 4 but does not fill the second groove. This can avoid the situation where the film layer thickens due to the setting of the filling part in unnecessary areas, which would lead to the subsequent etching load effect fixture.

[0093] In some embodiments, the ratio of the depth of the first groove 4 to the thickness of the second planarization layer PLN2 is greater than 0.8. 0.8 times the thickness of the second planarization layer PLN2 can be regarded as the threshold of the groove depth. When the depth of the groove is greater than 0.8 times the thickness of the second planarization layer PLN2, it needs to be filled with the filling part 3. For grooves with a depth less than 0.8 times the thickness of the second planarization layer PLN2, it is not necessary to fill them.

[0094] In some embodiments, please refer to Figure 4 The depth of the first groove 4 is greater than the thickness of the second planarization layer PLN2. The first groove 4 not only penetrates the second planarization layer PLN2, but also extends further downward into the second passivation layer PV2, thus increasing the depth of the first groove 4. By using the filling part 3 to fill the first groove 4, the problem of etching residue or over-etching caused by uneven photoresist can be avoided.

[0095] In some embodiments, the depth of the first groove 4 may be less than the thickness of the second planarization layer PLN2, but it is necessary to ensure that the ratio of the depth of the first groove 4 to the thickness of the second planarization layer PLN2 is greater than 0.8. In this way, the problem of etching residue or over-etching due to uneven photoresist can be avoided, while also avoiding the situation where the film layer thickens due to the presence of filling parts in unnecessary areas, which would lead to subsequent etching load effect fixtures.

[0096] In some embodiments, the ratio of the depth of the first groove 4 to the thickness of the insulating layer 2 is greater than or equal to 0.8 and less than or equal to 1.5, so as to avoid the situation where the filling part 3 cannot be filled due to the excessive depth of the first groove 4.

[0097] In some embodiments, please refer to Figure 4 The filling portion 3 includes a filling sub-portion 31 and an extension sub-portion 32. The filling sub-portion 31 is disposed within the first groove 4 to fill the first groove 4, and the extension sub-portion 32 is disposed outside the first groove 4 and connected to the filling sub-portion 31. The thickness of the filling portion 3 is greater than the depth of the first groove 4. The extension sub-portion 32 can be considered as the portion overflowing from the first groove 4 to the peripheral edge of the first groove 4. The extension sub-portion 32 is formed on the surface of the second flat layer PLN2 at the peripheral edge of the first groove 4, thus ensuring that the filling portion 3 completely fills the first groove 4.

[0098] In some embodiments, please refer to Figure 4 The angle between the tangent plane TP1 at at least one point on the side of the extended sub-part 32 and the reference plane RP1 is a first included angle a1. The first included angle a1 is greater than or equal to 15 degrees and less than or equal to 30 degrees. The first included angle a1 can be 15 degrees, 18 degrees, 20 degrees, 25 degrees, 28 degrees or 30 degrees, etc. The reference plane RP1 is parallel to the light-emitting surface of the display panel.

[0099] In some embodiments, the material of the filling portion 3 includes a photosensitive organic material, and the angle between the tangent plane TP1 at at least one point on the side of the extension portion 32 and the reference plane RP1 can be regarded as the slope angle of the extension portion 32. By limiting the slope angle of the filling portion 3 at the edge of the first groove 4 to between 15 degrees and 30 degrees through photolithography, a gentle slope structure can be formed at the edge of the first groove 4 using the filling portion 3. During subsequent deposition of the metal layer, the metal layer can be guided to form a gradual thickness transition at the step, thereby avoiding the occurrence of fracture due to abrupt thickness changes at steep steps.

[0100] It should be noted that, Figure 4 This illustration only shows the structure and relative position of the first groove and the filling part, and only shows a portion of the film layer structure of the display panel, not the entire film layer structure of the display panel, nor does it represent the film layer structure of the display panel in actual applications. In actual applications, the film layer structure of the display panel can be replaced with the film layer structure of an existing display panel to achieve the same or similar function, and no restrictions are imposed here.

[0101] Please see Figure 5 , Figure 5This is a diagram showing the film structure of a display panel according to the fourth embodiment of this application. The fourth embodiment is a combination of the first, second, and third embodiments. Specifically, the display panel 100 of the fourth embodiment includes the first signal line 11 and the second signal line 12 described in the first embodiment, the multilayer insulating layer 2 and transition layer described in the second embodiment, and the insulating layer 2 and filling portion 3 described in the third embodiment. The specific configuration of each of the above structures can be referred to the corresponding descriptions in the first to third embodiments, and will not be repeated here.

[0102] By combining the technical solutions of the first to third embodiments, this embodiment can simultaneously achieve the following beneficial effects: First, it solves the problem of limited pattern miniaturization capability, improves the accuracy of key signal lines without replacing existing exposure equipment, and reduces their short-circuit defect rate to less than one in ten thousand; Second, it optimizes the stress distribution of the film layer, so that the stress of adjacent film layers in the display panel stacking structure cancels each other out, and the overall net stress approaches zero, thereby suppressing film layer bulging and peeling; Third, it improves the trench coverage quality, reduces the risk of metal lines breaking in trenches with greater depth, and avoids etching residue or over-etching caused by uneven photoresist coverage.

[0103] In summary, this embodiment achieves the manufacturing of low-cost, mass-producible high-performance glass-based organic light-emitting diode (OLED) display panels while ensuring high yield and high reliability. This helps to break through the cost bottleneck of silicon-based OLED display panels and promotes the large-scale popularization of high-end virtual reality and augmented reality display devices.

[0104] In some embodiments, such as Figure 5 As shown, the display panel includes a substrate 1 and a buffer layer, an active layer AL, a first gate insulating layer GI1, a first gate layer GE1, a first interlayer dielectric layer ILD1, a first source-drain layer SD1, a second interlayer dielectric layer ILD2, a second source-drain layer SD2, a third interlayer dielectric layer ILD3, a second gate layer GE2, a first passivation layer PV1, a first planarization layer PLN1, a third source-drain layer SD3, a second passivation layer PV2, a first metal overlap layer M1, a second planarization layer PLN2, a third passivation layer PV3, a fourth source-drain layer SD4, a fourth passivation layer PV4, an anode layer ANO, a pixel definition layer PDL, a light-emitting layer, and a cathode layer (not shown in the figure) stacked sequentially on the substrate 1.

[0105] In some embodiments, the substrate 1 is made of glass, i.e., the substrate 1 is a glass substrate. Using a glass substrate as the substrate of the display panel helps to reduce the cost of the display panel.

[0106] In some embodiments, please refer to Figure 2 and Figure 5The display panel 100 includes a first signal line 11 and a second signal line 12, both of which have the same structure as in the first embodiment. The first signal line 11 and the second signal line 12 are disposed on the same layer and can be disposed simultaneously on at least one of the first gate layer GE1, the second gate layer GE2, the first source-drain layer SD1, the second source-drain layer SD2, and the third source-drain layer SD3.

[0107] It should be noted that when the first signal line 11 and the second signal line 12 are simultaneously disposed in two or more metal film layers, the first signal line 11 is only compared with the second signal line 12 located in the same layer in terms of linewidth change rate. For example, the first signal line 11 in the second gate layer GE2 is only compared with the second signal line 12 in the second gate layer GE2, and the first signal line 11 in the second source-drain layer SD2 is only compared with the second signal line 12 in the second source-drain layer SD2. In this way, the accuracy of critical signal lines in different metal film layers can be improved and the short-circuit defect rate can be reduced.

[0108] In some embodiments, the display panel 100 includes a plurality of insulating layers 2, which may be selected from at least two of the following: a buffer layer, a first gate insulating layer GI1, a first interlayer dielectric layer ILD1, a second interlayer dielectric layer ILD2, a third interlayer dielectric layer ILD3, a first passivation layer PV1, a first planarization layer PLN1, a second passivation layer PV2, a second planarization layer PLN2, a third passivation layer PV3, a fourth passivation layer PV4, and a pixel definition layer PDL.

[0109] In some embodiments, at least two adjacent insulating layers 2 have opposite stress types, i.e., one is compressive stress and the other is tensile stress. The stress type setting of the insulating layers 2 in this embodiment can be referred to in the second embodiment. For example, the first gate insulating layer GI1 has a compressive stress type, and the adjacent first interlayer dielectric layer ILD1 has a tensile stress type.

[0110] In some embodiments, Figure 5 The first gate insulating layer GI1, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, the first passivation layer PV1, the second passivation layer PV2, the third passivation layer PV3, and the fourth passivation layer PV4 shown can be regarded as inorganic insulating layers in the second embodiment.

[0111] In some embodiments, the display panel 100 further includes at least one transition layer disposed between two adjacent insulating layers with opposite stress types. The stress value of the transition layer 205 is between the stress values ​​of the films above and below it to eliminate stress abruptness at the interface, disperse the interface peeling driving force into the transition layer, thereby suppressing film bulging and peeling.

[0112] In some embodiments, the transition layer 205 may be selected from at least one of the first gate insulating layer GI1, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, the first passivation layer PV1, the first planarization layer PLN1, the second passivation layer PV2, the second planarization layer PLN2, the third passivation layer PV3, and the fourth passivation layer PV4, or it may be a new layer added on the basis of an existing film layer.

[0113] In some embodiments, please refer to Figure 5 If the stress type of the third interlayer dielectric layer ILD3 is set to compressive stress, and the stress type of the first planarization layer PLN1 is set to tensile stress, then the first passivation layer PV1 can be reused as a transition layer. The stress value of the first passivation layer PV1 is between the stress value of the third interlayer dielectric layer ILD3 and the stress value of the first planarization layer PLN1, and gradually changes along the thickness direction. The specific structure of the first passivation layer PV1 as a transition layer can be referred to in the second embodiment.

[0114] In some embodiments, please refer to Figure 3 and Figure 5 In the second embodiment, the first inorganic insulating layer 201, the second inorganic insulating layer 202, and the third inorganic insulating layer 203 can correspond one-to-one with the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the third interlayer dielectric layer ILD3 of this embodiment, or they can correspond to other inorganic insulating layers.

[0115] In some embodiments, please refer to Figure 3 and Figure 5 In the second embodiment, the organic insulating layer 204 can correspond to the first planarization layer PLN1, the second planarization layer PLN2, or the pixel definition layer PDL in this embodiment.

[0116] In some embodiments, please refer to Figure 5 The display panel has a first groove 4 and a filling portion 3, with the filling portion 3 disposed within the first groove 4. The first groove 4 can be formed in the insulating layer of the display panel, such as a second planarization layer PLN2, a first interlayer dielectric layer ILD1, a second interlayer dielectric layer ILD2, a third interlayer dielectric layer ILD3, a first passivation layer PV1, a first planarization layer PLN1, a second passivation layer PV2, or a third passivation layer PV3, etc. When the depth of the first groove 4 is greater than a threshold, the filling portion 3 is used to fill it to avoid etching residue or over-etching caused by uneven photoresist coverage. The structure of the filling portion 3 can be referred to in the third embodiment.

[0117] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 6 , Figure 6The diagram below shows the structure of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be any of the display panels provided in the above embodiments and can achieve the same technical effects as the above embodiments. Further details are omitted here.

[0118] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel and a display device. The display panel includes a first signal line and a second signal line. The first signal line includes a first sub-line located in a first region and a second sub-line located in a second region and connected to the first sub-line. The second signal line is disposed on the same layer as the first signal line and includes a third sub-line located in the first region and a fourth sub-line located in the second region and connected to the third sub-line. A first rate of change is set as the ratio of the absolute value of the linewidth difference between the first sub-line and the second sub-line to the linewidth of the first sub-line. A first rate of change is set as the ratio of the absolute value of the linewidth difference between the third sub-line and the second sub-line to the linewidth of the first sub-line. The ratio of the absolute value of the linewidth difference of the four sub-lines to the linewidth of the third sub-line is the second rate of change. The first rate of change is smaller than the second rate of change. Since the absolute linewidth fluctuation amplitude experienced by the signal lines in the same layer during the photolithography and etching processes is basically the same, the smaller linewidth change rate makes the actual linewidth of the first signal line deviate from the design value by a smaller relative amplitude under the same process fluctuation. The first signal line is less likely to short-circuit with adjacent lines due to excessive linewidth, and is less likely to open-circuit due to excessive linewidth. This effectively reduces the short-circuit and open-circuit defect rate of the first signal line, thereby improving the yield of the display panel.

[0119] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0120] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0121] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0122] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a first zone and a second zone. The first signal line includes a first sub-line located in the first region and a second sub-line located in the second region and connected to the first sub-line; The second signal line is disposed on the same layer as the first signal line, and includes a third sub-line located in the first area and a fourth sub-line located in the second area and connected to the third sub-line; Specifically, the ratio of the absolute value of the linewidth difference between the first sub-line and the second sub-line to the linewidth of the first sub-line is set as the first rate of change, and the ratio of the absolute value of the linewidth difference between the third sub-line and the fourth sub-line to the linewidth of the third sub-line is set as the second rate of change, wherein the first rate of change is less than the second rate of change.

2. The display panel as described in claim 1, characterized in that, The first rate of change is less than or equal to 5%; And / or, the second rate of change is greater than or equal to 15%.

3. The display panel as described in claim 1, characterized in that, The absolute value of the linewidth difference between the first sub-line and the second sub-line is less than the absolute value of the linewidth difference between the third sub-line and the fourth sub-line.

4. The display panel as described in claim 1, characterized in that, The width of the first sub-line is less than or equal to the width of the second sub-line, and the width of the third sub-line is less than the width of the fourth sub-line.

5. The display panel as described in claim 1, characterized in that, The sum of the line width of the first sub-line and the spacing between the two adjacent first sub-lines is less than the sum of the line width of the third sub-line and the spacing between the two adjacent third sub-lines. And / or, the sum of the line width of the second sub-line and the spacing between two adjacent second sub-lines is less than the sum of the line width of the third sub-line and the spacing between two adjacent third sub-lines.

6. The display panel as described in claim 1, characterized in that, The sum of the line width of the first sub-line and the spacing between two adjacent first sub-lines is less than the sum of the line width of the second sub-line and the spacing between two adjacent second sub-lines; And / or, the sum of the line width of the third sub-line and the spacing between the two adjacent third sub-lines is less than the sum of the line width of the fourth sub-line and the spacing between the two adjacent fourth sub-lines.

7. The display panel as described in claim 1, characterized in that, The distance between two adjacent first sub-lines is less than the distance between two adjacent second sub-lines; And / or, the spacing between two adjacent third sub-lines is less than the spacing between two adjacent fourth sub-lines.

8. The display panel as described in claim 1, characterized in that, The first signal line is selected from at least one of a data line, a scan line, an initialization signal line, a reference voltage signal line, and a clock signal line; And / or, the second signal line is selected from at least one of a power signal line, a shielded signal line, a dummy signal line, and a test signal line.

9. The display panel as claimed in claim 1, characterized in that, The display panel includes a display area, a fan-out trace area located on one side of the display area in the column direction of the display panel, and a gate drive circuit area located on at least one side of the display area in the row direction of the display panel. The first area is the display area, and the second area is selected from at least one of the fan-out routing area and the gate drive circuit area.

10. The display panel as claimed in any one of claims 1 to 9, characterized in that, The display panel includes multiple insulating layers, and in at least two adjacent insulating layers, one insulating layer has a compressive stress and the other insulating layer has a tensile stress.

11. The display panel as claimed in claim 10, characterized in that, The display panel further includes at least one transition layer, which is disposed between two adjacent insulating layers; The stress value of the transition layer is between the stress values ​​of the two adjacent insulating layers, and the stress value of the transition layer gradually changes along the thickness direction of the transition layer.

12. The display panel as claimed in claim 10, characterized in that, The display panel further includes a conductive layer and at least one transition layer, the transition layer being disposed between the conductive layer and an adjacent insulating layer; The stress value of the transition layer is between the stress value of the conductive layer and the stress value of the adjacent insulating layer, and the stress value of the transition layer gradually changes along the thickness direction of the transition layer.

13. The display panel as described in claim 11 or 12, characterized in that, Along the thickness direction of the transition layer, the absolute value of the stress variation gradient of the transition layer is greater than or equal to 5 MPa / nm.

14. The display panel as described in claim 11 or 12, characterized in that, Along the thickness direction of the transition layer, among two points in the transition layer that are no more than 10 nm apart, the absolute value of the difference between the stress value of one point and the stress value of the other point is less than or equal to 30% of the stress value of the first point.

15. The display panel as claimed in any one of claims 1 to 9, characterized in that, The display panel includes an insulating layer and a filling portion. The insulating layer has a first groove, and the filling portion is disposed within the first groove.

16. The display panel as claimed in claim 15, characterized in that, The ratio of the depth of the first groove to the thickness of the insulating layer is greater than or equal to 0.

8.

17. The display panel as claimed in claim 15, characterized in that, The filling portion includes: A filling sub-part is disposed within the first groove; and An extension sub-part is disposed outside the first groove and connected to the filling sub-part; Wherein, the angle between the tangent plane of at least one point on the side of the extended sub-part and the reference plane is greater than or equal to 15 degrees and less than or equal to 30 degrees, and the reference plane is parallel to the light-emitting surface of the display panel.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

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