Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided, the display device including a display panel including a display area and a non-display area including a first non-display area and a second non-display area, and a connection circuit part electrically connected to the display panel to overlap the first non-display area, wherein the display panel includes a base, a first inorganic layer, and a first organic layer, the first inorganic layer is disposed on the base and a first recessed area is defined in the first inorganic layer, and the first organic layer is disposed on the first inorganic layer to be in contact with the first inorganic layer, and wherein the first recessed area overlaps a first line that is a boundary line between the first non-display area and the second non-display area.

Description

[0001] This application claims priority and all benefits derived therefrom to Korean Patent Application No. 10-2025-0036622, filed on March 21, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to an apparatus, and more specifically, to a display apparatus and an electronic apparatus. Background Technology

[0003] Portable electronic devices are widely used. As mobile electronic devices, not only are compact electronic devices such as mobile phones widely used, but tablet personal computers are also widely used.

[0004] To support various functions, such mobile electronic devices include display devices to provide users with visual information such as images or videos. Recently, with the miniaturization of other components used to drive the display devices, the proportion of display devices in electronic devices is gradually increasing, and structures capable of bending display devices from a flat state to a predetermined angle are being developed. Summary of the Invention

[0005] The embodiment includes a display device comprising a display panel having improved adhesion between an inorganic layer and an organic layer.

[0006] However, such an objective is only one of many, and the objectives to be addressed are not limited to this.

[0007] Additional features will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the presented embodiments.

[0008] In the disclosed embodiments, the display device includes a display panel and a connection circuit portion. The display panel includes a display area and a non-display area comprising a first non-display area and a second non-display area. The connection circuit portion is electrically connected to the display panel to be superimposed on the first non-display area. The display panel includes a substrate, a first inorganic layer disposed on the substrate and defining a first recessed area, and a first organic layer disposed on the first inorganic layer to contact the first inorganic layer. The first recessed area is superimposed on a first line that serves as the boundary line between the first non-display area and the second non-display area.

[0009] In an embodiment, the first line may include: a first-1 line extending in a first direction parallel to the bending axis along which the connecting circuit portion bends; and a first-2 line extending from the first-1 line in a second direction intersecting the first direction, and the first groove region may overlap with the first-2 line.

[0010] In an embodiment, a plurality of first groove regions may be provided, and the plurality of first groove regions may be spaced apart from each other along a second direction at a position overlapping with the first-2 line.

[0011] In an embodiment, at least two of the plurality of first groove regions may have different sizes.

[0012] In an embodiment, the first groove region may include a first-1 groove region and a first-2 groove region connected to the first-1 groove region.

[0013] In an embodiment, the first-1 groove area can be disposed in the first non-display area, and the first-2 groove area can be disposed in the second non-display area.

[0014] In an embodiment, the first inorganic layer may further include a second recessed region defined within the first non-display area.

[0015] In an embodiment, the display panel may further include: a driving transistor disposed on a substrate to be stacked with the display area; and a light-emitting element disposed on a first organic layer to be stacked with the display area and electrically connected to the driving transistor.

[0016] In an embodiment, the driving transistor may include: a semiconductor layer disposed within a first inorganic layer; and a gate electrode disposed between the first inorganic layer and a first organic layer.

[0017] In an embodiment, the display panel may further include a pad portion disposed in a first non-display area to be spaced apart from the first recessed area and electrically connected to a connection circuit portion.

[0018] In the disclosed embodiments, the electronic device includes a display panel and a connection circuit portion. The display panel includes a display area and a non-display area comprising a first non-display area and a second non-display area. The connection circuit portion is electrically connected to the display panel to be stacked with the first non-display area. The display panel includes a substrate, a first inorganic layer disposed on the substrate and defining a first recessed area, and a first organic layer disposed on the first inorganic layer to contact the first inorganic layer. The first recessed area is configured to be stacked with each of the first non-display area and the second non-display area.

[0019] In an embodiment, the first groove region may include a first-1 groove region and a first-2 groove region connected to the first-1 groove region.

[0020] In an embodiment, the first-1 groove area can be disposed in the first non-display area, and the first-2 groove area can be disposed in the second non-display area.

[0021] In an embodiment, the first inorganic layer may further include a second recessed region configured to overlap with the first non-display area but not with the second non-display area.

[0022] In an embodiment, the display panel may further include: a driving transistor disposed on a substrate to be stacked with the display area; and a light-emitting element disposed on a first organic layer to be stacked with the display area and electrically connected to the driving transistor.

[0023] In an embodiment, the driving transistor may include: a semiconductor layer disposed within a first inorganic layer; and a gate electrode disposed between the first inorganic layer and a first organic layer.

[0024] In one embodiment, the first recessed region may be superimposed on a first line that serves as the boundary line between the first non-display region and the second non-display region.

[0025] In an embodiment, the first line may include: a first-1 line extending in a first direction parallel to the bending axis along which the connecting circuit portion bends; and a first-2 line extending from the first-1 line in a second direction intersecting the first direction; and the first groove region may overlap with the first-2 line.

[0026] In an embodiment, a plurality of first groove regions may be provided, and the plurality of first groove regions may be spaced apart from each other along a second direction at a position overlapping with the first-2 line.

[0027] In an embodiment, the display panel may further include a pad portion disposed in a first non-display area to be spaced apart from the first recessed area and electrically connected to a connection circuit portion.

[0028] Other features and advantages, in addition to those described above, will become apparent from the following figures, claims, and detailed embodiments. Attached Figure Description

[0029] The above and other features and advantages of the disclosed illustrative embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 and Figure 2 This is a plan view schematically illustrating an embodiment of the display device; Figure 3 This is a perspective view schematically illustrating an embodiment of the display panel; Figure 4 This is a schematic cross-sectional view illustrating an embodiment of the display device; Figure 5 and Figure 6 This is a cross-sectional view schematically illustrating an embodiment of the display panel; Figure 7 and Figure 8It can be set Figure 1 An equivalent circuit diagram of an embodiment of pixels in a display panel; Figure 9 This is a cross-sectional view schematically showing a portion of an embodiment of the display panel; Figure 10 and Figure 11 This is a cross-sectional view schematically showing a portion of an embodiment of the display device; Figure 12 and Figure 13 This is a plan view schematically showing a portion of an embodiment of a display device; Figure 14 This is a cross-sectional view schematically showing a portion of an embodiment of the display device; Figure 15 A block diagram of an embodiment of an electronic device; and Figure 16 This is a perspective view schematically illustrating an embodiment of an electronic device. Detailed Implementation

[0030] Referring now to the embodiments, illustrative embodiments shown in the accompanying drawings, in which the same reference numerals consistently denote the same elements. In this respect, the illustrated embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain the described features. As used herein, the term "and / or" can include any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0031] Because the disclosure allows for various variations and numerous embodiments, illustrative embodiments will be shown in the accompanying drawings and described in the detailed description. The effects and features of the disclosure, as well as methods of implementing it, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be embodied in various forms.

[0032] In the following description, embodiments will be described in detail with reference to the accompanying drawings, in which the same or corresponding elements are always represented by the same reference numerals, and repeated descriptions thereof are omitted.

[0033] Although terms such as "first," "second," etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0034] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0035] It will be understood that the terms “comprising” and “having” are intended to indicate the presence of a feature or element described in the specification, and not to exclude the possibility that one or more other features or elements may be present or added.

[0036] It will also be understood that when a layer, region, or component is referred to as being “on” another layer, region, or component, it may be directly on the other layer, region, or component, or indirectly on the other layer, region, or component, with an intermediary layer, region, or component in between.

[0037] For ease of explanation, the dimensions of components in the accompanying drawings may be exaggerated or reduced. For example, the disclosure is not limited thereto because the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of explanation.

[0038] In the following examples, the X-axis, Y-axis, and Z-axis directions are not limited to the directions corresponding to the three axes of a Cartesian coordinate system, but can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0039] When the illustrative embodiments can be implemented differently, the predetermined process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0040] In the instruction manual, "plan view" refers to a view perpendicular to the base at 100° (refer to...). Figure 1 The two-dimensional view seen in the direction of the base (refer to). That is, "A and B spaced apart from each other in the plan view" means "when viewed perpendicularly to the base 100 (see reference)". Figure 1 When viewed from the direction of A and B, they are spaced apart from each other.

[0041] In the instruction manual, "sectional view" refers to a view perpendicular to the base at 100° (refer to...). Figure 1 A two-dimensional view cut in a direction perpendicular to the base (refer to...). That is, "A and B, spaced apart from each other in the sectional view" means "cut in a direction perpendicular to the base 100 (refer to...)". Figure 1 A and B, separated from each other, are cut in the direction of the two-dimensional view.

[0042] Figure 1 and Figure 2 This is a plan view schematically showing an embodiment of display device 1. Figure 3 This is a perspective view schematically illustrating an embodiment of a display panel DP. Figure 4 This is a schematic cross-sectional view of the display device 1.

[0043] Reference Figures 1 to 4 The display device 1 may include a display panel DP, a connection circuit portion CP, and a connection portion CNP.

[0044] The display panel DP may include a display area DA and a non-display area NDA extending outside the display area DA. The display panel DP can display images through the display area DA. The display panel DP is described as an organic light-emitting display device in one embodiment, but the disclosed display device is not limited thereto. In embodiments, the display panel DP may include an inorganic light-emitting display device or a quantum dot light-emitting display device. The emitting layer of the light-emitting element (e.g., a light-emitting diode) disposed in the display panel DP may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0045] The display device 1 includes a substrate 100 and a package substrate 235. A sealing portion 303 may be disposed between the substrate 100 and the package substrate 235. The sealing portion 303 surrounds the periphery of the package substrate 235 and the substrate 100, and can bond the substrate 100 and the package substrate 235 together.

[0046] Display device 1 includes a display area DA and a non-display area NDA extending around the display area DA. Display device 1 can provide an image by emitting light from a plurality of pixels P disposed in the display area DA.

[0047] The display area DA may include a plurality of pixels P connected to a scan line SL extending in a first direction (e.g., the X-axis direction) and a data line DL extending in a second direction (e.g., the Y-axis direction) intersecting the first direction (e.g., the X-axis direction). Each pixel P may also be connected to a drive voltage line PL extending in the second direction (e.g., the Y-axis direction).

[0048] Each of the multiple pixels P may include a light-emitting element, such as an organic light-emitting diode (OLED) (see reference). Figure 7 The light-emitting diode (OLED) is used to emit light. In an embodiment, for example, each pixel P may emit red, green, blue, or white light via an OLED. In an embodiment, all OLEDs included in a plurality of pixels P emit the same color, and for example, the color of each pixel P may be achieved by means of a color filter or the like disposed on top of the OLED.

[0049] Each pixel P can be electrically connected to multiple built-in circuits disposed in the non-display area NDA. In an embodiment, for example, a first power supply wiring 304, a second power supply wiring 305, and a pad (or "solder pad") portion PD can be disposed in the non-display area NDA.

[0050] The first power supply line 304 can be disposed on one side of the display area DA, for example, at the bottom of the display device 1. The first power supply line 304 can be connected to the drive voltage ELVDD (refer to...) Figure 7 Multiple drive voltage lines PL are transmitted to pixel P. A second power supply wiring 305 may partially surround the display area DA in a ring shape with an opening on one side. The second power supply wiring 305 may provide a common voltage ELVSS (refer to...) to the counter electrode of pixel P. Figure 7 ).

[0051] The pad portion PD has multiple pad terminals 514 and can be disposed in the non-display area NDA of the substrate 100. Each pad terminal 514 can be connected to a first connection wiring 308 connected to a first power supply wiring 304, or can be connected to a connection wiring CW extending to the display area DA. Each pad terminal 514 can be electrically connected to a connection board 600. A drive terminal portion 700 of the connection board 600 can be electrically connected to the pad portion PD. The drive terminal portion 700 can include multiple drive terminals 710. The multiple drive terminals 710 can be electrically connected to multiple corresponding pad terminals 514.

[0052] The connection circuit board 600 can transmit signals or power from the control unit (not shown) to the pad portion PD. The control unit can transmit the drive voltage ELVDD (refer to...) via the first connection wiring 308. Figure 7 The common voltage ELVSS (refer to) is supplied to the first power supply wiring 304. The control unit can supply the common voltage ELVSS (refer to) via the second connection wiring 309. Figure 7 Provides a second power supply cabling 305.

[0053] The data drive circuit section 800 is electrically connected to the data line DL. The data signal of the data drive circuit section 800 can be provided to each pixel P through the connection wiring CW connected to the pad section PD and the data line DL connected to the connection wiring CW. Figure 1 The diagram shows a data drive circuit portion 800 disposed on a connection circuit board 600, but in another embodiment, the data drive circuit portion 800 may be disposed on a substrate 100. In an embodiment, for example, the data drive circuit portion 800 may be disposed between the pad portion PD and the first power supply wiring 304.

[0054] The dam portion 313 may be disposed in the non-display area NDA. The dam portion 313 may prevent organic material from flowing in the direction toward the edge of the substrate 100 during the formation of the organic encapsulation layer of the thin-film encapsulation layer, thereby preventing the formation of edge tails in the organic encapsulation layer. The dam portion 313 may surround at least a portion of the display area DA. The dam portion 313 may include multiple dams. When the dam portion 313 may include multiple dams, the individual dams may be disposed separately from each other. The dam portion 313 may be disposed closer to the display area DA than the sealing portion 303.

[0055] Figure 1 A connection circuit board 600 is shown attached to the pad portion PD, but as Figure 2 As shown, multiple connecting circuit boards 600 can be attached to the pad portion PD. The pad portion PD can be disposed along both sides of the substrate 100. The pad portion PD can include multiple sub-pad portions PDS, and each connecting circuit board 600 can be attached to each of the sub-pad portions PDS.

[0056] Reference Figure 4 The connecting circuit portion CP may include a first portion CPP1 fixed to the display panel DP, a second portion CPP2 bent around the bending axis BAX, and a third portion CPP3 disposed at the bottom of the display panel DP. The non-display area NDA may include a first non-display area NDA1 superimposed on the first portion CPP1 of the connecting circuit portion CP and a second non-display area NDA2 not superimposed on the first portion CPP1 of the connecting circuit portion CP. In the first non-display area NDA1, the connecting portion CNP may fix the display panel DP and the first portion CPP1 of the connecting circuit portion CP together. When the second portion CPP2 bends, the third portion CPP3 may be disposed at the bottom side of the display panel DP. However, when the second portion CPP2 bends, the elastic force of the second portion CPP2 may be transmitted to the display panel DP. Therefore, stress may occur in the first non-display area NDA1 of the display panel DP.

[0057] Figure 5 and Figure 6 This is a cross-sectional view schematically illustrating an embodiment of the display panel DP.

[0058] Reference Figure 5 The display panel DP includes a substrate 100, a display element layer 220 on the substrate 100, and an encapsulation member 230 covering the display element layer 220.

[0059] The substrate 100 may include a polymer resin. The substrate 100 may have a single-layer structure or a multi-layer structure, and in the case of a multi-layer structure, the substrate 100 may further include an inorganic layer (not shown). The substrate 100 may have flexible, rollable, or bendable properties.

[0060] Display element layer 220 includes a plurality of pixels, and each pixel may include an organic light-emitting diode (OLED) and pixel circuitry electrically connected to the OLED. The pixel circuitry may include transistors, storage capacitors, and wires connected thereto, and may include an insulating layer.

[0061] The encapsulation member 230 can protect the display element layer 220 from foreign matter such as moisture. The encapsulation member 230 can be a thin film encapsulation layer including at least one inorganic encapsulation layer 231 or 233 (hereinafter also referred to as the first inorganic encapsulation layer 231 or the second inorganic encapsulation layer 233) and at least one organic encapsulation layer 232.

[0062] Figure 5 The encapsulation component 230 includes a first inorganic encapsulation layer 231, a second inorganic encapsulation layer 233, and an organic encapsulation layer 232 disposed between the first inorganic encapsulation layer 231 and the second inorganic encapsulation layer 233, but the disclosure is not limited thereto. The stacking order of the inorganic encapsulation layers 231 and 233 and the organic encapsulation layer 232 can be changed in various ways. Figure 5 The encapsulation component 230 is shown as a thin-film encapsulation layer, but the disclosure is not limited thereto.

[0063] Reference Figure 6 The display panel DP may include a substrate 100, a display element layer 220 on the substrate 100, and an encapsulation member 230 including a sealing portion 303 and an encapsulation substrate 235. Figure 6 The substrate 100 may include glass or polymer resin.

[0064] The encapsulation substrate 235 is positioned facing the substrate 100, and a sealing portion 303 may be disposed between the substrate 100 and the encapsulation substrate 235. The sealing portion 303 may surround the display area DA. The internal space defined by the substrate 100, the encapsulation substrate 235, and the sealing portion 303 is spatially separated from the outside and can prevent the intrusion of moisture or impurities. The encapsulation substrate 235 may include glass, polymer resin, etc., and the sealing portion 303 may use materials such as glass frit or epoxy resin.

[0065] Figure 7 and Figure 8 It can be set Figure 1 An equivalent circuit diagram of an embodiment of pixel P in a display panel DP.

[0066] Reference Figure 7 Each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0067] The pixel circuit PC includes a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. The switching transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving transistor T1 according to the scan signal Sn input through the scan line SL.

[0068] The storage capacitor Cst is connected to the switching transistor T2 and the drive voltage line PL, and stores the voltage corresponding to the difference between the voltage received from the switching transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0069] The driving transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing through the organic light-emitting diode (OLED) from the driving voltage line PL can be controlled in response to the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness according to the driving current.

[0070] Figure 7 The illustration shows a pixel circuit PC comprising two transistors and a storage capacitor, but the disclosure is not limited thereto.

[0071] Reference Figure 8 Each pixel P may include an organic light-emitting diode (OLED) and a pixel circuit PC including multiple transistors for controlling the OLED. The pixel circuit PC may include a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst.

[0072] The scan line SL can be connected to the gate electrode G2 of the switching transistor T2, the data line DL can be connected to the source electrode S2, and the first electrode CE1 of the storage capacitor Cst can be connected to the drain electrode D2. Therefore, in response to the scan signal Sn from the scan line SL of each pixel P, the switching transistor T2 supplies the data voltage Dm of the data line DL to the first node N.

[0073] The gate electrode G1 of the driving transistor T1 is connected to the first node N, the source electrode S1 is connected to the driving voltage line PL that transmits the driving voltage ELVDD, and the drain electrode D1 can be connected to the pixel electrode (e.g., the anode electrode) of the organic light-emitting diode OLED. Therefore, the driving transistor T1 can adjust the amount of current flowing in the organic light-emitting diode OLED according to the source-gate voltage (i.e., the voltage difference between the driving voltage ELVDD and the voltage of the first node N).

[0074] The sensing control line SSL can be connected to the gate electrode G3 of the sensing transistor T3, the source electrode S3 can be connected to the second node S, and the drain electrode D3 can be connected to the reference voltage line RL. In some embodiments, the sensing transistor T3 can be controlled by the scan line SL instead of the sensing control line SSL.

[0075] The sensing transistor T3 can sense the potential of the pixel electrode (e.g., the anode electrode) of the organic light-emitting diode (OLED). In response to a sensing signal SSn from the sensing control line SSL, the sensing transistor T3 supplies a pre-charge voltage from the reference voltage line RL to the second node S, or supplies the voltage of the pixel electrode (e.g., the anode electrode) of the organic light-emitting diode (OLED) to the reference voltage line RL during the sensing period.

[0076] The storage capacitor Cst has a first electrode CE1 connected to a first node N and a second electrode CE2 connected to a second node S. The storage capacitor Cst stores the voltage difference between the voltages supplied to each of the first node N and the second node S, and supplies this voltage difference as the drive voltage for the driving transistor T1. In an embodiment, for example, the storage capacitor Cst may store the voltage difference between a data signal Dm and a pre-charge voltage supplied to each of the first node N and the second node S.

[0077] The bias electrode BSM is formed to correspond to the driving transistor T1 and can be connected to the source electrode S3 of the sensing transistor T3. The bias electrode BSM receives a voltage combined with the potential of the source electrode S3 of the sensing transistor T3, thereby stabilizing the driving transistor T1. In some embodiments, the bias electrode BSM can be connected to a separate bias wiring instead of the source electrode S3 of the sensing transistor T3.

[0078] The counter electrode (e.g., the cathode electrode) of an organic light-emitting diode (OLED) can receive a common voltage ELVSS. The OLED emits light after receiving a drive current from the driving transistor T1.

[0079] although Figure 8 The illustration shows a configuration where signal lines SL, SSL, and DL, a reference voltage line RL, and a drive voltage line PL are provided for each pixel P; however, the disclosure is not limited thereto. In embodiments, for example, at least one of the signal lines SL, SSL, and DL, as well as the reference voltage line RL and the drive voltage line PL, may be shared by adjacent pixels P.

[0080] Pixel circuit PC is not limited to reference Figure 7 and Figure 8 The number of transistors and storage capacitors and the circuit design are described, and their number and circuit design can be varied.

[0081] Figure 9 This is a cross-sectional view schematically showing a portion of an embodiment of a display panel DP.

[0082] In detail, Figure 9 It is based on Figure 1 Cross-sectional views of the display panel DP along lines I-I', II-II', and III-III'. Figure 9 References are shown Figure 7 The described pixel circuit PC includes a driving transistor T1 and a storage capacitor Cst.

[0083] Reference Figure 9 The display panel DP includes a substrate 100. The substrate 100 may include materials such as glass, ceramic, metal, or polymer. A first inorganic layer IL1 may be disposed on the substrate 100. The first inorganic layer IL1 may include a first-1 inorganic layer IL1-1, a first-2 inorganic layer IL1-2, and a first-3 inorganic layer IL1-3.

[0084] The first inorganic layer IL1-1 can be disposed on the substrate 100. The first inorganic layer IL1-1 can block foreign matter or moisture that penetrates the substrate 100. In embodiments, for example, the first inorganic layer IL1-1 may include inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, and may comprise a single layer or multiple layers.

[0085] A bias electrode BSM can be disposed on the first inorganic layer IL1-1. A driving transistor T1 can be disposed on the substrate 100 to be stacked with the display area DA. Specifically, the driving transistor T1 can be disposed on the bias electrode BSM. The bias electrode BSM can be stacked with the semiconductor layer A1 of the driving transistor T1. A voltage can be applied to the bias electrode BSM. In an embodiment, for example, the bias electrode BSM can be connected to the sensing transistor T3 (see reference). Figure 8 The source electrode S3 (refer to) Figure 8 This allows a voltage to be applied to the source electrode S3. Additionally, the bias electrode BSM blocks external light from reaching the semiconductor layer A1. Therefore, the characteristics of the driving transistor T1 can be stabilized. In another embodiment, the bias electrode BSM can be omitted.

[0086] The first-second inorganic layer IL1-2 may cover the bias electrode BSM. The first-second inorganic layer IL1-2 may be disposed throughout the entire area of ​​the substrate 100. The first-second inorganic layer IL1-2 may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may be a single layer or multiple layers.

[0087] Semiconductor layer A1 can be disposed on the first-2 inorganic layer IL1-2. Semiconductor layer A1 may include polycrystalline silicon, amorphous silicon, oxide semiconductor, organic semiconductor materials, etc. In an embodiment, semiconductor layer A1 may include a channel region, a source region, and a drain region. The channel region is stacked with the gate electrode G1. The source region and drain region are disposed on opposite sides of the channel region and include or consist of impurities with a higher concentration than those in the channel region. Impurities may include N-type impurities or P-type impurities.

[0088] The first inorganic layer IL1-3 can cover the semiconductor layer A1. That is, the semiconductor layer A1 can be disposed within the first inorganic layer IL1. The first inorganic layer IL1-3 can be an inorganic layer such as silicon nitride, silicon oxide, or silicon oxynitride, and can be a single layer or multiple layers. A gate electrode G1 can be disposed on the first inorganic layer IL1-3. The gate electrode G1 can include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The gate electrode G1 can be a single layer or multiple layers.

[0089] A first organic layer OL1 may be disposed on and in contact with a first inorganic layer IL1. The first electrode CE1 of the storage capacitor Cst may be disposed in the same layer as the gate electrode G1. The first electrode CE1 may comprise the same material as the gate electrode G1. The first organic layer OL1 may cover both the gate electrode G1 and the first electrode CE1 of the storage capacitor Cst. That is, the gate electrode G1 may be disposed between the first inorganic layer IL1 and the first organic layer OL1. The first organic layer OL1 may be an organic layer such as a polymer. The first organic layer OL1 may be monolayer or multilayer.

[0090] The source electrode S1, drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL can be disposed on the first organic layer OL1. The source electrode S1, drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL can include Al, Cu, Ti, etc., and can all be single-layer or multi-layer. In an embodiment, the source electrode S1, drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the driving voltage line PL can have a Ti / Al / Ti multilayer structure. The source electrode S1 and drain electrode D1 can be connected to the source and drain regions of the semiconductor layer A1, respectively, through contact holes. The source electrode S1 can be connected to the driving voltage line PL.

[0091] The storage capacitor Cst has a second electrode CE2 stacked with a first electrode CE1, and a first organic layer OL1 disposed between the second electrode CE2 and the first electrode CE1, thus forming a capacitor. In this case, the first organic layer OL1 can be used as the dielectric layer of the storage capacitor Cst. The thickness of the first organic layer OL1 can be designed according to the capacitance value of the storage capacitor Cst.

[0092] The protective layer 400 may cover the source electrode S1, drain electrode D1, the second electrode CE2 of the storage capacitor Cst, and the drive voltage line PL. The protective layer 400 may be an inorganic layer such as silicon nitride, silicon oxide, or silicon oxynitride. The protective layer 400 may protect the conductive layer or wiring disposed on the first organic layer OL1.

[0093] In the display area DA, a planarization layer 508 may be disposed on the protective layer 400. The planarization layer 508 may include an organic material, and the organic material may include imide polymers, general-purpose polymers (such as polymethyl methacrylate or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or any combination thereof. In an embodiment, the planarization layer 508 may include polyimide.

[0094] When the protective layer 400 containing inorganic material is absent, wiring or conductive layers such as the drive voltage line PL may be oxidized or corroded due to reaction with oxygen penetrating from the planarization layer 508. However, since the embodiments may include the protective layer 400, wiring or conductive layers such as the drive voltage line PL may not directly contact the planarization layer 508.

[0095] An organic light-emitting diode (OLED) is disposed on a first organic layer OL1 to be stacked with a display area DA, and can be electrically connected to a driving transistor T1. Specifically, the OLED can be disposed on a planarization layer 508. The OLED includes a pixel electrode 509, a counter electrode 511, and an intermediate layer 510 including an emission layer.

[0096] The pixel electrode 509 can be electrically connected to the drain electrode D1 through contact holes penetrating the planarization layer 508. The pixel electrode 509 can also be connected to the drain electrode D1 via a first conductive protective layer 513. The first conductive protective layer 513 can cover the drain electrode D1. The first conductive protective layer 513 can be a metal layer to prevent damage to the drain electrode D1.

[0097] The pixel electrode 509 can be a (semi-)transparent electrode or a reflective electrode. In an embodiment, the pixel electrode 509 may have a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any combination thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may comprise at least one material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO), or composed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 509 may be ITO / Ag / ITO.

[0098] A dam layer 512 may be disposed on the planarization layer 508. The dam layer 512 defines an opening OP that exposes a portion of the pixel electrode 509, and the light-emitting area may be defined by the opening OP. The dam layer 512 may be an organic material such as polyimide or hexamethyldisiloxane.

[0099] The intermediate layer 510 may include an emission layer. Functional layers such as hole transport layers, hole injection layers, electron transport layers, and electron injection layers may optionally be further disposed below and above the emission layer. The emission layer may include low molecular weight organic materials or polymeric organic materials.

[0100] When the emitter layer may include low molecular weight organic materials, the intermediate layer 510 may be stacked in the form of a single structure or a composite structure including a hole injection layer, a hole transport layer, an emitter layer, an electron transport layer, and an electron injection layer. The low molecular weight organic materials may include various organic materials (including copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine, tri-8-hydroxyquinoline aluminum (Alq3), etc.). The emitter layer may be formed by vacuum deposition.

[0101] When the emitter layer may comprise a polymeric organic material, the intermediate layer 510 may have a structure including a hole transport layer and an emitter layer. The emitter layer may comprise a polymeric material based on polyphenylene oxide (PPV), polyfluorene, etc. The emitter layer may be formed by screen printing, inkjet printing, laser-induced thermal imaging (LITI), etc.

[0102] The counter electrode 511 can be a transparent electrode or a reflective electrode. In embodiments, the counter electrode 511 can be a transparent or translucent electrode and can include a metal thin film with a relatively low work function and comprising Li, Ca, LiF, Al, Ag, Mg and any combination thereof, as well as multilayer structures such as LiF / Ca and / or LiF / Al. Furthermore, transparent conductive oxide (TCO) films such as ITO, IZO, ZnO, In2O3, etc., can also be disposed on the metal thin film. The counter electrode 511 can extend not only to the display area DA, but also to areas such as... Figure 1 The non-display area NDA is shown outside the display area DA. The counter electrode 511 can be disposed on the intermediate layer 510.

[0103] In the non-display area NDA, the connection wiring CW can be disposed on the first inorganic layer IL1 (specifically, the first-3 inorganic layers IL1-3). The connection wiring CW can extend to the display area DA. The connection wiring CW can include the same material as the gate electrode G1. The first organic layer OL1 can cover the connection wiring CW.

[0104] The pad portion PD may include pad terminals 514 and a conductive protective layer 515. Pad terminals 514 may be disposed on a first organic layer OL1. Pad terminals 514 may be electrically connected to the connection wiring CW via contact holes. Pad terminals 514 may include Al, Cu, Ti, etc., and may be a single layer or multiple layers. The protective layer 400 may cover the edges of the pad terminals 514. The conductive protective layer 515 may cover the exposed upper surface of the pad terminals 514. The conductive protective layer 515 may include a metal having a lower degree of oxidation than the material included in the pad terminals 514 or having excellent corrosion resistance. In an embodiment, the top layer of the pad terminals 514 may include Cu, and the conductive protective layer 515 may include Ti.

[0105] Figure 10 and Figure 11 This is a cross-sectional view schematically showing a portion of an embodiment of the display device 1. Figure 12 and Figure 13 This is a plan view schematically showing a portion of an embodiment of the display device 1.

[0106] In detail, Figure 10 and Figure 11 It is along Figure 1 A cross-sectional view of display device 1 taken by line IV-IV'. Figure 10 and Figure 12 This diagram shows the state of the connection circuit section CP before it is connected to the display panel DP. Figure 11 and Figure 13 This diagram shows the state in which the connection circuit section CP is connected to the display panel DP.

[0107] Reference Figures 10 to 13 The display device 1 may include a display panel DP, a connection circuit portion CP, and a connection portion CNP.

[0108] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. When the display panel DP and the connection circuit portion CP are connected to each other, the first non-display area NDA1 may be an area superimposed on the connection circuit portion CP. That is, the connection circuit portion CP may be electrically connected to the display panel DP so as to be superimposed on the first non-display area NDA1. In addition, the connection portion CNP may be superimposed on the first non-display area NDA1.

[0109] When the display panel DP and the connection circuit section CP are connected to each other, the second non-display area NDA2 can be an area that does not overlap with the connection circuit section CP. Figure 12 and Figure 13 In the illustration, the planar shape of the first non-display area NDA1 is shown as a square, but this is only an illustrative embodiment, and the shape of the first non-display area NDA1 is not limited thereto.

[0110] In the plan view, the boundary between the first non-display area NDA1 and the second non-display area NDA2 can be defined as a first line LN1. The first line LN1 may include a first-1 line LN1-1 extending in a first direction (e.g., the X-axis direction) parallel to the bending axis BAX of the connecting circuit portion CP, and a first-2 line LN1-2 extending in a second direction (e.g., the Y-axis direction). Figure 12 and Figure 13 As shown, when the planar shape of the first non-display area NDA1 is square, one first-1 line LN1-1 can be set, and two first-2 lines LN1-2 can be set.

[0111] The first non-display area NDA1 may include a first-1 non-display area NDA1-1 and a first-2 non-display area NDA1-2. The first-1 non-display area NDA1-1 may be triangular in shape, having two sides that are part of a first-2 line LN1-2 and a first-1 line LN1-1 extending from the first-2 line LN1-2. The first-2 non-display area NDA1-2 may be a region within the first non-display area NDA1 that does not overlap with the first-1 non-display area NDA1-1. In an embodiment, as... Figure 12 and Figure 13 As shown, for example, the first non-display area NDA1 may include two first-1 non-display areas NDA1-1 and one first-2 non-display area NDA1-2. Figure 4As shown, when the connecting circuit portion CP is bent, the stress applied to the display panel DP in a third direction (e.g., the Z-axis direction) may be greatest at the location where it overlaps with the first-1 non-display area NDA1-1.

[0112] The first inorganic layer IL1 can be disposed on the substrate 100. Specifically, the first-2 inorganic layer IL1-2 can be disposed on the first-1 inorganic layer IL1-1, and the first-3 inorganic layer IL1-3 can be disposed on the first-2 inorganic layer IL1-2. The first organic layer OL1 can be disposed on the first inorganic layer IL1.

[0113] The pad portion PD can be disposed in the first non-display area NDA1 (specifically, the first-2 non-display areas NDA1-2). The pad portion PD may include a plurality of pad terminals 514 and a plurality of conductive protective layers 515. The pad terminals 514 are disposed on the first organic layer OL1 and can be connected to the corresponding connection wiring CW through contact holes penetrating the first organic layer OL1. The pad terminals 514 may be spaced apart along a first direction (e.g., the X-axis direction). The edge of each pad terminal 514 may be covered by the protective layer 400. A portion of the upper surface of each of the pad terminals 514 may be exposed from the protective layer 400. The conductive protective layer 515 may be disposed on the upper surface of the exposed pad terminal 514.

[0114] The connection circuit portion CP can be disposed on the substrate 100. The connection circuit portion CP can be a chip-on-film (COF). The connection circuit portion CP can include a connection circuit board 600 and a drive terminal portion 700 disposed on the connection circuit board 600, the connection circuit board 600 comprising or composed of a flexible film. The drive terminal portion 700 can be configured to face the pad portion PD and can include a plurality of drive terminals 710. The drive terminals 710 can include at least one conductive layer, such as a copper layer. An additional conductive layer (e.g., a tin layer) (not shown) can also be disposed on the outer surface of the drive terminals 710. The material used for the drive terminals 710 is not limited thereto, and the drive terminals 710 can be made of any material with excellent conductivity. The drive terminals 710 can be spaced apart in a first direction (e.g., the X-axis direction).

[0115] The drive terminal portion 700 can be electrically connected to each pad portion PD. In an embodiment, for example, the drive terminal portion 700 and the pad terminal 514 can be connected in a third direction (e.g., the Z-axis direction). Figure 10 and Figure 11As shown, the connecting portion CNP that electrically connects the drive terminal portion 700 and the pad terminal 514 to each other may be disposed between the drive terminal portion 700 and the pad terminal 514. In another embodiment, the drive terminal portion 700 and the pad terminal 514 may be directly connected to each other. In the following description, the explanation is provided assuming that the connecting portion CNP is disposed between the drive terminal portion 700 and the pad terminal 514.

[0116] The connection portion CNP can be a conductive film that allows current to flow in the thickness direction (e.g., the Z-axis direction) and is insulating in the width direction (e.g., the Y-axis direction) or length direction (e.g., the X-axis direction). In an embodiment, the connection portion CNP can be an anisotropic conductive film (ACF). The connection portion CNP may include conductive particles 791 (such as conductive balls) and insulating resin 792, the conductive particles 791 forming an electrical path between the pad portion PD and the drive terminal portion 700, and the insulating resin 792 fixing the conductive particles 791 in place to improve connection reliability.

[0117] When the pad portion PD and the drive terminal portion 700 are pressed by a pressure device such as a hot rod utilizing heat and pressure, the pad portion PD can be electrically connected to the drive terminal portion 700 via conductive particles 791. Insulating resin 792 is distributed outside the area where the pad terminals 514 and the drive terminal portion 700 are connected, such that a pair of pad terminals 514 and drive terminals 710 corresponding to each other along a third direction (e.g., the Z-axis direction) and another pair of pad terminals 514 and drive terminals 710 immediately adjacent to each other can insulate each other.

[0118] The display panel DP may include a first alignment mark MK1. The first alignment mark MK1 may be located in a first non-display area NDA1 (specifically, a first-2 non-display area NDA1-2). The first alignment mark MK1 may be configured not to overlap with the pad portion PD. The connection circuit portion CP may include a second alignment mark MK2. The second alignment mark MK2 may be located at a position corresponding to the first alignment mark MK1. For example... Figure 13 As shown, when the display panel DP and the connection circuit portion CP are connected, the first alignment mark MK1 and the second alignment mark MK2 can be superimposed on each other. In the alignment process, the display panel DP and the connection circuit portion CP are configured such that the first alignment mark MK1 and the second alignment mark MK2 are superimposed on each other in a plan view, and then the display panel DP and the connection circuit portion CP can be connected.

[0119] like Figure 10 and Figure 11As shown, the first groove region GR1 can be defined within the first inorganic layer IL1. At least a portion of the first organic layer OL1 can be accommodated within the first groove region GR1. The first groove region GR1 can have a rough structure with a predetermined pattern. The first groove region GR1 can be used to improve interfacial adhesion by increasing the contact area with the first organic layer OL1. In addition, the first groove region GR1 provides a mechanical interlocking effect that can reduce delamination caused by external stress or temperature changes. Therefore, the adhesion between the first inorganic layer IL1 and the first organic layer OL1 can be improved, and the overall structural stability can be enhanced.

[0120] like Figure 12 and Figure 13 As shown, multiple first recessed regions GR1 can be configured and superimposed on a first line LN1. At least one of the first recessed regions GR1 can be superimposed on a first-1 line LN1-1. The first recessed region GR1 can be superimposed on each of a first non-display region NDA1 and a second non-display region NDA2. The first recessed region GR1 can be spaced apart from the pad portion PD. In an embodiment, in a plan view, for example, the first recessed region GR1 can be configured as a straight line extending in a direction from the first non-display region NDA1 toward the second non-display region NDA2.

[0121] However, this is an illustrative embodiment, and the structure of the first groove region GR1 can be designed in various ways according to the desired purpose. The shape, depth, and pattern of the first groove region GR1 can be optimized, and can be formed, for example, as fine grooves or protrusions. In embodiments, such as Figure 12 As shown, for example, at least two of the plurality of first groove regions GR1 may be different in size from each other. Figure 10 and Figure 11 In the process, the upper surface of the first organic layer OL1, which overlaps with the first groove region GR1, is depicted as flat, but the upper surface of the first organic layer OL1 can be curved depending on the degree of exposure of the first organic layer OL1 during the process of patterning the first organic layer OL1.

[0122] The first recessed regions GR1, superimposed on the first-1 line LN1-1, can be spaced apart from each other along a first direction (e.g., the X-axis direction). At least one of the first recessed regions GR1 can be superimposed on the first-2 line LN1-2. The first recessed regions GR1 superimposed on the first-2 line LN1-2 can be spaced apart from each other along a second direction (e.g., the Y-axis direction). In this structure, the first recessed regions GR1 can be disposed in the first-1 non-display area NDA1-1, where the stress applied to the display panel DP is the highest. Therefore, the phenomenon of damage to the display panel DP caused by stress applied to the display panel DP due to the elasticity of the connecting circuit portion CP can be reduced.

[0123] like Figure 10 and Figure 11 As shown, the second groove region GR2 can be defined within the first inorganic layer IL1. The second groove region GR2 can have a rough structure with a predetermined pattern. At least a portion of the first organic layer OL1 can be accommodated within the second groove region GR2. The second groove region GR2 can be used to improve interfacial adhesion by increasing the contact area with the first organic layer OL1. In addition, the second groove region GR2 provides a mechanical bonding effect that can reduce delamination between layers caused by external stress or temperature changes. Therefore, the adhesion between the first inorganic layer IL1 and the first organic layer OL1 can be improved, and the overall structural stability can be enhanced.

[0124] like Figure 12 and Figure 13 As shown, the second recessed region GR2 may be defined within the first non-display region NDA1. In an embodiment, for example, the second recessed region GR2 may be disposed within the first-1 non-display region NDA1-1. The second recessed region GR2 may be spaced apart from the pad portion PD. In an embodiment, in a plan view, for example, the second recessed region GR2 may be disposed in the shape of a square dot.

[0125] However, this is an illustrative embodiment, and the structure of the second groove region GR2 can be designed in various ways according to the desired purpose. The shape, depth, and pattern of the second groove region GR2 can be optimized, and can be formed, for example, as fine grooves or protrusions.

[0126] In this structure, the second recessed region GR2 can be located in the first non-display region NDA1-1, where the stress applied to the display panel DP is the highest. Therefore, the phenomenon of damage to the display panel DP caused by stress applied to it due to the elasticity of the connecting circuit portion CP can be reduced.

[0127] Figure 14 This is a cross-sectional view schematically showing a portion of an embodiment of the display device 1.

[0128] In detail, Figure 14 It is along Figure 1 A cross-sectional view of display device 1 taken by line IV-IV'. Figure 14 This diagram shows the state in which the connection circuit section CP is connected to the display panel DP.

[0129] exist Figure 14 In, with Figures 10 to 13 The same reference numerals in the figures denote the same elements, and redundant descriptions are omitted.

[0130] Reference Figure 14The display device 1 may include a display panel DP, a connection circuit portion CP, and a connection portion CNP.

[0131] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. In a plan view, the boundary between the first non-display area NDA1 and the second non-display area NDA2 can be defined as a first line LN1. The first non-display area NDA1 may include a first-1 non-display area NDA1-1 and a first-2 non-display area NDA1-2.

[0132] The first inorganic layer IL1 can be disposed on the substrate 100. Specifically, the first-2 inorganic layer IL1-2 can be disposed on the first-1 inorganic layer IL1-1, and the first-3 inorganic layer IL1-3 can be disposed on the first-2 inorganic layer IL1-2. The first organic layer OL1 can be disposed on the first inorganic layer IL1.

[0133] The pad portion PD can be disposed in the first non-display area NDA1 (specifically, the first-2 non-display areas NDA1-2). The pad portion PD may include a plurality of pad terminals 514 and a plurality of conductive protective layers 515. The pad terminals 514 are disposed on the first organic layer OL1 and can be connected to the corresponding connection wiring CW through contact holes penetrating the first organic layer OL1. The edge of each pad terminal 514 may be covered by the protective layer 400. A portion of the upper surface of each of the pad terminals 514 may be exposed from the protective layer 400. The conductive protective layer 515 may be disposed on the upper surface of the exposed pad terminal 514.

[0134] The connection circuit portion CP can be disposed on the substrate 100. The connection circuit portion CP may include a connection circuit board 600 and a drive terminal portion 700 disposed on the connection circuit board 600. The drive terminal portion 700 may be configured to face the pad portion PD and may include a plurality of drive terminals 710.

[0135] Between the drive terminal portion 700 and the pad terminal 514, a connection portion CNP may be provided to electrically connect the drive terminal portion 700 and the pad terminal 514 to each other. The connection portion CNP may include conductive particles 791 (such as conductive balls) and insulating resin 792. The conductive particles 791 form an electrical path between the pad portion PD and the drive terminal portion 700, and the insulating resin 792 fixes the conductive particles 791 in place to improve connection reliability.

[0136] like Figure 10 and Figure 11As shown, a first groove region GR1, superimposed on the first line LN1, can be defined within a first inorganic layer IL1. At least a portion of the first organic layer OL1 can be accommodated within the first groove region GR1. The first groove region GR1 can have a rough structure with a predetermined pattern. The first groove region GR1 can be used to improve interfacial adhesion by increasing the contact area with the first organic layer OL1.

[0137] The first recessed region GR1 may include a first-1 recessed region GR1-1 and a first-2 recessed region GR1-2 connected to the first-1 recessed region GR1-1. The first-1 recessed region GR1-1 may be disposed in a first non-display region NDA1, and the first-2 recessed region GR1-2 may be disposed in a second non-display region NDA2. The first-1 recessed region GR1-1 and the first-2 recessed region GR1-2, which are connected to each other, may be configured as a straight line extending in a direction from the first non-display region NDA1 toward the second non-display region NDA2. However, this is an illustrative embodiment, and the structure of the first-1 recessed region GR1-1 and the first-2 recessed region GR1-2 may be designed in various ways according to the desired purpose.

[0138] Figure 15 This is a block diagram of an embodiment of electronic device 10.

[0139] Reference Figure 15 The electronic device 10 in the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0140] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0141] The data required for the operation of the processor 12 or the display module 11 can be stored in the memory 13. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0142] The power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0143] At least one of the components of the electronic device 10 described above may be included in the display device according to the above embodiments. Additionally, some of the modules functionally included within the electronic device 10 may be included within the display device, while other modules may be disposed separately from the display device. In embodiments, for example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed as other devices within the electronic device 10 besides the display device.

[0144] Figure 16 This is a perspective view schematically illustrating an embodiment of an electronic device.

[0145] Reference Figure 16 The various electronic devices of the display device in the application embodiments may include not only image display electronic devices (such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c) that include display modules, as well as vehicle electronic devices 10_3 that include display modules (such as car dashboards, central instrument panels, or central information displays (CIDs) and interior mirror displays mounted on the dashboard).

[0146] Through these examples, the durability of the display device can be improved.

[0147] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, the display device comprising: A display panel includes a display area and a non-display area including a first non-display area and a second non-display area, and further includes: a substrate; a first inorganic layer disposed on the substrate and including a first recessed area; and a first organic layer disposed on the first inorganic layer and in contact with the first inorganic layer; and The connection circuit is electrically connected to the display panel and is superimposed on the first non-display area. The first groove area overlaps with the first line, which is the boundary line between the first non-display area and the second non-display area.

2. The display device according to claim 1, wherein, The first line includes: a first-1 line extending in a first direction parallel to the bending axis along which the connecting circuit portion bends; and a first-2 line extending from the first-1 line in a second direction intersecting the first direction. The first groove area overlaps with the first -2 line.

3. The display device according to claim 2, wherein, The first groove region is configured as multiple, and Multiple first groove regions are spaced apart from each other along the second direction at positions where they overlap with the first-2 lines.

4. The display device according to claim 3, wherein, At least two of the plurality of first groove regions are different in size from each other.

5. The display device according to claim 1, wherein, The first groove region includes a first-1 groove region and a first-2 groove region connected to the first-1 groove region.

6. The display device according to claim 5, wherein, The first -1 groove area is disposed in the first non-display area, and the first -2 groove area is disposed in the second non-display area.

7. The display device according to claim 1, wherein, The first inorganic layer further includes a second recessed region defined within the first non-display area.

8. The display device according to claim 1, wherein, The display panel also includes: Driving transistors, disposed on the substrate and superimposed on the display area; and A light-emitting element is disposed on the first organic layer, stacked with the display area, and electrically connected to the driving transistor.

9. The display device according to claim 8, wherein, The driving transistor includes: A semiconductor layer is disposed within the first inorganic layer; and The gate electrode is disposed between the first inorganic layer and the first organic layer.

10. The display device according to claim 1, wherein, The display panel also includes a pad portion disposed in the first non-display area, spaced apart from the first recessed area and electrically connected to the connection circuit portion.

11. An electronic device, the electronic device comprising: The display panel includes a display area and a non-display area including a first non-display area and a second non-display area, and includes a substrate; a first inorganic layer is disposed on the substrate, and a first recessed area is defined in the first inorganic layer; And a first organic layer, disposed on the first inorganic layer and in contact with the first inorganic layer; as well as The connection circuit is electrically connected to the display panel and is superimposed on the first non-display area. The first recessed area overlaps with each of the first non-display area and the second non-display area.

12. The electronic device according to claim 11, wherein, The first groove region includes a first-1 groove region and a first-2 groove region connected to the first-1 groove region.

13. The electronic device according to claim 12, wherein, The first -1 groove area is disposed in the first non-display area, and the first -2 groove area is disposed in the second non-display area.

14. The electronic device according to claim 11, wherein, A second recessed region is defined in the first inorganic layer, which overlaps with the first non-display area but does not overlap with the second non-display area.

15. The electronic device according to claim 11, wherein, The display panel also includes: Driving transistors, disposed on the substrate and superimposed on the display area; and A light-emitting element is disposed on the first organic layer, stacked with the display area, and electrically connected to the driving transistor.

16. The electronic device according to claim 15, wherein, The driving transistor includes: A semiconductor layer is disposed within the first inorganic layer; and The gate electrode is disposed between the first inorganic layer and the first organic layer.

17. The electronic device according to claim 11, wherein, The first groove area overlaps with the first line, which is the boundary line between the first non-display area and the second non-display area.

18. The electronic device according to claim 17, wherein, The first line includes: The first-1 line extends in a first direction parallel to the bending axis along which the connecting circuit portion bends; and Line 1-2 extends from line 1-1 in a second direction that intersects with the first direction, and The first groove area overlaps with the first -2 line.

19. The electronic device according to claim 18, wherein, The first groove region is configured as multiple, and Multiple first groove regions are spaced apart from each other along the second direction at positions where they overlap with the first-2 lines.

20. The electronic device according to claim 11, wherein, The display panel also includes a pad portion disposed in the first non-display area, spaced apart from the first recessed area and electrically connected to the connection circuit portion.

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