Silicon-based micro-OLED anode structure and preparation method thereof, and silicon-based organic light emitting diode

Abstract

The application provides a silicon-based Micro-OLED anode structure and a preparation method thereof, and a silicon-based organic light-emitting diode, and belongs to the field of semiconductors. The preparation method of the silicon-based Micro-OLED anode structure comprises the following steps: providing a silicon-based CMOS back plate; depositing a buffer layer on the surface of the silicon-based CMOS back plate, wherein the buffer layer comprises a texture composite structure of a tantalum layer and a ruthenium layer, the tantalum layer is in an amorphous structure, the ruthenium layer is in a hexagonal closest packing structure, the tantalum layer covers the surface of the silicon-based CMOS back plate, and the ruthenium layer covers the surface of the tantalum layer. In the scheme, the tantalum layer adopts an amorphous structure, the amorphous tantalum layer can obtain extremely low surface roughness, the ruthenium layer is in a hexagonal closest packing crystalline structure, the crystal grains are regularly oriented and form a texture, the ruthenium layer is used for inducing the orientation of the upper layer of crystal lattices, blocking the transmission of roughness, reducing the roughness of a metal reflection layer, and further reducing diffuse reflection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon-based Micro-OLED anode structure and its fabrication method, and a silicon-based organic light-emitting diode. Background Technology

[0002] Micro-OLEDs, equipped with CMOS silicon driving backplanes, not only achieve ultra-high resolution displays but also boast advantages such as low power consumption and miniaturization, making them a mainstream core device for future AR, VR, and near-eye displays. The anode structure of a micro-OLED, as the core functional layer for hole injection, conductivity, and light reflection, directly determines the device's luminous efficiency, dark spot defect rate, lifespan, and reliability due to the adhesion between its film layers, interface stability, elemental diffusion resistance, and surface roughness.

[0003] However, the existing anode structures of micro organic light-emitting diodes suffer from the problem of roughness between film layers propagating upwards, which can easily lead to defects such as diffuse reflection and poor ohmic contact. In addition, when the roughness between film layers propagates upwards, the average surface roughness of the entire anode structure cannot meet the requirements, further resulting in low hole injection efficiency and increased device turn-on voltage, which fails to meet the requirements of microcavity displays.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a silicon-based Micro-OLED anode structure and its fabrication method, as well as a silicon-based organic light-emitting diode, to solve the problem that the average surface roughness of the entire anode structure cannot meet the requirements, resulting in low hole injection efficiency, increased device turn-on voltage, and failure to meet the requirements of microcavity displays.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a silicon-based Micro-OLED anode structure, comprising:

[0007] S10, Provides a silicon-based CMOS backplane;

[0008] S20. A buffer layer is deposited on the surface of the silicon-based CMOS backplane; wherein the buffer layer comprises a textured composite structure of a tantalum layer and a ruthenium layer, the tantalum layer is an amorphous structure, the ruthenium layer is a hexagonal close-packed structure, the tantalum layer covers the surface of the silicon-based CMOS backplane, and the ruthenium layer covers the surface of the tantalum layer;

[0009] S30. A metal reflective layer, a diffusion barrier layer, and a hole injection layer are sequentially deposited on the surface of the ruthenium layer to form an anode structure.

[0010] Preferably, step S10 further includes:

[0011] The surface of the silicon-based CMOS backplane is pre-treated by CMP planarization to make the surface roughness of the silicon-based CMOS backplane less than or equal to 0.5 nm.

[0012] Preferably, between steps S10 and S20, the following step is further included:

[0013] S11. The surface of the silicon-based CMOS backplane is cleaned using at least one of the following: plasma formed by argon ionization, plasma formed by hydrogen discharge, and plasma formed by discharge of a mixed gas of helium and hydrogen.

[0014] Preferably, in step S20, the tantalum layer and the ruthenium layer are deposited using a DC magnetron sputtering process.

[0015] Preferably, when depositing the tantalum layer, the sputtering power of the reaction chamber is in the range of 3800 to 5000 W, the gas pressure is in the range of 3.5 to 5 mTorr, the deposition temperature is in the range of 25 to 100 °C, and the deposition thickness is in the range of 3 to 5 nm.

[0016] Preferably, when depositing the ruthenium layer, the sputtering power of the reaction chamber is in the range of 2000-4000W, the gas pressure is in the range of 2-5mTorr, the deposition temperature is in the range of 150-250℃, and the deposition thickness is in the range of 5-7nm.

[0017] Preferably, the method further includes:

[0018] S40. Under an inert gas environment, perform an annealing process on the formed anode structure.

[0019] Preferably, the annealing process is performed in a nitrogen or argon atmosphere at a temperature of 200–400°C and held at the annealing temperature for 20–60 minutes.

[0020] Preferably, the buffer layer, the metal reflective layer, the diffusion barrier layer, and the hole injection layer are all deposited in different vacuum reaction chambers of the same device.

[0021] Based on the same inventive concept, the present invention also provides a silicon-based Micro-OLED anode structure, comprising:

[0022] Silicon-based CMOS backplane;

[0023] A buffer layer comprising a textured composite structure of a tantalum layer and a ruthenium layer, wherein the tantalum layer is amorphous and the ruthenium layer is hexagonal close-packed; the tantalum layer covers the surface of the silicon-based CMOS backplane and the ruthenium layer covers the surface of the tantalum layer.

[0024] A metallic reflective layer covers the surface of the ruthenium layer;

[0025] A diffusion barrier layer covers the surface of the metal reflective layer;

[0026] A hole injection layer covers the surface of the diffusion barrier layer.

[0027] Preferably, the thickness of the buffer layer is in the range of 8–12 nm.

[0028] Preferably, the thickness of the tantalum layer is 3–5 nm and the roughness Ra is ≤0.3 nm, and the thickness of the ruthenium layer is 5–7 nm.

[0029] Preferably, the metal reflective layer comprises an aluminum layer, the thickness of which ranges from 80 to 150 nm;

[0030] And / or, the diffusion barrier layer includes a titanium nitride layer, the thickness of which ranges from 2 to 5 nm;

[0031] And / or, the hole injection layer includes an ITO layer, the thickness of which ranges from 10 to 20 nm.

[0032] Based on the same inventive concept, the present invention also provides a silicon-based organic light-emitting diode, including the anode structure as described above.

[0033] Compared with the prior art, the method for preparing the silicon-based Micro-OLED anode structure of the present invention has the following advantages:

[0034] The present invention deposits a buffer layer on the surface of a silicon-based CMOS backplane. The buffer layer comprises a textured composite structure of a tantalum layer and a ruthenium layer. The tantalum layer is an amorphous structure, and the ruthenium layer is a hexagonal close-packed structure.

[0035] The bottom tantalum layer adopts an amorphous structure with disordered atomic arrangement, which can achieve extremely low surface roughness and provide a flat growth substrate for the upper ruthenium layer. The amorphous tantalum layer has no through grains or grain boundaries, and there are no through-type fast diffusion channels extending along the grain boundaries, thus forming a primary diffusion barrier layer to inhibit the upward diffusion of ions. The tantalum layer is directly deposited on the surface of the silicon-based CMOS backplane, with strong interfacial chemical bonding, avoiding peeling and detachment of the film layer of the anode structure.

[0036] The upper ruthenium layer has a hexagonal close-packed (hcp) crystalline structure with regular grain orientation and texture. Through epitaxial induction, the ruthenium layer induces a highly preferred orientation crystalline structure in the metal reflective layer, inhibiting the growth of coarse columnar grains and reducing the surface roughness of the metal reflective layer itself from the source. The lattice mismatch between the ruthenium layer and the metal reflective layer is low, enabling atomic-level bonding at the interface. The ruthenium layer is used to induce the upper lattice orientation, block roughness transmission, reduce the roughness of the metal reflective layer, reduce diffuse reflection, and prevent device failure due to poor ohmic contact. The ruthenium layer has excellent conductivity, reducing the overall contact resistance of the anode structure. The ruthenium layer can also act as a barrier layer, effectively blocking metal diffusion, optimizing interface flatness, further reducing the average surface roughness of the entire anode structure, improving hole injection efficiency, reducing device turn-on voltage, and meeting the requirements of microcavity displays. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the anode structure in one embodiment of the present invention.

[0038] Figure 2 This is a flowchart of a method for preparing a silicon-based Micro-OLED anode structure according to an embodiment of the present invention.

[0039] Figure 3 An AFM test morphology image of an amorphous tantalum layer in one embodiment of the present invention.

[0040] Figure 4 An AFM test morphology image of the ruthenium layer in one embodiment of the present invention.

[0041] Figure 5 An AFM test morphology diagram of the anode structure in one embodiment of the present invention.

[0042] Figure 6 AFM test morphology image of the amorphous tantalum layer in another embodiment of the present invention.

[0043] Figure 7 AFM test morphology diagram of the ruthenium layer in another embodiment of the present invention.

[0044] Figure 8 AFM test morphology diagram of the anode structure in another embodiment of the present invention.

[0045] In the figure, 100-silicon-based CMOS backplane; 200-buffer layer; 210-tantalum layer; 220-ruthenium layer; 300-metal reflective layer; 400-diffusion barrier layer; 500-hole injection layer. Detailed Implementation

[0046] To make the objectives, advantages, and features of the present invention clearer, the silicon-based Micro-OLED anode structure and its fabrication method, as well as the silicon-based organic light-emitting diode, proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that the accompanying drawings do not necessarily show the specific structure of the present invention to scale, and the illustrative features used to illustrate certain principles of the present invention in the accompanying drawings are also drawn in a slightly simplified manner. Specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are used. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0049] Silicon-based Micro-OLEDs use a CMOS silicon substrate as the driving backplane and are the core device for next-generation near-eye displays. The anode structure of a silicon-based Micro-OLED typically includes a titanium (Ti) layer, an aluminum (Al) layer, a titanium nitride (TiN) layer, and an ITO thin film. The titanium layer is used to buffer the interface mismatch between the dielectric layer and metal holes of the silicon-based CMOS backplane and the aluminum layer. However, due to the lattice constant difference of ≥37% between Ti and Al, an "orange peel" texture is formed at the interface, causing roughness to be transferred to the upper layers, which easily leads to problems such as diffuse reflection and poor ohmic contact. Secondly, the Al layer is prone to forming coarse columnar crystals (particle size ≥50nm), and the TiN layer exhibits random crystal orientation, further aggravating the surface undulation of the anode structure. Ultimately, the average surface roughness of the entire anode structure is ≥1.8nm, resulting in low hole injection efficiency and increased device turn-on voltage, which cannot meet the requirements of microcavity displays.

[0050] The core idea of ​​this invention is to provide a method for fabricating a silicon-based Micro-OLED anode structure. The anode structure obtained by this method can reduce the roughness between film layers, avoid the transmission of roughness between different film layers, avoid defects such as diffuse reflection and poor ohmic contact in the anode structure, improve the hole injection efficiency of the anode structure, reduce the device turn-on voltage, and meet the requirements of microcavity display.

[0051] To achieve the above-mentioned ideas, this embodiment discloses a method for fabricating a silicon-based Micro-OLED anode structure. Figures 1 to 8 A specific embodiment of the method for fabricating a silicon-based Micro-OLED anode structure is disclosed. The method for fabricating the silicon-based Micro-OLED anode structure includes the following steps.

[0052] Step S10: Provide a silicon-based CMOS backplane;

[0053] Step S20: Deposit a buffer layer on the surface of the silicon-based CMOS backplane; wherein the buffer layer comprises a textured composite structure of a tantalum layer and a ruthenium layer, the tantalum layer is an amorphous structure, the ruthenium layer is a hexagonal close-packed structure, the tantalum layer covers the surface of the silicon-based CMOS backplane, and the ruthenium layer covers the surface of the tantalum layer;

[0054] Step S30: Sequentially deposit a metal reflective layer, a diffusion barrier layer, and a hole injection layer on the surface of the ruthenium layer to form an anode structure.

[0055] refer to Figure 1As shown, in this embodiment, a buffer layer 200 with a textured composite structure consisting of a tantalum (Ta) layer 210 and a ruthenium (Ru) layer 220 is deposited on the surface of a silicon-based CMOS backplane. The tantalum layer 210 is amorphous and is directly deposited on the surface of the silicon-based CMOS backplane 100. The interfacial chemical bonding is strong, which avoids peeling and detachment of the film layer of the anode structure. The amorphous tantalum layer 210 has no through grains or grain boundaries inside, and there are no through-type fast diffusion channels extending along the grain boundaries. This forms a primary diffusion barrier layer to inhibit the upward diffusion of silicon atoms and impurity metal ions. The amorphous tantalum layer 210 can obtain extremely low surface roughness. Typically, the roughness Ra of the amorphous tantalum layer 210 is ≤0.3nm, forming an atomically flat substrate. It also has high chemical stability, which can avoid interfacial oxidation.

[0056] The upper ruthenium layer 220 has a hexagonal close-packed (also known as hexagonal densest packing) crystalline structure with regular grain orientation and texture. The grain morphology of the upper metal reflective layer 300 can be controlled by epitaxial growth to suppress coarse columnar crystals, reduce roughness, reduce film roughness and diffuse reflection, and avoid poor ohmic contact of the metal reflective layer 300. Ruthenium metal has stable chemical properties and extremely strong high-temperature oxidation resistance, which can isolate the tantalum layer 210 from direct contact with the upper metal reflective layer 300 and suppress atomic interdiffusion and interface alloying. At the same time, the ruthenium layer acts as a second barrier layer to prevent the metal in the through hole from moving upward. The ruthenium layer 220 has excellent conductivity and can form a continuous conductive path in an ultra-thin state, reducing the overall contact resistance of the anode structure.

[0057] The composite buffer layer 200 effectively reduces the surface roughness of the entire anode structure, improves the film quality and light reflectivity of the metal reflective layer 300, increases hole injection efficiency, and reduces the device turn-on voltage, thus meeting the requirements of microcavity displays. Therefore, the anode structure prepared using this method can reduce the average surface roughness of the entire anode structure to less than 1.8 nm, while simultaneously improving the hole injection efficiency in the anode structure and reducing the device turn-on voltage, thus meeting the requirements of microcavity displays.

[0058] In some embodiments, step S10 further includes: performing CMP planarization pretreatment on the surface of the silicon-based CMOS backplane 100 to make the surface roughness of the silicon-based CMOS backplane less than or equal to 0.5 nm.

[0059] For example, a silicon-based CMOS backplane 100 includes a substrate, CMOS transistors formed on the substrate, and an insulating dielectric layer formed on the CMOS transistors. In this embodiment, the insulating dielectric layer and the vias formed on the insulating dielectric layer are subjected to chemical mechanical polishing (CMP) to reduce the surface roughness of the insulating dielectric layer. This can reduce the surface roughness of the insulating dielectric layer to less than or equal to 0.5 nm, thereby reducing interface defects in subsequently formed films (e.g., buffer layer 200) and improving the quality of the films.

[0060] In some embodiments, before performing step S20, that is, between step S10 and step S20, the method further includes: S11, cleaning the surface of the silicon-based CMOS backplane using at least one of plasma formed by argon ionization, plasma formed by hydrogen discharge, and plasma formed by discharge of a mixed gas of helium and hydrogen.

[0061] After vias are formed, the metal filling them is exposed to air and oxidizes. For example, in vias formed with tungsten, the tungsten oxidizes to form tungsten oxide, affecting the electrical properties and power consumption of subsequently formed devices, and increasing the device's turn-on voltage. In some embodiments, plasma generated by Ar ionization can be used to bombard the surface of tungsten oxide to remove it and expose the tungsten metal. Alternatively, plasma generated by H2 discharge can be used to react with tungsten oxide in a redox reaction, reducing the tungsten oxide to tungsten metal. Preferably, plasma generated by a mixture of helium (He) and hydrogen (H2) can be used to clean the surface of the silicon-based CMOS backplane, where He acts as a buffer carrier gas. The light ions generated by helium ionization reduce the overall ion bombardment energy, and hydrogen active species are used to reduce and remove the tungsten oxide layer (WO). x At the same time, it reduces the damage caused by plasma bombardment to the silicon-based CMOS backplane. By cleaning the surface of the silicon-based CMOS backplane, secondary oxidation of the exposed tungsten metal is avoided during the cleaning process, ultimately obtaining a clean tungsten metal interface with no oxidation and low contact resistance.

[0062] In some embodiments, in step S20, the tantalum layer 210 and the ruthenium layer 220 are deposited using a DC magnetron sputtering process. Depositing the tantalum layer 210 and the ruthenium layer 220 using a DC magnetron sputtering process allows for precise control of the thicknesses of both the tantalum layer 210 and the ruthenium layer 220, thereby enabling precise control of the total thickness of the buffer layer 200. This results in controllable stress in the buffer layer 200, a moderate overall film thickness, and low interlayer stress.

[0063] In some embodiments, when the tantalum layer 210 is deposited using a DC magnetron sputtering process in step S20, the sputtering power of the reaction chamber is in the range of 3800 to 5000 W, the gas pressure is in the range of 3.5 to 5 mTorr, the deposition temperature is in the range of 25 to 100 °C, and the deposition thickness is in the range of 3 to 5 nm.

[0064] When depositing the tantalum layer 210 on the surface of the insulating dielectric layer and the via, i.e., on the surface of the silicon-based CMOS backplane 100, the sputtering power of the reaction chamber is in the range of 3000–5000 W. For example, the sputtering power can be 3000 W, 4000 W, 5000 W, or any value within the range of 3000–5000 W. The gas pressure range is 3.5–5 mTorr. For example, the gas pressure of the reaction chamber can be 3.5 mTorr, 4 mTorr, 5 mTorr, or any value within the range of 3.5–5 mTorr. The deposition temperature is 25–100 °C. For example, the temperature of the reaction chamber can be 25 °C, 50 °C, 100 °C, or any value within the range of 25–100 °C, and the deposition temperature is maintained constant during deposition to avoid temperature rise during the deposition process. The deposition thickness is 3–5 nm. The tantalum layer 210 formed using this process condition has an amorphous structure. By selecting higher sputtering pressure and sputtering power, the bombardment effect of Ar ions on the grown film is enhanced. Simultaneously, at lower temperatures, the long-range diffusion migration of deposited atoms is significantly suppressed, inhibiting nucleation and grain growth, resulting in a long-range disordered amorphous tantalum layer. The amorphous tantalum layer 210 is directly deposited on the surface of the silicon-based CMOS backplane 100, exhibiting strong interfacial chemical bonding with the insulating dielectric layer on top of the silicon-based CMOS backplane 100. This significantly improves the adhesion between the entire anode structure and the silicon-based CMOS backplane 100, preventing film peeling and flaking of the anode structure. The amorphous tantalum layer 210 lacks grain boundaries and fast diffusion channels, thus forming a primary diffusion barrier layer that effectively blocks the upward diffusion of silicon atoms and impurity metal ions within the substrate. The roughness Ra of the tantalum layer 210 is ≤0.3 nm, forming an atomically flat substrate, providing a smooth growth substrate for the upper ruthenium layer 220. Furthermore, the high chemical stability of tantalum prevents interfacial oxidation.

[0065] In some embodiments, when the ruthenium layer 220 is deposited using a DC magnetron sputtering process in step S20, the sputtering power of the reaction chamber is in the range of 2000 to 4000 W, the gas pressure is in the range of 2 to 5 mTorr, the deposition temperature is in the range of 150 to 250 °C, and the deposition thickness is in the range of 5 to 7 nm.

[0066] When depositing the ruthenium layer 220 on the surface of the tantalum layer 210, the sputtering power of the reaction chamber is in the range of 2000–4000 W, and the sputtering power can be any value within the range of 2000 W, 3000 W, 4000 W, or 2000–4000 W. The gas pressure is in the range of 2–5 mTorr, for example, the gas pressure of the reaction chamber can be any value within the range of 2–5 mTorr. For example, the gas pressure is in the range of 2–5 mTorr, and the deposition temperature is in the range of 150–250 °C, for example, the temperature of the reaction chamber can be any value within the range of 150 °C, 200 °C, 250 °C, or 150–250 °C. The deposition thickness is 5–7 nm. The ruthenium layer 220 formed using this process condition has a hexagonal close-packed structure. The upper ruthenium layer 220 has a hexagonal close-packed (hcp) crystalline structure with regular grain orientation and texture. The lattice mismatch between the ruthenium layer 220 and the subsequently formed metal reflective layer 300 is low (less than 6%), enabling atomic-level bonding at the interface. Through epitaxial induction, the ruthenium layer 220 induces a highly preferred orientation crystalline structure in the metal reflective layer 300, suppressing the growth of coarse columnar grains and reducing the surface roughness of the metal reflective layer 300 from the source. Furthermore, the ruthenium layer 220 can regulate the lattice orientation of the upper thin film and prevent the upward transmission of morphological undulations from the lower substrate, further optimizing the surface smoothness of the metal reflective layer 300. The low-roughness metal reflective layer 300 effectively reduces diffuse reflection and prevents device failure due to poor ohmic contact. Ruthenium metal is chemically stable and has extremely strong high-temperature oxidation resistance. It can isolate the tantalum layer 210 from direct contact with the upper metal reflective layer 300, prevent atoms in the metal reflective layer 300 from diffusing downwards, and avoid interface alloying. The ruthenium layer 220 has excellent conductivity and can form a continuous conductive path even in an ultra-thin state, reducing the overall contact resistance of the anode structure. The ruthenium layer 220 can also act as a second barrier layer, effectively blocking the upward diffusion of metal in the via, while optimizing the interface flatness, further reducing the average surface roughness of the entire anode structure, improving the film quality and light reflectivity of the metal reflective layer 300, increasing hole injection efficiency, reducing device turn-on voltage, and meeting the requirements of microcavity displays.

[0067] refer to Figure 1 As shown, in some embodiments, in step S30, a metal reflective layer 300, a diffusion barrier layer 400, and a hole injection layer 500 are sequentially deposited on the surface of the ruthenium layer 220 by a DC magnetron sputtering process to form an anode structure.

[0068] A metal reflective layer 300 is disposed on the surface of the ruthenium layer 220. The material of the metal reflective layer 300 may include an aluminum (Al) layer with a thickness ranging from 80 to 150 nm. During the deposition of the aluminum layer, the sputtering power of the reaction chamber ranges from 3000 to 12000 W, the gas pressure is 2 to 3 mTorr, and the deposition temperature ranges from 0 to 100 °C, preferably 25 °C. A diffusion barrier layer 400 is disposed on the surface of the metal reflective layer 300. The diffusion barrier layer 400 may include a titanium nitride (TiN) layer with a thickness ranging from 2 to 5 nm. During the deposition of the titanium nitride layer, the sputtering power of the reaction chamber ranges from 2000 to 5000 W, the gas pressure is 4 to 8 mTorr, and the deposition temperature ranges from 0 to 100 °C, preferably 25 °C. During the deposition of the titanium nitride layer, nitrogen and argon are used as auxiliary gases, with nitrogen flow rates ranging from 30 to 100 sccm and argon flow rates ranging from 50 to 100 sccm. A hole injection layer 500 is disposed on the surface of the diffusion barrier layer 400. The hole injection layer 500 may include an ITO layer with a thickness ranging from 10 to 20 nm. During the deposition of the ITO layer, the sputtering power of the reaction chamber ranges from 2000 to 5000 W, the gas pressure is 4 to 8 mTorr, and the deposition temperature ranges from 150 to 400 °C. During the deposition of the titanium nitride layer, oxygen is also used as a reactive gas, with an oxygen flow rate ranging from 1 to 5 sccm.

[0069] In this embodiment, the lattice mismatch between Ru (2.70 Å) and Al(111) (2.86 Å) is less than 6%, enabling atomic-level bonding between the Ru and Al layers. The Ru layer induces a highly oriented structure in the Al layer through epitaxial growth, suppressing the coarse columnar crystals of traditional Al layers and reducing roughness. Furthermore, the Ru layer induces the upper lattice orientation, blocking roughness transmission, thereby reducing the roughness of the Al layer, decreasing diffuse reflection, and preventing poor ohmic contact. Ru exhibits strong chemical stability and high-temperature oxidation resistance, isolating the Ta layer from direct contact with the upper Al layer, preventing Al atoms from diffusing downwards, and avoiding interfacial alloying. The Ru layer can improve the overall anode structure's film density, forming a secondary diffusion barrier layer, while simultaneously optimizing interface smoothness, improving the film quality and light reflectivity of the Al layer. Additionally, Ta has a thermal expansion coefficient of 6.5 × 10⁻⁶. -6 The coefficient of thermal expansion of Ru is 8.3 × 10⁻⁶ K. -6 The coefficient of thermal expansion of Al is 23.1 × 10⁻⁶ K. -6 / K means that along the direction perpendicular to the silicon-based CMOS backplane 100, the thermal expansion coefficients of the Ta, Ru, and Al layers transition in a gradient manner, and the stress is gradually released during the cooling process, thereby avoiding the problem of film peeling caused by excessive difference in thermal expansion coefficients.

[0070] Furthermore, in some embodiments, the buffer layer 200, the metal reflective layer 300, the diffusion barrier layer 400, and the hole injection layer 500 are formed in different vacuum reaction chambers of the same device. In this scheme, the substrate continuously completes multilayer thin film deposition in an ultra-high purity vacuum reaction chamber. During the formation of each film layer, exposure to air is avoided, thereby preventing the formation of insulating metal oxide interlayers and the adsorption of moisture and particulate impurities between the film layers. The fresh and clean metal interface enables the film layers to form a high-strength metallurgical bond, making the film layers less prone to thermal cracking and peeling. A single vacuum process completes the entire stack preparation in different vacuum reaction chambers of the same device, reducing particulate contamination defects and improving device yield.

[0071] In some embodiments, in order to improve the reliability of the device, the method for fabricating the silicon-based Micro-OLED anode structure further includes step S40: performing an annealing process on the formed anode structure in an inert gas environment.

[0072] In this scheme, the formed anode structure is annealed in an inert gas environment at a temperature of 200–400°C. The inert gas can include argon, nitrogen (N2), etc. The annealing temperature can be 200°C, 300°C, 400°C, or any value within the range of 200–400°C. By annealing the anode structure, residual stress within the multilayer sputtered film can be released, stress protrusions and interface cracks can be eliminated, and the overall surface roughness of the anode can be reduced. The inert atmosphere completely isolates oxygen and water vapor, preventing oxidation and degradation of aluminum, ruthenium, and titanium nitrides. Ultimately, a low-resistance, high-reflectance, interface-stable, and low-leakage-current anode structure is obtained, improving the device's luminous efficiency and reliability.

[0073] In some embodiments, after the annealing process, in-situ annealing is performed at 200–400°C in an inert atmosphere (e.g., nitrogen or argon) for 20–60 min. For example, the anode structure can be held at a set temperature (any value within the range of 200–400°C) for 20 min, 30 min, 60 min, or any value within the range of 20–60 min. By holding the temperature, the entire silicon-based CMOS backplane can be heated uniformly, continuously providing the heat energy required for atomic migration, fully releasing the residual stress inside the multiple sputtered film layers such as the tantalum layer 210, ruthenium layer 220, metal reflective layer 300, diffusion barrier layer 400, and hole injection layer 500, reducing the overall surface roughness of the anode structure, and further improving the luminous efficiency and reliability of the device.

[0074] Example 1

[0075] The substrate is placed into the DC magnetron sputtering cavity, which is then evacuated to a vacuum of 3 × 10⁻⁶. -7 Torr uses high-purity argon gas with a purity greater than 99.999% as the sputtering gas.

[0076] Step 1: Fabrication of a 4nm amorphous Ta layer: A circular tantalum target with a purity of 99.99% and a diameter of 440mm was used. The distance between the target and the substrate could be 60mm. The DC sputtering power was 5000W, the working pressure inside the chamber was 3.5mTorr, and the substrate was kept at a constant temperature of 25℃. By controlling the deposition time, a 4nm amorphous Ta layer was obtained. (Reference) Figure 3 As shown, in this embodiment, the AFM morphology image of the Ta layer was obtained by atomic force microscopy (AFM), and the average Ra of the Ta layer in this embodiment was obtained by AFM as 0.09 nm.

[0077] Step 2: Fabricate a 6nm textured Ru layer on the Ta layer surface: Transfer the substrate to another DC magnetron sputtering cavity, which is then evacuated to a vacuum of 3×10⁻⁶. -7 Torr was used as the sputtering gas, employing high-purity argon gas with a purity greater than 99.999%. The chamber contained a 99.99% high-purity Ru target of the same size and a 440mm diameter circular ruthenium target, with a target-substrate distance of 60mm. The sputtering power was adjusted to 4000W, the working pressure to 2mTorr, and the substrate temperature to 150℃. By controlling the deposition time, a hexagonal close-packed textured ruthenium layer with a thickness of 6nm was obtained. (Reference) Figure 4 The image shows the AFM morphology of the Ru layer in this embodiment, and the average Ra of the Ru layer in this embodiment is 0.25 nm, obtained through AFM. Subsequently, Al, TiN, and ITO layers are deposited sequentially to form the anode structure. (Reference) Figure 5 As shown, the AFM test morphology of the anode structure Ta (4nm) / Ru (6nm) / Al (100nm) / TiN (3nm) / ITO (15nm) in this embodiment is obtained. The average Ra of the anode structure in this embodiment is 0.59nm, which is obtained by AFM.

[0078] Example 2

[0079] The substrate is placed into the DC magnetron sputtering cavity, which is then evacuated to a vacuum of 3 × 10⁻⁶. -7 Torr uses high-purity argon gas with a purity greater than 99.999% as the sputtering gas.

[0080] Step 1: Fabrication of a 4nm amorphous Ta layer: A circular tantalum target with a purity of 99.99% and a diameter of 440mm was used. The distance between the target and the substrate could be 60mm. The DC sputtering power was adjusted to 3800W, the working pressure in the chamber was 5mTorr, and the substrate temperature was kept constant at 100℃. By controlling the deposition time, a 4nm amorphous Ta layer was obtained, and the furnace was cooled to room temperature. (Reference) Figure 6 As shown, the AFM topography of the Ta layer in this embodiment shows that the average Ra of the Ta layer in this embodiment is 0.095 nm, obtained by AFM.

[0081] Step 2: Fabricate a 6nm textured Ru layer on the Ta layer surface: Transfer the substrate to another DC magnetron sputtering cavity, which is then evacuated to a vacuum of 3×10⁻⁶. -7 Torr was used, introducing high-purity argon gas with a purity greater than 99.999% as the sputtering gas. The cavity contained a 99.99% high-purity ruthenium target, a 440mm diameter circular metallic ruthenium target, with the target and substrate maintained at a distance of 60mm. The sputtering power was adjusted to 2000W, the working pressure to 5mTorr, and the substrate temperature to be constant at 250℃. By controlling the deposition time, a hexagonal close-packed textured ruthenium layer with a thickness of 6nm was obtained. (Reference) Figure 7 As shown in the AFM topography image of the Ru layer in this embodiment, the average Ra of the Ru layer in this embodiment is 0.27 nm, obtained by AFM. Subsequently, Al, TiN, and ITO layers are deposited sequentially to form the anode structure. Figure 8 The image shows the AFM test morphology of the anode structure Ta(4nm) / Ru(6nm) / Al(100nm) / TiN(3nm) / ITO(15nm) in this embodiment. The average Ra of the anode structure in this embodiment is 0.68nm, obtained by AFM.

[0082] The anode structure fabricated using the method disclosed in this embodiment for preparing a silicon-based Micro-OLED anode structure achieves an amorphous structure for the tantalum layer 210 by modifying process parameters. This amorphous tantalum layer 210 has a roughness Ra ≤ 0.3 nm, forming an atomically flat substrate that provides a smooth growth substrate for the upper ruthenium layer 220. Furthermore, the amorphous tantalum layer 210 lacks interconnected grains and grain boundaries, eliminating the need for continuous rapid diffusion channels along grain boundaries. This forms a primary diffusion barrier layer, effectively blocking the upward diffusion of silicon atoms and impurity metal ions from the substrate.

[0083] The ruthenium layer 220 has a hexagonal close-packed (hcp) crystalline structure with regular grain orientation and texture. The lattice mismatch between Ru (2.70 Å) and Al(111) (2.86 Å) is less than 6%, enabling atomic-level bonding between the Ru and Al layers. The Ru layer induces a highly oriented structure in the Al layer through epitaxial growth, suppressing the coarse columnar crystals of traditional Al layers and reducing the surface roughness of the Al layer itself from the source. Furthermore, the Ru layer is used to induce the lattice orientation of the upper layer, blocking roughness transmission, thereby reducing the roughness of the Al layer, reducing diffuse reflection, and avoiding poor ohmic contact in the Al layer.

[0084] When the light-emitting layer, hole transport layer and other functional layers of the device remain unchanged, the turn-on voltage is determined solely by the anode structure. The anode structure suppresses grain protrusion through the amorphous Ta layer, reduces the overall surface roughness of the anode structure, reduces interface spikes, micro-short circuits and interface contact defects between the anode structure and the hole injection layer, and reduces interface contact resistance. The decrease in interface contact resistance directly leads to a reduction in the device's turn-on voltage.

[0085] To achieve the above-mentioned ideas, this invention provides a silicon-based Micro-OLED anode structure, as shown in the figure. Figure 1 This paper discloses a specific embodiment of a silicon-based Micro-OLED anode structure.

[0086] The silicon-based Micro-OLED anode structure includes a silicon-based CMOS backplane 100, a buffer layer 200, a metal reflective layer 300, a diffusion barrier layer 400, and a hole injection layer 500. The buffer layer 200 comprises a textured composite structure of a tantalum layer 210 and a ruthenium layer 220. The tantalum layer 210 is amorphous, and the ruthenium layer 220 is hexagonal close-packed. The tantalum layer 210 covers the surface of the silicon-based CMOS backplane 100, and the ruthenium layer 220 covers the surface of the tantalum layer 210. The metal reflective layer 300 covers the surface of the ruthenium layer 220. The diffusion barrier layer 400 covers the surface of the metal reflective layer 300. The hole injection layer 500 covers the surface of the diffusion barrier layer 400.

[0087] In this embodiment, the buffer layer 200 is configured as a textured composite structure comprising a tantalum layer 210 and a ruthenium layer 220. The textured composite structure is a bilayer composite thin film system formed by stacking an amorphous tantalum layer 210 with no crystal orientation at the bottom layer and a hexagonal close-packed ruthenium layer 220 on top. The amorphous tantalum layer 210 has a strong interfacial chemical bond with the insulating dielectric layer on top of the silicon-based CMOS backplane 100, which improves the adhesion between the entire anode structure and the silicon-based CMOS backplane 100. The amorphous tantalum layer 210 has no through grains or grain boundaries inside, and there are no through-type fast diffusion channels extending along the grain boundaries, thus forming a primary diffusion barrier layer that effectively blocks the upward diffusion of impurities. The roughness Ra of the amorphous tantalum layer 210 is ≤0.3nm, forming an atomically flat substrate, providing a flat growth substrate for the ruthenium layer 220.

[0088] The upper ruthenium layer 220 has a hexagonal close-packed (hcp) crystalline structure with regular grain orientation and texture. The ruthenium layer 220 induces the metal reflective layer 300 to form a highly preferred orientation crystalline structure through epitaxial induction, inhibiting the growth of coarse columnar grains and reducing the surface roughness of the metal reflective layer 300 itself from the source. Furthermore, the ruthenium layer 220 can regulate the lattice orientation of the upper thin film and block the upward transmission of the morphological undulations of the lower substrate, further optimizing the surface smoothness of the metal reflective layer 300. The low-roughness metal reflective layer 300 can effectively reduce slow reflection and prevent device failure due to poor ohmic contact. The ruthenium layer 220 has excellent conductivity, reducing the overall contact resistance of the anode structure. The ruthenium layer 220 can also serve as a second barrier layer, effectively blocking the upward diffusion of metal in the via, further reducing the roughness of the anode structure. This reduces the average surface roughness of the entire anode structure, improves the film quality and light reflectivity of the metal reflective layer 300, increases hole injection efficiency, reduces device turn-on voltage, and meets the requirements of microcavity displays.

[0089] refer to Figure 1 As shown, in some embodiments, the silicon-based CMOS backplane 100 includes a substrate, CMOS transistors formed on the substrate, and an insulating dielectric layer formed on the CMOS transistors. The substrate material is a single-crystal silicon wafer; therefore, the Micro-OLED is referred to as a silicon-based Micro-OLED. The CMOS transistors include NMOS transistors and PMOS transistors, constituting the driving circuit, switching circuit, etc., of the Micro-OLED. The insulating dielectric layer material can include insulating materials such as silicon dioxide and silicon nitride. The insulating dielectric layer can be a single layer or multiple layers. The insulating dielectric layer formed on the CMOS transistors can be defined as the first insulating dielectric layer, and the other insulating dielectric layers can be defined as intermediate insulating dielectric layers. Contact holes are formed on the first insulating dielectric layer, and through-holes are formed on the intermediate insulating dielectric layers. Simultaneously, metal interconnect layers are formed on the first and intermediate insulating dielectric layers. Through the metal interconnect layers, tungsten contact holes, and through-holes formed on the insulating dielectric layers, the source, drain, and gate of the NMOS and PMOS transistors are electrically connected to the upper anode structure. The metal filling the contact holes and through-holes can be metals such as tungsten and copper.

[0090] refer to Figure 1As shown, in some embodiments, a buffer layer 200 is disposed on the surface of the silicon-based CMOS backplane 100, that is, a buffer layer 200 is disposed on the surface of the insulating dielectric layer to buffer the interface mismatch between the insulating dielectric layer and vias of the silicon-based CMOS backplane 100 and the metal reflective layer 300. The buffer layer 200 includes a textured composite structure comprising a tantalum (Ta) layer 210 and a ruthenium (Ru) layer 220. The tantalum layer 210 has an amorphous structure, and the ruthenium layer 220 has a hexagonal close-packed structure. The tantalum layer 210 covers the surface of the silicon-based CMOS backplane 100, and the ruthenium layer 220 covers the surface of the tantalum layer 210.

[0091] In some embodiments, the thickness of the buffer layer 200 ranges from 8 to 12 nm. For example, the thickness of the buffer layer 200 can be 8 nm, 10 nm, 12 nm, or any value within the range of 8 to 12 nm. By setting the thickness of the buffer layer 200 to a bilayer composite film of 8 to 12 nm, the stress of the buffer layer 200 is controllable, the overall film thickness is moderate, and the interlayer stress is small. During the formation of the buffer layer 200, for example, under high-temperature sputtering and encapsulation processes, warping, peeling, and microcracks are less likely to occur.

[0092] In some embodiments, the thickness of the tantalum layer 210 ranges from 3 to 5 nm, and the roughness Ra ≤ 0.3 nm. For example, the thickness of the tantalum layer 210 can be 3 nm, 4 nm, or 5 nm. The thickness of the ruthenium layer 220 ranges from 5 to 7 nm. For example, the thickness of the ruthenium layer 220 can be 5 nm, 6 nm, or 7 nm. That is, the thickness of the tantalum layer 210 can be any value within the range of 3 to 5 nm, and the thickness of the ruthenium layer 220 can be any value within the range of 5 to 7 nm, as long as the sum of the thicknesses of the tantalum layer 210 and the ruthenium layer 220 (i.e., the thickness of the buffer layer 200) is within the range of 8 to 12 nm. Controlling the thickness of the tantalum layer 210 to 3 to 5 nm and the roughness Ra ≤ 0.3 nm allows the formation of a continuous amorphous barrier film. This provides a flat substrate with a roughness of less than or equal to 0.3 nm, without a fixed crystal orientation, resulting in extreme smoothness. This further bridges minor interface undulations, alleviates stress, blocks trace element interdiffusion, and makes the interface more stable. The ruthenium 220 layer has a well-developed and regular HCP texture, providing a uniform crystal orientation template for the upper metal reflective layer. This forces the upper conductive metal to grow along a preferred crystal orientation, which is used to induce the upper lattice orientation, block roughness transmission, and suppress the formation of coarse columnar crystals. The Ru lattice matching is excellent, which greatly reduces the interlayer lattice mismatch and solves the orange peel-like interface wrinkles of the traditional Ti and Al layer system from the source.

[0093] refer to Figure 1As shown, in some embodiments, the metal reflective layer 300 includes an aluminum layer with a thickness ranging from 80 to 150 nm; and / or, the diffusion barrier layer includes a titanium nitride layer with a thickness ranging from 1 to 5 nm; and / or, the hole injection layer 500 includes an ITO layer with a thickness ranging from 10 to 20 nm. The metal reflective layer 300 may include an aluminum layer, and may also include a titanium layer, a ruthenium layer; the diffusion barrier layer 400 may include a titanium nitride layer, and may also include a tantalum nitride layer, a tungsten nitride layer, etc.; the hole injection layer 500 may include an ITO layer, and may also include an IZO layer, an IGZO layer, etc.

[0094] refer to Figure 1 As shown, in some embodiments, a metal reflective layer 300 is disposed on the surface of the ruthenium layer 220. The metal reflective layer includes an aluminum (Al) layer or a silver (Ag) layer.

[0095] In some embodiments, the metal reflective layer 300 includes an aluminum layer with a thickness ranging from 80 to 150 nm. The textured composite structure of the tantalum layer 210 and the ruthenium layer 220 induces the subsequent Al layer to form ultrafine (111) preferred orientations, resulting in a smooth aluminum layer surface and reduced scattering loss. This allows the aluminum layer to achieve specular reflection of visible light, with a visible light reflectivity ≥92% (compared to ≤90% for traditional Al layers). Simultaneously, it ensures an overall anode roughness Ra ≤0.6 nm, fully meeting the stringent flatness requirements (Ra ≤1.0 nm) of silicon-based Micro-OLED microcavities. The trace solid solution of Ru (1-2 at.%) does not affect the reflectivity of Al, but rather inhibits the oxidation and discoloration of Al. The hole injection layer 500 (ITO layer) formed subsequently maintains ≥90% visible light transmittance, and works in synergy with the Al reflective layer to achieve efficient optical coupling. The ITO layer grown on the flat aluminum layer is uniform and dense with low light scattering loss, thereby improving the visible light transmittance of the ITO layer. The flat interface of the anode structure can reduce the interface contact resistance, optimize hole injection, and reduce the device turn-on voltage.

[0096] In this embodiment, the lattice mismatch between Ru (2.70 Å) and Al(111) (2.86 Å) is less than 6%, enabling atomic-level bonding between the Ru and Al layers. The Ru layer induces a highly oriented structure in the Al layer through epitaxial growth, suppressing the coarse columnar crystals of traditional Al layers and reducing roughness. Furthermore, the Ru layer induces the upper lattice orientation, blocking roughness transmission, thereby reducing the roughness of the Al layer, decreasing diffuse reflection, and preventing poor ohmic contact. Ru exhibits strong chemical stability and high-temperature oxidation resistance, isolating the Ta layer from direct contact with the upper Al layer, preventing Al atoms from diffusing downwards, and avoiding interfacial alloying. The Ru layer can improve the overall anode structure's film density, forming a secondary diffusion barrier layer, while simultaneously optimizing interface smoothness, improving the film quality and light reflectivity of the Al layer.

[0097] Ta has a coefficient of thermal expansion of 6.5 × 10⁻⁶. -6 The coefficient of thermal expansion of Ru is 8.3 × 10⁻⁶ K. -6 The coefficient of thermal expansion of Al is 23.1 × 10⁻⁶ K. -6 / K means that along the direction perpendicular to the silicon-based CMOS backplane 100, the thermal expansion coefficients of the Ta, Ru, and Al layers transition in a gradient manner, and the stress is gradually released during the cooling process, thereby avoiding the problem of film peeling caused by excessive difference in thermal expansion coefficients.

[0098] refer to Figure 1 As shown, in some embodiments, a diffusion barrier layer 400 is disposed on the surface of the metal reflective layer 300. The material of the diffusion barrier layer 400 may include tantalum nitride (TaN), titanium nitride (TiN), or similar materials.

[0099] Preferably, the diffusion barrier layer 400 may include a titanium nitride (TiN) layer with a thickness ranging from 2 to 5 nm. By setting the diffusion barrier layer 400, Al atoms can be blocked from diffusing upwards in both directions, while oxygen and metal elements in the hole injection layer 500 can diffuse downwards, thus avoiding the formation of a high-resistance oxide layer and impurity contamination at the interface and preventing an increase in the contact resistance of the anode structure.

[0100] refer to Figure 1 As shown, in some embodiments, a hole injection layer 500 is disposed on the surface of the diffusion barrier layer 400. The material of the hole injection layer 500 may include an ITO layer, an IZO layer, etc.

[0101] Preferably, the hole injection layer 500 may include an ITO layer with a thickness ranging from 10 to 20 nm. The ITO layer is a transparent indium tin oxide layer, whose work function matches the energy level of the organic light-emitting layer, enabling efficient hole injection into the subsequently formed organic semiconductor thin film stack. It also has high visible light transmittance, ensuring that reflected light is emitted upwards; furthermore, it can optimize interface adhesion, improve the quality of organic thin film formation, and reduce device leakage current.

[0102] It should be noted that the anode structure disclosed in this embodiment is not only applied to silicon-based Micro-OLED, but also to near-eye display micro-display devices such as AR and VR. It has good technical versatility and broad industrial application prospects.

[0103] To achieve the above-described idea, this embodiment discloses a silicon-based organic light-emitting diode, including the anode structure as described above.

[0104] The silicon-based organic light-emitting diode disclosed in this embodiment has high hole injection efficiency and low turn-on voltage, which can meet the requirements of microcavity display.

[0105] In summary, the above embodiments have provided a detailed description of the silicon-based Micro-OLED anode structure and its fabrication method, as well as different configurations of silicon-based organic light-emitting diodes. Of course, the above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for fabricating a silicon-based Micro-OLED anode structure, characterized in that, include: S10, Provides a silicon-based CMOS backplane; S20. A buffer layer is deposited on the surface of the silicon-based CMOS backplane; wherein the buffer layer comprises a textured composite structure of a tantalum layer and a ruthenium layer, the tantalum layer is an amorphous structure, the ruthenium layer is a hexagonal close-packed structure, the tantalum layer covers the surface of the silicon-based CMOS backplane, and the ruthenium layer covers the surface of the tantalum layer; S30. A metal reflective layer, a diffusion barrier layer, and a hole injection layer are sequentially deposited on the surface of the ruthenium layer to form an anode structure.

2. The method for preparing a silicon-based Micro-OLED anode structure according to claim 1, characterized in that, Step S10 also includes: The surface of the silicon-based CMOS backplane is pre-treated by CMP planarization to make the surface roughness of the silicon-based CMOS backplane less than or equal to 0.5 nm.

3. The method for fabricating a silicon-based Micro-OLED anode structure according to claim 1, characterized in that, Between steps S10 and S20, the following is also included: S11. The surface of the silicon-based CMOS backplane is cleaned using at least one of the following: plasma formed by argon ionization, plasma formed by hydrogen discharge, and plasma formed by discharge of a mixed gas of helium and hydrogen.

4. The method for preparing a silicon-based Micro-OLED anode structure according to claim 1, characterized in that, In step S20, the tantalum layer and the ruthenium layer are deposited using a DC magnetron sputtering process.

5. The method for preparing a silicon-based Micro-OLED anode structure according to claim 4, characterized in that, When depositing the tantalum layer, the sputtering power of the reaction chamber ranges from 3800 to 5000 W, the gas pressure ranges from 3.5 to 5 mTorr, the deposition temperature ranges from 25 to 100 °C, and the deposition thickness ranges from 3 to 5 nm.

6. The method for preparing a silicon-based Micro-OLED anode structure according to claim 4, characterized in that, When depositing the ruthenium layer, the sputtering power of the reaction chamber ranges from 2000 to 4000 W, the gas pressure ranges from 2 to 5 mTorr, the deposition temperature ranges from 150 to 250 °C, and the deposition thickness ranges from 5 to 7 nm.

7. The method for preparing a silicon-based Micro-OLED anode structure according to claim 1, characterized in that, The method also includes: S40. Under an inert gas environment, perform an annealing process on the formed anode structure.

8. The method for preparing a silicon-based Micro-OLED anode structure according to claim 7, characterized in that, The annealing process is performed in a nitrogen or argon atmosphere at a temperature of 200–400°C and held at the annealing temperature for 20–60 minutes.

9. The method for fabricating a silicon-based Micro-OLED anode structure according to claim 1, characterized in that, The buffer layer, the metal reflective layer, the diffusion barrier layer, and the hole injection layer are all formed in different vacuum reaction chambers of the same device during deposition.

10. A silicon-based Micro-OLED anode structure, characterized in that, include: Silicon-based CMOS backplane; A buffer layer comprising a textured composite structure of a tantalum layer and a ruthenium layer, wherein the tantalum layer is amorphous and the ruthenium layer is hexagonal close-packed. The tantalum layer covers the surface of the silicon-based CMOS backplane, and the ruthenium layer covers the surface of the tantalum layer. A metallic reflective layer covers the surface of the ruthenium layer; A diffusion barrier layer covers the surface of the metal reflective layer; A hole injection layer covers the surface of the diffusion barrier layer.

11. The silicon-based Micro-OLED anode structure according to claim 10, characterized in that, The thickness of the buffer layer ranges from 8 to 12 nm.

12. The silicon-based Micro-OLED anode structure according to claim 10, characterized in that, The thickness of the tantalum layer ranges from 3 to 5 nm, and the roughness Ra ≤ 0.3 nm; the thickness of the ruthenium layer ranges from 5 to 7 nm.

13. The silicon-based Micro-OLED anode structure according to claim 10, characterized in that, The metal reflective layer includes an aluminum layer, the thickness of which ranges from 80 to 150 nm. And / or, the diffusion barrier layer includes a titanium nitride layer, the thickness of which ranges from 2 to 5 nm; And / or, the hole injection layer includes an ITO layer, the thickness of which ranges from 10 to 20 nm.

14. A silicon-based organic light-emitting diode, characterized in that, Includes the anode structure as described in any one of claims 10-13.

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