Deposition mask, method of manufacturing a deposition mask, and electronic device

Abstract

Disclosed are a deposition mask, a method of manufacturing a deposition mask, and an electronic device. The deposition mask can include a base layer having a first opening and a second opening having different widths from each other, and a mask pattern layer disposed on the base layer and including a cell pattern portion overlapping the first opening and a key pattern portion overlapping the second opening, wherein a first virtual line substantially parallel to the base layer and passing through a center of the cell pattern portion is substantially parallel to a second virtual line substantially parallel to the base layer and passing through a center of the key pattern portion.

Description

Technical Field

[0001] One or more embodiments of this disclosure relate to deposition masks, methods of manufacturing deposition masks, and electronic devices manufactured using deposition masks. Background Technology

[0002] Electronic devices including display panels include multiple pixels. Each pixel may include driving elements such as thin-film transistors and display elements such as organic light-emitting diodes. Display elements can be formed by stacking electrodes along with multiple organic layers and multiple inorganic layers on a substrate.

[0003] The electrodes, organic layers, and inorganic layers in a display element can be deposited patterns formed in specific areas by a deposition process. Such deposited patterns can be formed using a mask having openings defined in specific areas (e.g., desired patterned areas).

[0004] As display panels utilizing organic light-emitting diodes continue to advance towards higher resolutions, the mask patterns used in their manufacture must also be produced at the micrometer scale. Accordingly, one or more technologies (or research) are being developed to achieve the manufacture of masks with ultra-fine patterns. Summary of the Invention

[0005] One or more aspects of embodiments of this disclosure relate to deposition masks capable of improving deposition accuracy in deposition processes and methods for manufacturing deposition masks.

[0006] One or more aspects of embodiments of this disclosure relate to electronic devices that have improved or enhanced display quality due to increased deposition accuracy.

[0007] Further aspects of the embodiments will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0008] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects and features of specific embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the detailed description provided.

[0009] According to one or more embodiments, a deposition mask includes: a substrate layer having a first opening and a second opening, the first opening and the second opening having different widths from each other; and a mask pattern layer disposed on the substrate layer, and including: a cell pattern portion overlapping the first opening; and a bond pattern portion overlapping the second opening, wherein a first virtual line substantially parallel to the substrate layer and passing through the center of the cell pattern portion is substantially parallel to a second virtual line substantially parallel to the substrate layer and passing through the center of the bond pattern portion.

[0010] In one or more embodiments, the second virtual line may be adjacent (e.g., closer) to the base layer than the first virtual line.

[0011] In one or more embodiments, the mask pattern layer may include silicon nitride.

[0012] In one or more embodiments, the thickness of the mask pattern layer can range from about 0.5 micrometers to about 2 μm.

[0013] In one or more embodiments, the key pattern portion may be spaced (or separated) from the center of the mask pattern layer more far than the unit pattern portion may be spaced from the center of the mask pattern layer.

[0014] In one or more embodiments, the first opening and the second opening may each be formed or arranged such that the width on one side is smaller than the width on the other side.

[0015] According to one or more embodiments, a method of manufacturing a deposition mask includes: forming a first material layer on a substrate layer; forming at least one groove in a surface of the first material layer; forming a mask pattern layer on the first material layer; patterning the surface of the mask pattern layer to form a bond pattern portion overlapping the at least one groove and a cell pattern portion spaced apart and / or separated (e.g., spaced apart or separated) from the bond pattern portion; forming a first opening overlapping the cell pattern portion and a second opening overlapping the bond pattern portion in the substrate layer; and removing portions of the first material layer disposed between the cell pattern portion and the first opening and between the bond pattern portion and the second opening.

[0016] In one or more embodiments, the width of the at least one slot may be greater than the width of the key pattern portion.

[0017] In one or more embodiments, the width of the at least one slot may be equal to or less than twice the width of the key pattern portion.

[0018] In one or more embodiments, the depth of the at least one groove may have a value in the range of approximately 30% to approximately 80% of the thickness of the first material layer.

[0019] In one or more embodiments, a first virtual line that is substantially parallel to the base layer and passes through the center of the unit pattern portion may be substantially parallel to a second virtual line that is substantially parallel to the base layer and passes through the center of the key pattern portion.

[0020] In one or more embodiments, the second virtual line may be adjacent (e.g., closer) to the base layer than the first virtual line.

[0021] In one or more embodiments, the mask pattern layer may include silicon nitride.

[0022] In one or more embodiments, the thickness of the mask pattern layer can range from about 0.5 micrometers to about 2 μm.

[0023] In one or more embodiments, the key pattern portion may be spaced (or separated) from the center of the mask pattern layer more far than the unit pattern portion may be spaced from the center of the mask pattern layer.

[0024] In one or more embodiments, the first opening and the second opening may each be formed or arranged such that the upper width is smaller than the lower width.

[0025] In one or more embodiments, the first material layer may include silicon oxide.

[0026] In one or more embodiments, the thickness of the unit pattern portion may be substantially equal to the thickness of the key pattern portion.

[0027] In one or more embodiments, the width of the key pattern portion may be smaller than the width of the unit pattern portion.

[0028] According to one or more embodiments, an electronic device includes: a substrate; a plurality of thin-film transistors disposed on the substrate; a plurality of pixel electrodes electrically connected to the plurality of thin-film transistors; a plurality of intermediate layers disposed on the plurality of pixel electrodes; and a counter electrode disposed on the plurality of intermediate layers, wherein at least one selected from the plurality of thin-film transistors, the plurality of pixel electrodes, the plurality of intermediate layers and the counter electrode is formed or applied using a deposition mask as described in one or more embodiments.

[0029] For example, the deposition masks and related fabrication methods described herein enable precise patterning of functional layers in electronic devices, such as display panels. By improving the geometry and alignment of mask features, such as cell pattern portions and bond pattern portions, the disclosed techniques support high-resolution deposition processes. This, for example, contributes to improved or enhanced device performance and reliability in applications requiring fine pixel structures and uniform (e.g., substantially uniform) material deposition.

[0030] Other aspects, effects, and / or embodiments of this disclosure will be better understood through the detailed description, the appended claims and their equivalents, and the accompanying drawings. Attached Figure Description

[0031] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a schematic cross-sectional view of an apparatus for manufacturing a display device according to one or more embodiments;

[0033] Figure 2 It is a schematic plan view of a deposition mask according to one or more embodiments;

[0034] Figure 3 It is along Figure 2 A schematic cross-sectional view of the deposition mask taken by line I-I';

[0035] Figure 4 yes Figure 3 A magnified view of region AA;

[0036] Figure 5 yes Figure 3 A magnified view of region BB;

[0037] Figures 6 to 11 This is a schematic cross-sectional view of a method for manufacturing a deposition mask according to one or more embodiments;

[0038] Figure 12 This is a schematic perspective view of a display device according to one or more embodiments;

[0039] Figure 13 This is a schematic cross-sectional view of a display device according to one or more embodiments;

[0040] Figure 14 This is a diagram of the equivalent circuit of a pixel in a display device according to one or more embodiments;

[0041] Figure 15 It is a schematic cross-sectional view of a display panel according to one or more embodiments;

[0042] Figure 16 It is a block diagram of an electronic device according to one or more embodiments; and

[0043] Figure 17 This is a set of schematic diagrams of an electronic device according to one or more embodiments. Detailed Implementation

[0044] In the following, the subject matter of this disclosure will be described more fully with reference to the accompanying drawings, which illustrate one or more suitable embodiments of this disclosure. However, the subject matter of this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein, and one or more changes and modifications may be made. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art to which this disclosure pertains.

[0045] When describing embodiments of this disclosure, the word "may" refers to "one or more embodiments of this disclosure".

[0046] In the context of this application, unless otherwise defined, the term “use” may be regarded as synonymous with the term “utilize”.

[0047] In this disclosure, the terms "first," "second," etc., are used not in a limiting sense, but to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element discussed herein may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0048] Unless the context clearly indicates otherwise, the singular form used herein is intended to include the plural form as well. As used herein, “a,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural (e.g., both singular and plural) unless the context clearly indicates otherwise. For example, unless the context clearly indicates otherwise, “element” has substantially the same meaning as “at least one element.” “At least one” should not be construed as limiting “a.”

[0049] "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0050] It will be further understood that the terms “having,” “comprising,” and / or “including” as used herein specify the presence of a stated feature or element, but do not exclude the presence or addition of one or more other features or elements. For example, it should be understood that the terms “comprising,” “including,” or “having” specify the presence of a stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising,” “including,” “having,” or similar terms include or support the terms “consisting of,” and “substantially consisting of,” indicating the presence of a stated feature, integer, step, operation, element, and / or component, while other features, integers, steps, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0051] As used herein, “approximately” includes the stated value and refers to an acceptable deviation from the stated value, determined by a person skilled in the art considering the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] Furthermore, it should be understood that even if (for example, when) the terms “approximately,” “about,” or “substantially” are not explicitly stated in a given element (e.g., a claim element), the scope of such an element is intended to include non-substantial variations or variations within the understanding of a person skilled in the art. For example, the numerical values ​​and ranges provided herein are intended to include tolerances and measurement uncertainties that would be recognized by a person skilled in the art, and these elements (e.g., claim elements) should be interpreted accordingly to include such equivalents.

[0053] Any numerical ranges listed herein are intended to include all subranges with the same numerical precision contained within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between the listed minimum value 1.0 and the listed maximum value 10.0 (and including both the listed minimum value 1.0 and the listed maximum value 10.0), such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit listed in this specification is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to amend the specification (including the claims) to expressly list any subranges contained within the ranges expressly listed herein.

[0054] In this disclosure, it will be understood that if (e.g., when) a portion such as a membrane, zone, or element is referred to as being "on" another portion, this can include not only the case where the portion is directly on the other portion, but also the case where an intervening membrane, zone, or element may be present between them. In contrast, if (e.g., when) a portion is referred to as being "directly on" another portion, an intervening membrane, zone, or element may not be present between them.

[0055] For ease of illustration, the dimensions of the elements in the drawings may be enlarged or reduced. For example, since the dimensions and / or thicknesses of the elements in the drawings are arbitrarily illustrated for ease of illustration, the embodiments of this disclosure are not limited thereto.

[0056] In the following examples, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system, and can be interpreted in a general sense that includes such axes. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also represent different directions that are not orthogonal to each other.

[0057] In the context of this disclosure and unless otherwise defined, a plan view is an orthographic projection of a three-dimensional object onto a horizontal plane intersecting the object. For example, it is a top view showing the layout and spatial relationships of one or more elements in an object or structure. A plan view perpendicular to the z-axis (e.g., thickness) refers to a top view of the object, as if (e.g., when) viewed directly downwards from above on a surface. In this context, the z-axis direction is perpendicular to or orthogonal to the horizontal plane defined by the x-axis and y-axis directions.

[0058] If (for example, when) an embodiment can be implemented differently, then a particular process sequence can be performed differently than the described sequence. For example, two processes described consecutively can be performed substantially simultaneously, or they can be performed in the reverse order of the described sequence.

[0059] In the following description, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the description of one or more embodiments with reference to the accompanying drawings, substantially the same or corresponding elements are indicated by the same reference numerals, and redundant descriptions may be omitted.

[0060] Figure 1 This is a schematic cross-sectional view of an apparatus for manufacturing a display device according to one or more embodiments.

[0061] The manufacturing equipment 1 for the display device may include a chamber CH, a first support SP1, a second support SP2, a deposition mask MA, a deposition source SC, a magnetic section MG, a vision section VS, and a pressure regulating section PSC.

[0062] The chamber CH can have internal space, and the display substrate DS and deposition mask MA can be accommodated within the chamber CH. In this case, a portion of the chamber CH can be formed or arranged as open, and a gate valve GB can be installed in the open portion of the chamber CH. The open portion of the chamber CH can be opened or closed according to the operation of the gate valve GB.

[0063] At this point, the display substrate DS can refer to substrate 301 in which at least one of an organic layer, an inorganic layer, and a metal layer is deposited (as described in more detail herein). Figure 15 The display substrate DS is a substrate on which organic, inorganic, and metal layers have not yet been deposited during the manufacturing process of a display device. In one or more embodiments, the display substrate DS may be a substrate on which organic, inorganic, and metal layers have not yet been deposited.

[0064] The first support portion SP1 can be used to support the display substrate DS. In this case, the first support portion SP1 may include a plate fixed inside the cavity CH. In one or more embodiments, the first support portion SP1 may include a shuttle, on which the display substrate DS is placed, and the shuttle is linearly movable inside the cavity CH. In one or more embodiments, the first support portion SP1 may include an electrostatic chuck or a viscous chuck fixed to or located within the cavity CH for movable movement within the cavity CH.

[0065] The second support SP2 can be used to support the deposition mask MA. In this case, the second support SP2 can be arranged inside the chamber CH. The second support SP2 can be used for fine adjustment of the position of the deposition mask MA. The second support SP2 may include a separate actuator or alignment unit for enabling the deposition mask MA to move in different directions.

[0066] In one or more embodiments, the second support SP2 may include a shuttle. In this case, the deposition mask MA may be placed on the second support SP2, and the second support SP2 may be used to transport the deposition mask MA. For example, the second support SP2 may be used to move to the outside of the chamber CH such that the deposition mask MA is placed thereon, and then move from the outside of the chamber CH to the inside of the chamber CH.

[0067] In this case, the first support portion SP1 and the second support portion SP2 can also be integrally formed with each other. In this example, the first support portion SP1 and the second support portion SP2 can include movable shuttles. At this time, the first support portion SP1 and the second support portion SP2 can include a structure that fixes the deposition mask MA and the display substrate DS when the display substrate DS is placed on the deposition mask MA, and it is also desirable to move the display substrate DS and the deposition mask MA linearly together (e.g., simultaneously).

[0068] However, for ease of explanation, the following description will be given in more detail of an example in which the first support portion SP1 and the second support portion SP2 are formed separately from each other and arranged in different positions, and an example in which the first support portion SP1 and the second support portion SP2 are arranged inside the chamber CH.

[0069] The deposition mask MA can be arranged inside the cavity CH opposite the display substrate DS. The deposition material M can be deposited on the display substrate DS through the deposition mask MA.

[0070] The deposition source SC can be arranged opposite the deposition mask MA and can be used to supply deposition material M such that the deposition material M passes through the deposition mask MA and is deposited on the display substrate DS. In this case, the deposition source SC can be used to evaporate or sublimate the deposition material M by applying heat to it. The deposition source SC can be fixedly located inside the chamber CH, or it can be located inside the chamber CH and linearly movable in one direction.

[0071] The magnetic component MG can be arranged inside the cavity CH, opposite to the display substrate DS and / or the deposition mask MA. In this case, the magnetic component MG can be used to apply a magnetic force to the deposition mask MA, causing the deposition mask MA to be pushed toward the display substrate DS.

[0072] A vision unit VS can be arranged in a cavity CH and can be used to capture the positions of the display substrate DS and the deposition mask MA. In this case, the vision unit VS may include a camera that captures images of the display substrate DS and the deposition mask MA. Based on the images captured in the vision unit VS, the positions of the display substrate DS and the deposition mask MA can be identified, and any deformation of the deposition mask MA can be confirmed. Based on the images, the position of the display substrate DS on the first support SP1 or the position of the deposition mask MA on the second support SP2 can be finely adjusted. However, the following description will give a more detailed example in which the positions of the display substrate DS and the deposition mask MA are aligned by finely adjusting the position of the deposition mask MA on the second support SP2.

[0073] A pressure regulating unit (PSC) can be connected to the chamber CH to regulate the internal pressure of the chamber CH. For example, the pressure regulating unit PSC can be used to regulate the internal pressure of the chamber CH to be substantially equal to or similar to atmospheric pressure. In one or more embodiments, the pressure regulating unit PSC can be used to regulate the internal pressure of the chamber CH to be substantially the same as or similar to a vacuum state.

[0074] The pressure regulating unit PSC may include a connecting pipe 81 connected to the chamber CH and a pump 82 installed in the connecting pipe 81. When the pump 82 is operated, external air can be introduced through the connecting pipe 81, or gas inside the chamber CH can be guided to the outside through the connecting pipe 81.

[0075] In one or more embodiments, a method for manufacturing a display device using a display device manufacturing apparatus 1 is described, in which a display substrate DS may first be prepared.

[0076] The pressure regulating unit PSC can be used to maintain the interior of chamber CH at a pressure substantially the same as or similar to atmospheric pressure, and can operate the gate valve GB to open the open portion of chamber CH.

[0077] Subsequently, the display substrate DS can be loaded from the outside of the cavity CH into the inside of the cavity CH. The display substrate DS can be loaded into the cavity CH in one or more suitable ways. For example, the display substrate DS can be loaded from the outside of the cavity CH into the cavity CH by means of a robotic arm or the like arranged outside the cavity CH. In one or more embodiments, if (for example, when) the first support portion SP1 has a shuttle shape, the first support portion SP1 inside the cavity CH can be pulled out of the cavity CH, the display substrate DS can be placed on the first support portion SP1 by means of a separate robotic arm or the like arranged outside the cavity CH, and the first support portion SP1 can be loaded from the outside of the cavity CH into the inside of the cavity CH.

[0078] As described in one or more embodiments, the deposition mask MA can be positioned inside the cavity CH. In one or more embodiments, the deposition mask MA can be loaded into the cavity CH from outside the cavity CH in a manner substantially the same as or similar to that of the display substrate DS.

[0079] If (for example, when) the display substrate DS is loaded into the chamber CH, the display substrate DS can be placed on the first support SP1. At this time, the vision unit VS can be used to capture the positions of the display substrate DS and the deposition mask MA. The positions of the display substrate DS and the deposition mask MA can be identified based on the image captured in the vision unit VS. At this time, the manufacturing apparatus 1 of the display device may include a separate control unit for identifying the positions of the display substrate DS and the deposition mask MA.

[0080] Once the positions of the display substrate DS and the deposition mask MA are identified, the second support SP2 can finely adjust the position of the deposition mask MA.

[0081] Subsequently, the deposition source SC can be operated to supply deposition material M toward the deposition mask MA, and the deposition material M passing through the deposition mask MA can be deposited onto the display substrate DS. The deposition source SC can be used to move substantially parallel to the display substrate DS and the deposition mask MA, or the display substrate DS and the deposition mask MA can be used to move substantially parallel to the deposition source SC. For example, the deposition source SC can be used to move relative to the display substrate DS and the deposition mask MA. At this time, the pump 82 can be used to draw in gas inside the chamber CH and discharge the gas to the outside of the chamber CH, thereby maintaining the internal pressure of the chamber CH in a state substantially the same as or similar to a vacuum state.

[0082] As described in one or more embodiments, deposition material M supplied from deposition source SC can be deposited on display substrate DS through deposition mask MA to form at least one of a plurality of layers selected, for example, organic layers, inorganic layers, and metal layers stacked in a display device, which will be described in more detail herein.

[0083] Figure 2 It is a schematic plan view of a deposition mask according to one or more embodiments, and Figure 3 It is along Figure 2 A schematic cross-sectional view of the deposition mask taken by line I-I'. Figure 4 yes Figure 3 A magnified view of region AA, and Figure 5 yes Figure 3 A magnified view of region BB.

[0084] According to one or more embodiments, the deposition mask MA can be a mask for manufacturing ultra-high resolution displays. For example, the deposition mask MA can be a mask for manufacturing displays in extended reality (XR) devices such as virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices.

[0085] In one or more embodiments, the deposition mask MA can be used to perform pixel deposition processes on silicon wafers other than those used in large substrates in related technology displays. For displays in XR devices, the screen can be directly in front of the user's eyes. Therefore, such XR devices can have small screens rather than large screens. Because XR devices are close to the user's eyes, such devices may also require ultra-high resolution. For example, displays in XR devices may need or expect to have a resolution of approximately at least 1000 pixels per inch (PPI), and may need or expect to have an ultra-high resolution of at least 2000 PPI. The deposition mask MA according to one or more embodiments can be a mask used to manufacture such ultra-high resolution displays.

[0086] refer to Figures 2 to 5 The deposition mask MA may include a substrate layer 110, a first material layer 120, and a mask pattern layer 130. In one or more embodiments, the deposition mask MA may include a cell region CA and a bond region KA. Hereinafter, the cell region CA and the bond region KA may be regions formed by dividing the deposition mask MA by lines perpendicular to (e.g., substantially perpendicular to) a surface MA-a of the deposition mask MA, and may be defined, respectively, as the region where the cell pattern portion CA-P is arranged and the region where the bond pattern portion KA-P is arranged.

[0087] In one or more embodiments, when viewed in a plane, the cell region CA may be located at the central portion of the deposition mask MA. Herein, "when viewed in a plane" can be defined as the state of surface MA-a of the deposition mask MA, on which the cell pattern portion CA-P and the bond pattern portion KA-P are formed, viewed in the z-axis direction. The cell region CA may be arranged as a plurality of cell regions, and the plurality of cell regions CA may form a specific arrangement.

[0088] In one or more embodiments, the bond region KA may be arranged in the outer portion outside the cell region CA. The bond region KA of the deposition mask MA may be spaced further from the center of the deposition mask MA than the cell region CA may be spaced further from the center of the deposition mask MA.

[0089] The bond regions KA can be arranged as multiple bond regions. For example, if (e.g., when) the deposition mask MA has a square plate shape (e.g., substantially square plate shape; e.g., in the form of a plate), then the bond regions KA can be arranged at the various corners of the deposition mask MA. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the bond regions KA can be located between adjacent (e.g., close to) cell regions CA.

[0090] In one or more embodiments, the substrate 110 may include a silicon substrate. By utilizing techniques developed in semiconductor processes, the silicon substrate can be processed with fine and precise processes compared to large substrates, and thus can be used as a substrate for ultra-high resolution displays. In one or more embodiments, the deposition mask MA can utilize the silicon mask substantially equally to form pixels on the silicon substrate of the ultra-high resolution display.

[0091] The shape of the substrate 110 can be the same as that of the display substrate DS (see...) Figure 1 The shape corresponds to that of the display substrate DS. For example, the substrate 110 may have substantially the same size or shape as the display substrate DS. However, embodiments of this disclosure are not limited thereto, and in one or more embodiments, the substrate 110 may have a size larger than that of the display substrate DS. For example, the substrate 110 may comprise materials such as glass, quartz, and / or polymer resin.

[0092] The substrate 110 may include a first opening OP1 and a second opening OP2 formed or arranged through the substrate 110 in the thickness direction (e.g., the z-axis direction). The first opening OP1 may overlap with the cell region CA (or the cell pattern portion CA-P), and the second opening OP2 may overlap with the bond region KA (or the bond pattern portion KA-P).

[0093] In one or more embodiments, the first opening OP1 and the second opening OP2 may each be arranged such that the width on one side is smaller than the width on the other side. The first opening OP1 and / or the second opening OP2 may be formed or arranged such that the width on the side adjacent to (e.g., close to) the cell pattern portion CA-P or the bond pattern portion KA-P is smaller than the width on the opposite side. In one or more embodiments, the first opening OP1 and / or the second opening OP2 may be formed or arranged such that the inner peripheral surface is inclined relative to the surface MA-a of the deposition mask MA. However, embodiments of this disclosure are not limited thereto, and the first opening OP1 and / or the second opening OP2 may be formed or arranged such that the inner peripheral surface is perpendicular (e.g., substantially perpendicular to) the surface MA-a of the deposition mask MA.

[0094] The first opening OP1 and the second opening OP2 may have different cross-sectional dimensions (e.g., different widths) in a direction perpendicular to (e.g., substantially perpendicular to) the thickness direction (e.g., the z-axis direction) of the substrate 110. In one or more embodiments, the width of the first opening OP1 may be greater than the width of the second opening OP2. Hereinafter, the width of the first opening OP1 and / or the second opening OP2 may refer to the width of the substrate 110 in a cross-section cut perpendicular to (e.g., substantially perpendicular to) the thickness direction (e.g., the z-axis direction).

[0095] The first opening OP1 and the second opening OP2 can be used to provide the deposited material M (see...). Figure 1 The portion of the substrate 110 that does not form the first opening OP1 and the second opening OP2 can be used to shield the deposited material from passing through that portion, and can also be used to support the mask pattern layer 130.

[0096] A first material layer 120 may be disposed on a substrate layer 110. The first material layer 120 may be located between the substrate layer 110 and the mask pattern layer 130. In one or more embodiments, the first material layer 120 may completely (e.g., substantially completely) cover the outer surface of the substrate layer 110. The first material layer 120 may be formed as an insulating (e.g., electrically insulating) layer comprising a material such as silicon oxide.

[0097] A mask pattern layer 130 may be disposed on the first material layer 120. In one or more embodiments, the mask pattern layer 130 may completely (e.g., substantially completely) cover the outer surface of the first material layer 120. For example, the mask pattern layer 130 may form a surface MA-a and another surface MA-b of a deposition mask MA. In an example, surface 130a of the mask pattern layer 130 may form surface MA-a of the deposition mask MA, and the other surface 130b of the mask pattern layer 130 may form the other surface MA-b of the deposition mask MA.

[0098] The mask pattern layer 130 may include a material that can be patterned by semiconductor processes. For example, the mask pattern layer 130 may be formed as an insulating (e.g., electrically insulating or electrically insulator) layer comprising a material such as silicon nitride. For example, the mask pattern layer 130 may have a thickness in the range of about 0.5 μm to about 2 μm (e.g., about 1 μm to about 2 μm).

[0099] The unit pattern portion CA-P and the bond pattern portion KA-P can be on the surface 130a of the mask pattern layer 130. A first virtual line L1 passing through the center of the unit pattern portion CA-P in the thickness direction (e.g., the z-axis direction) of CA-P can be substantially parallel to a second virtual line L2 passing through the center of the bond pattern portion KA-P in the thickness direction (e.g., the z-axis direction) of KA-P. In this document, both the first virtual line L1 and the second virtual line L2 (e.g., simultaneously) can be lines substantially parallel to the substrate layer 110 and can extend substantially parallel to each other without overlapping or intersecting. In one or more embodiments, the thickness of the unit pattern portion CA-P can be substantially equal to the thickness of the bond pattern portion KA-P. In one or more embodiments, the width w4 of the bond pattern portion KA-P can be smaller than the width of the unit pattern portion CA-P.

[0100] The second virtual line L2 can be arranged to be adjacent (e.g., closer) to the substrate layer 110 than the first virtual line L1. For example, the center of the bond pattern portion KA-P in the thickness direction (e.g., the z-axis direction) can be located to be adjacent (e.g., closer) to the substrate layer 110 than the center of the unit pattern portion CA-P in the thickness direction (e.g., the z-axis direction).

[0101] The unit pattern portion CA-P may include a plurality of first through holes TH1. The plurality of first through holes TH1 may form a specific (e.g., set or predetermined) arrangement. For example, the plurality of first through holes TH1 may be arranged in a grid shape (e.g., substantially a grid shape).

[0102] Figure 2 and Figure 4 This is an example in which the shape of the first through-hole TH1 in the plan view is circular (e.g., substantially circular), but the embodiments of this disclosure are not limited thereto, and the shape of the first through-hole TH1 may be changed to one or more suitable shapes such as elliptical (e.g., substantially elliptical) or polygonal (e.g., substantially polygonal) depending on the purpose and use.

[0103] The first via TH1 may be formed in the cell region CA through the mask pattern layer 130 and / or the first material layer 120 in the thickness direction (e.g., the z-axis direction). The first via TH1 may be used to provide deposited material M applied from the other surface MA-b of the deposition mask MA (see Figure 1 () through its channels through the mask pattern layer 130 and / or the first material layer 120.

[0104] In one or more embodiments, such as Figure 3 and Figure 4 As shown, the cell region CA may have a structure in which the mask pattern layer 130 and the first material layer 120 are stacked. In this case, the first via TH1 may be formed through both the mask pattern layer 130 and the first material layer 120 (e.g., through both the mask pattern layer 130 and the first material layer 120 simultaneously).

[0105] In one or more embodiments, the first via TH1 may include a third opening 132 and a fourth opening 122. The third opening 132 may be formed through the mask pattern layer 130, and the fourth opening 122 may be formed through the first material layer 120. The third opening 132 and the fourth opening 122 may overlap each other. In a cross-section cut in the thickness direction (e.g., the z-axis direction) of the deposition mask MA, the width w1 of the third opening 132 may be smaller than the width w2 of the fourth opening 122. In a plan view, the area of ​​the third opening 132 may be smaller than the area of ​​the fourth opening 122.

[0106] In one or more embodiments, the first via TH1 and the first opening OP1 of the substrate 110 may overlap each other. Therefore, the deposited material M (see...) Figure 1 The first opening OP1, the fourth opening 122, and the third opening 132 can pass through sequentially. The width of the first opening OP1 can be greater than or equal to the width of the unit pattern portion CA-P in which multiple first through holes TH1 are arranged.

[0107] The key pattern portion KA-P may include at least one second via TH2. The second via TH2 may be formed in the key region KA through the mask pattern layer 130 in the thickness direction (e.g., the z-axis direction). The second via TH2 may be used to perform alignment with the display substrate DS.

[0108] Figure 5 This is an example in which the shape of the second through-hole TH2 in the plan view is rectangular (e.g., substantially rectangular), but the embodiments of this disclosure are not limited thereto, and the shape of the second through-hole TH2 may be changed to one or more suitable shapes such as square or cross depending on the purpose and use.

[0109] like Figure 3 and Figure 5As shown, the bond pattern portion KA-P in the bond region KA may consist only of the mask pattern layer 130. For example, only the mask pattern layer 130 may be arranged in the bond region KA, and both the substrate layer 110 and the first material layer 120 (e.g., simultaneously) may be removed. Since the substrate layer 110 and the first material layer 120 are removed from the bond region KA, the deposition mask MA and the display substrate DS (see Figure 1) are then deposited. Figure 1 Alignment of the KA-P key pattern portion can be performed more quickly and accurately.

[0110] The width w3 of the key region KA can be greater than the width w5 of the second via TH2. In one or more embodiments, if (e.g., when) the key region KA includes a plurality of second vias TH2, the width w3 of the key region KA can be greater than the width w4 of the key pattern portion KA-P. In this case, the key pattern portion KA-P can be defined along the outermost periphery of the second via TH2. The size of the key region KA in the plane can be greater than the size of the key pattern portion KA-P in the plane. For example, the size of the key region KA can have a value in the range of approximately 1 to 2 times the size of the key pattern portion KA-P. In one or more embodiments, the width w5 of the second via TH2 can be greater than the width w1 of the first via TH1.

[0111] The mask pattern layer 130 may include a first portion 131 corresponding to a region other than the bond region KA and a second portion 134 disposed in the bond region KA. A second via TH2 may be formed in the second portion 134. The first portion 131 and the second portion 134 may be integrally formed with each other. The first portion 131 and the second portion 134 may have substantially the same thickness, but embodiments of this disclosure are not limited thereto.

[0112] A surface 131a of the first portion 131 and a surface 134a of the second portion 134 may form a step. In one or more embodiments, the surface 134a of the second portion 134 may be made to be lower than the surface 131a of the first portion 131 by a second height h2 in the direction along which the base layer 110 is arranged (e.g., the -z axis direction). For example, the second height h2 of the second portion 134 may have a value in the range of about 30% to about 80% (e.g., about 50% to about 80%) of the thickness h1 of the second portion 134.

[0113] Since the surface 134a of the second portion 134 is lowered inward relative to the surface 131a of the first portion 131, damage to the bond pattern portion KA-P due to contact between the deposition mask MA and the display substrate DS can be suppressed or reduced if (for example, when) the deposition mask MA moves toward the display substrate DS.

[0114] Figures 6 to 11This is a schematic cross-sectional view of a method for manufacturing a deposition mask according to one or more embodiments.

[0115] In the following text, reference will be made to Figures 6 to 11 A method for manufacturing a deposition mask according to one or more embodiments is described in more detail. First, as... Figure 6 As shown, the first material layer 120 may be formed on the substrate layer 110. The substrate layer 110 and the first material layer 120 may include materials that can be patterned by semiconductor processes.

[0116] For example, the substrate 110 may be a substrate comprising a silicon material. The substrate 110 may be a silicon wafer. The first material layer 120 may be formed as an insulating (e.g., electrically insulating) layer comprising a material such as silicon oxide.

[0117] The first material layer 120 may be used to suppress deformation or damage to the mask pattern layer 130 stacked on the first material layer 120 (or to reduce the degree or incidence of deformation or damage) during the process of manufacturing the deposition mask. In one or more embodiments, the first material layer 120 may be stacked together with the mask pattern layer 130 on the substrate layer 110 to counteract the tensile stress of the mask pattern layer 130.

[0118] Next, at least one first groove 120H may be formed in the surface 120a of the first material layer 120. The first groove 120H may be formed or arranged to correspond to the number, position, and size of the bond regions KA in which the bond pattern portions KA-P, which will be described in more detail herein, are arranged. In one or more embodiments, the dimensions of the first groove 120H in the plane may correspond to those of the manufacturing apparatus 1 of the display device (see [link to equipment]). Figure 1 The visual field of the visual part corresponds to the field of vision of the VS.

[0119] In one or more embodiments, such as Figure 6 As shown, the first photoresist 210 can be stacked on the first material layer 120 and exposed using a photomask. A development process can then be performed to form a first pattern 211 corresponding to the first trench 120H in the first photoresist 210. Next, as... Figure 7 As shown, the surface 120a of the first material layer 120 can be patterned using a first pattern 211 of the first photoresist 210 to form a first trench 120H. In one or more embodiments, the first material layer 120 can be patterned using a dry etching process such as reactive ion etching (RIE).

[0120] Since the first groove 120H is in the first material layer 120, the thickness of the portion of the first material layer 120 arranged in the bond region KA can be less than the thickness of the portion of the first material layer 120 arranged in the cell region CA.

[0121] The depth t2 of the first trench 120H can have a value selected in the range of approximately 30% to approximately 80% of the thickness t1 of the portion of the first material layer 120 in the bond region KA before the formation of the first trench 120H, and for example, can have a value selected in the range of approximately 50% to approximately 80% of the thickness t1. In one or more embodiments, the depth t2 of the first trench 120H can have a value in the range of approximately 30% to approximately 80% of the thickness t1 of the first material layer 120. The width w6 of the first trench 120H can be substantially equal to the width w3 of the bond region KA (see...). Figure 5 ), and can be greater than the width w4 of the key pattern portion KA-P (see Figure 5 In one or more embodiments, the width w6 of the first groove 120H may be equal to or less than the width w4 of the key pattern portion KA-P (see...). Figure 5 Twice as much as 1.

[0122] like Figure 7 As shown, if (for example, when) the first trench 120H is fully (e.g., substantially fully) formed, the first photoresist 210 can be removed from the surface 120a of the first material layer 120. The removal of the first photoresist 210 can be performed by a dry process or a wet process.

[0123] Next, as Figure 8 As shown, the mask pattern layer 130 can be formed on the first material layer 120 in which the first trench 120H is formed. For example, the mask pattern layer 130 can be formed as an insulating (e.g., electrically insulating) layer comprising a material such as silicon nitride. For example, the mask pattern layer 130 can have a thickness in the range of about 0.5 μm to about 2 μm (e.g., about 1 μm to about 2 μm).

[0124] The second groove 130H can be in the surface 130a of the mask pattern layer 130, so as to be lowered inward through the first groove 120H in the direction from the surface 130a of the mask pattern layer 130 toward the substrate layer 110.

[0125] In the accompanying drawings, the first material layer 120 and the mask pattern layer 130 are stacked on opposite surfaces of the substrate layer 110, but the first material layer 120 and the mask pattern layer 130 may be stacked on only a single surface of the substrate layer 110.

[0126] Next, as Figure 9As shown, the unit pattern portion CA-P and the bond pattern portion KA-P may be in the surface 130a of the mask pattern layer 130. In one or more embodiments, the surface 130a of the mask pattern layer 130 may be patterned to form a bond pattern portion KA-P overlapping at least one first groove 120H and a unit pattern portion CA-P spaced apart from the bond pattern portion KA-P.

[0127] The unit pattern portion CA-P may overlap with the unit region CA, and the bond pattern portion KA-P may overlap with the bond region KA. In one or more embodiments, the bond pattern portion KA-P may be spaced (or separated) from the center of the mask pattern layer 130 more than the unit pattern portion CA-P may be spaced from the center of the mask pattern layer 130.

[0128] For example, the unit pattern portion CA-P and the bond pattern portion KA-P can be formed by photolithography and dry etching processes, but the embodiments of this disclosure are not limited thereto, and one or more suitable patterning methods such as laser lithography can be used.

[0129] The first virtual line L1 passing through the center of the unit pattern portion CA-P can be substantially parallel to the second virtual line L2 passing through the center of the bond pattern portion KA-P. In this document, both the first virtual line L1 and the second virtual line L2 (e.g., simultaneously) can be lines substantially parallel to the substrate layer 110 and can extend substantially parallel to each other without overlapping or intersecting.

[0130] The second virtual line L2 can be arranged to be adjacent (e.g., closer) to the substrate layer 110 than the first virtual line L1. For example, the center of the bond pattern portion KA-P can be arranged to be adjacent (e.g., closer) to the substrate layer 110 than the center of the unit pattern portion CA-P.

[0131] Next, a first opening OP1 and a second opening OP2 can be formed through the substrate layer 110. The first opening OP1 can be formed or arranged to overlap with the cell region CA (or the cell pattern portion CA-P), and the second opening OP2 can be formed or arranged to overlap with the bond region KA (or the bond pattern portion KA-P). In one or more embodiments, the first opening OP1 and the second opening OP2 can each be formed such that the upper width is smaller than the lower width.

[0132] In one or more embodiments, such as Figure 10As shown, the second photoresist 220 can be stacked on the opposite surface of the mask pattern layer 130 to the surface 130a, and the second pattern 221 corresponding to the first opening OP1 and the third pattern 222 corresponding to the second opening OP2 can be formed using a photomask through the second photoresist 220. This embodiment illustrates an example in which the first material layer 120 and the mask pattern layer 130 are stacked on opposite surfaces of the substrate layer 110, and correspondingly, the second photoresist 220 can be stacked on the other surface of the mask pattern layer 130.

[0133] Next, as Figure 11 As shown, the substrate 110 can be patterned using the second pattern 221 and the third pattern 222 of the second photoresist 220 to form the first opening OP1 and the second opening OP2. The substrate 110 can be etched using a deep reactive ion etching (DRIE) process. At this time, the first material layer 120 stacked on the unit pattern portion CA-P and the bond pattern portion KA-P can act as a stop layer for the etching process. If (e.g., when) the first opening OP1 and the second opening OP2 are fully (e.g., substantially fully) formed, the second photoresist 220 can be removed.

[0134] Next, return to the reference. Figure 3 The portion of the first material layer 120 stacked on the unit pattern portion CA-P and the bond pattern portion KA-P can be removed to complete the production of the deposition mask MA. In one or more embodiments, the portions of the first material layer 120 between the unit pattern portion CA-P and the first opening OP1, and between the bond pattern portion KA-P and the second opening OP2, can be removed. The first material layer 120 can be removed by a wet process. In this case, the thickness of the portion of the first material layer 120 remaining between the second opening OP2 and the bond pattern portion KA-P can be less than the thickness of the portion of the first material layer 120 remaining between the first opening OP1 and the unit pattern portion CA-P. Therefore, the portion of the first material layer 120 between the second opening OP2 and the bond pattern portion KA-P can be removed first.

[0135] Accordingly, in the deposition mask MA according to one or more embodiments, the portion of the first material layer 120 in the bond region KA can be completely (e.g., substantially completely) removed, and the bond pattern portion KA-P can be used to perform precise alignment without being interrupted by the first material layer 120. The wet process time for removing the portion of the first material layer 120 in the bond region KA can be shortened, and the phenomenon of damage to the cell pattern portion CA-P due to the increased time required to perform the wet process can be suppressed or reduced.

[0136] Figure 12It is a schematic perspective view of a display device according to one or more embodiments.

[0137] refer to Figure 12 The display device 2 may include a display area DA and a peripheral area PA surrounding the display area DA (e.g., around the display area DA). The display area DA may be a portion of the image being displayed, and multiple pixels PX (see...) Figure 14 The display area DA can be arranged in the display area DA. The display area DA can have one or more suitable shapes such as a circle (e.g., essentially a circle), an ellipse (e.g., essentially an ellipse), a polygon (e.g., essentially a polygon), or a shape of a particular graphic.

[0138] Each pixel PX of the display device 2 can be an area that emits light of a specific (e.g., set or predetermined) color, and the display device 2 can be used to provide an image using light emitted from each of the pixels PX. Each pixel PX can be used to emit, for example, red light, green light, blue light, or white light. Each of the pixels PX can represent a subpixel and can include a display element and pixel circuitry connected to the display element. The display element can include an organic light-emitting diode (e.g., a quantum dot organic light-emitting diode).

[0139] Multiple pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 can be defined as directions that intersect each other.

[0140] The peripheral region PA can be completely surrounding the display region DA (e.g., completely surrounding the display region DA). The peripheral region PA can be a type (or class) of non-display area where no pixels are arranged, and drivers or wires for applying electrical signals or power to pixels PX can be arranged in the peripheral region PA.

[0141] like Figure 12 As shown, the display device 2 may have a rectangular shape (e.g., a substantially rectangular shape) with a horizontal length greater than its vertical length, but embodiments of this disclosure are not limited thereto. The display device 2 may have one or more suitable shapes such as polygons (e.g., substantially polygons), circles (e.g., substantially circles), or ellipses (e.g., substantially ellipses).

[0142] In the following description, the organic light-emitting display device will be shown in more detail as an example of display device 2 according to one or more embodiments, but the display device is not limited thereto. In one or more embodiments, other types (or kinds) of display devices, such as quantum dot light-emitting displays, may be utilized.

[0143] Figure 13 This is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 13It can be along Figure 12 A cross-sectional view taken from line A-A'.

[0144] refer to Figure 13 The display device 2 may include a display panel 20, an input sensing layer 40 on the display panel 20, and an optical functional layer 50, and these components may be covered by a window 60. The display device 2 may be one or more suitable types (or categories) of electronic devices such as mobile phones, laptop computers, and smartwatches.

[0145] Display panel 20 can be used to display images. Display panel 20 may include pixels in display area DA. Each pixel may include a display element and pixel circuitry connected to the display element. The display element may include an organic light-emitting diode (e.g., a quantum dot organic light-emitting diode).

[0146] The input sensing layer 40 can be used to obtain coordinate information based on external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 20. The input sensing layer 40 can be used to sense external input via mutual capacitance and / or self-capacitance methods.

[0147] The input sensing layer 40 can be directly on the display panel 20, or it can be formed separately and then bonded by an adhesive layer such as an optically transparent (e.g., substantially transparent) adhesive. For example, the input sensing layer 40 can be formed continuously after the process of forming the display panel 20. In this case, the input sensing layer 40 can be understood as part of the display panel 20, and the adhesive layer may not be disposed between the input sensing layer 40 and the display panel 20. Although Figure 13 For example, the input sensing layer 40 is arranged between the display panel 20 and the optical functional layer 50, but in one or more embodiments, the input sensing layer 40 may be arranged above the optical functional layer 50.

[0148] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer can be used to reduce the reflectivity of light (e.g., external light) incident from the outside toward the display panel 20 through the window 60. In one or more embodiments, the anti-reflective layer may include a black matrix and color filters. The color filters may be arranged to take into account the color of light emitted from each pixel of the display panel 20.

[0149] In one or more embodiments, the antireflective layer may include a phase retarder and a polarizer. The phase retarder may have a film type (or variety) or a liquid crystal coating type (or variety). The polarizer may also have a film type (or variety) or a liquid crystal coating type (or variety). The film type (or variety) may include a stretched synthetic resin film, and the liquid crystal coating type (or variety) may include liquid crystals arranged in a specific (e.g., set or predetermined) manner. The phase retarder and polarizer may further include a protective film. The phase retarder and polarizer or protective film may be defined as the base layer of the antireflective layer.

[0150] In one or more embodiments, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer on different layers. First reflected light and second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can be used to destructively interfere with each other, and thus, the reflectivity of external light can be reduced.

[0151] In one or more embodiments, the optical functional layer 50 may be formed sequentially after the processes for forming the display panel 20 and / or the input sensing layer 40. In this case, the adhesive layer may not be disposed between the optical functional layer 50, the display panel 20, and / or the input sensing layer 40.

[0152] In one or more embodiments, a layer comprising an optically transparent (e.g., substantially transparent) adhesive or an optically transparent (e.g., substantially transparent) resin may be included between the window 60 and the optical functional layer 50.

[0153] Figure 14 This is a diagram of the equivalent circuit of a pixel in a display device according to one or more embodiments.

[0154] refer to Figure 14 A pixel PX may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel PX may be used to emit, for example, red, green, or blue light, or red, green, blue, or white light through the OLED.

[0155] The second thin-film transistor T2 can be a switching thin-film transistor that can be connected to the scan line SL and the data line DL, and can be used to transmit the data signal Dm input from the data line DL to the first thin-film transistor T1 based on the switching signal Sn input from the scan line SL. The storage capacitor Cst can be connected to the second thin-film transistor T2 and the drive voltage line PL, and can be used to store a voltage corresponding to the difference between the voltage transmitted from the second thin-film transistor T2 and the drive voltage ELVDD applied to the drive voltage line PL.

[0156] The first thin-film transistor T1 can be a driving thin-film transistor that can be connected to a driving voltage line PL and a storage capacitor Cst, and can be used to control the driving current flowing from the driving voltage line PL into the organic light-emitting diode (OLED) according to the voltage value stored in the storage capacitor Cst. The OLED can be used to emit light with a specific (e.g., set or predetermined) brightness according to the driving current. The counter electrode (e.g., cathode) of the OLED can be used to receive a common voltage ELVSS.

[0157] Figure 14 The example shown is a pixel circuit PC comprising two thin-film transistors and one storage capacitor, but embodiments of this disclosure are not limited thereto. The number of thin-film transistors and the number of storage capacitors can vary depending on the design of the pixel circuit PC. For example, in addition to the two thin-film transistors as described in one or more embodiments, the pixel circuit PC may include four, five, or more thin-film transistors.

[0158] Figure 15 It is a schematic cross-sectional view of a display panel according to one or more embodiments.

[0159] refer to Figure 15 The display panel 20 may include a substrate 301, thin-film transistors (TRs) (e.g., multiple thin-film transistors TRs) on the substrate 301, and display elements LDs on the thin-film transistors TRs. Figure 15 The thin-film transistor TR and display element LD shown can be respectively connected to, for example, the thin-film transistor TR and the display element LD. Figure 14 The first thin-film transistor T1 shown corresponds to an organic light-emitting diode (OLED). The display panel 20 may include an organic light-emitting diode as a display element (LD), but the embodiments disclosed herein are not limited thereto.

[0160] The substrate 301 may include a glass material and / or a polymer resin. In one or more embodiments, the substrate 301 may have a multilayer structure in which a first layer of polymer resin and a second layer that inhibits the penetration of external foreign substances (or reduces the degree or occurrence of external foreign substance penetration) are cross-stacked.

[0161] The first layer may include polymeric resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and / or cellulose acetate propionate (CAP).

[0162] The second layer may include inorganic materials, such as silicon nitride (e.g., SiN). xWhere 0 < x ≤ 2; for example, Si3N4) and / or silicon oxide (for example, SiO2), where 0 < x ≤ 2. x , where 0 < x ≤ 2; for example, SiO2).

[0163] A buffer layer 302 may be present on the substrate 301 to suppress impurities from penetrating into the semiconductor layer AP of the thin-film transistor TR (or to reduce the extent or rate of impurity penetration into the semiconductor layer AP of the thin-film transistor TR). The buffer layer 302 may comprise an inorganic insulating (e.g., electrically insulating) material, such as silicon nitride (e.g., SiN). x Where 0 < x ≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO2), where 0 < x ≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO2). x N y Where 0 < x ≤ 2 and 0 < y ≤ 2; for example, SiON or Si2N2O) and silicon dioxide (for example, SiO2). x , where 0 < x ≤ 2; for example SiO2), and can have a single-layer structure or a multi-layer structure including the inorganic insulating material.

[0164] The thin-film transistor TR can be disposed on the buffer layer 302. The thin-film transistor TR may include a semiconductor layer AP, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0165] The semiconductor layer AP may include a source region S, a drain region D, and a channel region C between the source region S and the drain region D. The semiconductor layer AP may include polycrystalline silicon. In one or more embodiments, the semiconductor layer AP may include amorphous (e.g., non-crystalline) silicon, oxide semiconductors, and / or organic semiconductors. The gate electrode GE may include a low-resistance (e.g., low-impedance) metallic material. The gate electrode GE may include a conductive (e.g., electrically conductive) material, including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or monolayer structure including such material.

[0166] The gate insulating layer 303 between the semiconductor layer AP and the gate electrode GE may include an inorganic insulating (e.g., electrically insulating) material, such as silicon oxide (e.g., SiO2). x Where 0 < x ≤ 2; for example, SiO2), silicon nitride (for example, SiN). x Where 0 < x ≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO2), where 0 < x ≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO2). x N y Where 0 < x ≤ 2 and 0 < y ≤ 2; for example, SiON or Si2N2O), aluminum oxide (for example, AlO) x Where 0 < x ≤ 2; for example, Al2O3), titanium dioxide (for example, TiO2), where 0 < x ≤ 2; for example, Al2O3, titanium dioxide (for example, TiO2). x, wherein 0 < x≤2; for example, TiO2), tantalum oxide (for example, TaO x , wherein 0 < x≤ 3; for example, Ta2O5) and hafnium oxide (for example, HfO x , wherein 0 < x≤ 2; for example, HfO2). The gate insulating layer 303 may have a single-layer structure or a multilayer structure comprising the material.

[0167] The interlayer insulating layer 305 may be disposed on the gate electrode GE. The interlayer insulating layer 305 may comprise an inorganic insulating (for example, electrically insulating) material, such as silicon oxide (for example, SiO x , wherein 0 < x≤ 2; for example, SiO2), silicon nitride (for example, SiN x , wherein 0 < x≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO x N y , wherein 0 < x ≤ 2 and 0 < y ≤ 2; for example, SiON or Si2N2O), aluminum oxide (for example, AlO x , wherein 0 < x≤ 2; for example, Al2O3), titanium oxide (for example, TiO x , wherein 0 < x≤2; for example, TiO2), tantalum oxide (for example, TaO x , wherein 0 < x≤ 3; for example, Ta2O5) and hafnium oxide (for example, HfO x , wherein 0 < x≤ 2; for example, HfO2). The interlayer insulating layer 305 may have a single-layer structure or a multilayer structure comprising the material.

[0168] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer 305. The source electrode SE and the drain electrode DE may comprise a material with good or suitable conductivity (for example, electrical conductivity). The source electrode SE and the drain electrode DE may comprise a conductive (for example, electrically conductive) material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer structure or a single-layer structure comprising the material. In one or more embodiments, the source electrode SE and the drain electrode DE may have a multilayer structure of Ti / Al / Ti.

[0169] Planarization layer 307 may be present on the source electrode SE and drain electrode DE. Planarization layer 307 may include an organic insulating (e.g., electrically insulating) layer, such as a general polymer like polymethyl methacrylate (PMMA) and / or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof (e.g., any suitable). In one or more embodiments, planarization layer 307 may include polyimide. Planarization layer 307 may be used to eliminate steps caused by the thin-film transistor TR. The surface of planarization layer 307 opposite to the display element LD may be a flat (e.g., substantially flat) surface.

[0170] A display element LD electrically connected to a thin-film transistor TR can be on a planarization layer 307. The display element LD may include pixel electrodes E1 (e.g., multiple pixel electrodes E1), intermediate layers EL (e.g., multiple intermediate layers EL), and counter electrodes E2, which are sequentially stacked on the planarization layer 307.

[0171] Pixel electrode E1 may be located on planarization layer 307. Pixel electrode E1 may be electrically connected to the drain electrode DE of thin-film transistor TR through a contact hole formed through planarization layer 307. Pixel electrode E1 may comprise a conductive (e.g., electrically conductive) oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (e.g., ZnO). x Where 0 < x ≤ 2; for example, ZnO or ZnO2), indium oxide (for example, InO) x Where 0 < x ≤ 2; for example, In₂O₃), indium gallium oxide (IGO), and / or zinc aluminum oxide (AZO). In one or more embodiments, the pixel electrode E1 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In one or more embodiments, the pixel electrode E1 may further include a film comprising ITO, IZO, ZnO, and / or In₂O₃ and located above and / or below the reflective film.

[0172] A pixel defining layer 309 may be present on the pixel electrode E1. The pixel defining layer 309 may have an opening corresponding to a pixel, for example, an opening that defines an emission region by exposing at least a central portion of the pixel electrode E1. When viewed from a direction perpendicular to (e.g., substantially perpendicular to) the substrate 301 (e.g., the DR3 direction), the pixel defining layer 309 may overlap with the edge of the pixel electrode E1. The pixel defining layer 309 may comprise an inorganic insulating (e.g., electrically insulating) material, such as silicon nitride (e.g., SiN). x, wherein 0 < x ≤ 2; for example, Si3N4), silicon oxynitride (for example, SiO x N y , wherein 0 < x ≤ 2 and 0 < y ≤ 2; for example, SiON or Si2N2O) and / or silicon oxide (for example, SiO x , wherein 0 < x ≤ 2; for example, SiO2). The pixel electrode E1 can be used as an anode electrode.

[0173] The intermediate layer EL can include low-molecular-weight materials and / or high-molecular-weight materials. If (for example, when) the intermediate layer EL includes low-molecular-weight materials, the intermediate layer EL can have a single-layer structure or a multi-layer stacked structure including a hole injection layer, a hole transport layer, an emission layer, an electron transport layer and an electron injection layer, and can include one or more suitable organic materials, including copper phthalocyanine (CuPc), N,N'-di(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB) and / or tris(8-hydroxyquinolinato)aluminum (Alq3). These layers can be formed by vacuum deposition.

[0174] If (for example, when) the intermediate layer EL includes high-molecular-weight materials, the intermediate layer EL can have a structure including a hole transport layer (HTL) and an emission layer (EML). In this case, the hole transport layer can include poly(3,4-ethylenedioxythiophene) (PEDOT), and the emission layer can include high-molecular-weight materials such as polyphenylene vinylene (PPV) and / or polyfluorene. The structure of the intermediate layer EL is not limited to the structure described herein, and can have one or more suitable structures. For example, at least one layer selected from the layers forming the intermediate layer EL can be integrally formed across a plurality of pixel electrodes E1. In one or more embodiments, the intermediate layer EL can include layers patterned to correspond to each of the plurality of pixel electrodes E1.

[0175] The counter electrode E2 can be used as a cathode electrode. The counter electrode E2 can be a transparent (for example, substantially transparent) electrode or a reflective electrode. In one or more embodiments, the counter electrode E2 can be a transparent electrode or a semi-transparent electrode, and can be a thin metal film with low work function including Li, Ca, Al, Ag, Mg and compounds thereof (for example, LiF) or materials with a multi-layer structure such as LiF / Ca or LiF / Al. The counter electrode E2 can be arranged across a plurality of pixels, and can be a common electrode of the display panel 20.

[0176] Pixel electrode E1, intermediate layer EL, and counter electrode E2 can form a display element LD. The display element LD can be used to emit light based on a drive current transmitted from a thin-film transistor TR. In one or more embodiments, at least one selected from the thin-film transistor TR, pixel electrode E1, intermediate layer EL, and counter electrode E2 can be formed using the deposition mask MA described in one or more embodiments.

[0177] The display device 2 according to one or more embodiments can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments may include the display device 2 as described in one or more embodiments, and may further include modules or devices with additional functions in addition to the display device 2.

[0178] Figure 16 It is a block diagram of an electronic device according to one or more embodiments.

[0179] refer to Figure 16 The electronic device 10 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0180] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0181] The memory 13 can be used to store data information expected or required for the operation of the processor 12 or the display module 11. If (for example, when) the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can be used to process the received signals and output image information through the display screen.

[0182] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power desired or required for the operation of the electronic device 10.

[0183] At least one of the components selected from electronic device 10 may be in the display device according to one or more embodiments. One or more independent modules that are functionally part of a single module may be in the display device, and other modules may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as other devices within electronic device 10 besides the display device.

[0184] Figure 17This is a set of schematic diagrams of an electronic device according to one or more embodiments.

[0185] refer to Figure 17 One or more suitable electronic devices that apply a display device according to one or more embodiments may include image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d and desktop monitors 10_1e, wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c, and vehicle electronic devices 10_3 including display modules such as dashboards, central instrument panels, central information displays (CIDs) arranged on dashboards and interior mirror displays of automobiles.

[0186] According to one or more embodiments, the recognition rate of the key pattern used for alignment with the substrate to be deposited on the deposition mask can be improved or increased, and the alignment of the deposition mask can be performed more accurately.

[0187] According to one or more embodiments, the durability and manufacturing efficiency of the deposition mask can be improved or enhanced.

[0188] According to one or more embodiments, the improved recognition rate of the bond pattern not only facilitates more accurate alignment between the deposition mask and the substrate, but also helps reduce alignment errors during high-resolution deposition processes. This accuracy reduces material waste and improves or enhances the layer uniformity desired in advanced electronics. Furthermore, the improved or enhanced durability of the deposition mask, achieved through designed material selection and structural design, extends its lifespan across two or more manufacturing cycles. Combined with streamlined manufacturing processes such as efficient or suitable trench formation and selective material removal, these advancements result in greater throughput and cost-effectiveness in production environments, thereby supporting scalable manufacturing of next-generation display technologies.

[0189] The light-emitting device, display device, display apparatus, electronic device, electronic device, apparatus for manufacturing substantially these devices and apparatus, and / or any other related devices or components according to one or more embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware (e.g., any suitable). For example, one or more components of the device may be provided on an integrated circuit (IC) chip or formed on separate IC chips. Further, one or more components of the device may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), and / or a printed circuit board (PCB), or provided on a substrate. Further, one or more components of the device may be a process or thread that runs on one or more processors in one or more computing devices, executes computer program instructions, and interacts with other system components to perform one or more functions described herein. The computer program instructions may be stored in memory, which may be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored on other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of multiple computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of this disclosure.

[0190] Although the subject matter of this disclosure has been described in conjunction with specific embodiments, it should be understood that the subject matter of this disclosure is not limited to the disclosed embodiments, but rather, this disclosure is intended to cover one or more suitable modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A deposition mask, comprising: The base layer has a first opening and a second opening, the first opening and the second opening having different widths; as well as A mask pattern layer, on the substrate layer, comprising: The unit pattern portion overlaps with the first opening; and The key pattern portion overlaps with the second opening. The first virtual line, which is parallel to the base layer and passes through the center of the unit pattern portion, is parallel to the second virtual line, which is parallel to the base layer and passes through the center of the key pattern portion.

2. The deposition mask of claim 1, wherein the second virtual line is closer to the substrate layer than the first virtual line.

3. The deposition mask according to claim 1, wherein the mask pattern layer comprises silicon nitride.

4. The deposition mask according to claim 1, wherein the thickness of the mask pattern layer is in the range of 0.5 μm to 2 μm.

5. The deposition mask of claim 1, wherein the bond pattern portion is spaced further from the center of the mask pattern layer than the cell pattern portion is spaced further from the center of the mask pattern layer.

6. The deposition mask of claim 1, wherein the first opening and the second opening are each arranged such that the width on one side is smaller than the width on the other side.

7. A method for manufacturing a deposition mask, comprising: A first material layer is formed on the substrate layer; At least one groove is formed in the surface of the first material layer; A mask pattern layer is formed on the first material layer; The surface of the mask pattern layer is patterned to form a key pattern portion that overlaps with the at least one slot and a unit pattern portion that is spaced apart from the key pattern portion; A first opening that overlaps with the unit pattern portion and a second opening that overlaps with the bond pattern portion are formed in the base layer; as well as Remove the portions of the first material layer between the unit pattern portion and the first opening, and between the key pattern portion and the second opening.

8. The method of claim 7, wherein the width of the at least one slot is greater than the width of the key pattern portion.

9. The method of claim 8, wherein the width of the at least one slot is equal to or less than twice the width of the key pattern portion.

10. The method of claim 7, wherein the depth of the at least one groove has a value in the range of 30% to 80% of the thickness of the first material layer.

11. The method of claim 7, wherein a first virtual line parallel to the substrate and passing through the center of the unit pattern portion is parallel to a second virtual line parallel to the substrate and passing through the center of the key pattern portion.

12. The method of claim 11, wherein the second virtual line is closer to the substrate layer than the first virtual line.

13. The method of claim 7, wherein the mask pattern layer comprises silicon nitride.

14. The method of claim 7, wherein the thickness of the mask pattern layer is in the range of 0.5 μm to 2 μm.

15. The method of claim 7, wherein the key pattern portion is spaced further from the center of the mask pattern layer than the unit pattern portion is spaced further from the center of the mask pattern layer.

16. The method of claim 7, wherein the first opening and the second opening are each formed such that the upper width is smaller than the lower width.

17. The method of claim 7, wherein the first material layer comprises silicon oxide.

18. The method of claim 7, wherein the thickness of the unit pattern portion is equal to the thickness of the key pattern portion.

19. The method of claim 7, wherein the width of the key pattern portion is smaller than the width of the unit pattern portion.

20. An electronic device comprising: substrate; Multiple thin-film transistors are disposed on the substrate; Multiple pixel electrodes are electrically connected to the multiple thin-film transistors, respectively; Multiple intermediate layers are respectively disposed on the multiple pixel electrodes; as well as For the electrodes, on the plurality of intermediate layers, At least one of the plurality of thin-film transistors, the plurality of pixel electrodes, the plurality of intermediate layers and the counter electrode is formed using a deposition mask according to any one of claims 1 to 6.

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