A vertical hall device structure and a method of manufacturing the same

Abstract

The application discloses a vertical Hall device structure and a manufacturing method thereof. The vertical Hall device structure comprises a substrate, a buried layer and a first well region which are arranged in layers; the substrate is arranged as a second conductive type, and the buried layer and the first well region are both arranged as a first conductive type; the second conductive type is different from the first conductive type; the vertical Hall device structure further comprises a first epitaxial layer which is located between the buried layer and the first well region; the first epitaxial layer is arranged as the first conductive type; and the ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer. The embodiment of the application can improve the linearity of the vertical Hall device, and improve the measurement accuracy and stability of the vertical Hall device.

Description

Technical Field

[0001] This invention relates to the field of microelectronic magnetic field sensing technology, and in particular to a vertical Hall device structure and its manufacturing method. Background Technology

[0002] A Hall sensor is a magnetoelectric conversion device with a Hall element as its core sensing unit. It converts magnetic field strength into an electrical signal based on the Hall effect. Hall sensors offer advantages such as non-contact measurement, no mechanical wear, monolithic integration on a standard complementary metal-oxide-semiconductor (CMOS) chip, wide magnetic field range, and strong environmental adaptability. They are widely used in automotive electronics, industrial control, and consumer electronics.

[0003] Hall sensors include horizontal Hall devices and vertical Hall devices. Among them, vertical Hall devices are prone to nonlinearity due to factors such as geometric asymmetry, uneven doping distribution in the active region, and trench isolation etching deviations, which can significantly affect the accuracy of subsequent magnetic field measurements. Summary of the Invention

[0004] This invention provides a vertical Hall effect device structure and its manufacturing method to improve the linearity of the vertical Hall effect device and enhance its measurement accuracy and stability.

[0005] According to one aspect of the present invention, a vertical Hall device structure is provided, comprising: a substrate, a buried layer, and a first well region stacked thereon; The substrate is configured with a second conductivity type, and the buried layer and the first well region are both configured with a first conductivity type; the second conductivity type is different from the first conductivity type. It also includes: a first epitaxial layer located between the buried layer and the first well region; the first epitaxial layer is configured with the first conductivity type; The ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer.

[0006] Optionally, the ion concentration of the first epitaxial layer is less than the ion concentration of the first well region, and the ion concentration of the first well region is less than the ion concentration of the buried layer.

[0007] Optionally, the first conductivity type is N-type, and the first epitaxial layer is an N-type lightly doped region.

[0008] Optionally, the vertical Hall device structure further includes: a plurality of second well regions; Multiple second well regions are located on the side surface of the first well region away from the first epitaxial layer, embedded in the first well region, and the multiple second well regions are arranged at intervals. The second well region is configured with the first conductivity type, and the ion concentration in the second well region is greater than the ion concentration in the first well region.

[0009] Optionally, the vertical Hall device structure further includes: A field oxide layer is located on the surface of the first well region away from the first epitaxial layer; A dielectric layer is located on the side of the field oxide layer away from the first well region; the dielectric layer is provided with through contact holes; The metal electrode layer is in contact with the corresponding second well region through the contact hole; A passivation layer is located on the side of the metal electrode layer away from the dielectric layer.

[0010] According to another aspect of the present invention, a method for manufacturing a vertical Hall device is provided, comprising: A substrate is provided; the substrate is configured with a second conductivity type; Ion implantation is performed on the surface of the substrate to form a buried layer; the buried layer is configured with a first conductivity type, and the second conductivity type is different from the first conductivity type. A first epitaxial layer is formed on the surface of the buried layer away from the substrate; the first epitaxial layer is configured with the first conductivity type; Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form a first well region; the first well region is configured with the first conductivity type; wherein the ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer.

[0011] Optionally, the step of ion implantation on the surface of the substrate to form a buried layer includes: Ion implantation is performed on the surface of the substrate to form the buried layer with a first ion concentration; The formation of a first epitaxial layer on the surface of the buried layer away from the substrate includes: A first epitaxial layer with a second ion concentration is formed on the surface of the buried layer on the side away from the substrate; The step of performing ion implantation on the surface of the first epitaxial layer away from the buried layer to form a first well region includes: Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form the first well region with a third ion concentration; Wherein, the concentration of the second ion is less than the concentration of the first ion, and the concentration of the first ion is less than the concentration of the third ion.

[0012] Optionally, the first conductivity type is N-type, and the formation of the first epitaxial layer on the surface of the buried layer away from the substrate includes: An N-type lightly doped region is formed on the surface of the buried layer away from the substrate.

[0013] Optionally, the method for manufacturing the vertical Hall device further includes: Ion implantation is performed on the surface of the first well region away from the first epitaxial layer to form a plurality of second well regions; the plurality of second well regions are embedded in the first well region and are arranged at intervals; the second well regions are configured with the first conductivity type, and the ion concentration of the second well regions is greater than the ion concentration of the first well region.

[0014] Optionally, the method for manufacturing the vertical Hall device further includes: A field oxide layer is formed on the surface of the first well region away from the first epitaxial layer; A dielectric layer is formed on the side of the field oxide layer away from the first well region; A through-hole is provided in the dielectric layer, and a metal electrode layer is formed on the side of the dielectric layer away from the field oxide layer, so that the metal electrode layer is in contact with the corresponding second well region; A passivation layer is formed on the side of the metal electrode layer away from the dielectric layer.

[0015] The vertical Hall device structure provided in this invention adds a first epitaxial layer between the buried layer and the first well region in the vertical Hall device, and the ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer. The addition of the first epitaxial layer with the corresponding ion concentration creates a weak connection between the buried layer and the first epitaxial layer. When a high voltage is applied to the buried layer of the vertical Hall device, the voltage on the side of the first well region near the buried layer can be increased through the first epitaxial layer, thereby increasing the carrier concentration and making the carrier distribution in the first well region more uniform. This improves the linearity of the vertical Hall device and ensures the accuracy and stability of the magnetic field measurement of the device.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a cross-sectional structure of a vertical Hall effect device provided by related technologies; Figure 2 This is a cross-sectional structural diagram of another vertical Hall effect device provided by related technologies; Figure 3 This is a cross-sectional structural diagram of a vertical Hall effect device structure provided in an embodiment of the present invention; Figure 4 This is a schematic flowchart of a manufacturing method for a vertical Hall effect device according to an embodiment of the present invention; Figures 5 to 7 yes Figure 4 A structural diagram corresponding to each relevant step in the process. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] As described in the background section, Hall sensors include horizontal Hall devices and vertical Hall devices. Among them, the vertical Hall devices provided by current related technologies include the following two structures: Figure 1 This is a schematic diagram of a cross-sectional structure of a vertical Hall effect device provided by related technologies. Figure 2 This is a cross-sectional structural diagram of another vertical Hall effect device provided by related technologies. See also... Figure 1 This illustrates the simplest vertical Hall effect device structure. The N-well layer 01 serves as the magnetic sensing layer for the vertical Hall effect device, and the P-epi epitaxial layer 02 is connected to the outer P-well layer (…). Figure 1(Not shown in the diagram) A P-ring is formed for lateral isolation, achieving grounding. See also Figure 2 It shows in Figure 1 Based on the existing structure, an N-type buried layer 03 was added. This is achieved through the outer Deep N-well layer (…). Figure 2 (Not shown in the image) and N-well layer 04 form an N-ring to isolate the P-type substrate 05, which is typically connected to a high voltage.

[0022] However, the linearity of a vertical Hall device is closely related to the uniformity of carrier distribution in the magnetically sensitive layer. Both of the aforementioned Hall device structures have inherent defects. Figure 1 In the Hall device structure, the reverse PN junction is formed only by the top N-well layer 01 and the bottom grounded P-epi epitaxial layer 02. The carrier transport channel is easily affected by substrate noise and process deviation, and the uniformity of longitudinal carrier distribution is limited by the doping process. Figure 2 Although the Hall device structure in China adds an N-type buried layer O3 with high voltage to shield the influence of substrate noise on the device, the uniformity of longitudinal carrier distribution of the device is still limited by the doping process.

[0023] Based on the above-mentioned technical problems, the embodiments of the present invention propose the following technical solutions: This invention provides a vertical Hall effect device structure. Figure 3 This is a cross-sectional structural diagram of a vertical Hall effect device structure provided in an embodiment of the present invention. Figure 3 As shown, the vertical Hall device structure includes a substrate 10, a buried layer 11, and a first well region 12 stacked together.

[0024] The substrate 10 is configured with the second conductivity type, while the buried layer 11 and the first well region 12 are both configured with the first conductivity type; the second conductivity type is different from the first conductivity type. The vertical Hall device structure further includes: a first epitaxial layer 13 located between the buried layer 11 and the first well region 12; the first epitaxial layer 13 is configured with a first conductivity type; The ion concentration of the first epitaxial layer 13 is different from the ion concentration of the first well region 12 and the ion concentration of the buried layer 11.

[0025] Specifically, the first well region 12 serves as the magnetic sensitive layer, i.e., the active region, of the vertical Hall device, and has a relatively deep ion implantation depth. The ion doping distribution of the first well region 12 exhibits a Gaussian distribution, meaning that the carrier concentration is high on the upper surface away from the substrate 10, gradually decreasing towards the substrate 10. Therefore, there is an uneven carrier distribution in the first well region 12 alone, resulting in high nonlinearity of the vertical Hall device and affecting its measurement accuracy and stability. A buried layer 11 of the first conductivity type is disposed on the surface of the substrate 10, which has a large ion concentration. This layer is used to reduce the transmission resistance and connect to high voltage, thereby effectively shielding the noise generated by the substrate 10 and reducing its impact on the vertical Hall device. Exemplarily, the main carriers of the first well region 12 of the vertical Hall device can be either electrons or holes. Specifically, when the first well region 12 is an N-type doped region, the carriers are electrons; when the first well region 12 is a P-type doped region, the carriers are holes. However, the hole mobility in silicon is much lower than the electron mobility. Therefore, to ensure the performance of the vertical Hall device, in this embodiment of the invention, the first conductivity type is N-type, that is, the first well region 12 is an N-type well region, for the description of the vertical Hall device. Thus, the substrate 10 is a P-type doped silicon substrate, the buried layer 11 is an N-type doped region, and the first epitaxial layer 13 is an N-type epitaxial layer. The working principle of the vertical Hall device is as follows: the deep N-well of the first well region 12 on the P-type silicon substrate 10 is used as the magnetic field-sensitive active region, with free electrons as the majority carriers. When the vertical Hall device is working, the P-type silicon substrate 10 forms a P-type ring-shaped doped region through the P-type doped region on the periphery to achieve lateral isolation and grounding. The buried layer 11 is connected to a high voltage, and the first well region 12 is connected to an intermediate potential. The applied bias voltage drives the free electrons in the active region of the first well region 12 to form a longitudinal current perpendicular to the device surface. When a parallel magnetic field in the plane acts on the active region, the moving electrons are deflected laterally by the Lorentz force, resulting in charge accumulation. This leads to the generation of a differential Hall voltage between the corresponding output electrodes, which is positively correlated with the magnetic induction intensity, thus realizing the detection of the in-plane magnetic field.

[0026] In this embodiment of the invention, to improve the non-uniform carrier distribution in the first well region 12 and ensure the accuracy of magnetic field detection, a first epitaxial layer 13 is added between the buried layer 11 and the first well region 12. The ion concentration of the first epitaxial layer 13 is different from the ion concentration of the first well region 12 and the ion concentration of the buried layer 11. Due to the significant difference in ion concentration between the first well region 12 and the buried layer 11, adding a first epitaxial layer 13 with a corresponding ion concentration allows for a weak connection between the buried layer 11 and the first epitaxial layer 13. When a high voltage is applied to the buried layer 11, the first epitaxial layer 13 can appropriately increase the voltage on the side of the first well region 12 closest to the buried layer 11, i.e., increase the carrier concentration, resulting in a uniform carrier distribution in the first well region 12. This improves the linearity of the vertical Hall device, thereby ensuring its measurement accuracy and stability.

[0027] The vertical Hall device structure provided in this embodiment of the invention adds a first epitaxial layer 13 between the buried layer 11 and the first well region 12 in the vertical Hall device, and the ion concentration of the first epitaxial layer 13 is different from the ion concentration of the first well region 12 and the ion concentration of the buried layer 11. The addition of the first epitaxial layer 13 with a corresponding ion concentration forms a weak connection between the buried layer 11 and the first epitaxial layer 13. When a high voltage is applied to the buried layer 11 of the vertical Hall device, the voltage on the side of the first well region 12 near the buried layer 11 can be increased through the first epitaxial layer 13, thereby increasing the carrier concentration and making the carrier distribution in the first well region 12 more uniform. This can improve the linearity of the vertical Hall device and ensure the accuracy and stability of the magnetic field measurement of the device.

[0028] Based on the above embodiments, see below. Figure 3 Optionally, the ion concentration of the first epitaxial layer 13 is less than the ion concentration of the first well region 12, and the ion concentration of the first well region 12 is less than the ion concentration of the buried layer 11.

[0029] Specifically, a first epitaxial layer 13 with a relatively low doped ion concentration is added between the buried layer 11 and the first well region 12. That is, the ion concentration of the buried layer 11 is greater than the ion concentration of the first well region 12, and the ion concentration of the first well region 12 is greater than the ion concentration of the first epitaxial layer 13. For example, if the first conductivity type is N-type, and the first epitaxial layer 13 is a lightly doped N-type region, then the first well region 12 is an N-type doped region, and the N-type doped ion concentration of the buried layer 11 is greater than the N-type doped ion concentration of the first well region 12. If the first epitaxial layer 13 is set with a large ion concentration, for example, if the ion concentration of the first epitaxial layer 13 is set to be the same as that of the first well region 12, then the first epitaxial layer 13 and the first well region 12 form an integral structure, which cannot play the role of increasing the carrier concentration of the first well region 12 near the buried layer 11; or, if the ion concentration of the first epitaxial layer 13 is set to be the same as or even greater than that of the buried layer 11, the first epitaxial layer 13 will be directly turned on when a high voltage is applied due to the excessively high ion concentration, which also cannot play the role of increasing the carrier concentration of the first well region 12 near the buried layer 11, and thus cannot improve the linearity of the vertical Hall device.

[0030] For example, based on the vertical Hall device structure provided in any of the above embodiments, Table 1 provides respective... Figure 1 , Figure 2 The test results of the nonlinearity of the vertical Hall device in the related technologies and the vertical Hall device provided in the embodiments of the present invention.

[0031] Table 1. Measured results of nonlinearity of vertical Hall effect devices As can be seen from Table 1, compared with the nonlinearity of the vertical Hall device provided in the related technology, the nonlinearity of the vertical Hall device provided in the embodiment of the present invention is significantly reduced, that is, the linearity is effectively improved, which is beneficial to improving the magnetic field measurement accuracy of the vertical Hall device.

[0032] Based on the above embodiments, see below. Figure 3 Optionally, the vertical Hall device structure also includes: a plurality of second well regions 14.

[0033] Multiple second well regions 14 are located on the side surface of the first well region 12 away from the first epitaxial layer 13, embedded in the first well region 12, and the multiple second well regions 14 are arranged at intervals. The second well region 14 is configured with a first conductivity type, and the ion concentration of the second well region 14 is greater than the ion concentration of the first well region 12.

[0034] Specifically, a plurality of second well regions 14 are disposed on the surface of the first well region 12 away from the first epitaxial layer 13. Each second well region 14 is a heavily doped region of a first conductivity type. For example, taking electrons as the charge carrier, the second well region 14 in this vertical Hall device is an N-type heavily doped region, meaning the ion concentration in the second well region 14 is greater than the ion concentration in the first well region 12, so that the second well region 14, as a contact electrode, has good conductivity. The plurality of second well regions 14 are arranged at intervals on the surface, serving as functional contact electrodes for transmitting different electrical signals. For example, the number of second well regions 14 can be determined by the user according to the actual application function of the vertical Hall device, and is not limited here. For example, for a horizontal Hall device, four second well regions 14 can be set, i.e., a 4-contact horizontal Hall device; for a vertical Hall device, three, five, six, or seven second well regions 14 can be set, i.e., three-contact vertical Hall devices, five-contact vertical Hall devices, six-contact vertical Hall devices, or seven-contact vertical Hall devices, respectively. Among them, the most commonly used in industry is the 5-contact vertical Hall device, and the 5-contact symmetrical vertical Hall device is also used as an example in the embodiments of this invention. Figure 3 The image also shows a vertical Hall effect device structure with five second well regions 14, which can be configured by... Figure 3 The electrodes, labeled from left to right, are contact electrodes C1, C2, C3, C4, and C5. Contact electrodes C1 and C5 serve as bias electrodes and are shorted together by a metal interconnect. Contact electrode C3 is the central common electrode. When the vertical Hall device is operating, a bias voltage is applied between the shorted outer contact electrodes C1 and C5 and the central common electrode C3, causing charge carriers to transport perpendicularly to the plane along the thickness direction of the first well region 12. Thus, under the influence of a magnetic field parallel to the surface, the vertical Hall device generates a Hall voltage, which is differentially output from contact electrodes C2 and C4.

[0035] Optionally, based on the above embodiments, the vertical Hall device structure further includes: A field oxide layer is located on the surface of the first well region away from the first epitaxial layer; A dielectric layer is located on the side of the field oxide layer away from the first well region; the dielectric layer is provided with through contact holes; The metal electrode layer is in contact with the corresponding second well region through contact holes; The passivation layer is located on the side of the metal electrode layer away from the dielectric layer.

[0036] Specifically, the field oxide layer can be fabricated using silicon dioxide. The dielectric layer serves to insulate the metal electrode layer from the semiconductor silicon material, and to insulate the multiple metal layers that may comprise the metal electrode layer. For example, the dielectric layer can be fabricated using silicon dioxide. The metal electrode layer may include a metal circuit layout for correspondingly connecting multiple second well regions that serve as contact electrodes. A passivation layer is disposed on the outermost layer for a vertical Hall device structure.

[0037] This invention also provides a method for manufacturing a vertical Hall effect device. Figure 4 This is a schematic flowchart of a manufacturing method for a vertical Hall effect device provided in an embodiment of the present invention. Figures 5 to 7 yes Figure 4 A structural diagram corresponding to each relevant step. See also... Figures 3 to 7 The manufacturing method of this vertical Hall device specifically includes the following steps: S110, Provide a substrate; the substrate is configured as a second conductivity type.

[0038] Specifically, see Figure 5 The substrate 10 is configured as the second conductivity type.

[0039] S120. Ion implantation is performed on the surface of the substrate to form a buried layer; the buried layer is set to a first conductivity type, and the second conductivity type is different from the first conductivity type.

[0040] Specifically, see Figure 6 Ion implantation is performed on the surface of substrate 10 to form a buried layer 11. The buried layer 11 is configured with a first conductivity type, and a second conductivity type is different from the first conductivity type. Ions of the first conductivity type are implanted into the surface of substrate 10 to a certain depth to form a buried layer 11 of the first conductivity type on the surface of substrate 10. For example, taking electrons as the charge carrier, the substrate 10 is a P-type silicon substrate, and the buried layer 11 is an N-type doped region.

[0041] S130, A first epitaxial layer is formed on the surface of the buried layer away from the substrate; the first epitaxial layer is configured with a first conductivity type.

[0042] Specifically, see Figure 7 A first epitaxial layer 13 is formed on the surface of the buried layer 11 away from the substrate 10; the first epitaxial layer 13 is configured with a first conductivity type. The first epitaxial layer 13 of the first conductivity type is epitaxially grown on the surface of the buried layer 11. For example, still taking electrons as the charge carrier, the first epitaxial layer 13 is an N-type epitaxial layer.

[0043] S140. Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form a first well region; the first well region is configured with a first conductivity type; wherein the ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer.

[0044] Specifically, see Figure 3 Ion implantation is performed on the surface of the first epitaxial layer 13 away from the buried layer 11 to form a first well region 12. The first well region 12 is configured with a first conductivity type. The ion concentration of the first epitaxial layer 13 is different from that of the first well region 12 and the buried layer 11. Ions of the first conductivity type are implanted to a relatively deep depth into the surface of the first epitaxial layer 13 to form a deep well region 12. The ion concentration of the first epitaxial layer 13 is different from that of the first well region 12 and the buried layer 11, and there is a significant difference between the ion concentration of the first well region 12 and the ion concentration of the buried layer 11. The carrier distribution in the first well region 12 exhibits a Gaussian distribution, and the carrier concentration is lower on the side closer to the buried layer 11. By epitaxially growing a first epitaxial layer 13 between the buried layer 11 and the first well region 12, the carrier concentration on the side of the first well region 12 closer to the buried layer 11 can be appropriately increased, so that the first well region 12 exhibits a uniform carrier distribution, improving the linearity of the vertical Hall device and ensuring the measurement accuracy and stability of the device.

[0045] The manufacturing method of the vertical Hall device structure provided in this embodiment of the invention involves epitaxially growing a first epitaxial layer 13 on the surface of a buried layer 11. The first epitaxial layer 13 has a first conductivity type, and the ion concentration of the first epitaxial layer 13 is different from the ion concentration of the first well region 12 and the ion concentration of the buried layer 11. The epitaxially grown first epitaxial layer 13 can form a weak connection with the buried layer 11. When a high voltage is applied, the first epitaxial layer 13 can increase the carrier concentration on the side of the first well region 12 near the buried layer 11, making the carrier distribution in the first well region 12 more uniform, thereby improving the linearity of the vertical Hall device and ensuring measurement accuracy and stability.

[0046] Based on the above embodiments, optionally, step S120 involves ion implantation on the surface of the substrate to form a buried layer, specifically including the following steps: Ion implantation is performed on the surface of the substrate to form a buried layer with a first ion concentration.

[0047] Step S130, forming a first epitaxial layer on the surface of the buried layer away from the substrate, specifically includes the following steps: A first epitaxial layer with a second ion concentration is formed on the surface of the buried layer on the side away from the substrate.

[0048] Step S140 involves ion implantation on the surface of the first epitaxial layer away from the buried layer to form a first well region, specifically including the following steps: Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form a first well region with a third ion concentration; wherein the second ion concentration is less than the first ion concentration, and the first ion concentration is less than the third ion concentration.

[0049] Specifically, a first epitaxial layer 13 with a relatively small second ion concentration is added between the buried layer 11 and the first well region 12. That is, the third ion concentration of the buried layer 11 is greater than the first ion concentration of the first well region 12, and the first ion concentration of the first well region 12 is greater than the second ion concentration of the first epitaxial layer 13. Thus, when the device is operating, a high voltage is applied to the buried layer 11 with a higher ion concentration, and the first epitaxial layer 13 with a lower ion concentration can appropriately increase the carrier concentration on the side of the first well region 12 closer to the buried layer 11, thereby making the carrier distribution in the first well region 12 more uniform and improving the linearity of the vertical Hall device.

[0050] Based on the above embodiments, optionally, the first conductivity type is N-type, and step S130, forming a first epitaxial layer on the surface of the buried layer away from the substrate, includes: An N-type lightly doped region is formed on the surface of the buried layer on the side away from the substrate.

[0051] Specifically, the majority carriers in the first well region of the vertical Hall device can be either electrons or holes. When the carriers are electrons, the first well region is an N-type doped region; when the carriers are holes, the first well region is a P-type doped region. Since the hole mobility in silicon is much lower than the electron mobility, in the manufacturing method of the vertical Hall device provided in this embodiment of the invention, when electrons are the carriers, an N-type lightly doped region is formed on the surface of the buried layer away from the substrate as the first epitaxial layer to increase the carrier concentration in the first well region near the buried layer.

[0052] Based on the above embodiments, the manufacturing method of the vertical Hall device may optionally further include the following steps: Ion implantation is performed on the surface of the first well region away from the first epitaxial layer to form multiple second well regions; the multiple second well regions are embedded in the first well region and arranged at intervals; the second well regions are set to a first conductivity type, and the ion concentration of the second well regions is greater than that of the first well region.

[0053] Specifically, taking electrons as the charge carriers, multiple second well regions are formed on the surface of the first well region away from the first epitaxial layer. These second well regions are heavily N-type doped regions, with an ion concentration greater than that of the first well region, to ensure good conductivity as contact electrodes. These multiple second well regions are arranged at intervals, serving as functional contact electrodes for transmitting different electrical signals, thus enabling the normal operation of the vertical Hall device.

[0054] Based on the above embodiments, the manufacturing method of the vertical Hall device may optionally further include the following steps: A field oxide layer is formed on the surface of the first well region away from the first epitaxial layer; A dielectric layer is formed on the side of the field oxide layer away from the first well region; A through-hole is provided in the dielectric layer, and a metal electrode layer is formed on the side of the dielectric layer away from the field oxide layer, so that the metal electrode layer is in contact with the corresponding second well region; A passivation layer is formed on the side of the metal electrode layer away from the dielectric layer.

[0055] Specifically, a field oxide layer can be formed on the surface of the first well region using silicon dioxide. A relatively thick dielectric layer is then formed on the surface of the field oxide layer using silicon dioxide to insulate the metal electrode layer from the semiconductor silicon material, and to insulate the multiple metal layers that may be included in the metal electrode layer. A metal electrode layer with a corresponding pattern is formed on the surface of the dielectric layer, and through contact holes penetrating the dielectric layer, it contacts the corresponding second well region, which serves as a contact electrode, thus enabling the normal operation of the vertical Hall device. A passivation layer is formed on the surface of the metal electrode layer to protect the vertical Hall device.

[0056] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A vertical Hall effect device structure, characterized in that, include: A substrate, a buried layer, and a first well region are stacked together; The substrate is configured with a second conductivity type, and the buried layer and the first well region are both configured with a first conductivity type. The second conductivity type is different from the first conductivity type; It also includes: a first epitaxial layer located between the buried layer and the first well region; the first epitaxial layer is configured with the first conductivity type; The ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer.

2. The vertical Hall device structure according to claim 1, characterized in that, The ion concentration of the first epitaxial layer is less than the ion concentration of the first well region, and the ion concentration of the first well region is less than the ion concentration of the buried layer.

3. The vertical Hall effect device structure according to claim 2, characterized in that, The first conductivity type is N-type, and the first epitaxial layer is an N-type lightly doped region.

4. The vertical Hall device structure according to claim 1, characterized in that, Also includes: Multiple second well regions; Multiple second well regions are located on the side surface of the first well region away from the first epitaxial layer, embedded in the first well region, and the multiple second well regions are arranged at intervals. The second well region is configured with the first conductivity type, and the ion concentration in the second well region is greater than the ion concentration in the first well region.

5. The vertical Hall device structure according to claim 4, characterized in that, Also includes: A field oxide layer is located on the surface of the first well region away from the first epitaxial layer; The dielectric layer is located on the side of the field oxide layer away from the first well region; The dielectric layer is provided with through contact holes; The metal electrode layer is in contact with the corresponding second well region through the contact hole; A passivation layer is located on the side of the metal electrode layer away from the dielectric layer.

6. A method for manufacturing a vertical Hall effect device, characterized in that, include: Provide substrate; The substrate is configured with a second conductivity type; Ion implantation is performed on the surface of the substrate to form a buried layer; The buried layer is configured with a first conductivity type, and the second conductivity type is different from the first conductivity type; A first epitaxial layer is formed on the surface of the buried layer away from the substrate; the first epitaxial layer is configured with the first conductivity type; Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form a first well region; the first well region is configured with the first conductivity type; wherein the ion concentration of the first epitaxial layer is different from the ion concentration of the first well region and the ion concentration of the buried layer.

7. The method for manufacturing a vertical Hall device according to claim 6, characterized in that, The step of ion implantation on the surface of the substrate to form a buried layer includes: Ion implantation is performed on the surface of the substrate to form the buried layer with a first ion concentration; The formation of a first epitaxial layer on the surface of the buried layer away from the substrate includes: A first epitaxial layer with a second ion concentration is formed on the surface of the buried layer on the side away from the substrate; The step of performing ion implantation on the surface of the first epitaxial layer away from the buried layer to form a first well region includes: Ion implantation is performed on the surface of the first epitaxial layer away from the buried layer to form the first well region with a third ion concentration; Wherein, the concentration of the second ion is less than the concentration of the first ion, and the concentration of the first ion is less than the concentration of the third ion.

8. The method for manufacturing a vertical Hall device according to claim 7, characterized in that, The first conductivity type is N-type, and the formation of a first epitaxial layer on the surface of the buried layer away from the substrate includes: An N-type lightly doped region is formed on the surface of the buried layer away from the substrate.

9. The method for manufacturing a vertical Hall device according to claim 6, characterized in that, Also includes: Ion implantation is performed on the surface of the first well region away from the first epitaxial layer to form multiple second well regions; Multiple second well regions are embedded within the first well region and are arranged at intervals; the second well regions are configured with the first conductivity type, and the ion concentration of the second well regions is greater than the ion concentration of the first well region.

10. The method for manufacturing a vertical Hall device according to claim 9, characterized in that, Also includes: A field oxide layer is formed on the surface of the first well region away from the first epitaxial layer; A dielectric layer is formed on the side of the field oxide layer away from the first well region; A through-hole is provided in the dielectric layer, and a metal electrode layer is formed on the side of the dielectric layer away from the field oxide layer, so that the metal electrode layer is in contact with the corresponding second well region; A passivation layer is formed on the side of the metal electrode layer away from the dielectric layer.

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