A superconducting field effect transistor based on ordered layered bc3 and a method for switching the superconducting state by gate control

Abstract

The application discloses a superconducting field effect transistor based on ordered layered BC3 and a gate-controlled superconducting state switching method thereof. The transistor comprises a substrate, a channel layer composed of an ordered layered BC3 superconducting film, a source electrode and a drain electrode, a gate dielectric layer and a gate electrode. The channel layer can be in a strain-free state, or a biaxial tensile strain can be passively applied to the channel layer through a thermal expansion mismatch method to enhance the superconducting critical temperature to 85-100K. By applying a voltage to the gate electrode, the Fermi level position of the channel layer can be continuously regulated. When the Fermi level is adjusted to the sigma band saddle point, the channel layer enters a superconducting state above the liquid nitrogen temperature zone; when the Fermi level is adjusted away from the saddle point, the channel layer returns to a normal resistance state, thereby realizing reversible electrically controlled switching between the superconducting state and the normal state. The application directly regulates the Fermi level position of the channel layer through the gate voltage, realizes reversible electrically controlled switching between the superconducting state and the normal state above the liquid nitrogen temperature zone, is compatible with a silicon-based CMOS in a preparation process, and has a wide application prospect in the field of superconducting electronics.

Description

1. Technical Field

[0001] This invention relates to the field of superconducting electronic device technology, specifically to a superconducting field-effect transistor with an ordered layered BC3 superconducting thin film as the channel layer, a gate-controlled superconducting switch incorporating the transistor, and a method for reversibly switching between a superconducting state and a normal state using gate voltage. The channel layer can be in a strain-free state or subjected to biaxial tensile strain to enhance its superconducting performance. 2. Background Technology

[0002] Superconducting electronic devices, utilizing the zero resistance and macroscopic quantum coherence properties of the superconducting state, have irreplaceable application value in fields such as single-photon detection, quantum computing, terahertz communication, superconducting quantum interference, and high-speed digital circuits. However, existing superconducting electronic devices generally face the following bottlenecks:

[0003] (1) Extremely low operating temperature. Traditional superconducting electronic devices based on niobium (Nb), niobium nitride (NbN) or aluminum (Al) typically have a superconducting critical temperature Tc below 15K, requiring cooling by liquid helium (boiling point 4.2K) or expensive and complex cryogenic refrigerators, which greatly limits their large-scale deployment and civilian application.

[0004] (2) Lack of effective electrical control methods. Existing superconducting switches or superconducting transistors mostly rely on control through critical current density (Ic) or critical magnetic field (Hc), such as injecting current exceeding Ic to desuperconduct the superconductor, or applying a magnetic field to change the superconducting state. These methods are slow, consume high power, and are difficult to integrate with the voltage-driven architecture of existing semiconductor integrated circuits. A few reported superconducting field-effect transistors (e.g., based on NbN or YBa2Cu3O)... 7-x FETs either operate in the liquid helium temperature range or cannot achieve complete "on-off" switching due to limited carrier concentration control capabilities.

[0005] (3) Poor material and process compatibility. Traditional superconducting electronic devices rely on niobium-based tunnel junctions (Nb / AlO). x The fabrication process of Nb or complex oxide heterojunctions is incompatible with standard silicon-based CMOS processes, making large-scale integration difficult.

[0006] Therefore, there is an urgent need for a superconducting field-effect transistor that can operate above the liquid nitrogen temperature range (≥77K), can be rapidly and continuously controlled by the gate voltage, and whose fabrication process is compatible with semiconductor planar processes. 3. Summary of the Invention

[0007] This invention is based on the applicant's deficiency variational framework theory (which reveals the correspondence between the peak electronic density of states and high-temperature superconductivity when the Fermi level coincides with the σ-band saddle point in honeycomb-lattice light element compounds). Through first-principles calculations, the following technical solution is derived: For the ordered layered compound BC3 with a honeycomb lattice (coordination number z = 3), when the Fermi level is precisely tuned to the σ-band saddle point (Van Hove singularity), the electronic density of states reaches its peak, and the electron-phonon coupling strength λ reaches its maximum value, thus exhibiting high-temperature superconductivity characteristics with a Tc of approximately 50-85 K at ambient pressure. Furthermore, by applying 2%-3% biaxial tensile strain, the Tc can be increased to 85-100 K, ensuring stable operation of the device in the liquid nitrogen temperature range.

[0008] Based on the above principles, this invention proposes a superconducting field-effect transistor (FET) with an ordered layered BC3 superconducting thin film as the channel layer. This device achieves precise control of the Fermi level position in the channel layer by continuously changing the carrier concentration in the channel layer through the voltage applied to the gate electrode. When the Fermi level is tuned to the σ-band saddle point, the channel layer enters a zero-resistance superconducting state below the critical temperature (Tc≥77K); when the Fermi level is tuned away from the saddle point, the superconducting state is destroyed, and the channel layer returns to its normal resistive state. Thus, this invention achieves reversible switching between the superconducting and normal states via gate voltage above the liquid nitrogen temperature range.

[0009] Furthermore, the present invention also provides a gate-controlled superconducting switch comprising the above-described superconducting field-effect transistor, and a method for controlling the superconducting state using gate voltage. 4. Description of the attached drawings

[0010] Figure 1 This is a schematic cross-sectional view of the superconducting field-effect transistor of the present invention. Wherein: 1-substrate, 2-ordered layered BC3 channel layer, 3-source electrode, 4-drain electrode, 5-gate dielectric layer, 6-gate electrode.

[0011] Figure 2 This is a schematic diagram illustrating the functional relationship between the superconducting critical temperature Tc of ordered layered BC3 and the gate voltage VG (reflecting the position of the Fermi level relative to the saddle point of the σ band), calculated based on a deficit variational framework. The diagram shows a sharp single peak in Tc at a specific VG, with the peak corresponding to the Fermi level located at the saddle point of the σ band, and Tc approximately 80-120 K.

[0012] Figure 3 This is a schematic diagram of the drain current-drain voltage (Id-Vd) characteristic curves of the superconducting field-effect transistor of the present invention under different gate voltages VG. When VG tunes the Fermi level to the saddle point of the σ-band, the Id-Vd curve exhibits a superconducting branch with zero resistance; when VG tunes the Fermi level away from the saddle point, the Id-Vd curve exhibits ohmic resistance behavior. 5. Detailed Implementation Methods

[0013] Based on the applicant's established deficiency variational framework theory, and combined with first-principles calculations and existing mature semiconductor processes, this invention proposes the following technical solution:

[0014] Example 1: Superconducting field-effect transistor with strain-free BC3 channel layer (predictive example)

[0015] This embodiment provides a back-gate structured superconducting field-effect transistor, the fabrication steps of which are as follows:

[0016] Step (a): Provide a substrate 1 with an insulating surface. The substrate is a heavily doped p-type silicon wafer with a 300 nm thick SiO2 insulating layer formed by thermal oxidation of the surface.

[0017] Step (b): An ordered layered BC3 superconducting thin film is formed on the SiO2 surface of substrate 1 as channel layer 2 by mechanical exfoliation or chemical vapor deposition (CVD). The BC3 film has a thickness of 5-20 nm, a honeycomb lattice structure, and boron and carbon atoms arranged in an ordered stoichiometric ratio of B:C = 1:3, with the Fermi level located at the saddle point of the σ band. The method for preparing this film has been described in detail in the related application filed by the applicant on the same day [referenced parent application], which is incorporated herein by reference.

[0018] Step (c): Source electrode 3 and drain electrode 4 are fabricated at both ends of BC3 channel layer 2 using electron beam lithography and metal thermal evaporation / lift-off processes. The electrode material is Cr / Au (5nm / 50nm), forming good ohmic contact or superconducting proximity contact with BC3.

[0019] Step (d): A 20 nm thick hafnium dioxide (HfO2) layer was deposited as the gate dielectric layer 5 on the BC3 channel layer 2 and the source / drain electrodes using atomic layer deposition (ALD). The deposition temperature was 200 °C to ensure that the crystal structure of BC3 was not damaged.

[0020] Step (e): The gate electrode 6 is fabricated on the gate dielectric layer 5, above the channel region between the source and drain electrodes, using photolithography and metal evaporation / lift-off processes. The electrode material is Cr / Au (5nm / 50nm).

[0021] After preparation, the device was placed in a cryostat and cooled to 77 K (the boiling point of liquid nitrogen).

[0022] Example 2: Superconducting field-effect transistor with strain-enhanced BC3 channel layer (predictive example)

[0023] This embodiment describes how to use an ordered layered BC3 thin film enhanced by passive strain due to thermal expansion mismatch as a channel layer to further improve the superconducting operating temperature and performance of the device.

[0024] Step (a): An ordered layered BC3 superconducting thin film was prepared and transferred onto a polytetrafluoroethylene (PTFE) thin film substrate using a polymer-assisted transfer method. The in-plane thermal expansion coefficient of PTFE is α≈100-120×10⁻⁶. -6 K -1 The in-plane thermal expansion coefficient of ordered layered BC3 is negative, α≈-6×10- 6 K -1 .

[0025] Step (b): Immerse the PTFE / BC3 assembly from room temperature (approximately 300K) into liquid nitrogen (77K). The PTFE substrate undergoes approximately 2.2%–2.7% in-plane shrinkage due to thermal shrinkage, and the BC3 film is carried by the substrate, bearing approximately 2.3%–2.8% in-plane biaxial tensile strain.

[0026] Step (c): This strain softens the E2g phonon frequency of BC3 from approximately 192 meV to approximately 180 meV, enhances the σ-band saddle point state density, and increases the electron-phonon coupling constant λ from approximately 0.85 to approximately 1.10–1.15. Based on the McMillan formula, its superconducting critical temperature Tc increases from approximately 65 K to approximately 90–100 K.

[0027] Step (d): The strain-enhanced BC3 film is transferred from the PTFE substrate to a heavily doped p-type silicon substrate with a SiO2 insulating layer as a channel layer.

[0028] Step (e): Following steps (c)-(e) of Example 1, the source electrode, drain electrode, HfO2 gate dielectric layer and gate electrode are fabricated sequentially.

[0029] After fabrication, the device was cooled to 77 K in a cryostat. Thanks to the channel layer's Tc ≥ 85 K, the device has sufficient thermodynamic margin at 77 K and can stably switch between the zero-resistance superconducting state and the normal resistive state.

[0030] As an alternative, nylon can also be used as the thermal expansion substrate (α≈80-100×10). -6 K -1 The resulting net tensile strain is approximately 1.9%-2.3%, which can raise the temperature coefficient (Tc) to 80-95K, thus meeting the requirements for stable operation in the liquid nitrogen temperature range. This passive strain method requires no external high-voltage power supply or piezoelectric crystal, making it the simplest and most economical approach to applying strain enhancement. The applicant has described this method in detail in a related application filed on the same day [referencing the parent application].

[0031] Example 3: Operation method for gate-controlled superconducting state switching (predictive example)

[0032] The superconducting field-effect transistor prepared in Example 1 or 2 is used to perform gate voltage modulation operation from superconducting state to normal state. The steps are as follows: Step (i): At an operating temperature of 77K, the source electrode 3 is grounded, a constant small bias current Id (e.g., 1μA) is applied to the drain electrode 4, and the channel resistance is measured by the four-terminal method.

[0033] Step (ii): Apply a scanning gate voltage VG to gate electrode 6, the range of which is determined based on the carrier concentration and gate dielectric capacitance of the BC3 channel layer, typically from -5V to +5V.

[0034] Step (iii): When VG is adjusted to a specific value Vopt, the Fermi level in the channel layer is precisely aligned to the σ-band saddle point. At this point, the measured channel resistance drops sharply to zero (beyond the noise floor of the measuring instrument), indicating that the channel layer has entered the superconducting state. The critical temperature corresponding to this superconducting state is Tc ≥ 77 K (using unstrained BC3) or Tc ≥ 85 K (using strain-enhanced BC3).

[0035] Step (iv): When VG is adjusted to a value deviating from Vopt (e.g., Vopt ± 1 V), the Fermi level is shifted out of the σ-band saddle point, the density of states decreases, the electron-phonon coupling strength weakens, and the superconducting state is completely destroyed. At this point, the channel layer reverts to a normal metallic state, exhibiting a finite ohmic resistance (e.g., hundreds to thousands of ohms).

[0036] Step (v): Repeating steps (iii) and (iv) enables reversible switching between the superconducting state (“on” state) and the normal resistive state (“off” state). The switching speed is determined by the gate RC time constant and is theoretically predicted to be on the sub-nanosecond scale.

[0037] 6. Industrial applicability

[0038] This invention proposes a superconducting field-effect transistor based on ordered layered BC3, operating in the liquid nitrogen temperature range (77K) without liquid helium cooling, significantly reducing the operating cost and system complexity of superconducting electronic devices. The BC3 channel layer, enhanced by passive strain due to thermal expansion mismatch, provides sufficient thermodynamic margin for the superconducting state at 77K. The operating principle of this invention is based on the direct manipulation of the Fermi level by an electric field, naturally compatible with existing semiconductor CMOS voltage-driven architectures, and easily enabling superconducting-semiconductor hybrid integration. This device has broad application prospects in single-photon detector arrays, quantum computing cryogenic control / readout circuits, superconducting logic units, and terahertz high-speed switches. All fabrication processes are compatible with existing silicon-based planar processes, possessing the potential for large-scale production and commercialization.

Claims

1. (Device structure - strain-free) A superconducting field-effect transistor, comprising a substrate, a channel layer, a source electrode, a drain electrode, a gate dielectric layer, and a gate electrode, characterized in that: The channel layer is composed of an ordered layered BC3 superconducting thin film, in which boron atoms and carbon atoms are arranged in an ordered manner according to a stoichiometric ratio of B:C = 1:3, and the Fermi level in the electronic structure of the thin film is located at the saddle point of the σ band. The source electrode and drain electrode are electrically connected to the channel layer; The gate dielectric layer covers the channel layer; The gate electrode is formed on the gate dielectric layer; By applying a gate voltage to the gate electrode, the Fermi level position of the channel layer can be tuned, allowing it to switch between a superconducting state and a normal resistive state.

2. (Device Structure - Strain Enhancement) The superconducting field-effect transistor according to claim 1 is characterized in that, The ordered layered BC3 superconducting thin film channel layer is subjected to 2%-3% biaxial tensile strain, and its superconducting critical temperature Tc≥80K.

3. (Device structure – strain enhancement further limits) The superconducting field-effect transistor according to claim 2 is characterized in that, The biaxial tensile strain is 2.3%-2.8%. The superconducting critical temperature Tc of the channel layer is 85-100K.

4. (Grid-controlled superconducting switch) A grid-controlled superconducting switch, characterized in that, A superconducting field-effect transistor comprising any one of claims 1-3, wherein the gate-controlled superconducting switch reversibly switches between a superconducting on-state and a normal resistive state via the gate voltage.

5. (Operating Method) A method for controlling the superconducting state using gate voltage, characterized in that, include: Provide a superconducting field-effect transistor according to any one of claims 1-3; A gate voltage is applied to the gate electrode to change the Fermi level position of the ordered layered BC3 superconducting thin film channel layer; Specifically, when the gate voltage adjusts the Fermi level to the σ-band saddle point, the channel layer exhibits a superconducting state below the critical temperature; when the gate voltage moves the Fermi level away from the σ-band saddle point, the channel layer exhibits a normal resistive state.

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