A planar capacitive superconducting quantum bit device and method of fabrication thereof

Abstract

The application discloses a flat-plate capacitance superconducting quantum bit device and a preparation method thereof. The flat-plate capacitance superconducting quantum bit device comprises a substrate, a planar superconducting thin film formed on a first surface of the substrate, an insulating layer formed on a surface of the planar superconducting thin film, superconducting thin film capacitance electrodes comprising a first superconducting thin film capacitance electrode and a second superconducting thin film capacitance electrode, the first superconducting thin film capacitance electrode and the second superconducting thin film capacitance electrode are formed on a surface of the insulating layer and are parallel to the planar superconducting thin film, and constitute a parallel-plate capacitance structure, and a Josephson junction formed on a surface of the insulating layer and located between the first superconducting thin film capacitance electrode and the second superconducting thin film capacitance electrode.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum bit fabrication technology, specifically to a planar capacitor superconducting quantum bit device and its fabrication method. Background Technology

[0002] In existing technologies for superconducting qubit devices, there is often a problem of excessively high energy-participation ratio (EPR) at the device surface and interface. An excessively high EPR will exacerbate the coupling between the superconducting qubit and the external environment (such as substrate surface defects, two-level systems at the interface, dielectric loss, etc.), thereby adversely affecting key performance indicators such as coherence time of the qubit.

[0003] To reduce EPR and ensure the coherent performance of qubits, existing technologies typically employ a strategy of increasing the overall size of the qubit. However, this approach has significant drawbacks: increasing the size of the qubit directly leads to it occupying more chip area, which not only increases the manufacturing cost of the chip but also severely limits the number of qubits that can be integrated on a single chip, hindering the development of superconducting qubit systems towards large-scale and scalable architectures.

[0004] Furthermore, increasing the size also brings other adverse effects. On the one hand, a larger physical size introduces greater parasitic capacitance and inductance, making the design parameters of the qubit more sensitive to process deviations and increasing the difficulty of frequency tuning and coupling control. On the other hand, in integration schemes that require coupling multiple qubits through resonant cavities or buses, excessively large qubit sizes will encroach on wiring space, reduce the layout flexibility of peripheral components such as couplers and readout resonant cavities, and thus affect the overall chip integration complexity and performance consistency. Therefore, how to effectively reduce the energy participation ratio at the surface and interface without excessively increasing the size has become an important optimization direction in current superconducting qubit design. Summary of the Invention

[0005] To address the aforementioned deficiencies in this field, this application aims to provide a planar capacitor superconducting quantum bit device and its fabrication method.

[0006] According to one aspect of this application, a planar capacitor superconducting quantum bit is provided, comprising: Substrate; A planar superconducting thin film is formed on the first surface of a substrate; An insulating layer is formed on the surface of the planar superconducting thin film; The superconducting thin film capacitor electrode includes a first superconducting thin film capacitor electrode and a second superconducting thin film capacitor electrode. The first superconducting thin film capacitor electrode and the second superconducting thin film capacitor electrode are formed on the surface of the insulating layer and are parallel to each other with the planar superconducting thin film, forming a parallel plate capacitor structure. The Josephson junction is formed on the surface of the insulating layer and is located between the first superconducting thin-film capacitor electrode and the second superconducting thin-film capacitor electrode.

[0007] In some embodiments of this application, the insulating layer is a silicon insulating layer.

[0008] In some embodiments of this application, the insulating layer is a monocrystalline silicon insulating layer.

[0009] In some embodiments of this application, the thickness of the insulating layer is 1-50 μm.

[0010] In some embodiments of this application, the thickness of the planar superconducting thin film is 10-500 nm.

[0011] In some embodiments of this application, the thickness of the superconducting thin-film capacitor electrode is 10-500 nm.

[0012] In some embodiments of this application, the insulating layer covering the first superconducting thin-film capacitor electrode and the planar superconducting thin film has holes for forming an electrical connection between the first superconducting thin-film capacitor electrode and the planar superconducting thin film.

[0013] In some embodiments of this application, the insulating layer covering the second superconducting thin-film capacitor electrode and the planar superconducting thin film has holes for forming an electrical connection between the second superconducting thin-film capacitor electrode and the planar superconducting thin film.

[0014] According to another aspect of this application, a method for preparing the above-mentioned planar capacitor superconducting quantum bit is also provided, comprising: Provide substrate; Provide insulation; A first planar superconducting thin film is grown on the first surface of the insulating layer; The first surface of the substrate is bonded to the first planar superconducting thin film, and the second surface of the insulating layer is thinned. A second planar superconducting thin film is grown on the second surface of the insulating layer, and the second planar superconducting thin film is etched to prepare a first superconducting thin film capacitor electrode and a second superconducting thin film capacitor electrode. Josephson junctions are fabricated on the second surface of a second planar superconducting thin film with superconducting thin film capacitor electrodes to obtain planar capacitor superconducting qubits.

[0015] In some embodiments of this application, the preparation method further includes: etching an insulating layer to create holes, so that the first superconducting thin-film capacitor electrode or the second superconducting thin-film capacitor electrode forms an electrical connection with the first planar superconducting thin film.

[0016] In some embodiments of this application, mechanical polishing is used to thin the second surface of the insulating layer. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a superconducting quantum bit in the current technology.

[0018] Figure 2 This is a schematic diagram of the structure of a planar capacitor superconducting quantum bit in an example embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the structure of a planar capacitor superconducting quantum bit according to another embodiment of this application.

[0020] Figure 4 , Figure 5 This is a schematic diagram of the fabrication process of a planar capacitor superconducting quantum bit in an example embodiment of this application.

[0021] Figure 6 , Figure 7 This is a schematic diagram of the fabrication process of a planar capacitor superconducting quantum bit according to another embodiment of this application.

[0022] Figure 8 The electric field distribution of the qubits is shown in Comparative Example (top) and Example 2 (bottom). Detailed Implementation

[0023] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0025] Unless otherwise specified, this application is conducted under standard conditions or conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, whose manufacturers are not specified, are all conventional products that can be obtained commercially.

[0026] The following is a detailed description of this application.

[0027] This application finds that in existing superconducting quantum bit (QB) technologies, the energy-participation ratio (EPR) at the device surface and interface is typically significantly increased. The fundamental reason for this is that existing superconducting QBs generally employ a single-layer structure design, with their capacitor components primarily consisting of simpler-to-implement coplanar capacitors. Specifically, the superconducting thin film constituting the QB is entirely deposited within the same substrate plane. This planar layout causes the electric field generated by the coplanar capacitor to be mainly concentrated in the edge region of the electrodes, resulting in a significantly higher energy-participation ratio (EPR) at the surface and interface.

[0028] like Figure 1 The diagram shows a typical Transmon quantum bit structure in existing technologies, where 101 is a superconducting thin-film capacitor electrode; 102 is a Josephson junction; 103 is the other electrode of the superconducting thin-film capacitor; and 104 is a single-crystal silicon insulating layer. This application reveals that the two electrodes of this capacitor are coplanar, meaning they lie in the same plane. The advantage of this design is its simple structure and mature, reliable fabrication process. The disadvantage is that the electric field distribution of the coplanar capacitor is uneven, with the electric field concentrated at the capacitor edges, resulting in significant energy participation at the surface and interface, which affects the coherence time of the quantum bit.

[0029] This application addresses the shortcomings of existing technologies by proposing a superconducting quantum bit design scheme. It adopts a planar capacitor structure to replace the traditional coplanar capacitor, enabling the electric field to be uniformly distributed between the planar electrodes. This effectively reduces the surface and interface EPR, ensures the coherence performance of the quantum bit, and significantly reduces the overall size of the quantum bit. This resolves the contradiction between size and performance in existing technologies and provides technical support for the large-scale integration of superconducting quantum bits.

[0030] In some examples, this application provides a parallel-plate capacitor superconducting quantum bit. The superconducting quantum bit designed using a parallel-plate capacitor employs an insulating thin film to isolate the superconducting thin film, forming a parallel-plate capacitor. In the parallel-plate capacitor, the electric field is not concentrated at the edge of the thin film, but is uniformly distributed throughout the parallel plates, effectively reducing the energy participation ratio at the surface and interface. This reduces the quantum bit size while maintaining its coherence performance, thereby improving the integration density of the quantum chip.

[0031] In some examples, such as Figure 2 As shown, the planar capacitor superconducting quantum bit of this application includes: Substrate (206); A planar superconducting thin film (205) is formed on the first surface of a substrate (206); An insulating layer (204) is formed on the surface of a planar superconducting thin film (205); The superconducting thin film capacitor electrode (201, 203) includes a first superconducting thin film capacitor electrode and a second superconducting thin film capacitor electrode. The first superconducting thin film capacitor electrode and the second superconducting thin film capacitor electrode are formed on the surface of the insulating layer (204) and are parallel to each other with the planar superconducting thin film (205) to form a parallel plate capacitor structure. Josephson junction (202) is formed on the surface of insulating layer (204) and located between the first superconducting thin film capacitor electrode and the second superconducting thin film capacitor electrode.

[0032] In an optional example, the insulating layer is a monocrystalline silicon insulating layer.

[0033] In an optional example, the thickness of the insulating layer (204) is 1-50 μm.

[0034] In an optional example, the thickness of the planar superconducting thin film (205) is 10-500 nm.

[0035] In an optional example, the thickness of the superconducting thin-film capacitor electrodes (201, 203) is 10-500 nm.

[0036] In optional examples, such as Figure 3 As shown, the insulating layer covering the first superconducting thin-film capacitor electrode and the planar superconducting thin film has holes for forming an electrical connection between the first superconducting thin-film capacitor electrode and the planar superconducting thin film.

[0037] In optional examples, such as Figure 3 As shown, the insulating layer covering the second superconducting thin-film capacitor electrode and the planar superconducting thin film has holes (A) for forming an electrical connection between the second superconducting thin-film capacitor electrode and the planar superconducting thin film.

[0038] Optionally, this application prepares holes in the insulating layer to connect the upper and lower superconducting thin films, forming a parallel plate capacitor on only one electrode, which can further reduce the size of the superconducting quantum bit.

[0039] In some examples, such as Figure 4 , Figure 5 As shown, this application provides a method for fabricating the above-mentioned planar capacitor superconducting quantum bit, comprising: Step (S110): Provide a substrate; Step (S120): Provide an insulating layer; Step (S130): A first planar superconducting thin film is grown on the first surface of the insulating layer; Step (S140): Bond the first surface of the substrate to the first planar superconducting thin film, and thin the second surface of the insulating layer; Step (S150): A second planar superconducting thin film is grown on the second surface of the insulating layer, and the second planar superconducting thin film is etched to prepare the first superconducting thin film capacitor electrode and the second superconducting thin film capacitor electrode. Step (S160): A Josephson junction is prepared on the second surface of a second planar superconducting thin film with superconducting thin film capacitor electrodes to obtain a planar capacitor superconducting quantum bit.

[0040] In some examples, such as Figure 6 , Figure 7 As shown, this application provides a method for fabricating the above-mentioned planar capacitor superconducting quantum bit, comprising: Step (S210): Provide a substrate; Step (S220): Provide an insulating layer; Step (S230): A first planar superconducting thin film is grown on the first surface of the insulating layer; Step (S240): Bond the first surface of the substrate to the first planar superconducting thin film, and thin the second surface of the insulating layer; Step (S250): Etch the insulating layer to create holes; Step (S260): A second planar superconducting thin film is grown on the second surface of the insulating layer, the second planar superconducting thin film is etched, and a first superconducting thin film capacitor electrode and a second superconducting thin film capacitor electrode are prepared; the first superconducting thin film capacitor electrode or the second superconducting thin film capacitor electrode is electrically connected to the first planar superconducting thin film. Step (S270): A Josephson junction is prepared on the second surface of a second planar superconducting thin film with superconducting thin film capacitor electrodes to obtain a planar capacitor superconducting quantum bit.

[0041] In an optional example, mechanical polishing is used to thin the second surface of the insulating layer.

[0042] The technical solution of this application will be further described below with reference to specific embodiments.

[0043] Example 1 A 100 nm thick tantalum film was grown on a 300 μm thick silicon substrate by magnetron sputtering. The substrate is inverted and bonded to another silicon substrate with a thickness of 300μm using a wafer bonding method; The first substrate was thinned using a chemical mechanical polishing method, reducing its thickness to 10 μm. A 100 nm tantalum film was grown using magnetron sputtering, then patterned using ultraviolet lithography, and then the tantalum film was etched using dry etching with CF4 as the etching gas at a flow rate of 30 sccm, an etching power of 50 W, and an etching time of 3 minutes. Josephson junctions were fabricated using a dual-angle evaporation method. A bilayer of MMA+PMMA adhesive was used. After electron beam exposure and development, an undercut structure was formed. A first aluminum film with a thickness of 40 nm was then evaporated in an electron beam evaporation apparatus, followed by in-situ oxidation at an oxidation pressure of 10 Torr for 30 minutes. A second aluminum film with a thickness of 100 nm was then evaporated. The two aluminum films act as superconductors, with an alumina film formed by oxidation in between serving as a barrier layer, thus forming the Josephson junction.

[0044] Example 2 A 100 nm thick tantalum film was grown on a 300 μm thick silicon substrate by magnetron sputtering. The substrate is inverted and bonded to another silicon substrate with a thickness of 300μm using a wafer bonding method; The first substrate was thinned using a chemical mechanical polishing method, reducing its thickness to 10 μm. The silicon through-hole pattern is defined using ultraviolet lithography, and then the silicon wafer is etched down to the first tantalum film using the Bosch process. The through-holes are circular, with a diameter of 5-10 μm.

[0045] A 100 nm tantalum film was grown using magnetron sputtering, then patterned using ultraviolet lithography, and then the tantalum film was etched using dry etching with CF4 as the etching gas at a flow rate of 30 sccm, an etching power of 50 W, and an etching time of 3 minutes. Josephson junctions were fabricated using a dual-angle evaporation method. A bilayer of MMA+PMMA adhesive was used. After electron beam exposure and development, an undercut structure was formed. A first aluminum film with a thickness of 40 nm was then evaporated in an electron beam evaporation apparatus, followed by in-situ oxidation at an oxidation pressure of 10 Torr for 30 minutes. A second aluminum film with a thickness of 100 nm was then evaporated. The two aluminum films act as superconductors, with an alumina film formed by oxidation in between serving as a barrier layer, thus forming the Josephson junction.

[0046] Comparative Example Traditional qubit structures such as Figure 1 As shown.

[0047] A 100 nm thick tantalum film was grown on a 300 μm thick silicon substrate by magnetron sputtering. Ultraviolet lithography defines the first layer pattern, and then dry etching is used to remove part of the tantalum film. Josephson junctions were fabricated using a dual-angle evaporation method. A bilayer of MMA+PMMA adhesive was used. After electron beam exposure and development, an undercut structure was formed. A first aluminum film with a thickness of 40 nm was then evaporated in an electron beam evaporation apparatus, followed by in-situ oxidation at an oxidation pressure of 10 Torr for 30 minutes. A second aluminum film with a thickness of 100 nm was then evaporated. The two aluminum films act as superconductors, with an alumina film formed by oxidation in between serving as a barrier layer, thus forming the Josephson junction.

[0048] Test case The surface energy participation ratios of the above embodiments and comparative examples were tested, and the test results are shown in the table below:

[0049] Through finite element simulation and numerical calculation, the surface energy participation ratio of the electric field under different design parameters can be obtained, as shown in the table above. Three types of surfaces were calculated: the surface of the thin film in air, the interface between the thin film and the substrate, and the surface of the substrate in air. Due to lattice adaptation and various defects at the surface, there is a significant loss, while the loss inside the material is much smaller and negligible. The parameters used in the calculation are: a dielectric constant of 11.9 for the silicon wafer; a perfect conductor for the superconducting thin film; no electric field distribution inside the film; and imperfect conductors only at the surface and the interface between the film and the substrate. The thickness of the superconducting thin film is 100 nm, and the thickness of the imperfect conductors at the surface and interface is 3 nm. Simulation and calculation show that the surface energy participation ratio of the two different designed planar capacitors is reduced to less than half of the coplanar capacitance.

[0050] This application not only addresses the problem of reducing the energy participation ratio using parallel-plate capacitors, but also provides specific implementation examples in micro / nano fabrication. The ultimate goal of reducing the energy participation ratio is to improve bit coherence time. However, parallel-plate capacitors made of ordinary insulating materials suffer from defects in the insulating material, which leads to a significant reduction in bit coherence time.

[0051] In the preferred embodiment described above, this application provides a design and fabrication method for using a silicon substrate as the insulating layer of a parallel-plate capacitor. Specifically, a superconducting thin film is deposited on one side of the silicon substrate, then wafer-bonded to another substrate. The silicon substrate is then thinned using a chemical mechanical polishing method, and another superconducting thin film is deposited on the thinned substrate. The thinner silicon substrate, located between the two superconducting thin films, serves as the insulating layer, forming the parallel-plate capacitor.

[0052] This application discloses a structure that reduces the electric field energy participation ratio, as well as a design and fabrication scheme for the application of this structure in superconducting qubits.

[0053] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A planar capacitor superconducting quantum bit device, characterized in that, include: Substrate; A planar superconducting thin film is formed on the first surface of the substrate; An insulating layer is formed on the surface of the planar superconducting thin film; A superconducting thin-film capacitor electrode includes a first superconducting thin-film capacitor electrode and a second superconducting thin-film capacitor electrode. The first superconducting thin-film capacitor electrode and the second superconducting thin-film capacitor electrode are formed on the surface of the insulating layer and are parallel to each other with the planar superconducting thin film, forming a parallel plate capacitor structure. A Josephson junction is formed on the surface of the insulating layer and located between the first superconducting thin-film capacitor electrode and the second superconducting thin-film capacitor electrode.

2. The planar capacitor superconducting quantum bit device according to claim 1, characterized in that, The insulating layer is a silicon insulating layer.

3. The planar capacitor superconducting quantum bit device according to claim 2, characterized in that, The thickness of the insulating layer is 1-50 μm.

4. The planar capacitor superconducting quantum bit device according to claim 1, characterized in that, The thickness of the planar superconducting thin film is 10-500 nm.

5. The planar capacitor superconducting quantum bit device according to claim 1, characterized in that, The thickness of the superconducting thin-film capacitor electrode is 10-500 nm.

6. The planar capacitor superconducting quantum bit device according to any one of claims 1-5, characterized in that, The insulating layer covering the first superconducting thin-film capacitor electrode and the planar superconducting thin film has holes for forming an electrical connection between the first superconducting thin-film capacitor electrode and the planar superconducting thin film.

7. The planar capacitor superconducting quantum bit device according to any one of claims 1-5, characterized in that, The insulating layer covering the second superconducting thin-film capacitor electrode and the planar superconducting thin film has holes for forming an electrical connection between the second superconducting thin-film capacitor electrode and the planar superconducting thin film.

8. A method for fabricating a planar capacitor superconducting quantum bit device according to any one of claims 1-7, characterized in that, include: Provide substrate; Provide insulation; A first planar superconducting thin film is grown on the first surface of the insulating layer; The first surface of the substrate is bonded to the first planar superconducting thin film, and the second surface of the insulating layer is thinned. A second planar superconducting thin film is grown on the second surface of the insulating layer, and the second planar superconducting thin film is etched to prepare a first superconducting thin film capacitor electrode and a second superconducting thin film capacitor electrode. A Josephson junction is fabricated on the second surface of the second planar superconducting thin film having the first superconducting thin film capacitor electrode and the second superconducting thin film capacitor electrode to obtain the planar capacitor superconducting quantum bit device.

9. The preparation method according to claim 8, characterized in that, Also includes: The insulating layer is etched to create holes, so that the first superconducting thin-film capacitor electrode or the second superconducting thin-film capacitor electrode forms an electrical connection with the first planar superconducting thin film.

10. The preparation method according to claim 8, characterized in that, The second surface of the insulating layer is thinned by mechanical grinding.

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