Synergistic integration of air-bridge and 3d integrated modules

Abstract

A method for fabricating one or more air-bridge structures and one or more 3D integrated modules on a patterned metallization layer of a wafer comprising quantum bits or superconducting electronic devices, the method comprising: providing a wafer having a patterned metallization layer; depositing an integrated metallization layer before or after providing and patterning a first resist layer; forming one or more air-bridge structures contacting the patterned metallization layer at openings in the first resist layer, wherein the one or more air-bridge structures are made of a superconducting material at working temperatures; and fabricating a 3D integrated module by electroplating predefined areas of the integrated metallization layer.

Description

Technical Field

[0001] This invention relates to the fields of quantum computing, superconducting electronic devices, and 3D heterogeneous integration. More specifically, this invention relates to a foundry-compatible method for integrating air-bridge structures with 3D integrated module systems, such as bumps, spacers, and through-silicon vias (TSVs). Background Technology

[0002] The development of large-scale quantum processors and superconducting digital logic necessitates heterogeneous 3D integration to achieve scalable and efficient qubit architectures and logic. This approach allows for the fabrication of quantum and classical elements on separate chips, which can then be stacked and interconnected to optimize signal routing and minimize footprint. By employing through-silicon vias (TSVs) and bumps, signals can be efficiently distributed across multiple metallization layers to ensure the addressability of quantum and classical elements across the chip.

[0003] Among the key components of quantum and classical processors, air bridges play a crucial role in mitigating crosstalk between control lines, suppressing parasitic circuit modes caused by broken ground planes, and preventing signal collisions in planar wiring as intersection points. These functions are essential for maintaining signal integrity and ensuring reliable operation of qubits and other classical logic.

[0004] Traditionally, the fabrication of 3D integrated components for quantum computing has relied on stripping-based processes, which are incompatible with foundry manufacturing. While stripping techniques are sufficient for small-scale quantum circuits, they face challenges in terms of yield, uniformity, and scalability, making them less suitable for manufacturing large-scale quantum processors with millions of qubits required for error correction. The same applies to superconducting digital logic circuits.

[0005] Therefore, alternative methods are needed to manufacture air bridges and other 3D integrated components (such as bumps, spacers, and TSVs) to address the limitations of stripping technology and provide a way to achieve scalability. Summary of the Invention

[0006] The purpose of embodiments of the present invention is to provide a preferred method for fabricating one or more air bridge structures and 3D integrated modules on a patterned metallization layer of a wafer including qubits and / or superconducting electronic devices.

[0007] The above objectives are achieved by the method and apparatus according to the present invention.

[0008] In a first aspect, embodiments of the present invention relate to a method for fabricating one or more air-bridge structures and 3D integrated modules on a patterned metallization layer of a wafer comprising qubits and / or superconducting electronic devices. The method includes providing a wafer having a patterned metallization layer. Depositing an integrated metallization layer on the wafer before or after providing and patterning a first etch resist layer. Forming one or more air-bridge structures on the patterned metallization layer. The one or more air-bridge structures contact the patterned metallization layer at an opening in the first etch resist layer. The one or more air-bridge structures are superconducting at an operating temperature. The one or more air-bridge structures contact the patterned metallization layer at an opening in the first etch resist layer. At such an opening, there is direct contact between the associated air-bridge structure and the integrated metallization layer, and direct contact between the integrated metallization film and the patterned metallization layer. At least due to the proximity effect, the integrated metallization layer between the one or more air-bridge structures and the patterned metallization layer is superconducting at the operating temperature. Alternatively, the integrated metallization layer provides current contacts between one or more air-bridge structures and the patterned metallization layer at operating temperature with a resistance less than a predefined threshold to maintain qubit coherence and / or preserve superconductivity in superconducting electronic devices. In embodiments of the invention, qubit coherence is maintained by minimizing resistive losses. In embodiments of the invention, at operating temperature, the current contacts may have a resistance of less than 1000 nOhm, even less than 500 nOhm, or even less than 100 nOhm, or even less than 10 nOhm, or even less than 5 nOhm per current contact. The method also includes fabricating 3D integrated modules by electroplating predefined regions of the integrated metallization layer.

[0009] The advantage of embodiments of the present invention is that the method not only provides for the fabrication of air bridges, but also enables the fabrication of 3D integrated modules by performing electroplating. An advantage of embodiments of the present invention is that the integrated metallization layer can effectively integrate the air bridge structure and subsequent electroplating steps.

[0010] In embodiments of the present invention, the integrated metallization layer can be used to electroplat 3D integrated modules and serve as a contact between the air bridge structure and the patterned metallization layer.

[0011] In embodiments of the present invention, the method ensures superconductivity at operating temperature and maintains quantum bit correlation by minimizing resistance loss.

[0012] Embodiments of the present invention provide a process tailored for large-scale quantum and superconducting digital processors, utilizing foundry-compatible methods to fabricate air-bridge structures and 3D integrated modules, such as bumps and spacers. The use of integrated metallization layers in combination with barrier layers and seed layers simplifies the fabrication process and enhances its versatility.

[0013] Furthermore, compatibility with electroplating and the elimination of stripping techniques improve manufacturing uniformity, yield, and scalability.

[0014] In embodiments of the present invention, the superconducting material includes Al, Ta, Nb, or TiN.

[0015] In embodiments of the present invention, the integrated metallization layer includes a barrier layer and a seed layer.

[0016] In embodiments of the invention, the barrier material is superconducting (TiN, TaN, NbTiN, Ta, Nb). It acts as a diffusion barrier for the seed material. In embodiments of the invention, it also serves as a protective layer for the quantum circuit material during 3DI processing.

[0017] In embodiments of the present invention, the seed layer may be made of materials such as Cu or Ru. Ru can be used to implement different spacer materials other than Cu.

[0018] In embodiments of the present invention, the integrated metallization layer may be made of a single material that is superconducting at operating temperature and conductive at room temperature for efficient electroplating.

[0019] In an embodiment of the invention, the method includes locally etching a seed layer using the same mask as the patterned first resist layer.

[0020] In embodiments of the invention, patterning the first resist layer includes a reflow step for fabricating tapered sidewalls. This is the case with organic resists. Alternatively, when using a hard mask, tapered sidewalls can be obtained by controlling the etch parameters of the mask.

[0021] An advantage of embodiments of the present invention is that the tapered sidewalls ensure conformal coverage (e.g., after subsequent metal deposition).

[0022] In embodiments of the invention, the method includes depositing an integrated metallization layer prior to providing and patterning a first resist layer. Superconducting material is deposited using thin-film deposition to form one or more air-bridge structures. The deposited superconducting material is patterned and etched using a second resist layer to define regions for the one or more air-bridge structures, thereby obtaining one or more air-bridge structures. The second resist layer and the first resist layer are then removed. After fabricating the 3D integrated module, the integrated metallization layer is etched to release the one or more air-bridge structures and the 3D integrated module.

[0023] In embodiments of the present invention, thin film deposition can be performed by PVD, CVD, or ALD.

[0024] In embodiments of the invention, the method includes depositing an integrated metallization layer after providing and patterning a first resist layer. One or more airbridge structures are formed by defining regions for one or more airbridge structures by applying a second resist layer. Superconducting material for the one or more airbridge structures is electroplated in the regions defined by the second resist layer. After fabricating the 3D integrated module, a protective resist is provided to protect the 3D integrated module and the one or more airbridge structures. The integrated metallization layer is then etched, and the protective resist material is removed to release the one or more airbridge structures and the 3D integrated module.

[0025] One advantage of embodiments of the present invention is that the method incorporates electroplating to form superconducting airbridge structures, thereby enabling the deposition of thick and robust materials with well-defined geometries, which are crucial for shielding, crosstalk mitigation, and mechanical stability. Rhenium (Re), aluminum (Al), and ruthenium (Ru) are examples of superconducting materials that can be plated.

[0026] In embodiments of the invention, the method includes depositing an integrated metallization layer after providing and patterning a first resist layer. One or more air bridge structures are formed by defining regions for one or more air bridge structures by applying a second resist layer. A metal hard mask is electroplated in the regions defined by the second resist layer. After fabricating the 3D integrated module, a protective resist is provided to protect the 3D integrated module while leaving the metal hard mask exposed. The integrated metallization layer is etched except for the regions of the protective resist layer and the regions where the metal hard mask serves as protection. Any remaining metal hard mask is then removed using a resist mask that exposes only the hard mask, and then the resist mask is removed to release one or more air bridge structures.

[0027] An advantage of embodiments of the present invention is that the air bridge structure is based on its material composition being fully superconducting and is independent of proximity effects.

[0028] In embodiments of the present invention, the length between the contacts of one or more air bridge structures on the patterned metallization layer is between 20 µm (micrometers) and 100 µm.

[0029] In embodiments of the present invention, the width of one or more air bridge structures is greater than 10µm.

[0030] An advantage of embodiments of the present invention is that air bridge structures can also be used for shielding. For example, their width can reach several hundred micrometers.

[0031] In embodiments of the present invention, one or more air bridge structures are formed using electroplating and have a width greater than one hundred micrometers.

[0032] The advantages of embodiments of the present invention are that the air bridge structures formed using electroplating can achieve widths exceeding one hundred micrometers, even reaching several hundred micrometers or more, thereby providing enhanced functionality (such as electromagnetic shielding) and improved mechanical stability. This increased width allows the air bridge to not only serve as a signal crossing point but also to effectively shield crosstalk and spurious modes, which is crucial for maintaining signal integrity in quantum processors. Furthermore, the use of electroplating ensures the scalability required to manufacture such wide structures, making this method particularly suitable for industrial-scale manufacturing of quantum processors or superconducting digital logic processors, where robust and versatile components are essential. One advantage of embodiments of the present invention is that it avoids stripping, making electroplating more compatible with foundry manufacturing.

[0033] One advantage of this invention is that the plating allows for the creation of mechanically robust thick structures.

[0034] In embodiments of the invention, the electroplating process for manufacturing 3D integrated modules includes forming bumps made of a superconducting material to achieve superconducting connections between the bonded wafers. The bumps may be made, for example, of indium or an indium-tin alloy.

[0035] In embodiments of the present invention, the electroplating process for manufacturing a 3D integrated module includes forming spacers. The spacer material may be composed of copper (Cu), ruthenium (Ru), or other suitable metals.

[0036] In a second aspect, embodiments of the present invention relate to a method for forming a quantum processor.

[0037] The method includes fabricating air-bridge structures and 3D integrated modules on a patterned metallization layer of a wafer comprising qubits and / or superconducting electronic devices using a method according to a first aspect of the invention. The method includes using the 3D integrated modules of two wafers to bond the wafer to an additional wafer comprising the 3D integrated modules to establish electrical and mechanical connections.

[0038] In embodiments of the present invention, at least one air bridge structure is configured to mitigate crosstalk and spurious modes in a quantum processor.

[0039] Specific preferred aspects of the invention are set forth in the appended independent and dependent claims. Features in the dependent claims may be suitably combined with features of the independent claim and other features of the dependent claims, and not merely as expressly stated in the claims.

[0040] These and other aspects of the invention will become apparent and will be clarified with reference to the embodiments described below. Attached Figure Description

[0041] Figure 1A schematic diagram of an intermediate stack obtained during method steps of an exemplary embodiment of the present invention is shown, wherein an integrated metallization layer is deposited prior to providing and patterning a first resist layer.

[0042] Figure 2 A schematic diagram of an intermediate stack obtained during method steps of an exemplary embodiment of the present invention is shown, wherein an integrated metallization layer is deposited after a first resist layer is provided and patterned.

[0043] Figure 3 A schematic diagram of an intermediate stack obtained during a method step in an exemplary embodiment of the invention is shown, wherein a metal hard mask is provided by electroplating.

[0044] Any reference symbols in the claims should not be construed as limiting the scope.

[0045] In different figures, the same reference numerals denote the same or similar elements. Detailed Implementation

[0046] The invention will be described with reference to specific embodiments and certain accompanying drawings, but is not limited thereto by the claims alone. The described drawings are illustrative only and are not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. Dimensions and relative dimensions do not correspond to an actual reduction in the practice of the invention.

[0047] The terms "first," "second," etc., used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe sequences, whether temporally, spatially, in rank, or in any other way. It should be understood that such terms are interchangeable where appropriate, and the embodiments of the invention described herein can operate in orders other than those described or shown herein.

[0048] Furthermore, the terms "upper," "lower," etc., used in the specification and claims are for descriptive purposes and are not necessarily used to describe relative positions. It should be understood that such terms are interchangeable where appropriate, and the embodiments of the invention described herein can operate in directions other than those described or shown herein.

[0049] It should be noted that the word "comprising" as used in the claims should not be construed as limited to the means listed below; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned features, integers, steps, or components, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the expression "device comprising means A and B" should not be limited to devices consisting solely of components A and B. This means that, for the purposes of this invention, the only relevant components of the device are A and B.

[0050] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" or "in an embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, as will be obvious to those skilled in the art from this disclosure, particular features, structures, or characteristics can be combined in any suitable manner.

[0051] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplifying the disclosure and aiding in the understanding of one or more inventive aspects. However, this method of disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects exist in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the claims appended following the detailed description are thus explicitly incorporated into this detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0052] Furthermore, while some embodiments described herein include features that are included in other embodiments but not others, it will be understood by those skilled in the art that combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments. For example, any embodiment of the claimed embodiments in the appended claims can be used in any combination.

[0053] Numerous specific details are set forth in the description provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0054] In embodiments of the present invention, when referring to an "air bridge structure," the term refers to a conductive bridge that rises above the surface of a substrate and spans features or gaps in a wafer including qubits and / or superconducting electronic devices. These air bridge structures are made of materials that are superconducting at operating temperatures.

[0055] In embodiments of the invention, when referring to "3D integrated modules," the term refers to structures formed on wafers that enable vertical electrical and mechanical connections between stacked wafers or layers in a three-dimensional configuration. These modules are manufactured by electroplating designated areas of an integrated metallization layer. Examples of 3D integrated modules include electroplated pillars or bumps made of superconducting materials that facilitate inter-wafer connections in quantum processors.

[0056] In embodiments of the invention, when referring to a “patterned metallization layer,” it refers to a conductive material layer on a wafer comprising qubits and / or superconducting electronic devices, which has been selectively etched or deposited to define qubit circuitry and / or superconducting electronic device circuitry and associated components. This patterning creates the structures required for qubit operation, such as resonators, control lines, and coupling elements. Examples include superconducting layers patterned using photolithography and etching techniques to form superconducting qubits and associated circuitry.

[0057] In embodiments of the present invention, when referring to a “wafer comprising qubits and / or superconducting electronic devices,” it refers to a semiconductor or insulating substrate on which qubit devices and / or superconducting electronic devices and related circuitry are fabricated for quantum computing applications. Examples of wafers that can be used as a basic platform for constructing quantum processors include silicon, sapphire, or silicon-on-insulator (SOI) wafers for realizing superconducting or semiconductor qubits and / or superconducting electronic devices.

[0058] In embodiments of the present invention, when referring to an "integrated metallization layer," the term refers to a conductive layer deposited on a wafer including qubits and / or superconducting electronic devices, which has multiple functions, including acting as a seed layer for electroplating and providing electrical connections between various structures. This layer may include one or more sublayers (such as barrier layers and seed layers) to enhance adhesion and conductivity.

[0059] In embodiments of the invention, when referring to a "resist layer," the term refers to a layer of photosensitive or electronically sensitive material applied to the surface of a wafer, which can be patterned using photolithography to define specific processing areas. The resist layer serves as a mask during etching, deposition, or electroplating processes. Examples include positive or negative photoresists used in ultraviolet lithography to create patterns for subsequent manufacturing steps. In embodiments of the invention, the "resist mask" can also be a hard mask, which can be selectively removed relative to other materials on the wafer after its purpose has been achieved.

[0060] In embodiments of the invention, a patterned metallization layer of a wafer comprising qubits and / or superconducting electronic devices is used for a quantum processor. In embodiments of the invention, when referring to "superconducting materials at operating temperatures," the term refers to materials that exhibit superconductivity (zero resistance) at the operating temperatures of the quantum processor in the qubit device. These operating temperatures are typically low. Examples of such materials include aluminum, tantalum, niobium, or niobium nitride, which become superconducting below the critical temperatures associated with quantum computing applications.

[0061] In embodiments of the invention, when referring to "operating temperature," the term refers to the temperature at which the quantum processor or qubit device is designed to operate effectively, typically requiring cryogenic conditions to maintain superconductivity. These operating temperatures can, for example, be below 4 Kelvin.

[0062] In embodiments of the present invention, when referring to the "proximity effect," it refers to the phenomenon where, when two non-superconducting materials are in close contact, superconducting properties are induced in the non-superconducting material due to Cooper pairs penetrating into the non-superconducting region. This effect allows the integrated metallization layer material between the air-bridge structure and the patterned metallization layer to become superconducting.

[0063] In embodiments of the invention, when referring to a "reflow step," it refers to the process of heating the resist layer to a temperature sufficient to soften and flow the resist material, resulting in a smooth resist profile or the formation of tapered sidewalls. This modification aids subsequent deposition processes by improving material coverage on the resist features. An example is heating the photoresist above its glass transition temperature to achieve tapered sidewalls, thereby obtaining better coverage of metallic steps.

[0064] In embodiments of the present invention, when "electroplating" is mentioned, it refers to a method of depositing a metal layer onto a conductive surface by passing an electric current through a solution containing metal ions to reduce them and form a solid metal coating on the cathode surface. This technique is used to manufacture features such as 3D integrated modules and air bridge structures.

[0065] In embodiments of the present invention, when referring to a "quantum processor," it refers to a computing device that uses qubits (qubits) to perform calculations using quantum mechanical principles (such as superposition and entanglement). The processor includes qubit devices and associated circuitry fabricated on a wafer, which includes qubits and / or superconducting electronic devices.

[0066] In embodiments of the present invention, when referring to a "bump," the term refers to a raised metallic feature formed on the surface of a wafer, typically used to establish electrical and mechanical connections between bonded wafers in flip-chip or wafer-level packaging.

[0067] In embodiments of the invention, when referring to a "spacer," the term refers to a raised structure formed on the wafer surface, typically used as a mechanical stop during bonding. Spacers help to precisely control the gap between bonded chips, ensuring accurate alignment and mechanical stability in 3D integration processes. In all embodiments of the invention, the spacers are made of an electroplatable material. In embodiments of the invention, the spacers are made of a metallic material. An advantage of embodiments of the invention is that they provide rigid spacers resistant to deformation.

[0068] In embodiments of the present invention, when referring to a “seed layer”, it refers to a thin conductive film that provides nucleation sites for subsequent metal deposition processes (such as electroplating).

[0069] In embodiments of the present invention, when referring to a "barrier layer," it refers to a thin film between the substrate and the seed layer, used to prevent interdiffusion of materials and enhance adhesion. The barrier layer ensures the integrity of the metallization system during subsequent processing steps. In embodiments of the present invention, the barrier layer protects the patterned metallization layer throughout the process. In embodiments of the present invention, the barrier layer is etched away while the patterned metallization layer is retained.

[0070] In a first aspect, embodiments of the invention relate to a method (100) for fabricating one or more air bridge structures (240) and 3D integrated modules (251, 252) on a patterned metallization layer (211) of a wafer (210) including qubits and / or superconducting electronic devices. The patterned metallization layer may, for example, include aluminum (Al), tantalum (Ta), niobium (Nb), and titanium nitride (TiN).

[0071] Figure 1 , Figure 2 and Figure 3 An example of this method is shown in the figure.

[0072] Method (100) includes providing (110) a wafer (210) having a patterned metallization layer (211). Figure 1 , Figure 2 and Figure 3 As shown, a wafer (210) including qubits and / or superconducting electronic devices is shown as a rectangular block, representing a substrate, having a patterned metallization layer (211) as a thin layer thereon.

[0073] The method further includes depositing (120) an integrated metallization layer (220) on the wafer before or after providing and patterning (130) a first resist layer (230). One or more air bridge structures (240) are formed (140) on the patterned metallization layer (211). The one or more air bridge structures (240) contact the patterned metallization layer (211) at openings in the first resist layer (230). These openings are obtained during the patterning of the first resist layer (230). The air bridge structures (240) comprise a superconducting material at the operating temperature. At least due to proximity effect, the integrated metallization layer (220) between the air bridge structure (240) and the patterned metallization layer (211) is superconducting at the operating temperature, or the integrated metallization layer provides a current contact between the air bridge structure (240) and the patterned metallization layer (211) at the operating temperature with a resistance less than a predefined threshold, so as to maintain the coherence of the qubit and / or maintain the superconductivity in the superconducting electronic device by minimizing resistance loss.

[0074] The method also includes fabricating (150) one or more 3D integrated modules (251, 252) by electroplating predefined areas of an integrated metallization layer (220). A resist (253, 254) may be provided to define the areas of the electroplated 3D integrated modules (251, 252). This resist is subsequently removed.

[0075] In an embodiment of the invention, the integrated metallization layer (220) includes a barrier layer (221) and a seed layer (222). This is in Figures 1 to 3 As shown in the figure. In embodiments of the invention, the barrier material is superconducting, including materials such as titanium nitride (TiN), tantalum nitride (TaN), or titanium niobium nitride (NbTiN). It acts as a diffusion barrier to prevent the migration of seed materials (e.g., Cu, Ru). Additionally, it serves as a protective layer for quantum circuit materials during 3D integration processing. In embodiments of the invention, the barrier layer is used for the adhesion of the seed layer.

[0076] In an embodiment of the invention, the method includes locally etching the seed layer (222) using the same mask as the patterned (130) first resist layer (230). The result is... Figure 1 and Figure 2 As shown in the bottom stack, Figure 1 and Figure 2 The bottom stack only shows the barrier layer (221) between the air bridge structure (240) and the patterned metallization layer (211).

[0077] In an embodiment of the invention, patterning (130) the first resist layer includes a reflow step for creating tapered sidewalls.

[0078] In embodiments of the invention, an integrated metallization layer (220) is deposited before the first resist layer (230) is provided and patterned. An example of this method is... Figure 1 As shown in the image.

[0079] In embodiments of the present invention, the first resist layer may be composed of an organic resist or a hard mask material.

[0080] (141a) A superconducting material is deposited by using thin-film deposition to form (140) one or more air bridge structures (240). In embodiments of the invention, conformal coverage is ensured.

[0081] The deposited superconducting material is then patterned and etched (142a) using a second resist layer (242a) to define areas for one or more air bridge structures, thereby obtaining one or more air bridge structures (240). The etching (142a) of the air bridge metal can be performed by wet or dry etching.

[0082] The second anti-corrosion layer (242a) and the first anti-corrosion layer (230) are then removed (143a) by selective removal relative to other materials used so far.

[0083] Manufacturing (150) 3D integrated modules (251, 252).

[0084] In embodiments of the invention, a spacer photolithographic mask (253) is provided and patterned, followed by electroplating of the spacer material (251). This achieves synergistic integration of the air bridge and the spacer. The spacer material can be copper (Cu) or any other electroplatable superconductor, such as ruthenium (Ru), rhenium (Re), or aluminum (Al). In embodiments of the invention, the selection of the seed layer (222) is influenced by the selection of the spacer material.

[0085] In an embodiment of the invention, a bump photomask (254) is patterned, and then a bump material (252) is electroplated. This achieves the synergistic integration of the air bridge and the bump. The bump material can be indium (In), a tin-indium (SnIn) alloy, or any other suitable superconductor. In an embodiment of the invention, the selection of the seed layer (222) is influenced by the selection of the bump material.

[0086] After providing the 3D integrated modules (spacers, bumps), the photolithography mask is removed.

[0087] In the next step, the integrated metallization layer (220) is etched (144a) to release one or more air bridge structures (240) and 3D integrated modules (251, 252). The etching can be wet or dry. In embodiments of the invention, the etching is selective for all other materials present.

[0088] exist Figure 2 In the exemplary embodiment shown, the method (100) includes depositing an integrated metallization layer (220) after providing and patterning a first resist layer (230). In embodiments of the invention, the first resist layer (230) may be an organic resist or a hard mask. In embodiments of the invention, the mask undergoes a reflow process to create tapered sidewalls. In embodiments of the invention, the first mask layer is designed such that an opening region on the substrate corresponds to a region where electroplating will be performed.

[0089] In embodiments of the present invention, the integrated metallization layer includes a barrier layer and a seed layer. The barrier material is superconducting and may include TiN, TaN, or NbTiN. It acts as a diffusion barrier to the seed material (e.g., Cu or Ru), serves as a protective layer for the quantum circuit material during 3D integration processing, and can also enhance the adhesion of the seed layer. Depending on the processing requirements, the seed material may be Cu or Ru. Alternatively, the integrated metallization layer may consist of a single superconducting material that fulfills the functions of both the barrier layer and the seed layer.

[0090] One or more air bridge structures (240) are formed by defining an area for one or more air bridge structures (240) by applying a second resist layer (241b). The second resist layer may be an organic resist or a hard mask. In embodiments of the invention, the second resist layer (241b) may be used for local seed (222) etching. Figure 2 The figure below shows the final stack without a seed layer.

[0091] One or more air bridge structures (240) are electroplated (142b) within a region defined by a second resist layer (241b). In embodiments of the invention, the air bridge metal is an electroplatable superconductor, such as Ru, Re, or Al.

[0092] In embodiments of the invention, a spacer photolithographic mask (253) is provided and patterned, and then spacer material (251) is electroplated. Thus, synergistic integration of the air bridge and the spacer is achieved. The spacer material can be Cu or any other electroplatable superconductor, such as Ru, Re, or Al. In embodiments of the invention, the selection of the seed layer (222) is influenced by the selection of the spacer material.

[0093] In an embodiment of the invention, a bump photolithography mask (254) is patterned, and then a bump material (252) is electroplated. This achieves the synergistic integration of the air bridge and the bump. The bump material can be In, SnIn alloy, or any other suitable superconductor. In an embodiment of the invention, the selection of the seed layer (222) is influenced by the selection of the bump material.

[0094] Before depositing bumps, local seed etching can be performed using a bump photolithography mask.

[0095] After fabricating the (150) 3D integrated modules (251, 252), a protective resist (243b) is applied (143b) to protect the 3D integrated modules (251, 252) and one or more air bridge structures (240). These critical structures are protected during the subsequent etching of the integrated metallization layer, ensuring process uniformity.

[0096] The integrated metallization layer (220) is then etched (144b), and the resist material (145b) is removed to release one or more air bridge structures (240) and 3D integrated modules (251, 252). The etching can be wet or dry. In embodiments of the invention, the etching is selective for all other materials present.

[0097] Next, the protective resist (243b) is removed. Depending on whether seed etching is performed, a stack with a seed layer (222) below the air bridge (140) is obtained (the penultimate stack), or a stack without a seed layer below the air bridge (140) is obtained (the bottommost stack).

[0098] exist Figure 3 In the exemplary embodiment shown, the method (100) includes depositing an integrated metallization layer (220) after providing and patterning a first resist layer (230). In embodiments of the invention, the first resist layer (230) may be an organic resist or a hard mask. In embodiments of the invention, the mask undergoes a reflow process to create tapered sidewalls. In embodiments of the invention, the first mask layer is designed such that an opening region on the substrate corresponds to a region where electroplating will be performed.

[0099] In embodiments of the present invention, the integrated metallization layer includes a barrier layer and a seed layer. The barrier material is superconducting and may include TiN, TaN, or NbTiN. It acts as a diffusion barrier for the seed material (e.g., Cu) and also serves as a protective layer for the quantum circuit material during 3D integration processing. In embodiments of the present invention, the seed material is Cu and may also be used to enhance the adhesion of the seed layer. Alternatively, the integrated metallization layer may consist of a single superconducting material that satisfies both the barrier layer and seed layer functions.

[0100] One or more air bridge structures (240) are formed by defining an area for one or more air bridge structures by applying (141c) a second resist layer (241c). The second resist layer may be an organic resist or a hard mask.

[0101] A metal hard mask (242c) is electroplated (142c) in the area defined by the second resist layer (241c). In an embodiment of the invention, the metal hard mask is made of copper. A copper air bridge is used as a hard mask for the subsequent formation of an actual air bridge, which will be superconducting under operating conditions.

[0102] In embodiments of the invention, a spacer photolithographic mask (253) is provided and patterned, and then spacer material (251) is electroplated. Thus, synergistic integration of the air bridge and the spacer is achieved. The spacer material can be Cu or any other electroplatable superconductor, such as Ru, Re, or Al. In embodiments of the invention, the selection of the seed layer (222) is influenced by the selection of the spacer material.

[0103] In an embodiment of the invention, a bump photolithography mask (254) is patterned, and then a bump material (252) is electroplated. This achieves the synergistic integration of the air bridge and the bump. The bump material can be In, SnIn alloy, or any other suitable superconductor. In an embodiment of the invention, the selection of the seed layer (222) is influenced by the selection of the bump material.

[0104] Before depositing bumps, local seed etching can be performed using a bump photolithography mask.

[0105] After manufacturing the (150) 3D integrated modules (251, 252), a protective resist (243c) is applied (143c) to protect the 3D integrated modules (251, 252) while keeping the metal hard mask exposed.

[0106] Then, except for the areas where the hard metal mask (242c) serves as a protective layer and the areas where the protective resist (243c) serves as a protective layer, the integrated metallization layer (220) is etched (144c). The etching can be wet or dry etching and is selective for all other materials present. The etching also removes the portion of the hard mask (242c) above the air bridge (240). Since the hard mask (242c) is thicker than the seed layer (222), it will remain in the etching step.

[0107] In the next step, a resist (245c) is applied to expose the remaining metal hard mask (242c). Then, any remaining metal hard mask (242c) and seed layer (222) are removed (145c), and the barrier material (221) is selectively etched to ensure that the remaining superconducting barrier material is preserved.

[0108] In the next step, the resist (146c) (245c) is removed to release one or more air bridge structures (240) and a superconducting bridge is obtained.

[0109] In embodiments of the invention, the length between the contacts of the air bridge structure on the patterned metallization layer (211) is between 20 µm and 100 µm. This length is measured according to the shortest distance between the contacts.

[0110] In an embodiment of the present invention, the width of the air bridge structure (240) is greater than 10µm.

[0111] The width of the air bridge structure is measured perpendicular to its length (between the contacts on the patterned metallized layer) and parallel to the surface of the patterned metallized layer.

[0112] In an embodiment of the invention, an air bridge structure (240) is formed (130) by electroplating, and the width of the air bridge structure is greater than one hundred micrometers.

[0113] In an embodiment of the present invention, the electroplating process for manufacturing (140) 3D integrated modules (251, 252) includes forming bumps made of superconducting material to achieve superconducting connections between the bonded wafers.

[0114] In a second aspect, embodiments of the invention relate to a method for forming a quantum processor. The method includes fabricating an air-bridge structure (240) and 3D integrated modules (251, 252) on a patterned metallization layer (211) of a wafer comprising qubits and / or superconducting electronic devices using a fabrication method (100) described in the first aspect of the invention. The 3D integrated modules of two wafers are used to bond the wafer to an additional wafer that also comprises 3D integrated modules to establish electrical and mechanical connections. This enables the creation of multilayer quantum processors with enhanced interconnectivity and optimized signal routing. In embodiments of the invention, at least one air-bridge structure is configured to mitigate crosstalk and suppress spurious modes in the quantum processor, thereby further improving the overall performance and scalability of the quantum computing system.

[0115] An advantage of this invention is that it provides an integration technology that ensures scalability while maintaining quantum coherence.

[0116] One advantage of embodiments of the present invention is that it achieves full 3D heterogeneous integration required for large-scale quantum computing by combining bump, spacer and through-silicon via (TSV) modules, which facilitates signal routing and improves the addressability of qubits in the third dimension.

[0117] Air bridges play a crucial role in mitigating stray circuit patterns and crosstalk in qubit control and readout lines, while also providing signal crossover points for planar wiring.

[0118] One advantage of embodiments of the present invention is that it provides a process flow compatible with qubits that integrates air bridges with 3D integration modules, thereby ensuring the advantages of both.

[0119] In embodiments of the invention, the method enables the co-integration of air bridges and 3D integration modules within a 300mm foundry-compatible process. The air bridge manufacturing process is designed to be compatible with electroplating steps used for 3D integration, thereby ensuring seamless integration with bumps, spacers, and through-silicon vias. Unlike conventional methods that rely on stripping techniques that lack scalability and result in high process variability, the proposed method provides a robust and manufacturable solution suitable for large-scale quantum processor fabrication.

Claims

1. A method (100) for fabricating one or more air bridge structures (240) and one or more 3D integrated modules (251, 252) on a patterned metallization layer (211) of a wafer (210) including qubits and / or superconducting electronic devices, the method comprising: Provide (110) the wafer (211) having the patterned metallization layer (211); Before or after providing and patterning (130) the first resist layer (230), an integrated metallization layer (220) is deposited (120) on the wafer (210). One or more air bridge structures (240) are formed (140) that contact the patterned metallization layer (211) at the opening in the first anti-corrosion layer (230). The one or more air bridge structures (240) are superconducting at the operating temperature, and Wherein, at least due to proximity effect, the integrated metallization layer (220) between the one or more air bridge structures (240) and the patterned metallization layer (211) is superconducting at operating temperature, or the integrated metallization layer (220) provides a current contact between the one or more air bridge structures (240) and the patterned metallization layer (211) at operating temperature with a resistance less than a predefined threshold, in order to maintain quantum bit coherence and / or maintain superconductivity in superconducting electronic devices; (150) One or more 3D integrated modules (251, 252) are manufactured by electroplating a predefined area of ​​the integrated metallization layer.

2. The method according to claim 1, characterized in that, The integrated metallization layer (220) includes a barrier layer (221) and a seed layer (222).

3. The method according to claim 2, characterized in that, The method includes using the same mask as the patterned (130) first resist layer (230) to locally etch the seed layer.

4. The method according to claim 1, characterized in that, Patterning (130) The first resist layer includes a reflow step for creating tapered sidewalls.

5. The method (100) according to claim 1, characterized in that, The integrated metallization layer (220) is deposited prior to providing and patterning the first resist layer (230), and wherein the one or more air bridge structures (240) are formed (140) by the following operations: The superconducting material (141a) is deposited using thin film deposition; The deposited superconducting material is patterned and etched (142a) using a second resist layer (242a) to define the area for the one or more air bridge structures in order to obtain the one or more air bridge structures; Remove (143a) the second anti-corrosion layer (242a) and the first anti-corrosion layer (230). After fabricating (150) the 3D integrated modules (251, 252), the integrated metallization layer (220) is etched (144a) to release the one or more air bridge structures (240) and the 3D integrated modules (251, 252).

6. The method (100) according to claim 1, characterized in that, The integrated metallization layer (220) is deposited after the first resist layer (230) is provided and patterned, and wherein the one or more air bridge structures (240) are formed (140) by the following operations: Apply (141b) a second anti-corrosion layer (241b) to define the area for the one or more air bridge structures (240); In the region defined by the second anti-corrosion layer (241b), the superconducting material of the one or more air bridge structures (240) is electroplated (142b); After manufacturing (150) the 3D integrated modules (251, 252), a protective resist (243b) is provided (143b) to protect the 3D integrated modules (251, 252) and the one or more air bridge structures (240), the integrated metallization layer (220) is etched (144b) and the resist material is removed (145b) to release the one or more air bridge structures (240) and the 3D integrated modules (251, 252).

7. The method (100) according to claim 1, characterized in that, The integrated metallization layer (220) is deposited after the first resist layer (230) is provided and patterned, and wherein the one or more air bridge structures (240) are formed (140) by the following operations: Apply (141c) a second anti-corrosion layer (241c) to define the area used for the one or more air bridge structures; Electroplating (142c) of a metal hard mask (242c) in the area defined by the second resist layer (241c); After manufacturing (150) the 3D integrated modules (251, 252), a protective resist (243c) is provided (143c) to protect the 3D integrated modules (251, 252) while exposing the metal hard mask, the integrated metallization layer (220) is etched (144c) except for the area protected by the metal hard mask (242c) and the area protected by the protective resist (243c) as a protective layer, any remaining metal hard mask layer (242c) is removed (145c), and the resist material is removed (146c) to release the one or more air bridge structures (240).

8. The method (100) according to claim 1, characterized in that, The length between the contacts of the one or more air bridge structures (240) on the patterned metallization layer (211) is between 20µm and 100µm.

9. The method (100) according to claim 1, characterized in that, The width of the one or more air bridge structures (240) is greater than 10µm.

10. The method (100) according to claim 1, characterized in that, The one or more air bridge structures (240) are formed by electroplating (130) and have a width greater than 100µm.

11. The method (100) according to claim 1, characterized in that, The electroplating process for manufacturing the 3D integrated modules (251, 252) of (140) includes forming bumps made of superconducting material to achieve superconducting connections between the bonded wafers.

12. A method for forming a quantum processor, comprising: Using the method (100) according to any of the preceding claims, one or more air bridge structures (240) and one or more 3D integrated modules (251, 252) are fabricated on a patterned metallization layer (211) of a wafer including qubits and / or superconducting electronic devices. A 3D integration module for two wafers is used to bond the wafer to an additional wafer including the 3D integration module to establish electrical and mechanical connections.

13. The method according to claim 12, characterized in that, At least one of the one or more air bridge structures (240) is configured to mitigate crosstalk and spurious modes in the quantum processor.

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