Contact, memory cell, and memory device and method of manufacturing the same

Abstract

A contact window, a storage unit, and a storage device, and a method for manufacturing the same, are disclosed. In the contact window, a conductive barrier layer forms a hollow shell. One end of the hollow shell is a sealed structure with a bottom surface, which is electrically connected to a preceding component to be connected. The other end of the hollow shell is an open structure without a bottom surface, which is electrically connected to a subsequent component to be connected. Filler metal only partially fills the hollow shell formed by the conductive barrier layer. On the open structure side, the filler metal is separated from the subsequent component to be connected. The area between the contact window and the subsequent component to be connected is only the end surface of the conductive barrier layer. The contact area between the contact window and the subsequent component to be connected is small, and the shape of the contact window changes minimally. This reduces the contact area while simplifying the manufacturing process, reducing the number of photomasks and process steps, lowering the process difficulty, and simultaneously reducing production costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a contact window, a memory cell, a memory device, and a method for manufacturing the same. Background Technology

[0002] In recent years, phase-change memory devices have been widely studied due to their characteristics such as low latency, balanced read and write times, long lifespan, low power consumption, and good radiation resistance, as well as the fact that they currently have no physical limitations and are easy to implement in high-density memory applications.

[0003] In phase-change memory devices, the storage element and the switching device are electrically connected through a contact window. Because phase-change memory devices require a high current density to induce a phase change in the phase change material, and because the contact area between the contact window and the storage element and switching device is relatively large, this high current density can easily lead to excessive power consumption in the phase-change memory device.

[0004] A common approach is to reduce the contact area to increase current density and reduce energy consumption. However, existing methods of reducing the contact area can lead to increased process complexity and higher process costs. Summary of the Invention

[0005] The problem solved by this invention is how to reduce process costs while reducing the contact area.

[0006] To address the above problems, the present invention provides a contact layer comprising:

[0007] A conductive barrier layer, which forms a hollow shell, has a sealed structure with a bottom surface at one end, which is electrically connected to the front layer component to be connected, and an open structure without a bottom surface at the other end, which is electrically connected to the rear layer component to be connected; and a filler metal, which fills part of the hollow shell formed by the conductive barrier layer.

[0008] Accordingly, the present invention also provides a storage unit, comprising:

[0009] A switching device; a first contact window, wherein the first contact window is the contact window of the present invention, and one end of the first contact window is electrically connected to one end of the switching device; a storage element, wherein the storage element is located on the side of the first contact window away from the switching device, and the storage element is electrically connected to the other end of the first contact window.

[0010] Furthermore, the present invention also provides a storage device, comprising:

[0011] A storage array, comprising storage units, wherein the storage units are the storage units of the present invention, the storage units being arranged in an array along intersecting first and second directions, wherein the first and second directions are both perpendicular to a third direction, the third direction being the direction of the line connecting the sealed structure and the open structure.

[0012] In addition, the present invention also provides a method for manufacturing a storage device, comprising:

[0013] A switching device is formed; a first contact window is formed, the first contact window being the contact window of the present invention, one end of the first contact window being electrically connected to one end of the switching device; a storage element is formed, the storage element being located on the side of the first contact window away from the switching device, the storage element being electrically connected to the other end of the first contact window.

[0014] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0015] In this invention, the conductive barrier layer forms a hollow shell. One end of the hollow shell is a sealed structure with a bottom surface, which is electrically connected to the front layer component to be connected. The other end of the hollow shell is an open structure without a bottom surface, which is electrically connected to the rear layer component to be connected. A filler metal is used to fill a portion of the hollow shell formed by the conductive barrier layer. The filler metal only fills a portion of the hollow shell formed by the conductive barrier layer. On one side of the open structure, the filler metal is separated from the rear layer component to be connected. The contact window's area with the rear layer component to be connected is only the end face of the conductive barrier layer. The contact area between the contact window and the rear layer component to be connected is small, and the shape of the contact window changes little. This reduces the contact area, simplifies the manufacturing process, lowers the process difficulty, and reduces production costs.

[0016] In an optional embodiment of the present invention, the contact window further includes an insulating material filled between the filler metal and the subsequent layer to be connected. The insulating material filling the space between the filler metal and the subsequent layer to be connected effectively ensures the reliability and stability of the contact window, and effectively guarantees manufacturing yield. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a cross-sectional structure of a storage unit;

[0018] Figure 2 These are schematic diagrams illustrating the structure of some embodiments of the contact window of the present invention;

[0019] Figure 3 These are three-dimensional structural schematic diagrams of some embodiments of the storage unit of the present invention;

[0020] Figure 4 These are three-dimensional structural schematic diagrams of some other embodiments of the storage unit of the present invention;

[0021] Figure 5 yes Figure 4 A schematic cross-sectional view of the storage unit embodiment shown along line A1A2;

[0022] Figures 6 to 16 These are schematic diagrams illustrating the structure of each step in some embodiments of the storage device manufacturing method of the present invention;

[0023] Figures 17 to 29 This is a schematic diagram of the structure of each step in some other embodiments of the storage device manufacturing method of the present invention. Detailed Implementation

[0024] As can be seen from the background technology, existing methods for reducing the contact area of ​​contact windows have problems such as increased process complexity and excessively high process costs.

[0025] refer to Figure 1 The diagram shows a cross-sectional structure of a storage cell.

[0026] The storage unit includes: a switching device 11; a storage element 12; a first contact window 13 located between the switching device 11 and the storage element 12; and a blade electrode 14 located between the first contact window 13 and the storage element 12, with one end of the blade electrode 14 electrically connected to the storage element 12 and the other end electrically contacting the first contact window 13.

[0027] The smaller the contact area between the storage element 12 and the switching device 11, the greater the current density between them. A greater current density can more effectively drive the phase change material to undergo a phase change, thereby effectively reducing the energy consumption of the storage unit.

[0028] like Figure 1 As shown, by setting a blade electrode 14 between the first contact window 13 and the storage element 12, the contact area is reduced and the current density is increased. However, the formation of the blade electrode 14 requires multiple process steps such as deposition and etching, which requires a large number of photomasks and is complex. Moreover, the setting of the blade electrode 14 increases the total height of the interconnect structure of the storage cell location, that is, the height of the interconnect structure is the sum of the heights of the first contact window 13 and the blade electrode 14, which will have an adverse effect on the connection of the electrodes in the peripheral circuit area. Therefore, more photomasks and processes need to be introduced to overcome the adverse effects.

[0029] To solve the aforementioned technical problem, the present invention provides a contact window suitable for realizing electrical connection between a front layer component to be connected and a rear layer component to be connected. The contact window includes: a conductive barrier layer forming a hollow shell, one end of which is a sealed structure with a bottom surface electrically connected to the front layer component to be connected, and the other end of which is an open structure without a bottom surface electrically connected to the rear layer component to be connected; and a filler metal filling a portion of the hollow shell formed by the conductive barrier layer.

[0030] In this invention, the filling metal only fills a portion of the hollow shell formed by the conductive barrier layer. On one side of the open structure, the filling metal is separated from the back layer to be connected. The area of ​​the contact window and the back layer to be connected is only the end face of the conductive barrier layer. The contact area between the contact window and the back layer to be connected is small, and the shape of the contact window changes little. This reduces the contact area, simplifies the manufacturing process, reduces the number of photomasks and process steps, lowers the process difficulty, and reduces production costs.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figure 2 The diagram shows a structural schematic of some embodiments of the contact window of the present invention.

[0033] The contact window includes: a conductive barrier layer 111, which forms a hollow shell. One end of the hollow shell is a sealed structure with a bottom surface, and the bottom surface of the sealed structure is electrically connected to the front layer component to be connected. The other end of the hollow shell is an open structure without a bottom surface, and the end face of the open structure is electrically connected to the rear layer component to be connected. A filler metal 112 fills part of the hollow shell formed by the conductive barrier layer 111.

[0034] The technical solution of the contact window embodiment is described in detail below with reference to the accompanying drawings.

[0035] It should be noted that an insulating material 101 is provided between the front layer to be connected (not shown in the figure) and the rear layer to be connected (not shown in the figure) to achieve electrical insulation; the contact window penetrates the insulating material 101 to achieve electrical connection between the front layer to be connected and the rear layer to be connected.

[0036] The conductive barrier layer 111 is adapted to prevent the filler metal 112 from diffusing into the insulating material 101; the material of the conductive barrier layer 111 is a conductor, and the conductive barrier layer 111 is also adapted to realize the electrical connection between the front layer to be connected and the rear layer to be connected.

[0037] Specifically, such as Figure 2 As shown, the conductive barrier layer 111 serves as the shell wall, forming a hollow shell. The end of the hollow shell facing the front layer to be connected has a sealing structure 111a with a bottom surface (e.g., ...). Figure 2 (As shown within the dashed circle), the bottom surface of the sealing structure 111a is electrically connected to the front layer component to be connected. For example, the bottom surface of the sealing structure 111a is in contact with the front layer component to be connected.

[0038] The hollow shell facing the rear layer to be connected has an open structure 111b without a bottom surface (e.g., Figure 2 (As shown in the midpoint coil); the end face of the open structure 111b, that is, the end face of the conductive barrier layer 111 of the hollow shell exposed on one side of the open structure 111b, is electrically connected to the subsequent layer to be connected. For example, the end face of the open structure 111b is in electrical contact with the subsequent layer to be connected.

[0039] The hollow shell makes electrical contact with the rear layer to be connected through the end face of the open structure 111b. The end face of the open structure 111b has a small area, which can greatly reduce the contact area of ​​the electrical contact and effectively increase the current density of the electrical contact. Moreover, the use of the hollow shell surrounded by the conductive barrier layer to achieve electrical connection is simple in process and low in process difficulty, which can effectively reduce the production cost of the contact window.

[0040] In some embodiments of the present invention, the conductive barrier layer 111 has a uniform thickness. A conductive barrier layer 111 with uniform thickness can effectively improve the uniformity of the current distribution transmitted in the conductive barrier layer, and can effectively improve its reliability and stability.

[0041] In some embodiments, the thickness of the conductive barrier layer 111 is in the range of 1 nm to 20 nm. Specifically, the thickness of the conductive barrier layer 111 is the wall thickness of the hollow shell formed by the conductive barrier layer 111. For example, the thickness of the conductive barrier layer 111 is the dimension of the bottom surface of the sealing structure 111a along a third direction z, where the third direction is the direction of the line connecting the sealing structure and the open structure.

[0042] In some embodiments of the present invention, the material of the conductive barrier layer 111 includes at least one of titanium nitride, tantalum nitride, titanium, tantalum and ruthenium. In other embodiments of the present invention, the material of the conductive barrier layer may also be other conductive materials capable of preventing metal diffusion.

[0043] The filler metal 112 fills part of the hollow shell formed by the conductive barrier layer 111 to reduce the resistance of the electrical connection between the front layer to be connected and the rear layer to be connected.

[0044] The filler metal 112 fills only a portion of the internal space of the hollow shell enclosed by the conductive barrier layer 111, and does not fill the remaining space of the hollow shell. In some embodiments, the filler metal 112 fills the portion of the hollow shell enclosed by the conductive barrier layer 111 near the front layer to be connected.

[0045] Specifically, such as Figure 2 As shown, the filling metal 112 fills a portion of the space on one side of the sealing structure 111a in the hollow shell, and the filling metal 112 is in direct contact with the bottom surface of the sealing structure 111a; the filling metal 112 does not fill a portion of the space on one side of the open structure 112 in the hollow shell.

[0046] In some embodiments of the present invention, the ratio of the thickness of the filler metal 112 to the depth of the hollow shell is less than 2 / 3. The depth of the hollow shell is the dimension of the internal space of the hollow shell along the z-direction of the line connecting the front and rear layers to be connected; the thickness of the filler metal 112 is the dimension of the filler metal 112 along the z-direction of the line connecting the front and rear layers to be connected.

[0047] In some embodiments of the present invention, the filler metal 112 is made of tungsten. In other embodiments of the present invention, the filler metal 112 may also be made of copper or aluminum.

[0048] In some embodiments of the present invention, the contact window further includes an insulating material 113, which fills the space between the filler metal 112 and the rear component to be connected. The insulating material 113 fills the remaining space of the hollow shell, avoiding direct contact between the filler metal 112 and the rear component to be connected, ensuring that the contact area between the contact window and the rear component to be connected is controllable, and ensuring the overall mechanical strength of the contact window.

[0049] In some embodiments, the surface of the insulating material 113 facing the rear layer to be connected is in contact with the rear layer to be connected. The insulating material 113 and the filler metal 112 fill the entire internal space of the hollow shell, with one side of the insulating material 113 in direct contact with the filler metal 112 and the other side of the insulating material 113 in direct contact with the rear layer to be connected.

[0050] In some embodiments, the thickness of the insulating material 113 is less than half the distance between the filler metal and the subsequent layer to be connected. The thickness of the insulating material 113 is the dimension of the insulating material 113 along the third direction z. The appropriate thickness of the insulating material 113 can effectively prevent direct contact between the filler metal 112 and the subsequent layer to be connected, and can effectively ensure the mechanical strength of the overall structure of the contact window.

[0051] It should be noted that in some embodiments, the insulating material 113 completely fills the remaining space of the hollow shell. In other embodiments of the present invention, the insulating material partially fills the remaining space of the hollow shell to form a gap between the insulating material and the subsequent layer to be connected. In still other embodiments of the present invention, no other material is disposed between the filler metal and the subsequent layer to be connected, to form a gap between the filler metal and the subsequent layer to be connected. Creating a gap on the side of the subsequent layer connector near the filler metal can effectively reduce the dielectric constant of the material between the subsequent layer to be connected and the filler metal, which is beneficial to improving the electrical performance of the contact window.

[0052] In some embodiments, the insulating material 113 is made of silicon nitride. In other embodiments of the present invention, the insulating material 113 may also be made of silicon oxide, silicon oxynitride, or other insulating materials.

[0053] Accordingly, the present invention also provides a storage unit.

[0054] refer to Figure 3 The diagram shows a three-dimensional structural schematic of some embodiments of the storage unit of the present invention.

[0055] The storage unit includes:

[0056] Switching device 210; first contact window 220, the first contact window 220 being the contact window of the present invention, one end of the first contact window 220 being electrically connected to one end of the switching device 210; storage element 230, the storage element 230 being located on the side of the first contact window 220 away from the switching device 210, the storage element 230 being electrically connected to the other end of the first contact window 220.

[0057] The technical solution of the storage unit embodiment is described in detail below with reference to the accompanying drawings.

[0058] The switching device 210 is used to select the storage unit, thereby enabling control operations such as writing, reading or erasing the storage unit.

[0059] In some embodiments of the present invention, the switching device 210 is a transistor switching device; the switching device 210 includes: a gate structure 211; a first doped layer 212 and a second doped layer 213, which are located in a plane perpendicular to the line connecting the switching device 210 and the memory element 230, the first doped layer 212 and the second doped layer 213 are located on both sides of the gate structure 211, and the first doped layer 212 is electrically connected to the first contact window 220.

[0060] The gate structure 211 controls the on and off of the channel of the transistor switching device.

[0061] In some embodiments of the present invention, the gate structure 211 includes: a gate electrode; a gate dielectric layer located below the gate electrode; and a gate sidewall located on the sidewall of the gate electrode.

[0062] like Figure 3 As shown, the storage cell includes a substrate 201. The substrate 201 includes a substrate 202; an isolation structure 203 located within the substrate 202; and an active region 204 located within the substrate 202 between adjacent isolation structures 203.

[0063] Specifically, the substrate 202 is a silicon substrate, and the material of the substrate 202 is silicon. For example, the material of the substrate 202 can be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the material of the substrate can also be selected from silicon, germanium, gallium arsenide, or silicon-germanium compounds; the substrate can also be selected from materials having an epitaxial layer or a silicon-on-epitaxy layer structure; the substrate can also be other semiconductor materials.

[0064] The isolation structure 203 is located within the substrate 202 to improve leakage current. Specifically, a plurality of the isolation structures 203 are arranged parallel to each other along a first direction x, wherein the first direction x is parallel to the surface of the substrate 202. The isolation structure 203 is made of an insulating material; for example, the material of the isolation structure 203 may be silicon oxide or silicon nitride.

[0065] The active region 204 is located between two adjacent isolation structures 203, providing a basis for the formation of the switching device 201. For example, the active region 204 can be a P-type doped region. In other embodiments of the present invention, the active region can also be an N-type doped region.

[0066] The gate structure 211 is located on the substrate 201. Specifically, the gate electrode is located on the active region 204 between adjacent isolation structures 203 in the substrate 201; the gate dielectric layer is located between the gate electrode and the active region 204.

[0067] In some embodiments of the present invention, the gate structure 211 is a polysilicon gate structure, that is, the material of the gate electrode is polysilicon; and the material of the gate dielectric layer is silicon oxide. In other embodiments of the present invention, the gate structure may also be a metal gate structure, that is, the material of the gate electrode is metal; and the material of the gate dielectric layer includes a high-k gate dielectric material.

[0068] The first doped layer 212 and the second doped layer 213 are the source and drain doped layers of the transistor switching device, respectively.

[0069] Specifically, the gate structure 211 is located on the active region 204 in the substrate 201, and the first doped layer 212 and the second doped layer 213 are located in the active regions 204 on both sides of the gate structure 211.

[0070] The first doped layer 212 and the second doped layer 213 have the same conductivity type. Specifically, the first doped layer 212 and the second doped layer 213 can both be P-type doped layers; in other embodiments, the first doped layer and the second doped layer can also both be N-type doped layers.

[0071] The first doped layer 212 and the second doped layer 213 can be formed in the active region 204 by ion implantation; the first doped layer 212 and the second doped layer 213 can also be formed by other doping processes.

[0072] It should be noted that, as Figure 3 As shown, in some embodiments of the present invention, the switching device 210 includes a connection layer 214, which is located between the first doped layer 212 and the first contact window 220.

[0073] The connection layer 214 is adapted to reduce the resistance of the electrical connection between the first doped layer 212 and the first contact layer 220 of the switching device 210.

[0074] Specifically, the material of the connecting layer 214 is a metal silicide. For example, the material of the connecting layer 214 can be at least one of nickel silicide (NiSi), nickel platinum silicide (NiPtSi), titanium silicide (TiSi2), and cobalt silicide (CoSi2).

[0075] The first contact window 220 is used to realize the electrical connection between the switching device 210 and the storage element 230.

[0076] The first contact window 220 is the contact window of the present invention. The specific technical solution of the first contact window 220 is described in the foregoing embodiments of the contact window; further details are omitted here.

[0077] like Figure 3 As shown, the switching device 210 is a transistor switching device, and the first contact window 220 is electrically connected to the first doped layer 212 of the switching device 210. The first doped layer 212 of the switching device 210, as a front-end connection element, is electrically connected to one end of the sealed structure of the hollow shell formed by the conductive barrier layer in the first contact window 220. Specifically, the bottom surface of the sealed structure is in direct contact with the surface of the connecting layer 214 on the first doped layer 212.

[0078] The first contact window 220 extends along a direction z perpendicular to the surface of the substrate 201, and the line connecting the open structure and the sealed structure of the first contact window 220 is parallel to the direction z perpendicular to the surface of the substrate 201.

[0079] The storage element 230 is used to store data.

[0080] The storage element 230 is located above the switching device 210 and is electrically connected to the switching device 210 through the first contact window 220.

[0081] Specifically, the storage element 230 is located above the first doped layer 212 of the switching device 210, and the storage element 230 is electrically connected to one end of the open structure of the hollow shell formed by the conductive barrier layer in the first contact window 220 as a back layer to be connected.

[0082] Only the end face of the open structure of the hollow shell formed by the conductive barrier layer is electrically connected to the storage element 230. Therefore, the contact area of ​​the electrical connection between the first contact window 220 and the storage element 230 is very small, which can effectively improve the current density of the electrical contact between the storage element 230 and the first contact window 220, effectively improve the efficiency of current heating, and effectively improve the data read and write efficiency of the storage element 230.

[0083] Moreover, the shape of the first contact window 230 changes little, the process is simple, the manufacturing process is less difficult, and the process can be achieved without adding an additional photomask, resulting in lower production costs.

[0084] Furthermore, by setting the first contact window 220 as the contact window of the present invention, there is no need to set other interconnection structures to reduce the contact area of ​​the electrical connection in order to increase the current density, which can effectively simplify the manufacturing process of the memory cell and reduce the manufacturing cost.

[0085] In some embodiments of the present invention, the storage element 230 is a phase-change memory element, for example, the storage element 230 is a phase-change random access memory (PCRAM), that is, the storage cell is a structure of one transistor plus one phase-change random access memory (1T1PCRAM).

[0086] Specifically, such as Figure 3 As shown, the storage element 230 includes: a phase change layer 231, which is electrically connected to the first contact window 220; and an upper electrode 232, which is located on the surface of the phase change layer 231 away from the first contact window 220.

[0087] The phase change layer 231, under the Joule heating effect of the current transmitted through the first contact window 220, transforms between a crystalline state and an amorphous state, exhibiting different resistivities to achieve data storage.

[0088] Specifically, the phase change layer 231 is electrically connected to the first contact window 220. For example, the phase change layer 231 is in direct contact with the end face of the open structure of the hollow shell formed by the conductive barrier layer in the first contact window 220.

[0089] In the first contact window 220, only the end face of the open structure of the hollow shell formed by the conductive barrier layer is electrically connected to the phase change layer 231. The contact area of ​​the electrical connection is very small, which can effectively improve the current density of the electrical contact, improve the current heating efficiency, effectively reduce the energy consumption required for the phase change layer 231 to switch between the crystalline and amorphous states, and reduce the energy consumption of the storage unit.

[0090] The upper electrode 232 is used to connect the phase change layer 231 to the external circuit.

[0091] The upper electrode 232 is located on the side of the phase change layer 231 away from the first contact window 220 and is electrically connected to the phase change layer 231. Specifically, the upper electrode 232 is located on the surface of the phase change layer 231 away from the first contact window 220.

[0092] Specifically, the upper electrode 232 can be made of titanium nitride. In other embodiments, the upper electrode 232 can also be made of other conductive materials.

[0093] It should be noted that in the foregoing embodiments, the switching device 210 in the storage unit is a transistor switching device, and the storage unit has a structure of one transistor plus one storage element, such as a structure of one transistor plus one phase-change memory unit (1T1PCRAM). In other embodiments of the present invention, the switching device may also be other types of switching devices.

[0094] It should also be noted that, in the memory cell, a dielectric material is formed on the substrate to achieve electrical isolation. Specifically, the dielectric material fills the space between the gate structure 211, the first contact window 220, the second contact window 240, the third contact window 250, the first metal MO2, the bit line BL2, and the memory element 230. For clarity, Figure 3 The medium material is not shown in the document.

[0095] refer to Figure 4 and Figure 5 The diagram shows structural schematics of some other embodiments of the storage unit of the present invention; wherein Figure 4 These are three-dimensional structural diagrams of other embodiments of the storage unit; Figure 5 yes Figure 4 The schematic diagram shows a cross-sectional structure along line A1A2 in the embodiment of the storage unit shown.

[0096] The similarities to the foregoing embodiments will not be repeated here. The difference from the foregoing embodiments is that, in some embodiments of the present invention, the switching device 310 is a diode switching device.

[0097] like Figure 4 and Figure 5 As shown, in some embodiments, the switching device 310 includes: a first doped layer 312, which is electrically connected to the first contact window 320; and a second doped layer 313, which is located on the side of the first doped layer 312 away from the first contact window 320, and the doping type of the second doped layer 313 is different from that of the first doped layer 312.

[0098] Specifically, the doping type of the second doped layer 313 is different from that of the first doped layer 312. For example, the first doped layer 312 can be a P-type doped layer, and the second doped layer 313 can be an N-type doped layer. The first doped layer 312 and the second doped layer 313 are in contact to form a diode.

[0099] In some examples, the second doped layer 313 is located within a substrate 302 between adjacent isolation structures 303 in the substrate 301; the first doped layer 312 is located on the surface of the second doped layer 313; and the surface of the first doped layer 312 also has a connecting layer 314.

[0100] In the first contact window 320, the bottom surface of the sealed structure of the hollow shell formed by the conductive barrier layer is in direct contact with the connecting layer 314 on the surface of the first doped layer 312; the end face of the open structure of the hollow shell formed by the conductive barrier layer is in direct contact with the surface of the phase change layer 331 of the storage element 330.

[0101] It should be noted that the storage element 330 is a phase-change memory element, that is, the storage element is a structure of one diode plus one phase-change random access memory (1D1PCRAM). In other embodiments of the present invention, the storage element may also be other types of storage elements, such as resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), or magnetic random access memory (MRAM).

[0102] It should also be noted that, in the memory cell, a dielectric material is formed on the substrate to achieve electrical isolation. Specifically, the dielectric material fills the space between the first contact window 320, the second contact window 340, the third contact window 350, the first metal MO3, the bit line BL3, and the memory element 330. For clarity, Figure 4 and Figure 5 The medium material is not shown in the document.

[0103] In addition, the present invention also provides a storage device.

[0104] refer to Figure 3 The diagram shows a three-dimensional structural schematic of some embodiments of the storage device of the present invention.

[0105] The storage device includes:

[0106] A storage array, comprising storage units, wherein the storage units are storage units of the present invention, the storage units are arranged in an array along an intersecting first direction x and second direction y, wherein the first direction x and the second direction y are both perpendicular to a third direction z, the third direction z being the direction of the line connecting the sealed structure and the open structure.

[0107] The technical solution of the storage device embodiment is described in detail below with reference to the accompanying drawings.

[0108] The storage unit is the storage unit of this invention. The specific technical solution of the storage unit is described in the aforementioned embodiment of the contact window; further details are omitted here.

[0109] Specifically, the intersecting first direction x and second direction y are both parallel to the surface of the substrate 201, and the third direction z is perpendicular to the surface of the substrate 201; the storage cells are arranged in an array within the substrate 201 along the first direction x and the second direction y.

[0110] In the substrate 201, the isolation structure 203 extends along the second direction y, and a plurality of isolation structures 203 are arranged in parallel along the first direction x; in addition, the isolation structure 203 also extends between adjacent memory cells along the second direction y.

[0111] In some embodiments, the switching device 210 in the memory cell is a transistor switching device; the switching device 210 includes: a gate structure 211; a first doped layer 212 and a second doped layer 213, which are located in a plane perpendicular to the third direction z, i.e., in a plane parallel to the surface of the substrate 201, with the first doped layer 212 and the second doped layer 213 located on both sides of the gate structure 211, and the first doped layer 212 being electrically connected to the first contact window 320; the gate structure 211 of the switching device 210 of the memory cell arranged along the second direction y extends and connects.

[0112] Specifically, such as Figure 3 As shown, the gate structure 211 of the switching device 210 extends along the second direction y and spans the isolation structure 203 between adjacent memory cells along the second direction y. The gate structures 211 of the switching device 210 in adjacent memory cells along the second direction y are connected.

[0113] In some embodiments of the present invention, the storage device further includes: a first metal MO2, the first metal MO2 extending along the second direction y, and the first metal MO2 being electrically connected to the other end of the switching device 210 through a third contact window 250.

[0114] The first metal M02 is suitable for connecting the storage unit to an external circuit.

[0115] The first metal M02 is located on and electrically connected to the second doped layer 213 of the switching device 210. For example, the first metal M02 extends along the second direction y, spanning over the second doped layer 213 of the switching device 210 in one of the plurality of memory cells.

[0116] The third contact window 250 is located on the second doped layer 213 of the switching device 210; specifically, one end of the third contact window 250 is in contact with the connection layer on the second doped layer 213, and the other end of the third contact window 250 is in contact with the first metal MO2.

[0117] In some embodiments, the second doped regions 213 of the memory cells arranged along the second direction y are connected to the same first metal M02. For example... Figure 3 As shown, a third contact window 250 is provided on the second doped layer 213 of the switching device 210 in each of the memory cells; the third contact window 250 on the second doped layer 213 of the switching device in the plurality of memory cells arranged along the second direction y is in contact with the same first metal MO2.

[0118] It should be noted that in some embodiments of the present invention, the shape of the first contact window 220 in the storage unit is the same as or similar to the shape of the third contact window 250, that is, the shape of the hollow shell surrounded by the conductive barrier layer in the first contact window 220 is the same as or similar to the shape of the third contact window 250; therefore, the manufacturing process of the first contact window 220 is similar to that of the third contact window 250. The shape of the first contact window 230 changes little, the manufacturing process is simple, the manufacturing process is less difficult, and the process can be realized without adding an additional photomask, resulting in lower production costs.

[0119] Continue to refer to Figure 3 In some embodiments of the present invention, the storage device further includes a bit line BL2, which extends along the first direction x and is electrically connected to the storage cell through a second contact window 240.

[0120] The bit line BL2 is suitable for connecting the memory cell to an external circuit.

[0121] In some embodiments, the bit line BL2 is located on the side of the memory element 230 away from the first contact window 320. The first contact window 232 is located below the memory element 230, and the bit line BL2 is located above the memory element 230 and electrically connected to the upper electrode 232 of the memory element 230. For example, the bit line BL2 extends along the first direction x, spanning above the memory element 230 of a plurality of memory cells.

[0122] The second contact window 240 is located on the upper electrode 232 of the storage element 230; specifically, one end of the second contact window 240 is in contact with the upper electrode 232 of the storage element 230, and the other end of the second contact window 240 is in contact with the bit line BL2.

[0123] In some embodiments, memory cells arranged along the first direction x are connected to the same bit line BL2. For example... Figure 3As shown, at least one second contact window 240 is provided on the storage element 230 in the storage cell; the second contact window on the storage element 230 in the plurality of storage cells arranged along the first direction x is in contact with the same bit line BL2.

[0124] It should be noted that in some embodiments of the present invention, the shape of the first contact window 220 in the storage unit is the same as or similar to the shape of the second contact window 240, that is, the shape of the hollow shell surrounded by the conductive barrier layer in the first contact window 220 is the same as or similar to the shape of the second contact window 240; therefore, the manufacturing process of the first contact window 220 is similar to that of the second contact window 240. The shape of the first contact window 230 changes little, the manufacturing process is simple, the manufacturing process is less difficult, and the process can be realized without adding an additional photomask, resulting in lower production costs.

[0125] It should also be noted that, in some embodiments, the switching device 210 in the memory cell is a transistor switching device; the first doped layer 212 and the second doped layer 213 of the switching device 210 are located on both sides of the gate structure 211 along the first direction x; the memory elements of two adjacent memory cells along the first direction x are extended and connected.

[0126] Specifically, in some embodiments, the two storage cells along the first direction x are a first storage cell 205 and a second storage cell 206, respectively; the storage element 230 of the first storage cell 205 and the storage element 230 of the second storage cell 206 are extended and connected; the first metal MO2 electrically connected to the first storage cell 205 and the first metal MO2 electrically connected to the second storage cell 206 are respectively located on both sides of the gate structure 211 of the switching device 210 of the first storage cell 205 and the gate structure 211 of the switching device 210 of the second storage cell 206 along the first direction x.

[0127] like Figure 3 As shown, the first memory cell 205 and the second memory cell 206 are arranged adjacent to each other along a first direction x; in the first memory cell 205, the first doped layer 212 is located on the side of the gate structure 211 closer to the second memory cell 206, and the second doped layer 213 is located on the side of the gate structure 211 away from the second memory cell 206; in the second memory cell 206, the first doped layer 212 is located on the side of the gate structure 211 closer to the first memory cell 205, and the second doped layer 213 is located on the side of the gate structure 211 away from the first memory cell 205.

[0128] One of the first metals M02 is located above the second doped layer 213 of the first memory cell 205 and is electrically connected to the second doped layer 213 of the first memory cell 205; one of the first metals M02 is located above the second doped layer 213 of the second memory cell 206 and is electrically connected to the second doped layer 213 of the second memory cell 206; therefore, the first metal M02 electrically connected to the second doped layer 213 of the first memory cell 205 is located on the side of the gate structure 211 of the first memory cell 205 away from the second memory cell 206; the first metal M02 electrically connected to the second doped layer 213 of the second memory cell 206 is located on the side of the gate structure 211 of the second memory cell 206 away from the first memory cell 205.

[0129] In the first storage cell 205, the phase change layer 231 and the upper electrode 232 of the storage element 230 both extend toward the second storage cell 206; in the second storage cell 206, the phase change layer 231 and the upper electrode 232 of the storage element 230 both extend toward the first storage cell 205; the phase change layer 231 and the upper electrode 232 of the storage element 230 in the first storage cell 205 are integrally connected with the phase change layer 231 and the upper electrode 232 of the storage element 230 in the second storage cell 206.

[0130] It should be noted that in the foregoing embodiments, the memory cell is a structure of one transistor plus one memory element, such as a structure of one transistor plus one phase-change memory cell (1T1PCRAM). In other embodiments of the present invention, the switching device may also be other types of switching devices.

[0131] refer to Figure 4 and Figure 5 The diagram illustrates structural schematics of some other embodiments of the storage device of the present invention; wherein... Figure 4 These are three-dimensional structural diagrams of other embodiments of the storage device; Figure 5 yes Figure 4 A schematic cross-sectional view of the storage device embodiment shown along line A1A2.

[0132] The similarities to the foregoing embodiments will not be repeated here. The difference from the foregoing embodiments is that, in some embodiments of the present invention, the switching device 310 in the storage unit is a diode switching device.

[0133] like Figure 4 and Figure 5As shown, in some embodiments, the switching device 310 includes: a first doped layer 312, which is electrically connected to the first contact window 320; and a second doped layer 313, which is located on the side of the first doped layer 312 away from the first contact window 320, and the doping type of the second doped layer 313 is different from that of the first doped layer 312.

[0134] Specifically, such as Figure 3 As shown, the second doped layer 313 and the first doped layer 312 are stacked sequentially along the third z-axis.

[0135] In some embodiments, the switching device 310 further includes: an interconnect layer 315 located on the side of the second doped layer 313 away from the first doped layer 312; the interconnect layer 315 of the switching device 310 of the memory cells arranged along the second direction y extends and connects.

[0136] Specifically, the interconnect layer 315 is located within the substrate 301 below the second doped layer 313, and the second doped layer 313 is located on the surface of the interconnect layer 315; the bottom surface of the second doped layer 313 is in contact with the surface of the interconnect layer 315. For example, the interconnect layer 315 extends along a second direction y; the interconnect layers 315 of the memory cells arranged along the second direction y are integrally connected.

[0137] In some embodiments, the storage device further includes: an interconnect activation layer 307 along the second direction y, the interconnect activation layer 307 being located on one side of the storage cells arranged along the second direction y; an interconnect layer 315 extending to the location of the interconnect activation layer 307 and electrically connected to the interconnect activation layer 307; and a first metal MO3 located on the side of the interconnect activation layer 307 away from the interconnect layer 315, and one end of the first metal MO3 along the second direction y being electrically connected to the interconnect activation layer 307 through a third contact window 350.

[0138] Specifically, the interconnect activation layer 307 is located on one side of a column of memory cells arranged along the second direction y. Each column of memory cells arranged along the second direction y is provided with the interconnect activation layer 307. Different interconnect activation layers 307 are provided on the same side of different columns of memory cells arranged along the second direction y.

[0139] Furthermore, the interconnect layer 315 extends to the location of the interconnect activation layer 307 and is electrically connected to the interconnect activation layer 307. Specifically, the interconnect activation layer 307 is located on the surface of the extended interconnect layer 315 and is in contact with the surface of the interconnect layer 315.

[0140] For example, in a column of memory cells arranged along the second direction y, the interconnect layers 315 of the switching devices 310 of different memory cells extend and connect to one side of the column of memory cells; the interconnect activation layer 307 is located on the surface of the interconnect layer 315 extending to one side of the column of memory cells.

[0141] It should be noted that the interconnect activation layer 307 is located on the surface of the extended interconnect layer 315 and is in the same layer as the stack of the second doped layer 313 and the first doped layer 312 of the switching device 310.

[0142] In some embodiments, the first metal M03 is located on the side of the interconnect activation layer 307 away from the interconnect layer 315, and one end of the first metal M03 along the second direction y is electrically connected to the interconnect activation layer 307 through a third contact window 350.

[0143] Specifically, the first metal M03 is located on the interconnect activation layer 307 and is electrically connected to the interconnect activation layer 307 through the third contact window 350. For example... Figure 4 As shown, one end of the third contact window 350 is in contact with the surface connection layer of the interconnect activation layer 307; the other end of the third contact window 350 is in contact with the first metal M03.

[0144] The first metal M03 extends from the top of the interconnect activation layer 307 along the second direction y in a direction away from the plurality of memory cells; one end of the first metal M03 near the memory cell is electrically connected to the third contact window 350.

[0145] Continue to refer to Figure 4 and Figure 5 In the storage device, the bit line BL3 is located on the side of the storage element 330 away from the first contact window 320, and is electrically connected to the upper electrode 332 of the storage element 330 through the second contact window 340.

[0146] Multiple memory cells arranged along the first direction x are connected to the same bit line BL3 extending along the first direction x. The surface of the upper electrode 332 of the memory element 330 in the multiple memory cells arranged along the first direction x is provided with a second contact window 340; the other end of the multiple second contact windows 340 is in contact with the same bit line BL3 extending along the first direction x.

[0147] Accordingly, the present invention also provides a method for manufacturing a storage device.

[0148] refer to Figures 6 to 16 The diagram shows a schematic representation of the structure of each step in some embodiments of the storage device manufacturing method of the present invention.

[0149] The manufacturing method includes:

[0150] A switching device is formed; a first contact window is formed, the first contact window being the contact window of the present invention, one end of the first contact window being electrically connected to one end of the switching device; a storage element is formed, the storage element being located on the side of the first contact window away from the switching device, the storage element being electrically connected to the other end of the first contact window.

[0151] The technical solution of the storage device embodiment is described in detail below with reference to the accompanying drawings.

[0152] In some embodiments, the manufacturing method of the present invention is suitable for manufacturing the storage device of the present invention. Specific technical solutions for the manufacturing method can be found in the aforementioned embodiments of the storage device. Further details of the present invention will not be repeated here.

[0153] refer to Figures 6 to 10 First, a switching device 410 is formed (such as...) Figure 10 (As shown).

[0154] In some embodiments of the present invention, in the step of forming the switching device 410, a transistor switching device 410 is formed, that is, the switching device 410 is a transistor switching device. The step of forming the switching device 410 is a logic front-end transistor process.

[0155] In some embodiments, the step of forming the switching device 410 is a standard CMOS process. The steps of forming the switching device 410 include: Figure 6 As shown, a substrate 401 is formed; as Figure 7 As shown, an active region 404 is formed in the substrate 401; as Figure 8 As shown, a gate structure 411 is formed on the active region 404; as Figure 9 As shown, a first doped layer 412 and a second doped layer 413 are formed in the active regions 404 on both sides of the gate structure 411; as Figure 10 As shown, interconnecting layers 414 are formed on the first doped layer 412 and the second doped layer 413, respectively.

[0156] Specifically, such as Figure 6 As shown, the step of forming the substrate 401 includes: providing a substrate 402; and forming an isolation structure 403 within the substrate 402. The step of forming the isolation structure 403 within the substrate 402 includes: etching the substrate 402 to form an isolation opening within the substrate 402; depositing a dielectric material into the isolation opening, the dielectric material filling the isolation opening and covering the surface of the substrate 402; and planarizing the dielectric material to form an isolation structure 403 with its top surface flush with the surface of the substrate 402.

[0157] Specifically, such as Figure 7 As shown, the step of forming an active region 404 in the substrate 401 includes: ion doping the substrate 402 between the isolation structures 403 to form the active region 404; for example, the substrate 402 between the isolation structures 403 can be ion doped by ion implantation; in other embodiments, the active region 404 can also be formed by other ion doping methods.

[0158] Specifically, such as Figure 8 As shown, the step of forming a gate structure 411 on the active region 404 includes: forming a gate dielectric material and a gate electrode material on the substrate 401; patterning the gate dielectric material and the gate electrode material to form a gate dielectric layer and a gate electrode; forming a sidewall structure on the sidewalls of the gate dielectric layer and the gate electrode, wherein the gate structure includes: a first sidewall located on the surface of the sidewall of the gate electrode and the gate dielectric layer and a second sidewall located on the sidewall of the first sidewall, the first sidewall further extending between the second sidewall and the substrate 401.

[0159] Specifically, such as Figure 9 As shown, the steps of forming a first doped layer 412 and a second doped layer 413 in the active regions 404 on both sides of the gate structure 411 include: lightly doping both sides below the gate structure 411 to form a drain lightly doped (LDD); after forming the drain lightly doped, forming the first doped layer 412 and the second doped layer 413 in the active regions 404 on both sides of the gate structure 411, respectively.

[0160] Specifically, such as Figure 10 As shown, the step of forming a connection layer 414 on the first doped layer 412 and the second doped layer 413 includes: forming a metal layer material on the surface of the substrate 401 and the gate structure 411; performing an annealing process to react the metal material with silicon to form the connection layer 414, wherein the connection layer 414 is located on the surface of the first doped layer 412, the second doped layer 413 and the gate electrode, respectively.

[0161] After forming the switching device 410, refer to Figure 11 A first contact window 420 is formed, which is the contact window of the present invention, and one end of the first contact window 420 is electrically connected to one end of the switching device 410.

[0162] It should be noted that, after forming the switching device 410 and before forming the first contact window 420, the manufacturing method further includes: forming a dielectric material on the substrate 401, the dielectric material covering the substrate 401 and the switching device 410. For clarity, Figures 11 to 16The medium material is not shown in the diagram. Therefore, in the step of forming the first contact window 420, the first contact window 420 penetrates the medium material.

[0163] In some embodiments of the present invention, such as Figures 12 to 14 As shown, the steps for forming the first contact window 420 include: Figure 12 As shown, a contact opening is formed, which penetrates the dielectric material 405, and the bottom of the contact opening exposes the connecting layer 414 on the first doped layer 412 (e.g., ...). Figure 11 (As shown); a conductive barrier layer 421 is formed, which covers the sidewalls and bottom of the contact opening; a filler metal 422 is formed in the contact opening where the conductive barrier layer 421 is formed on the sidewall, and the top surface of the filler metal 422 is flush with the top surface of the conductive barrier layer 421 covering the sidewalls of the contact opening; as shown Figure 13 As shown, the fill metal 422 is etched back, and the top surface of the remaining fill metal 422 is lower than the top surface of the conductive barrier layer 421 covering the sidewall of the contact opening. The top surface of the remaining fill metal 422 and the conductive barrier layer 421 covering the sidewall of the contact opening form a remaining opening 429 on the remaining fill metal 422; as shown Figure 14 As shown, the remaining opening 429 is filled with insulating material 423, the top surface of which is flush with the top surface of the conductive barrier layer 421 covering the sidewall of the contact opening.

[0164] In the step of forming the contact opening, the contact opening can be formed by photolithography (i.e., exposure and development) and etching.

[0165] In the step of forming the conductive barrier layer 421, the conductive barrier layer 421 can be formed by one of the deposition methods of atomic layer deposition, chemical vapor deposition and physical vapor deposition, or by other film deposition methods.

[0166] In the step of forming the filler metal 422, the filler metal 422 can be formed by one of the deposition methods of atomic layer deposition, chemical vapor deposition, and physical vapor deposition, or by other material deposition methods. For example, the step of forming the filler metal 422 includes: depositing a metal material in a contact opening in which the conductive barrier layer 421 is formed on the sidewall, the metal material also covering the top surface of the dielectric material 405; removing the metal material above the top surface of the dielectric material 405, forming a filler metal 422 with its top surface flush with the top surface of the conductive barrier layer 421 covering the sidewall of the contact opening, wherein the metal material above the top surface of the dielectric material 405 can be removed by at least one of etching and planarization.

[0167] In the step of filling the insulating material 423, the insulating material can be formed in the remaining opening 429 by one of the deposition methods of atomic layer deposition, chemical vapor deposition and physical vapor deposition, and the insulating material also covers the top surface of the dielectric material 405; the insulating material above the top surface of the dielectric material 405 is removed to form an insulating material 423 with the top surface flush with the top surface of the conductive barrier layer 421 covering the sidewall of the contact opening, wherein the insulating material above the top surface of the dielectric material 405 can be removed by at least one of etching and planarization.

[0168] Continue to refer to Figure 11 In some embodiments of the present invention, in the step of forming the first contact window 420, the first contact window 420 located on the first doped layer 412 and the third contact window 450 located on the second doped layer 413 are formed.

[0169] The first contact window 420 and the third contact window 450 are formed in the same process. The first contact window 420 can be manufactured without the need for an additional photomask, which can effectively reduce the difficulty and cost of forming the first contact window 420.

[0170] Specifically, the steps of forming the first contact window 420 on the first doped layer 412 and the third contact window 450 on the second doped layer 413 include: forming a plurality of contact openings that penetrate the dielectric material, with the bottom of a portion of the contact openings exposing the connection layer 414 on the first doped layer 412 and the bottom of a portion of the contact openings exposing the connection layer 414 on the second doped layer 413; forming a conductive barrier layer in each contact opening that covers the sidewalls and bottom of the contact opening; forming a filler metal in the contact opening where the conductive barrier layer is formed on the sidewall, with the top surface of the filler metal flush with the top surface of the conductive barrier layer covering the sidewalls of the contact opening; and the conductive barrier layer and filler metal on the connection layer 414 on the surface of the second doped layer 413 being suitable for forming the third contact window 450.

[0171] A protective layer is formed on the third contact window 450, exposing the fill metal on the connection layer 414 on the surface of the first doped layer 412. After forming the protective layer, in the step of etching back the fill metal 422, only the fill metal on the connection layer 414 on the surface of the first doped layer 412 is etched back to form the remaining opening 429. An insulating material 423 is filled into the remaining opening 429 to form the first contact window 420. The step of etching back the fill metal 422 can be performed using a photomask-free etching method.

[0172] Next, refer to Figure 15 A storage element 430 is formed, which is located on the side of the first contact window 420 away from the switching device 410, and the storage element 430 is electrically connected to the other end of the first contact window 420.

[0173] Specifically, the steps of forming the storage element 430 include: forming a phase change layer 431 on the first contact bed 420; and forming an upper electrode 432 on the phase change layer 431. For example, at least one of the steps of forming the phase change layer 431 and forming the upper electrode 432 can be achieved through a combination of material deposition and patterning.

[0174] like Figure 15 As shown, in some embodiments of the present invention, the manufacturing method further includes: forming a first metal MO4, the first metal MO4 extending along a second direction y, and the first metal MO4 being electrically connected to the other end of the switching device 410 through a third contact window 450.

[0175] In the step of forming the first metal MO4, the first metal MO4 can be formed by photolithography, etching, and material deposition. Specifically, the step of forming the first metal MO4 includes: forming a trench in a dielectric material, the bottom of the trench exposing the third contact window 450; and forming the first metal MO4 within the trench.

[0176] The step of forming the first metal MO4 in the trench includes: filling the trench with a metal material that covers the top surface of the dielectric material; removing the metal material above the top surface of the dielectric material to form the first metal MO4 in the trench; for example, the metal material above the top surface of the dielectric material can be removed by etching or planarization.

[0177] It should be noted that in some embodiments, the first metal M04 is formed after the storage element 430 is formed; in other embodiments, the storage element may be formed after the first metal is formed.

[0178] It should also be noted that after the storage element 430 and the first metal MO4 are formed, a dielectric material is formed on the storage element 430 and the first metal MO4. Figure 15 The medium material is not shown in the image for clarity.

[0179] In some embodiments of the present invention, the manufacturing method further includes: forming a bit line BL4, the bit line BL4 extending along a first direction x, and the bit line BL4 being electrically connected to the memory cell through a second contact window 440.

[0180] It should be noted that a dielectric material is formed on the storage element 430 and the first metal M04. Figure 16 The medium material is not shown in the image for clarity.

[0181] like Figure 16 As shown, before forming the bit line BL4, a second contact window 440 is formed that penetrates the dielectric material. Specifically, the steps of forming the second contact window 440 include: forming a contact opening that penetrates the dielectric material and exposes the upper electrode 432 of the memory element 430 at the bottom of the contact opening; and forming the second contact window 440 in the contact opening.

[0182] In the step of forming the bit line BL4, the bit line BL4 can be formed by photolithography, etching, and material deposition. Specifically, the step of forming the bit line BL4 includes: forming a trench in a dielectric material, the bottom of the trench exposing the second contact window 440; and forming the bit line BL4 within the trench.

[0183] The step of forming the bit line BL4 in the trench includes: filling the trench with a metal material that covers the top surface of the dielectric material; removing the metal material above the top surface of the dielectric material to form the bit line BL4 in the trench; for example, the metal material above the top surface of the dielectric material can be removed by etching or planarization.

[0184] It should be noted that in the foregoing embodiments, the switching device 410 is a transistor switching device, and the switching device 410 is fabricated using logic front-end transistor technology. In other embodiments of the present invention, the switching device may also be other types of switching devices, and the switching device may also be fabricated using other processes.

[0185] refer to Figures 17 to 29 The diagram shows structural schematics of various steps in other embodiments of the storage device manufacturing method of the present invention.

[0186] The similarities to the foregoing embodiments will not be repeated here. The difference lies in that, in some embodiments of the present invention, a diode switching device is formed in the step of forming the switching device; the switching device can be fabricated using a dual-channel diode process.

[0187] refer to Figures 17 to 23 This forms the switching device 510.

[0188] In some embodiments, the step of forming the switching device 510 is a dual-channel diode process. The steps of forming the switching device 510 include: Figures 17 to 20 As shown, substrate 501 is formed; as Figure 21 As shown, a second doped layer 513 and a first doped layer 512 are formed; as Figure 23 As shown, a connection layer 514 is formed on the first doped layer 512.

[0189] For example, the steps of forming the substrate 501 include: Figure 17 As shown, a substrate 502 is provided; a first prefabricated layer 515a and a second prefabricated layer 513a located on the first prefabricated layer 515a are formed within the substrate; as shown Figure 18 As shown, a deep trench isolation (DTI) precursor 503a is formed within the substrate 502. The deep trench isolation precursor 503a extends along a second direction y, and a plurality of deep trench isolation precursors 503a are arranged in parallel along a first direction x. A first prefabricated layer 515a between adjacent deep trench isolation precursors 503a is suitable for forming an interconnect layer 515; as Figure 19 As shown, a second trench 503c extending along a first direction x is formed within the second prefabricated layer 513a, the bottom of the second trench 503c exposing the interconnect layer 515, and a plurality of second trenches 503c are parallel to each other along a second direction y. The second prefabricated layer 513a between adjacent second trenches 503c is suitable for forming a second prefabricated layer 513b; as Figure 20 As shown, a shallow trench isolation precursor 503b (STI) is formed within the second trench 503c. The shallow trench isolation precursor 503b and the deep trench isolation precursor 503a are suitable for the isolation structure 503; as Figure 21 As shown, a first doped layer 512 is formed in the second prefabricated layer 513b, and the remaining second prefabricated layer 513b below the first doped layer 512 is suitable for forming the second doped layer 513.

[0190] The step of forming the first prefabricated layer 515a and the second prefabricated layer 513a in the substrate includes: performing a first doping on the substrate to form the first prefabricated layer 515a; performing a second doping on the substrate to form the second prefabricated layer 513a; for example, in the step of performing the second doping on the substrate, the substrate is lightly doped with N to form the second prefabricated layer 513a.

[0191] In some embodiments, the step of forming a diode switching device further includes: Figure 22 As shown, an interconnect activation layer 507 is formed along the second direction y, and the interconnect activation layer 507 is located on one side of the memory cells arranged along the second direction y.

[0192] In some specific embodiments, in the step of forming the first doped layer 512 and the second doped layer 513, a portion of the second prefabricated layers 513b arranged along the second direction y are doped to form the first doped layer 512 and the second doped layer 513, and at least one second prefabricated layer 513b is left on one side of the column of second doped layers 513 arranged along the second direction y; in the step of forming the interconnect activation layer 507, the second prefabricated layers 513b on one side of the column of second doped layers 513 arranged along the second direction y are doped to form the interconnect activation layer 507.

[0193] like Figure 23 As shown, in some embodiments, the step of forming the diode switching device further includes forming a connection layer 514 on the first doped layer 512. For example, in the step of forming the connection layer 514 on the first doped layer 512, the connection layer 514 is formed on both the first doped layer 512 and the interconnect activation layer 507.

[0194] refer to Figure 24 and Figure 25 A first contact window 520 is formed, as described in any one of claims 1 to 12, wherein one end of the first contact window 520 is electrically connected to one end of the switching device 510.

[0195] In some embodiments of the present invention, in the step of forming the first contact window 520, a third contact window 550 is formed located on the interconnect activation layer 507 (e.g., Figure 24 (as shown) and the first contact layer 520 located on the first doped layer 512 (as shown) Figure 25 (As shown).

[0196] In some embodiments, after forming a third contact window on the surface of the interconnect layer 514 on the interconnect activation layer 507, a first contact window 520 is formed on the surface of the interconnect layer 514 on the first doped layer 512.

[0197] In other embodiments of the present invention, a third contact window may be formed on the surface of the interconnect activation layer after a first contact window is formed on the surface of the interconnect activation layer; or, a first contact window on the surface of the interconnect activation layer and a third contact window on the surface of the interconnect activation layer may be formed simultaneously.

[0198] It should be noted that in some embodiments of the present invention, such as Figure 26 As shown, after the first contact window 520 is formed, a first metal M05 is formed, and the first metal M05 is electrically connected to the interconnect activation layer 507 through the third contact window 550.

[0199] refer to Figure 27 A storage element 530 is formed, which is located on the side of the first contact window 520 away from the switching device 510, and the storage element 530 is electrically connected to the other end of the first contact window 520.

[0200] It should be noted that, in some embodiments of the present invention, after the storage element 530 is formed, as... Figure 28 As shown, a second contact window 540 is formed on the upper electrode 532 of the storage element 530; as Figure 29 As shown, bit line BL5 is formed on the second contact window 540.

[0201] In summary, the filler metal only fills a portion of the hollow shell formed by the conductive barrier layer. On one side of the open structure, the filler metal is separated from the back layer to be connected. The area of ​​the contact window and the back layer to be connected is only the end face of the conductive barrier layer. The contact area between the contact window and the back layer to be connected is small, and the shape of the contact window changes little. This can simplify the manufacturing process, reduce the number of photomasks and process steps, reduce the difficulty of the process, and reduce production costs while reducing the contact area.

[0202] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A contact window, characterized in that, include: A conductive barrier layer is provided, which forms a hollow shell. One end of the hollow shell is a sealed structure with a bottom surface, and the bottom surface of the sealed structure is electrically connected to the front layer component to be connected. The other end of the hollow shell is an open structure without a bottom surface, and the end face of the open structure is electrically connected to the rear layer component to be connected. A filler metal that fills a portion of the hollow shell formed by the conductive barrier layer.

2. The contact window as described in claim 1, characterized in that, The filler metal fills the portion of the hollow shell formed by the conductive barrier layer near the front layer to be connected.

3. The contact window as described in claim 1, characterized in that, Also includes: An insulating material is used to fill the space between the filler metal and the subsequent layer to be connected.

4. The contact window as described in claim 3, characterized in that, The surface of the insulating material facing the back layer to be connected is in contact with the back layer to be connected.

5. The contact window as described in claim 3, characterized in that, In the direction of the line connecting the filler metal and the back layer to be connected, the thickness of the insulating material is less than 1 / 2 of the distance between the filler metal and the back layer to be connected.

6. The contact window as described in claim 3, characterized in that, The insulating material includes at least one of silicon nitride and silicon oxide.

7. The contact window as claimed in claim 1, characterized in that, The conductive barrier layer has a uniform thickness.

8. The contact window as claimed in claim 1, characterized in that, The thickness of the conductive barrier layer is in the range of 1 nm to 20 nm.

9. The contact window as claimed in claim 1, characterized in that, The material of the conductive barrier layer includes at least one of titanium nitride, tantalum nitride, titanium, tantalum, and ruthenium.

10. The contact window as claimed in claim 1, characterized in that, The ratio of the thickness of the filler metal to the depth of the hollow shell is less than 2 / 3.

11. The contact window as claimed in claim 1, characterized in that, The filler metal materials include: tungsten, copper, and aluminum.

12. A storage unit, characterized in that, include: Switching devices; A first contact window, as described in any one of claims 1 to 11, wherein one end of the first contact window is electrically connected to one end of the switching device; A storage element is located on the side of the first contact window away from the switching device, and the storage element is electrically connected to the other end of the first contact window.

13. The storage cell as claimed in claim 12, characterized in that, The storage element is a phase-change storage element; The storage element includes: Phase change layer, wherein the phase change layer is electrically connected to the first contact window; Upper electrode, the upper electrode being located on the surface of the phase change layer away from the first contact window.

14. The storage cell as claimed in claim 12, characterized in that, The switching device is a diode switching device; The switching device includes: A first doped layer, wherein the first doped layer is electrically connected to the first contact window; A second doped layer is located on the side of the first doped layer away from the first contact window, and the doping type of the second doped layer is different from that of the first doped layer.

15. The storage cell as claimed in claim 12, characterized in that, The switching device is a transistor switching device; The switching device includes: Gate structure; The first doped layer and the second doped layer are located in a plane perpendicular to the line connecting the switching device and the memory element. The first doped layer and the second doped layer are located on opposite sides of the gate structure. The first doped layer is electrically connected to the first contact window.

16. The storage cell as claimed in claim 14 or 15, characterized in that, The switching device further includes a connection layer located between the first doped layer and the first contact window.

17. A storage device, characterized in that, include: A storage array comprising storage cells, wherein the storage cells are arranged in an array along an intersecting first direction and a second direction, wherein the first direction and the second direction are both perpendicular to a third direction, the third direction being the direction of the line connecting the sealed structure and the open structure.

18. The storage device as claimed in claim 17, characterized in that, Also includes: Bit lines, which extend along the first direction, are electrically connected to the memory cells via a second contact window; A first metal extending along the second direction is electrically connected to the other end of the switching device via a third contact window.

19. The storage device as claimed in claim 18, characterized in that, The bit line is located on the side of the storage element away from the first contact window.

20. The storage device as claimed in claim 19, characterized in that, The memory cells arranged along the first direction are connected to the same bit line.

21. The storage device as claimed in claim 17, characterized in that, The switching device is a diode switching device; The switching device includes: A first doped layer, wherein the first doped layer is electrically connected to the first contact window; A second doped layer is located on the side of the first doped layer away from the first contact window, and the doping type of the second doped layer is different from that of the first doped layer.

22. The storage device as claimed in claim 21, characterized in that, The switching device further includes an interconnect layer, the interconnect layer being located on the side of the second doped layer away from the first doped layer; The interconnect layer of the switching devices of the memory cells arranged along the second direction extends and connects.

23. The storage device as claimed in claim 22, characterized in that, Also includes: An interconnect activation layer, along the second direction, is located on one side of the memory cells arranged along the second direction; The interconnect layer extends to the location of the interconnect activation layer and is electrically connected to the interconnect activation layer; The first metal is located on the side of the interconnect activation layer away from the interconnect layer, and one end of the first metal along the second direction is electrically connected to the interconnect activation layer through a third contact window.

24. The storage device as claimed in claim 17, characterized in that, The switching device is a transistor switching device; The switching device includes: Gate structure; The first doped layer and the second doped layer are located in a plane perpendicular to the line connecting the switching device and the memory element. The first doped layer and the second doped layer are located on opposite sides of the gate structure. The first doped layer is electrically connected to the first contact window. The gate structures of the switching devices of the memory cells arranged along the second direction extend and connect.

25. The storage device as claimed in claim 24, characterized in that, The second doped region of the memory cells arranged along the second direction is connected to the same first metal.

26. The storage device as claimed in claim 24, characterized in that, The two storage units along the first direction are the first storage unit and the second storage unit, respectively. The storage elements of the first storage unit and the storage elements of the second storage unit are extended and connected; The first metal electrically connected to the first memory cell and the first metal electrically connected to the second memory cell are respectively located on both sides of the gate structure of the switching device of the first memory cell and the gate structure of the switching device of the second memory cell along the first direction.

27. A method for manufacturing a storage device, characterized in that, include: Forming switching devices; A first contact window is formed, as described in any one of claims 1 to 11, wherein one end of the first contact window is electrically connected to one end of the switching device; A storage element is formed, the storage element being located on the side of the first contact window away from the switching device, and the storage element being electrically connected to the other end of the first contact window.

28. The manufacturing method as described in claim 27, characterized in that, Also includes: A bit line is formed, the bit line extends along a first direction, and the bit line is electrically connected to the memory cell through a second contact window; A first metal is formed, the first metal extends along a second direction, and the first metal is electrically connected to the other end of the switching device through a third contact window.

29. The manufacturing method as described in claim 27, characterized in that, In the step of forming a switching device, a diode switching device is formed; In the step of forming a switching device, an interconnect activation layer is formed along a second direction, the interconnect activation layer being located on one side of the memory cells arranged along the second direction; After the first contact window is formed and before the memory element is formed, a first metal is formed, and the first metal is electrically connected to the interconnect activation layer through a third contact window.

30. The manufacturing method as described in claim 27, characterized in that, In the step of forming a switching device, a transistor switching device is formed; In the step of forming the first contact window, the first contact window located on the first doped layer and the third contact window located on the second doped layer are formed.

31. The manufacturing method as described in claim 30, characterized in that, After the memory element is formed, a first metal is formed; after the first metal is formed, a bit line is formed.

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