A gallium arsenide-based optoelectronic memristor and a preparation method thereof

Abstract

The application discloses a gallium arsenide-based optoelectronic memristor and a preparation method thereof, and belongs to the technical field of semiconductor physics. The optoelectronic memristor disclosed by the application comprises a gallium arsenide substrate without thinning treatment, and an insulating layer is arranged on the upper surface of the gallium arsenide substrate; further comprising an etching through hole, source-drain electrodes, a gate dielectric layer and a gate electrode; the etching through hole penetrates through the insulating layer and exposes the underlying gallium arsenide substrate; the source-drain electrodes are arranged on both sides of the surface of the gallium arsenide substrate exposed in the etching through hole, and there is a spacing between the source-drain electrodes to form a channel region; the gate dielectric layer is deposited above the source-drain electrodes and the channel region; the gate electrode is deposited above the gate dielectric layer and is located directly above the channel region for applying a gate voltage to modulate the channel conductance. The technical problem that the existing method is prone to cause uneven thickness, crystal damage and yield loss is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor physics technology, specifically relating to a gallium arsenide-based photomemristor and its fabrication method. Background Technology

[0002] The exponential growth of artificial intelligence and data-intensive computing workloads is driving a dramatic increase in energy demand for global data centers and edge computing nodes. Meanwhile, the physical separation of computing and storage units in the traditional von Neumann architecture has led to frequent data movement becoming a major bottleneck for power consumption and latency. Furthermore, with Moore's Law slowing down and transistor scaling approaching the physical limits of thermodynamics and quantum tunneling, simply relying on advanced manufacturing processes is no longer sufficient to balance performance leaps with energy efficiency constraints. Neuromorphic computing draws inspiration from biological mechanisms such as massively parallel processing, sparse pulse coding, and synaptic plasticity in the cerebral cortex. It eliminates data movement overhead through in-memory computing arrays and employs an event-driven asynchronous circuit architecture, activating local computation only when triggered by input pulses. This significantly reduces static leakage power consumption, opening a promising alternative path for energy-efficient intelligent processing in the post-Moore's Law era. Among various neuromorphic hardware implementation schemes, optoelectronic devices, due to their inherent synergistic advantages of broadband, low-latency optical signal transmission and flexible electrical control, can integrate functions such as optical synaptic weight updates, optical pulse timing encoding, and electrical readout amplification on a single physical platform. This approach is expected to balance high parallelism, low interconnect crosstalk, and dynamic reconfigurability, thereby further alleviating electrical interconnect bottlenecks and supporting on-chip optical interconnects for ultra-large-scale neuromorphic networks. This hybrid integration scheme not only provides a solid device physical foundation for building next-generation neuromorphic processors with ultra-low power consumption and high computational density, but also helps achieve end-to-end energy consumption optimization from underlying materials and device structures to system architecture.

[0003] Remarkable progress has been made in optoelectronic neuromorphic devices based on two-dimensional materials, but limitations remain, particularly in terms of process compatibility and large-scale manufacturing of optoelectronic heterogeneous integration. To address these issues, traditional three-dimensional materials, with their mature process systems and large-scale manufacturing capabilities, offer a feasible path to the industrialization of neuromorphic devices. Existing silicon-based memristors rely on thinning the top silicon layer of SOI to 20-30 nm. This process demands extremely high etching uniformity, making it difficult to maintain yield in large-scale production. However, this process faces inherent difficulties: traditional methods such as chemical mechanical polishing cannot guarantee nanoscale thickness uniformity; high-energy ion bombardment during plasma etching introduces surface damage layers and crystal defects; and a thickness tolerance of ±5% makes the process window extremely stringent, directly leading to device threshold voltage drift, decreased reliability, and difficulty in maintaining yield in large-scale production. Summary of the Invention

[0004] The purpose of this invention is to provide a gallium arsenide-based opto-memristor, its fabrication method, and its application, in order to solve the technical problems that existing methods easily lead to uneven thickness, crystal damage, and yield loss.

[0005] To achieve the above objectives, the present invention employs the following technical solution: This invention discloses a gallium arsenide-based photomemristor, comprising an unthinned gallium arsenide substrate, wherein an insulating layer is disposed on the upper surface of the gallium arsenide substrate; It also includes etched vias, source / drain electrodes, a gate dielectric layer, and a gate electrode; the etched vias penetrate the insulating layer and expose the underlying gallium arsenide substrate; the source / drain electrodes are disposed on both sides of the gallium arsenide substrate surface exposed within the etched vias, and there is a gap between the source / drain electrodes to form a channel region; The gate dielectric is deposited above the source / drain electrodes and in the channel region; the gate electrode is deposited above the gate dielectric and located directly above the channel region, and is used to apply a gate voltage to modulate the channel conductivity.

[0006] Furthermore, the gallium arsenide substrate has a thickness ≥300 μm and a resistivity ≥10. 7 Ω·cm; The gallium arsenide substrate is a semi-insulating bulk substrate.

[0007] Furthermore, the insulating layer is made of silicon dioxide or silicon nitride; The source / drain electrodes and the gate electrode are each independently selected from chromium / gold composite metal layers or titanium / gold composite metal layers.

[0008] Furthermore, the etched via is formed using an inductively coupled plasma etching process. While etching to form the etched via, the inductively coupled plasma etching process introduces surface states on the exposed gallium arsenide substrate surface, and the dangling bond density and surface state energy level distribution on the gallium arsenide substrate surface are controlled by the etching conditions.

[0009] Furthermore, the material of the gate dielectric layer is selected from alumina, hafnium oxide, or silicon oxide.

[0010] Furthermore, the dimension of the gate electrode in the direction parallel to the width of the channel region is smaller than the channel width between the source and drain electrodes.

[0011] This invention also discloses a method for fabricating a gallium arsenide-based photomemristor, comprising the following steps: An unthinned gallium arsenide substrate is provided, and an insulating layer is subsequently formed on top of the gallium arsenide substrate; The insulating layer is etched to form etched vias that penetrate the insulating layer and expose the underlying gallium arsenide substrate. The etching simultaneously introduces surface states on the exposed gallium arsenide surface. Source and drain electrodes are formed on both sides of the gallium arsenide substrate surface exposed within the etched via, with a gap between the source and drain electrodes to form a channel region; A gate dielectric layer is formed above the source and drain electrodes and above the channel region; A gate electrode is formed above the gate dielectric layer and at a position corresponding to the channel region.

[0012] Furthermore, the insulating layer is formed by chemical vapor deposition; the gate dielectric layer is formed by atomic layer deposition; and the source / drain electrodes and the gate electrode are formed by electron beam evaporation deposition.

[0013] Furthermore, the deposition rate of the chemical vapor deposition method is 10~13 nm / min; the deposition rate of the atomic layer deposition method is 0.10~0.13 nm / cycle.

[0014] Furthermore, when the source / drain electrode and the gate electrode are made of chromium, the deposition rate of the electron beam evaporation deposition method is 0.1~0.3 A / s; when the source / drain electrode and the gate electrode are made of gold, the deposition rate of the electron beam evaporation deposition method is 0.2~0.5 A / s.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a gallium arsenide (GaAs)-based photomemristor. It employs a semi-insulating GaAs bulk substrate without thinning treatment. Surface states are introduced into the GaAs surface through etching in the etched via regions. Channel conductance is then modulated by applying a gate voltage through the gate electrode. This approach bypasses existing technological bottlenecks at the material source, directly using a bulk substrate with a thickness >300 μm without any thinning treatment. This completely eliminates the problems of thickness inhomogeneity, crystal damage, and narrow process windows caused by thinning to 20-30 nm in silicon-based solutions, significantly improving device consistency and scalability. Furthermore, the intrinsic high resistivity of the semi-insulating GaAs substrate is 2-3 orders of magnitude higher than that of intrinsic SOI silicon, resulting in a dark current as low as pA for devices fabricated based on this structure. Simultaneously, the direct bandgap characteristics of GaAs endow the device with far superior light absorption capabilities compared to silicon, supporting a light absorption rate of 0.97 mW / cm². 2 It achieves a responsivity of 3.9 A / W and a resolution of 1.5 × 10⁻⁶ A / W under 532 nm illumination. 12Jones's specific detectivity. Finally, this structural scheme is not only compatible with standard CMOS processes, but also has excellent scalability. Thanks to the high consistency and process window brought by the bulk substrate, a high yield (95.1%) of 2-inch wafer-level, 15×15 array (225 devices) has been successfully fabricated. The neural network built based on the light enhancement / electrical suppression data of a single device has achieved an accuracy of 98.4% and 98.5% in face recognition and motion trajectory recognition tasks, respectively, which fully demonstrates the engineering potential of this structural scheme in optoelectronic fusion neuromorphic computing and large-scale integration.

[0016] Furthermore, this invention specifies that the etched vias are formed by ICP (inductively coupled plasma) etching, and simultaneously introduces defect states such as dangling bonds on the surface during the etching process. The surface states are introduced by the etching process itself, rather than through additional processing steps, resulting in a compact process flow. Moreover, the surface state parameters can be actively controlled by adjusting the etching conditions. This limitation transforms the surface states in the independent claims from passively existing states into designable process variables. The position of the surface state energy level directly determines the potential barrier height that needs to be overcome after the channel carriers are captured and released, thus affecting the persistence and dynamic range of conductivity modulation.

[0017] Furthermore, this invention limits the gate electrode width to be smaller than the channel width between the source and drain electrodes. This geometric limitation avoids direct overlap between the gate electrode and the source / drain electrodes in the vertical direction, reducing the risk of parasitic capacitance and edge leakage. Simultaneously, the narrower gate electrode results in an edge distribution of the electric field generated by the gate voltage along the channel width direction, with different electric field strengths in the central and edge regions. This non-uniform electric field distribution, combined with the spatial distribution of surface states, facilitates finer channel conductance control and forms the structural basis for achieving stable multi-resistivity states during electrical suppression. Attached Figure Description

[0018] Figure 1 This is an overall structural diagram of the gallium arsenide-based photomemristor of the present invention; Figure 2 This is a scanning electron microscope image of the gallium arsenide-based photomemristor of this invention; Figure 3 The responsivity and detectivity of the gallium arsenide-based photomemristor of this invention are shown below; Figure 4 Images of a wafer-level array structure formed using gallium arsenide-based photomemristors and images of the array under an optical microscope; Figure 5 The transfer curves are for 214 devices in the array structure; Figure 6 For the optical enhancement (50 optical pulses) and electrical suppression (50 electrical pulses) of 25 random devices in the array; Figure 7 This invention provides the accuracy of face image recognition simulated using a single device with light enhancement and electrical suppression data. Figure 8 To improve the accuracy of electronic signature trajectory recognition using a single device by simulating data with optical enhancement and electrical suppression.

[0019] Wherein: 1-Gallium arsenide substrate; 2-Insulating layer; 3-Etched via; 4-Source / drain electrode; 5-Gate dielectric; 6-Gate electrode. Detailed Implementation

[0020] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0021] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0022] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0023] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0024] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0025] This invention is the first to propose using a bulk semi-insulating gallium arsenide substrate to directly introduce surface states through ICP etching to achieve the same or even better opto-memristor function without any thinning process, fundamentally overcoming the problems of uneven thickness, crystal damage and yield loss caused by the thinning process.

[0026] This invention discloses a gallium arsenide-based photomemristor, such as... Figure 1 As shown, it includes: Gallium arsenide substrate 1 is a semi-insulating bulk substrate with a thickness greater than 300 μm without thinning treatment. The high resistivity of semi-insulating gallium arsenide enables the dark current of the device to be reduced to the pA level, providing an extremely low noise substrate for photoelectric detection. An insulating layer 2 is deposited on top of the gallium arsenide substrate 1 and is used for electrical isolation between devices; Through-hole 3 is etched using inductively coupled plasma (ICP) etching, penetrating the insulating layer 2 to expose the underlying gallium arsenide substrate 1 and introducing surface states on the exposed gallium arsenide surface. During ICP etching, high-energy ions in the plasma bombard the gallium arsenide surface, breaking surface lattice bonds and forming surface states with a certain density and energy level distribution. By adjusting process parameters such as ICP etching power, gas composition, and bias voltage, the surface dangling bond density and surface state energy level distribution can be controlled. These surface states can capture photogenerated carriers, which is key to realizing the photoelectric memristor function.

[0027] Source and drain electrodes 4 are deposited on both sides of the gallium arsenide substrate 1 exposed in the etched via 3, with a gap in the middle as a channel. Gate dielectric 5 is deposited above the source / drain electrodes 4 and in the channel region; the gate dielectric layer 5 is made of a high dielectric constant material such as alumina, hafnium oxide or silicon oxide; the high dielectric constant gate dielectric can provide sufficient capacitive coupling with a thin physical thickness, thereby enhancing the efficiency of gate voltage in controlling channel conductivity. Gate electrode 6, deposited above gate dielectric 5 and located directly above the channel region, is used to apply a gate voltage to modulate the channel conductance. Gate electrode 6 is made of a composite metal layer such as chromium / gold or titanium / gold.

[0028] Preferably, the gallium arsenide substrate is an unthinned semi-insulating gallium arsenide substrate with a resistivity ≥10. 7 Ω·cm.

[0029] Preferably, the insulating layer 2 is made of insulating oxides such as silicon dioxide or silicon nitride.

[0030] Preferably, the etched via 3 is formed by ICP etching, which simultaneously controls the density of dangling bonds and the surface state energy levels of gallium arsenide.

[0031] Preferably, the source / drain electrode 4 and the gate electrode 6 are composite metal layers such as chromium / gold or titanium / gold.

[0032] Preferably, the gate dielectric 5 is made of high dielectric constant materials such as alumina, hafnium oxide, and silicon oxide.

[0033] Preferably, the gate electrode 6 is deposited above the channel covered by the gate dielectric and its width is smaller than the channel width between the source and drain electrodes 4. This geometric design avoids direct overlap of the gate electrode and the source and drain electrodes in the vertical direction, reducing the risk of parasitic capacitance and edge leakage.

[0034] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0035] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications conventional in the art. In this specification and the following examples, unless otherwise specified, "%" refers to weight percentage, "parts" refers to parts by weight, and "ratio" refers to weight proportion.

[0036] Example 1 A method for fabricating a gallium arsenide-based photomemristor includes the following steps: Step 1: Silicon dioxide (insulating layer 2) with a thickness of approximately 200 nm is deposited on the unthinned gallium arsenide substrate 1 using chemical vapor deposition; the thickness of the gallium arsenide substrate 1 is 350 μm, and its resistivity is 4.47 × 10⁻⁶. 8 Ω·cm; Step 2: Spin-coat the photoresist onto the sample after the insulating layer has been deposited, and expose the pattern on the photoresist. Then develop the pattern to form a rectangular pattern with a size of 20 μm × 9 μm. Then use inductively coupled plasma to etch and expose the underlying semi-insulating gallium arsenide at the etched pattern. Finally, remove the photoresist to form etched via 3. Step 3: Spin-coat photoresist onto the etched sample and remove it using N-methylpyrrolidone and isopropanol, and expose the pattern onto the photoresist, then develop the pattern; deposit chromium / gold electrodes (source / drain electrodes 4) using an electron beam evaporation deposition system, where chromium is 5 nm with a deposition rate of 0.2 A / s and gold is 40 nm with a deposition rate of 0.4 A / s. After deposition, remove the electrodes using N-methylpyrrolidone and isopropanol. The removed source / drain electrode pattern is located on both sides of the etched via, with a 3 μm wide channel in the middle; Step 4: Deposit the gate dielectric layer 5 (alumina) on the sample after the source and drain electrodes have been prepared using an atomic layer deposition system. The thickness is about 25 nm, and the deposition rate is 0.1 nm / cycle. Step 5: Spin-coat the photoresist onto the etched sample and remove it using N-methylpyrrolidone and isopropanol, and expose the pattern onto the photoresist, then develop the pattern; deposit a chromium / gold electrode (gate electrode 6) using an electron beam evaporation deposition system, where chromium is 5 nm with a deposition rate of 0.2 A / s and gold is 40 nm with a deposition rate of 0.4 A / s. After deposition, remove the gate electrode pattern using N-methylpyrrolidone and isopropanol. The removed gate electrode pattern is located in the middle of the channel and has a width of 1 μm.

[0037] Figure 2 The image shows a scanning electron microscope (SEM) image of the gallium arsenide-based photomemristor prepared in Example 1. The image reveals a clear and complete device structure with well-defined functional layer boundaries and dimensions that closely match the design values. The device fabricated using this process exhibits excellent morphological quality and structural controllability, providing a reliable foundation for subsequent stable testing of photoelectric performance and mechanism analysis.

[0038] A 532 nm laser was used as the light source, which was then irradiated at the channel. The photoresponse under different light intensities was measured. The results are as follows: Figure 3 As shown, at 0.97 mW / cm 2 Under intense light irradiation, the device's responsivity and detectivity reached 3.9 A / W and 1.5 × 10⁻⁶, respectively. 12 Jones. This high performance stems from the combined effect of the high resistivity (low dark current) and direct bandgap (high light absorption coefficient) of the semi-insulating gallium arsenide substrate.

[0039] Example 2 Extending the process to the wafer level, using a 2-inch semi-insulating gallium arsenide wafer, the process of Example 1 on a single device was redrawn in 15×15 array units, and 24 15×15 array photomask patterns were applied to the wafer. Figure 4 The image shows a physical device at the 2-inch semi-insulating gallium arsenide wafer level and a magnified 15×15 array image. Figure 5 The transfer curves for 214 devices at a bias voltage of 3 V show an array yield of 95.1%, indicating good device uniformity. This yield data validates the process consistency advantage of eliminating the need for bulk substrate thinning, avoiding device differences caused by uneven thickness during the thinning process.

[0040] We utilize the advantages of optoelectronic modulation of the device to perform neuromorphic computation verification. Figure 6The results show the light enhancement and electrical suppression of 25 randomly selected devices. During the test, 50 consecutive light pulses (8.67 μW / cm²) were applied to each device. 2 ) and 50 consecutive gate voltage pulses ( V g,pulse =10 V). Neural network simulations were performed using the light enhancement and electrical suppression results from a single device. Figure 7 The accuracy rate for face image recognition tasks was 98.4%. Figure 8 For the target motion trajectory recognition task, an accuracy of 98.5% was also achieved. These results demonstrate that the conductance non-volatile modulation realized based on the device structure of this invention can effectively simulate the weight update behavior of biological synapses, meeting the basic requirements of neuromorphic computing for device plasticity (LTP / LTP).

[0041] In summary, this invention successfully realizes a photoelectric memristor without the need for thinning processes by using a bulk semi-insulating gallium arsenide substrate and introducing surface states through ICP etching. This fundamentally overcomes the yield bottleneck caused by the thinning process in silicon-based solutions. At the same time, it achieves excellent optoelectronic performance by leveraging the high resistivity of the semi-insulating substrate and the direct bandgap characteristics of gallium arsenide, and shows great potential in array integration and neuromorphic computing applications.

[0042] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A gallium arsenide-based photomemristor, characterized in that, Includes an unthinned gallium arsenide substrate (1), wherein an insulating layer (2) is disposed on the upper surface of the gallium arsenide substrate (1); It also includes etched vias (3), source and drain electrodes (4), gate dielectric layer (5) and gate electrode (6); the etched vias (3) penetrate the insulating layer (2) and expose the gallium arsenide substrate (1) below; the source and drain electrodes (4) are disposed on both sides of the surface of the gallium arsenide substrate (1) exposed in the etched vias (3), and there is a gap between the source and drain electrodes (4) to form a channel region; The gate dielectric (5) is deposited above the source / drain electrode (4) and in the channel region; the gate electrode (6) is deposited above the gate dielectric (5) and located directly above the channel region, and is used to apply gate voltage to modulate the channel conductivity.

2. A gallium arsenide-based photomemristor according to claim 1, characterized in that, The gallium arsenide substrate (1) has a thickness ≥300 μm and a resistivity ≥10. 7 Ω·cm; The gallium arsenide substrate (1) is a semi-insulating bulk substrate.

3. A gallium arsenide-based photomemristor according to claim 1, characterized in that, The insulating layer (2) is made of silicon dioxide or silicon nitride. The source / drain electrodes (4) and gate electrodes (6) are each independently selected from chromium / gold composite metal layers or titanium / gold composite metal layers.

4. A gallium arsenide-based photomemristor according to claim 1, characterized in that, The etched via (3) is formed by inductively coupled plasma etching process. While etching to form the etched via (3), the inductively coupled plasma etching process introduces surface states on the exposed gallium arsenide substrate (1) surface and regulates the dangling bond density and surface state energy level distribution on the surface of the gallium arsenide substrate (1) by etching conditions.

5. A gallium arsenide-based photomemristor according to claim 1, characterized in that, The material of the gate dielectric layer (5) is selected from alumina, hafnium oxide or silicon oxide.

6. A gallium arsenide-based photomemristor according to claim 1, characterized in that, The gate electrode (6) has a dimension in the direction parallel to the width of the channel region that is smaller than the channel width between the source and drain electrodes (4).

7. A method for fabricating a gallium arsenide-based photomemristor according to any one of claims 1 to 6, characterized in that, Includes the following steps: An unthinned gallium arsenide substrate (1) is provided, and an insulating layer (2) is subsequently formed on top of the gallium arsenide substrate (1). The insulating layer (2) is etched to form an etched via (3) that penetrates the insulating layer (2) and exposes the underlying gallium arsenide substrate (1). The etching simultaneously introduces surface states on the exposed gallium arsenide surface. Source and drain electrodes (4) are formed on both sides of the surface of the gallium arsenide substrate (1) exposed in the etched via (3), and the source and drain electrodes (4) are spaced apart to form a channel region; A gate dielectric layer (5) is formed above the source / drain electrodes (4) and above the channel region. A gate electrode (6) is formed above the gate dielectric layer (5) and at a position corresponding to the channel region.

8. The method for fabricating a gallium arsenide-based photomemristor according to claim 7, characterized in that, The insulating layer (2) is formed by chemical vapor deposition; the gate dielectric layer (5) is formed by atomic layer deposition; the source / drain electrode (4) and the gate electrode (6) are formed by electron beam evaporation.

9. A method for fabricating a gallium arsenide-based photomemristor according to claim 8, characterized in that, The deposition rate of the chemical vapor deposition method is 10~13 nm / min; the deposition rate of the atomic layer deposition method is 0.10~0.13 nm / cycle.

10. A method for fabricating a gallium arsenide-based photomemristor according to claim 8, characterized in that, When the source / drain electrode (4) and the gate electrode (6) are made of chromium, the deposition rate of the electron beam evaporation deposition method is 0.1~0.3 A / s. When the source / drain electrode (4) and the gate electrode (6) are made of gold, the deposition rate of the electron beam evaporation deposition method is 0.2~0.5 A / s.

Images