A method for rapidly synthesizing a vertical stack of PdTe2 / PtTe2 van der Waals heterostructure

Abstract

This invention discloses a rapid method for synthesizing vertically stacked PdTe2 / PtTe2 van der Waals heterostructures, belonging to the field of two-dimensional nanomaterials and optoelectronic devices. Addressing the technical challenges of existing PdTe2 / PtTe2 heterojunctions, which rely on mechanical exfoliation and manual transfer leading to interface contamination, small size, and difficulty in industrial mass production, as well as the tendency of conventional CVD to form alloys or in-plane structures and lack controllable vertical growth, this invention prepares a patterned, cross-stacked Pd / Pt metal seed layer on a substrate and combines it with dual-temperature zone chemical vapor deposition to achieve a one-step in-situ tellurization reaction, directly obtaining vertically stacked PdTe2 / PtTe2 heterostructures in the patterned overlapping region. This invention eliminates the need for mechanical transfer, ensures atomically clean interfaces with no polymer residues or wrinkles, enables wafer-level large-area uniform growth, and is compatible with standard semiconductor production lines. The prepared heterojunctions exhibit high crystallinity and excellent interlayer coupling, possessing significant industrial application value in broadband photodetectors, low-power logic devices, and gas sensors.

Description

Technical Field

[0001] This invention belongs to the technical fields of two-dimensional layered materials, van der Waals heterostructures and nano-optoelectronic devices, specifically relating to a method for rapidly synthesizing vertically stacked PdTe2 / PtTe2 van der Waals heterostructures. Background Technology

[0002] In recent years, two-dimensional layered materials, represented by transition metal dichalcogenides (TMDCs), have become a major research hotspot in condensed matter physics and nanoelectronics due to their extraordinary electrical, optical, and mechanical properties at the atomic scale. More importantly, two-dimensional materials are not strictly limited by traditional lattice matching and can be flexibly stacked through weak interlayer van der Waals forces to form vertical or in-plane van der Waals heterostructures (vdW Heterostructures). Electron transport in these heterostructures occurs through atomically smooth interfaces between different material layers, not only creating entirely new theoretical models for device physics but also enabling band alignment and interlayer coupling effects not found in single materials. These heterostructures have been widely applied in core areas such as next-generation photodetectors, high-performance field-effect transistors, non-volatile memories, solar cells, and room-temperature gas sensors.

[0003] Among numerous TMDC (Transient Transmission Device) material systems, Group 10 noble metal chalcogenides (especially tellurides) have attracted considerable attention in nanoelectronic devices in recent years. Specifically, palladium ditelluride (PdTe2) and platinum ditelluride (PtTe2), as Dirac semimetals or topological materials with extremely strong interlayer interactions, exhibit superior physicochemical properties that are distinctly different from traditional Group 6 TMDCs (such as MoS2 and WS2). They not only possess a wide range of tunable band gaps from bulk to monolayer, extremely high room-temperature carrier mobility, and excellent high on / off ratios, but also exhibit extremely high environmental stability in air. Constructing vertically stacked heterostructures using PdTe2 and PtTe2 holds promise for breakthroughs in broadband photodetectors and low-power logic devices. However, despite the enormous application potential of PdTe2 / PtTe2 van der Waals heterostructures, their practical application and industrialization are severely constrained by fabrication techniques. Currently, the most commonly used methods for fabricating such heterostructures are mechanical exfoliation and artificial transfer stacking. This involves using adhesive tape to peel off single or few layers of thin film from a bulk crystal, precisely aligning them under a microscope using a polymer medium, and then manually stacking them. Although the peeled layer crystals obtained by this method are of high quality and exhibit excellent intrinsic properties, they have extremely fatal flaws: (1) the yield is extremely low and the size is limited. The peeled film is usually at the micrometer level, with small size and uncontrollable thickness, which cannot meet the needs of large-scale production at the wafer-scale of integrated circuits; (2) the interface is extremely prone to contamination and damage. During the transfer process, organic polymer residues (such as PDMS, PMMA, etc.) and water and oxygen inclusions in the air are inevitably introduced, resulting in a large number of impurities, vacancies and wrinkles at the heterojunction interface, which seriously deteriorates the carrier transport efficiency and interlayer coupling effect of the device.

[0004] To address the challenge of preparing large-area, high-quality heterostructures, researchers have begun exploring top-down or bottom-up growth strategies suitable for industrial mass production, such as chemical vapor deposition (CVD). For example, Woods et al. (ACS Nano 10(2), 2016, 2004-2009) reported a one-step synthesis of large-area van der Waals heterostructures between MoS2 and WS2 films; Yu et al. (Nano Lett. 15(2), 2015, 1031-1035) synthesized vertically aligned WSe2 / MoS2 heterostructures by controlling rapid selenization and sulfidation. However, these methods are mostly designed for traditional Group 6 TMDCs (molybdenum sulfide, tungsten-based, etc.) and cannot be directly applied to the PdTe2 / PtTe2 system. The main reason is that tellurium (Te) atoms have low reactivity, and the catalytic affinity and diffusion kinetics of Pd and Pt for tellurium atoms differ significantly. If conventional co-evaporation or multi-step CVD methods are used, Pd and Pt are very likely to form random alloy phases or in-plane (lateral) growing spliced ​​structures, making it extremely difficult to control the spontaneous formation of high-quality vertically stacked heterogeneous interfaces.

[0005] In summary, there is still a pressing technical challenge in the field of technology: the lack of a one-step synthesis method for vertically stacked PdTe2 / PtTe2 heterostructures that can avoid complex mechanical transfer, ensure a clean and pollution-free interface, and enable large-area, wafer-level, continuous industrial production. Summary of the Invention

[0006] To address the problems of existing technologies that rely primarily on the mechanical peeling and manual transfer stacking of bulk materials to create van der Waals heterostructures, resulting in extremely low yields, susceptibility to interface contamination, high breakage rates, and the inability to achieve large-area wafer-level fabrication, this invention aims to provide a method for rapidly synthesizing vertically stacked PdTe2 / PtTe2 van der Waals heterostructures. This method, by introducing a patterned metal seed layer and combining it with a chemical vapor deposition (CVD) followed by tellurization, achieves one-step in-situ growth of PdTe2 / PtTe2 heterojunctions. This method not only produces clean interfaces and high-quality structures but also fully meets the requirements for large-area continuous industrial production.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A method for rapidly synthesizing vertically stacked PdTe2 / PtTe2 van der Waals heterostructures, characterized by comprising the following steps: Step S1: Prepare a patterned Pd / Pt metal seed layer: A Pt film of a predetermined thickness is deposited on a substrate to form a first patterned window; subsequently, a Pd film of a predetermined thickness is deposited on the Pt film to form a second patterned window; the first and second patterned windows are arranged in a partially overlapping cross pattern, thereby obtaining a patterned vertically stacked Pd / Pt metal seed layer on the substrate. Step S2: Prepare vertically stacked PdTe2 / PtTe2 heterostructures: The substrate with the Pd / Pt metal seed layer prepared in step S1 above is placed together with the tellurium source in a dual-temperature chemical vapor deposition (CVD) system. Under an inert protective atmosphere, the tellurium source and the substrate are heated separately, causing the tellurium source to evaporate and be transported to the surface of the Pd / Pt metal seed layer by a carrier gas for in-situ tellurization reaction. After the heat preservation reaction is completed, the substrate is naturally cooled, thus obtaining a vertically stacked PdTe2 / PtTe2 heterostructure in the pattern intersection area of ​​the substrate.

[0008] In step S1, the substrate is selected from any one of SiO2 / Si substrate, sapphire substrate or quartz substrate.

[0009] In step S1, the deposition method of the Pt thin film and the Pd thin film is magnetron sputtering or electron beam evaporation; the thickness of the Pt thin film is 2~5 nm, and the thickness of the Pd thin film is 2~5 nm; the size of the first pattern window and the second pattern window is 10×2 mm, and the two are arranged in a perpendicular cross arrangement.

[0010] In step S2, the dual-temperature zone chemical vapor deposition (CVD) system includes an upstream temperature zone and a downstream temperature zone; the tellurium source is placed in the upstream temperature zone, and the substrate with a Pd / Pt metal seed layer is placed in the downstream temperature zone; the distance between the tellurium source and the substrate is 15~18 cm.

[0011] In step S2, the tellurium source is high-purity tellurium powder, and its dosage is 1.5~2.5 g.

[0012] In step S2, the heating procedure for the in-situ tellurization reaction specifically includes: Before heating, the system is evacuated and purged with inert gas to atmospheric pressure, and the gas is purged in circulation at least 3 times. During the heating process, an inert gas with a flow rate of 50~100 sccm is introduced as a carrier gas; The upstream temperature zone is controlled to rise to the first target temperature at a rate of 10~20 ℃ / min, and the downstream temperature zone is controlled to rise to the second target temperature at a rate of 15~30 ℃ / min. After reaching the target temperature, maintain the temperature for 1-3 hours for the tellurization reaction.

[0013] More preferably, the inert gas is argon, with an injection flow rate of 60 sccm, a first target temperature of 250~350℃, and a second target temperature of 400~500℃.

[0014] The beneficial effects of this invention are as follows: (1) One-step in-situ synthesis: This invention is the first to propose using patterned Pd / Pt metal thin films as a double-layer seed layer. Through precise dual-temperature zone CVD control, and utilizing the difference in affinity and diffusion rate between metal atoms and tellurium atoms, the direct growth of vertically stacked PdTe2 / PtTe2 heterostructures is achieved in one step at a relatively low temperature (around 300 °C). This completely eliminates the need for traditional mechanical stripping and manual alignment and transfer processes, avoiding damage, wrinkles, and contamination from air / organic matter at the heterojunction interface, and obtaining an atomically clean interface with high-quality van der Waals interactions.

[0015] (2) Extremely high industrial conversion potential and large-area uniformity: The magnetron sputtering combined with chemical vapor deposition (CVD) process used in this invention are both extremely mature standard processes in the semiconductor industry. By controlling the pattern of the mask in the early stage and the metal sputtering time (film thickness), the size, position and number of layers of the final heterojunction can be precisely and repeatably controlled. This method breaks through the bottleneck of the traditional two-dimensional noble metal telluride's extreme difficulty in large-area growth. The prepared film has good continuity, dense surface and no excess tellurium particles, laying a solid technical foundation for the wafer-level mass production of next-generation high-performance optoelectronic devices, sensors and logic devices based on PdTe2 / PtTe2 heterostructures. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the preparation process of the PdTe2 / PtTe2 heterostructure based on the present invention; Figure 2 The image shows the Raman spectrum of the PdTe2 / PtTe2 heterostructure in Example 1. Figure 3 The X-ray photoelectron spectroscopy (XPS) spectra of the PdTe2 / PtTe2 heterostructure in Example 1 are shown in Figure 1. (a) Pd element; (b) Pt element; (c) Te element. Figure 4 AFM surface morphology images of PdTe2 / PtTe2 heterostructures under different tellurization conditions in Examples 1 and 2: (a) tellurization condition at 250℃; (b) tellurization condition at 300℃. Figure 5 High-resolution transmission electron microscopy images of the PdTe2 / PtTe2 heterostructure in Example 1: (a) cross-sectional image and corresponding selected area electron diffraction analysis; (b) bright-field image; (c) high-angle annular dark-field image; (dg) elemental distribution map of Pt, Pd and Te. Detailed Implementation

[0017] To make the above-mentioned objectives, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to examples. The following content is merely illustrative and explanatory of the concept of the present invention. Those skilled in the art can make various modifications or additions to the described specific embodiments or use similar methods to replace them, as long as they do not deviate from the inventive concept, all of which should fall within the protection scope of the present invention. The preparation method of the present invention will be described below through specific embodiments. Example

[0018] Figure 1 This is a schematic diagram of the preparation process of the PdTe2 / PtTe2 heterostructure based on the present invention. The specific steps are as follows: Step S1: Prepare a patterned Pd / Pt metal seed layer First, the SiO2 / Si substrate was ultrasonically cleaned sequentially in acetone, deionized water, and isopropanol, and then dried with nitrogen. A 3 nm thick Pt film was deposited on the SiO2 / Si substrate using magnetron sputtering, with the exposure window size controlled to be 10 × 2 mm using a mask. Next, the Pt target in the sputtering chamber was switched to a Pd target, and the substrate was rotated 90 degrees so that the new 10 × 2 mm exposure window perpendicularly intersected the pre-deposited Pt film. A 3 nm thick Pd film was then deposited on the substrate, resulting in a patterned, vertically stacked Pd / Pt bilayer metal seed layer in the 2 × 2 mm intersection region at the center of the substrate.

[0019] Step S2: Prepare vertically stacked PdTe2 / PtTe2 heterostructures A quartz boat containing 2 g of high-purity tellurium powder was placed in the upstream temperature zone of a dual-zone chemical vapor deposition (CVD) growth furnace, while a substrate with a pre-deposited Pd / Pt metal seed layer was placed in the downstream temperature zone. The distance between the substrate and the tellurium powder was adjusted to 16 cm. Before growth, the quartz tube was evacuated to a low vacuum (below 1 Pa), and then filled with high-purity argon gas to ambient pressure. This evacuation-filling process was repeated three times to thoroughly remove oxygen and moisture from the system.

[0020] During the tellurization growth stage, an argon gas flow of 60 sccm was maintained throughout as the carrier gas. The heating rate of the upstream temperature zone was set to 15 °C / min, with a target temperature controlled at 300 °C; simultaneously, the heating rate of the downstream temperature zone was set to 22.5 °C / min, with a target temperature controlled at 450 °C. After reaching the target temperature, the reaction was held at this temperature for 2 hours. The tellurium powder evaporated at the high temperature and, under the transport of the argon gas flow, underwent an in-situ tellurization reaction on the surface of the downstream Pd / Pt metal layer. After the holding period ended, the heating power was turned off, and the mixture was allowed to cool naturally to room temperature under argon protection, thus obtaining a uniform, dense, and vertically stacked PdTe2 / PtTe2 heterostructure in the cross region.

[0021] Example 2: Low Temperature Boundary Condition Example The preparation steps in this embodiment are basically the same as those in Example 1, except for the heating parameters in step S2: In step S2, the heating rate of the upstream temperature zone was set to approximately 12.5 °C / min, the target temperature was controlled at 250 °C, and the holding time was adjusted to 1.5 hours. All other parameters (including a metal layer thickness of 3 nm, tellurium powder dosage of 2 g, downstream temperature zone of 450 °C, and argon flow rate of 60 sccm) remained consistent with those in Example 1.

[0022] The PdTe2 / PtTe2 heterostructure obtained under these conditions successfully underwent tellurization to form a heterojunction, but the surface density of the film was slightly lower than that of Example 1, and there were some unreacted residual large tellurium particles on the surface. Example

[0023] The preparation steps in this embodiment are basically the same as those in Example 1, with the only difference being some process parameters in steps S1 and S2: In step S1, a 5 nm thick Pt film is deposited on a sapphire substrate using electron beam evaporation, followed by a 5 nm thick Pd film. The pattern window size and cross arrangement are the same as in Example 1. In step S2, the amount of tellurium powder was adjusted to 2.5 g, and the distance between the substrate and the tellurium powder was set to 18 cm. An argon flow of 80 sccm was maintained as the carrier gas throughout the process. The heating rate of the upstream temperature zone was set to 20 ℃ / min, and the target temperature was controlled at 350 ℃. The heating rate of the downstream temperature zone was set to 30 ℃ / min, and the target temperature was controlled at 500 ℃. The heat preservation reaction time was adjusted to 3 hours.

[0024] The PdTe2 / PtTe2 heterostructure prepared under these conditions exhibits further improved crystallinity, excellent film thickness uniformity, no tellurium particle residue, atomically clean heterojunction interface, and no interlayer element interdiffusion. The overall structural quality meets the requirements for wafer-level device fabrication.

[0025] Example 4: Optimized Low Temperature Conditions The preparation steps in this embodiment are basically the same as those in Example 1, with the only difference being some process parameters in steps S1 and S2: In step S1, a 2 nm thick Pt film is deposited on a quartz substrate by magnetron sputtering, followed by a 2 nm thick Pd film. The pattern window size and cross arrangement are the same as in Example 1. In step S2, the amount of tellurium powder was adjusted to 1.5 g, and the distance between the substrate and the tellurium powder was set to 15 cm. An argon flow of 50 sccm was maintained as the carrier gas throughout the process. The heating rate of the upstream temperature zone was set to 10 ℃ / min, and the target temperature was controlled at 270 ℃. The heating rate of the downstream temperature zone was set to 15 ℃ / min, and the target temperature was controlled at 400 ℃. The heat preservation reaction time was adjusted to 1 hour.

[0026] Under these conditions, the synthesis of PdTe2 / PtTe2 heterostructures can be completed quickly. The resulting heterojunction film has uniform thickness and a smooth interface. Although the crystallinity is slightly lower than that of Example 1, it fully meets the performance requirements of basic optoelectronic devices, significantly shortens the preparation cycle, and improves the synthesis efficiency.

[0027] Structural characterization and performance analysis To verify the structure and quality of the heterojunction prepared by the method of the present invention, the sample obtained in Example 1 was subjected to detailed materials characterization.

[0028] Figure 2 The image shows the Raman spectrum of the PdTe2 / PtTe2 heterostructure in Example 1. Raman spectroscopy was used to characterize the monolayer regions of the PdTe2 and PtTe2 films prepared in this example, as well as the overlapping region of the PdTe2 / PtTe2 heterojunction. In the PtTe2 monolayer region, a 112.1 cm⁻¹ diameter was observed. -1 and 159.6 cm -1 The two sharp characteristic peaks correspond to the in-plane vibrational mode (Eg) and out-of-plane vibrational mode (Ag) of the Te atom, respectively. 1g In the PdTe2 monolayer region, a similar 80.3 cm⁻¹ was observed. -1 and 134.1 cm -1 Two distinct characteristic peaks correspond to the in-plane Eg and out-of-plane A of PdTe2, respectively. 1g Vibrational modes. Of particular importance, in the Raman spectrum of the heterojunction overlap region, all the aforementioned characteristic peaks of PtTe2 and PdTe2 can be observed simultaneously and clearly, and the peak positions do not show significant shifts or broadening. This indicates that the upper and lower materials maintain their respective excellent crystal structures, and that PtTe2 and PdTe2 form a high-quality vertical heterostructure through van der Waals forces.

[0029] Figure 3 The X-ray photoelectron spectroscopy (XPS) spectra of the PdTe2 / PtTe2 heterostructure in Example 1 are shown. (a) Pd element; (b) Pt element; (c) Te element. The chemical state of the material was confirmed using XPS. In the Pd 3d spectrum collected from the PdTe2 thin film region on the heterojunction surface, the binding energies of ~336.1 eV and 341.4 eV are attributed to Pd 3d... 5 / 2 and Pd 3d 3 / 2 Double peaks; in the Pt4f energy spectrum collected in the PtTe2 thin film region, the binding energies of 76.5 eV and 73.2 eV correspond to Pt4f, respectively. 5 / 2 and Pt4f 7 / 2 The structure exhibits a double peak. Furthermore, the XPS binding energies of Te were measured at approximately 573.0 eV and 583.4 eV, which are attributed to Te 3d... 5 / 2 and Te 3d 3 / 2 Double peaks. The above peak position data are in perfect agreement with standard noble metal ditelluride crystals, proving the successful synthesis of PdTe2 and PtTe2 with accurate stoichiometry.

[0030] Figure 4 The images show the AFM surface morphology of the PdTe2 / PtTe2 heterostructures under different tellurization conditions in Examples 1 and 2: (a) tellurization at 250℃; (b) tellurization at 300℃. The surface morphology under different tellurization conditions was characterized using AFM. Under the low-temperature tellurization condition of 250℃, there were obvious unreacted blocky tellurium (Te) particles in the local area of ​​the sample. Under the optimal conditions (300℃, 2 hours), the surface of the heterojunction became extremely dense and smooth, and almost no excess tellurium particles were observed, exhibiting excellent film uniformity and large-area continuity.

[0031] Figure 5High-resolution transmission electron microscopy (HRTEM) images of the PdTe2 / PtTe2 heterostructure in Example 1 are shown below: (a) cross-sectional image and corresponding selected area electron diffraction (SAED) analysis; (b) bright-field image; (c) high-angle annular dark-field image; and (dg) elemental distribution maps of Pt, Pd, and Te. The interface details of the PdTe2 / PtTe2 heterojunction were visually observed in cross-section using HRTEM. The sample exhibits a clear vertical layered structure, corresponding to the top PdTe2 layer, the middle PdTe2 / PtTe2 heterojunction interface, and the bottom PtTe2 layer, respectively. The SAED pattern shows bright and regular diffraction spots, confirming that both the upper and lower thin films possess highly ordered single-crystal or large-area polycrystalline characteristics. The high-angle annular dark-field (HAADF) image shows that, due to the significantly higher atomic number of platinum (Pt) in the bottom layer compared to palladium (Pd) in the top layer, the image brightness of the bottom PtTe2 is significantly higher than that of the top PdTe2, forming a distinct Z-contrast difference. Further analysis using the EDS elemental distribution map clearly shows the layered aggregation of Pd, Pt, and Te elements in the vertical direction. The distribution of different elements strictly follows the preset stacking order, and no obvious interlayer interdiffusion occurs. This confirms the successful preparation of high-quality PdTe2 / PtTe2 vertical heterostructures at the atomic scale.

Claims

1. A method for rapidly synthesizing vertically stacked PdTe2 / PtTe2 heterostructures, characterized in that, The steps include the following: Step S1: Prepare a patterned Pd / Pt metal seed layer: A Pt film of a predetermined thickness is deposited on a substrate to form a first patterned window; subsequently, a Pd film of a predetermined thickness is deposited on the Pt film to form a second patterned window. The first pattern window and the second pattern window are arranged in a partially overlapping cross pattern, thereby obtaining a patterned vertically stacked Pd / Pt metal seed layer on the substrate. Step S2: Prepare vertically stacked PdTe2 / PtTe2 heterostructures: The substrate with the Pd / Pt metal seed layer prepared in step S1 above is placed together with the tellurium source in a dual-temperature chemical vapor deposition (CVD) system. Under an inert protective atmosphere, the tellurium source and the substrate are heated separately, causing the tellurium source to evaporate and be transported to the surface of the Pd / Pt metal seed layer by a carrier gas for in-situ tellurization reaction. After the heat preservation reaction is completed, the substrate is naturally cooled, thus obtaining a vertically stacked PdTe2 / PtTe2 heterostructure in the pattern intersection area of ​​the substrate.

2. The method according to claim 1, characterized in that, In step S1, the substrate is selected from any one of SiO2 / Si substrate, sapphire substrate or quartz substrate.

3. The method according to claim 1, characterized in that, In step S1, the deposition method of the Pt thin film and the Pd thin film is magnetron sputtering or electron beam evaporation; the thickness of the Pt thin film is 2~5 nm, and the thickness of the Pd thin film is 2~5 nm; the size of the first pattern window and the second pattern window is 10×2 mm, and the two are arranged in a perpendicular cross arrangement.

4. The method according to claim 1, characterized in that, In step S2, the dual-temperature zone chemical vapor deposition system includes an upstream temperature zone and a downstream temperature zone; the tellurium source is placed in the upstream temperature zone, and the substrate with a Pd / Pt metal seed layer is placed in the downstream temperature zone; the distance between the tellurium source and the substrate is 15~18 cm.

5. The method according to claim 1, characterized in that, In step S2, the tellurium source is high-purity tellurium powder, and its dosage is 1.5~2.5 g.

6. The method according to claim 1, characterized in that, In step S2, the heating procedure for the in-situ tellurization reaction specifically includes: Before heating, the system is evacuated and purged with inert gas to atmospheric pressure, and the gas is purged in circulation at least 3 times. During the heating process, an inert gas with a flow rate of 50~100 sccm is introduced as a carrier gas; The upstream temperature zone is heated to the first target temperature at a rate of 10~20 ℃ / min, and the downstream temperature zone is heated to the second target temperature at a rate of 15~30 ℃ / min; after reaching the target temperature, the tellurization reaction is maintained for 1~3 hours. The inert gas is argon, and its flow rate is 60 sccm; the first target temperature is 250~350℃, and the second target temperature is 400~500℃.

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