Compound semiconductor epitaxial film transfer method

Abstract

The application relates to the technical field of semiconductor material and device manufacturing, and provides a compound semiconductor epitaxial film secondary transfer method. The method improves the quality of temporary bonding and target bonding through surface-activated bonding with a silicon intermediate layer, provides rigid support and a controllable release interface through a temporary silicon carrier containing an oxidation layer or a nitridation layer, protects an epitaxial functional layer in different etching steps through upper and lower double blocking layers of the epitaxial film, and protects a target carrier through a low-temperature wax bonding temporary etching protection carrier, so that GaAs, InP and other compound semiconductor epitaxial films are transferred to the target carrier with low damage and low warping.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials and device manufacturing technology, and in particular to a method for secondary transfer of compound semiconductor epitaxial thin films. Background Technology

[0002] Gallium arsenide (GaAs), indium phosphide (InP), and other III-V compound semiconductor materials possess high electron mobility, direct band gaps, and excellent optoelectronic properties, making them valuable for applications in high-speed electronic devices, optical communication devices, lasers, detectors, and heterogeneous integrated chips. With the development of silicon-based heterogeneous integration and on-chip optoelectronic fusion, the transfer of epitaxial functional thin films from bulk substrates such as GaAs and InP to silicon (Si), Si complementary metal-oxide-semiconductor (CMOS), or other target carriers is of great significance.

[0003] Existing thin film transfer methods mostly rely on organic bonding or high-temperature processes. After the original substrate is removed, the mechanical strength of the film is significantly reduced. For submicron or micron-scale compound semiconductor epitaxial films, problems such as insufficient mechanical support, high thermal mismatch stress, interface contamination, film warping, cracking, debonding, and damage to the epitaxial layer and target carrier during wet etching are prone to occur. Therefore, there is a need for a low-temperature, inorganic, supportive, selectively release method for secondary transfer of epitaxial films that can protect the film and target carrier during multiple etching processes. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a secondary transfer method for compound semiconductor epitaxial thin films to solve the problems that semiconductor epitaxial thin films prepared by existing thin film transfer methods are prone to have insufficient mechanical support, large thermal mismatch stress, interface contamination, film warping, cracking, debonding, and damage to the epitaxial layer and target carrier during wet etching.

[0005] A first aspect of the present invention provides a method for secondary transfer of compound semiconductor epitaxial thin films, comprising:

[0006] Prepare a compound semiconductor epitaxial wafer with a double barrier layer; the compound semiconductor epitaxial wafer includes at least a bulk material substrate and an epitaxial functional layer, the first barrier layer is located on the epitaxial functional layer, and the second barrier layer is located between the epitaxial functional layer and the bulk material substrate;

[0007] A temporary silicon support is prepared; the temporary silicon support includes a silicon layer, a first dielectric barrier layer located above the silicon layer, and a second dielectric barrier layer located below the silicon layer.

[0008] The first barrier layer and the second dielectric barrier layer are subjected to a first surface activation bonding to obtain a wafer after the first bonding.

[0009] Remove the bulk material substrate and the second barrier layer from the wafer after the first bonding to expose the surface of the epitaxial functional layer and obtain the wafer after the first transfer.

[0010] The epitaxial functional layer is then surface activated and bonded to the target carrier a second time to obtain a wafer after the second bonding.

[0011] The target carrier in the wafer after the second bonding is attached to the temporary corrosion protection carrier using low-temperature wax or temporary bonding adhesive.

[0012] The first dielectric barrier layer, silicon layer, second dielectric barrier layer and first barrier layer are removed sequentially, and the temporary corrosion protection carrier is removed by heating to obtain the compound semiconductor epitaxial film on the target carrier.

[0013] In some embodiments of the present invention, the compound semiconductor epitaxial wafer is a GaAs-based epitaxial wafer or an InP-based epitaxial wafer;

[0014] Among them, GaAs-based epitaxial wafers include GaAs bulk material substrates and GaAs-based, AlGaAs-based, or InGaP-based epitaxial functional layers; InP-based epitaxial wafers include InP bulk material substrates and InP-based, InGaAs-based, or InGaAsP-based epitaxial functional layers.

[0015] In response to the fact that the bulk material substrate is a GaAs substrate and the barrier layer is an InGaP layer;

[0016] The substrate is determined to be an InP substrate and the barrier layer is an InGaAs layer.

[0017] In some embodiments of the present invention, the thickness of the first barrier layer and the second barrier layer is 50 nanometers to 1 micrometer.

[0018] In some embodiments of the present invention, the first dielectric barrier layer and the second dielectric barrier layer are SiO2 layers or SiN layers;

[0019] The thickness of the first dielectric barrier layer and the second dielectric barrier layer is 100 nanometers to 1 micrometer.

[0020] The overall thickness of the temporary silicon carrier ranges from 100 micrometers to 700 micrometers.

[0021] In some embodiments of the present invention, the surface activation bonding process includes:

[0022] The surfaces to be bonded are sequentially subjected to surface activation, silicon intermediate layer sputtering, and lamination contact treatment to complete surface activation bonding;

[0023] The bonding surfaces after the press-fit contact treatment are reinforced by low-temperature annealing.

[0024] The bonding surfaces for the first surface activation bonding include the upper surface of the first barrier layer and the lower surface of the second dielectric barrier layer, while the bonding surfaces for the second surface activation bonding include the surface of the epitaxial functional layer and the upper surface of the target carrier.

[0025] In some embodiments of the present invention, removing the bulk substrate and the second barrier layer from the wafer after the first bonding includes:

[0026] Mechanical thinning and polishing are performed on the bulk material substrate in the wafer after the first bonding.

[0027] The remaining bulk material substrate and second barrier layer are removed by selective wet etching.

[0028] In some embodiments of the present invention, the bulk material substrate in the wafer after the first bonding is mechanically thinned to 10 micrometers to 500 micrometers.

[0029] In some embodiments of the present invention, in response to determining that the bulk material substrate is a GaAs substrate, the remaining bulk material substrate is removed by etching using an H3PO4:H2O2:H2O system.

[0030] In response to the determination that the bulk material substrate is an InP substrate, the remaining bulk material substrate is removed by etching using an HCl:H2O system;

[0031] In response to the determination that the second barrier layer material is an InP system, the second barrier layer is removed by etching using an H3PO4:H2O2:H2O system.

[0032] In response to the determination that the second barrier layer material is GaAs system, the second barrier layer is removed by etching using HCl:H2O system;

[0033] The process of using an H3PO4:H2O2:H2O system to etch and remove the remaining bulk substrate includes:

[0034] The remaining bulk material substrate was rapidly etched using a high concentration ratio to obtain a remaining bulk material substrate that is close to the barrier layer.

[0035] Selective etching of the remaining bulk material substrate near the barrier layer was performed using a low concentration ratio.

[0036] In some embodiments of the present invention, the silicon intermediate layer is an intermediate layer formed by sputtering during the surface activation bonding process;

[0037] The total thickness of the silicon interlayer ranges from 1 nanometer to 100 nanometers;

[0038] The annealing temperature for low-temperature annealing strengthening is 100℃ to 400℃.

[0039] In some embodiments of the present invention, the temporary corrosion protection carrier is a sapphire sheet;

[0040] The silicon layer in the temporary silicon carrier is removed by either a first wet etching method or a dry etching method. The first wet etching method uses potassium hydroxide (KOH) solution or tetramethylammonium hydroxide (TMAH) solution.

[0041] The first and second dielectric barrier layers are removed using a second wet etching method; the second wet etching method uses buffer oxide etching solution BOE or hydrofluoric acid HF solution.

[0042] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The embodiments of the present invention achieve low-damage secondary transfer of brittle compound semiconductor epitaxial films such as GaAs and InP based on a combination process of surface activation bonding, temporary silicon carrier with oxide or nitride layer, double barrier layer protection, temporary corrosion protection carrier and multi-stage selective wet release.

[0043] Compared with traditional organic adhesive bonding or single-barrier layer transfer methods, the embodiments of this invention utilize surface-activated bonding with a silicon interlayer to reduce interface contamination and thermal mismatch stress, thereby improving the stability of temporary bonding and target bonding. The temporary silicon carrier and its SiO2 or SiN dielectric layer provide rigid support and a controllable debonding interface for the thin film, reducing the risk of warping and cracking of submicron or micron-scale epitaxial films during transfer. The upper and lower double barrier layers continuously protect the epitaxial functional layer during the removal of the original substrate, release of the temporary carrier, and final surface exposure, reducing corrosion damage. Low-temperature wax bonding of temporary corrosion-protective carriers such as sapphire isolates the corrosion solution and protects the target carrier.

[0044] This method is applicable to the transfer of complete wafers or large-area epitaxial films of compound semiconductors such as GaAs and InP to target carriers such as Si and SiCMOS, providing a process solution with low thermal budget, low warpage, and high integrity for subsequent device manufacturing and heterogeneous integration. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic flowchart of a secondary transfer method for compound semiconductor epitaxial thin films provided in an embodiment of the present invention.

[0047] Figure 2This is a schematic diagram of the structure of the compound semiconductor epitaxial wafer and temporary silicon carrier prepared by the present invention.

[0048] Figure 3 This is a schematic diagram of the wafer after the first bonding provided in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of a wafer after mechanical thinning of a bulk material substrate provided in an embodiment of the present invention.

[0050] Figure 5 This is a schematic diagram of the wafer after the first transfer provided in an embodiment of the present invention.

[0051] Figure 6 This is a diagram showing the relative positions of the wafer and the target carrier after the first transfer during the second surface activation bonding process, provided in an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of the wafer after the second bonding provided in an embodiment of the present invention.

[0053] Figure 8 This is a schematic diagram of a wafer obtained by attaching a target carrier to a temporary corrosion protection carrier, as provided in an embodiment of the present invention.

[0054] Figure 9 This is a schematic diagram of the structure of a compound semiconductor epitaxial thin film on a target carrier obtained by the method provided in the embodiments of the present invention. Detailed Implementation

[0055] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0056] A method for secondary transfer of compound semiconductor epitaxial thin films according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0057] As mentioned above, existing thin film transfer methods mostly rely on organic bonding or high-temperature processes. After the original substrate is removed, the mechanical strength of the thin film is significantly reduced. For submicron or micron-scale compound semiconductor epitaxial films, problems such as insufficient mechanical support, large thermal mismatch stress, interface contamination, film warping, cracking, debonding, and damage to the epitaxial layer and target carrier during wet etching are likely to occur.

[0058] In view of this, embodiments of the present invention provide a secondary transfer method for GaAs, InP, and other compound semiconductor epitaxial films based on surface activation bonding, temporary carrier support, multi-barrier layer protection, and multi-stage selective wet etching. First, the epitaxial surface of the compound semiconductor epitaxial wafer is stably bonded to a temporary silicon carrier with an oxide or nitride layer through surface activation bonding with an intermediate layer, and then hardened by low-temperature annealing. Subsequently, the original substrate is thinned, polished, and selectively wet-etched, allowing the epitaxial film to complete its first transfer under the protection of the barrier layer. Next, the epitaxial film is stably bonded to the target carrier through surface activation bonding with an intermediate layer, and the interface is again hardened by low-temperature annealing. A temporary etching protection carrier is bonded using low-temperature wax to protect the target carrier. Finally, the oxide or nitride barrier layer, the temporary silicon carrier, and the remaining barrier layer of the epitaxial film are removed by multi-stage selective wet etching. The temporary etching protection carrier is then removed by heating, yielding the compound semiconductor epitaxial film located on the target carrier.

[0059] The embodiments of the present invention solve the problems of easy warping, cracking, debonding and corrosion damage of submicron or micron-scale epitaxial films of brittle materials such as GaAs, InP, gallium nitride (GaN) and germanium silicon (GeSi) alloys during whole wafer transfer by combining surface activation bonding, temporary carrier support with oxide or nitride layers, double barrier layer protection and temporary corrosion protection carrier. It can be used for subsequent device manufacturing and heterogeneous integration.

[0060] Figure 1 This is a schematic flowchart of a secondary transfer method for compound semiconductor epitaxial thin films provided in an embodiment of the present invention. Figure 1 As shown, the method includes the following steps:

[0061] In step S101, a compound semiconductor epitaxial wafer with a double barrier layer is prepared.

[0062] The compound semiconductor epitaxial wafer includes at least a bulk material substrate and an epitaxial functional layer, with a first barrier layer located above the epitaxial functional layer and a second barrier layer located between the epitaxial functional layer and the bulk material substrate.

[0063] In step S102, a temporary silicon support is prepared.

[0064] The temporary silicon carrier includes a silicon layer, a first dielectric barrier layer above the silicon layer, and a second dielectric barrier layer below the silicon layer.

[0065] In step S103, the first barrier layer and the second dielectric barrier layer are subjected to a first surface activation bonding to obtain a wafer after the first bonding.

[0066] In step S104, the bulk material substrate and the second barrier layer in the wafer after the first bonding are removed to expose the surface of the epitaxial functional layer, thus obtaining the wafer after the first transfer.

[0067] In step S105, the epitaxial functional layer is subjected to a second surface activation bonding with the target carrier to obtain a wafer after the second bonding.

[0068] In step S106, the target carrier in the wafer after the second bonding is attached to the temporary corrosion protection carrier using low-temperature wax or temporary bonding adhesive.

[0069] In step S107, the first dielectric barrier layer, silicon layer, second dielectric barrier layer and first barrier layer are removed sequentially, and the temporary corrosion protection carrier is removed by heating to obtain the compound semiconductor epitaxial film on the target carrier.

[0070] In some embodiments of the present invention, a compound semiconductor epitaxial wafer with a double barrier layer can be first prepared. The compound semiconductor epitaxial wafer may include a bulk material substrate and an epitaxial functional layer, as well as a space between the first barrier layer and the second barrier layer. The bulk material substrate is located at the bottom layer, the first barrier layer is located above the epitaxial functional layer, and the second barrier layer is located between the epitaxial functional layer and the bulk material substrate.

[0071] Simultaneously, a temporary silicon support can be prepared, which may include a silicon layer, a first dielectric barrier layer, and a second dielectric barrier layer. The first dielectric barrier layer is located above the silicon layer, and the second dielectric barrier layer is located below the silicon layer.

[0072] Figure 2 This is a schematic diagram of the structure of the compound semiconductor epitaxial wafer and temporary silicon carrier prepared by the present invention. Figure 2 The upper half is a temporary silicon carrier. The barrier layer in the temporary silicon carrier can be a dielectric barrier layer. The first dielectric barrier layer is above the silicon (Si) layer, and the second dielectric barrier layer is below the Si layer. Figure 2 The lower half is a compound semiconductor epitaxial wafer, wherein the epitaxial functional layer is represented by a compound epitaxial thin film, a first barrier layer is above the compound epitaxial thin film, and a second barrier layer is below the compound epitaxial thin film.

[0073] In some embodiments of the present invention, the compound semiconductor epitaxial wafer may be a GaAs-based epitaxial wafer or an InP-based epitaxial wafer.

[0074] Among them, GaAs-based epitaxial wafers include GaAs bulk material substrates and GaAs-based, AlGaAs-based, or InGaP-based epitaxial functional layers; InP-based epitaxial wafers include InP bulk material substrates and InP-based, InGaAs-based, or InGaAsP-based epitaxial functional layers.

[0075] The substrate is determined to be a GaAs substrate and the barrier layer is an InGaP layer; and the substrate is determined to be an InP substrate and the barrier layer is an InGaAs layer.

[0076] In some embodiments of the present invention, the thickness of the first barrier layer and the second barrier layer can be from 50 nanometers (nm) to 1 micrometer (μm).

[0077] In some other embodiments of the present invention, the first dielectric barrier layer and the second dielectric barrier layer may be silicon dioxide (SiO2) layer or silicon nitride (SiN) layer; and the thickness of the first dielectric barrier layer and the second dielectric barrier layer may be from 100 nm to 1 μm, and the overall thickness of the temporary silicon carrier may be from 100 μm to 700 μm.

[0078] In some embodiments of the present invention, the following can be employed: Figure 2 The relative positions shown illustrate the initial surface activation bonding of the compound semiconductor epitaxial wafer and the temporary silicon carrier. Specifically, the first surface activation bonding can be performed on the first barrier layer and the second dielectric barrier layer to obtain the wafer after the first bonding, as shown below. Figure 3 As shown.

[0079] Furthermore, the wafer after the first bonding can be annealed and strengthened, and then the bulk material substrate and the second barrier layer can be removed to expose the surface of the epitaxial functional layer, i.e., the compound epitaxial film, to obtain the wafer after the first transfer.

[0080] In some embodiments, removing the bulk substrate and the second barrier layer from the wafer after the first bonding may include: mechanically thinning and polishing the bulk substrate in the wafer after the first bonding; and removing the remaining bulk substrate and the second barrier layer by selective wet etching.

[0081] In this process, the bulk substrate in the wafer after the first bonding can be mechanically thinned to 10 μm to 500 μm. The wafer after mechanically thinning the bulk substrate is shown below. Figure 4 As shown. After selective wet etching to remove the remaining bulk substrate and the second barrier layer, the resulting wafer after the first transfer is shown. Figure 5 As shown.

[0082] Furthermore, when removing the remaining bulk substrate and the second barrier layer by selective wet etching, in response to determining that the bulk substrate is a GaAs substrate, the remaining bulk substrate can be removed by etching using an H3PO4:H2O2:H2O system; in response to determining that the bulk substrate is an InP substrate, the remaining bulk substrate can be removed by etching using an HCl:H2O system.

[0083] Simultaneously, in response to the determination that the second barrier layer material is an InP system, the second barrier layer can be removed by etching using an H3PO4:H2O2:H2O system; in response to the determination that the second barrier layer material is a GaAs system, the second barrier layer can be removed by etching using an HCl:H2O system. Wherein, H3PO4 is phosphoric acid, H2O2 is hydrogen peroxide, H2O is water, and HCl is hydrogen chloride.

[0084] The process of removing the remaining bulk material substrate using an H3PO4:H2O2:H2O system can include: rapidly etching the remaining bulk material substrate with a high concentration ratio to obtain a remaining bulk material substrate close to the barrier layer; and selectively etching the remaining bulk material substrate close to the barrier layer with a low concentration ratio. In the high-concentration solution, the volume fraction of the phosphate stock solution is 30%–70%, the volume fraction of the hydrogen peroxide stock solution is 10%–40%, and the remainder is deionized water; in the low-concentration solution, the volume fraction of the phosphate stock solution is 3%–25%, the volume fraction of the hydrogen peroxide stock solution is 8%–35%, and the remainder is deionized water.

[0085] In some embodiments of the present invention, after obtaining the wafer after the first transfer, the epitaxial functional layer and the target carrier can be subjected to a second surface activation bonding to obtain a second-bonded wafer. The relative positional relationship between the wafer after the first transfer and the target carrier during the second surface activation bonding is as follows: Figure 6 As shown, Figure 6 The upper half is the wafer after the first transfer, and the lower half is the target carrier. The wafer after the second bonding is shown below. Figure 7 As shown.

[0086] Next, the target carrier can be attached to the temporary corrosion protection carrier using low-temperature wax or temporary bonding adhesive. The structure after attachment is as follows. Figure 8 As shown.

[0087] Finally, the first dielectric barrier layer, silicon layer, second dielectric barrier layer, and first barrier layer are removed sequentially, and the temporary etching protection carrier is removed by heating to obtain the compound semiconductor epitaxial film on the target carrier. This compound semiconductor epitaxial film on the target carrier is the wafer after the second transfer, and its structure is as follows: Figure 9 As shown.

[0088] In some embodiments of the present invention, each surface activation bonding process may include: sequentially performing surface activation, silicon intermediate layer sputtering, and pressing contact treatment on the bonding surface to be bonded to complete the surface activation bonding; and then performing low-temperature annealing to strengthen the bonding surface after pressing contact treatment.

[0089] The bonding surfaces for the first surface activation bonding include the upper surface of the first barrier layer and the lower surface of the second dielectric barrier layer, while the bonding surfaces for the second surface activation bonding include the surface of the epitaxial functional layer and the upper surface of the target carrier.

[0090] In some embodiments of the present invention, the silicon intermediate layer is an intermediate layer formed by sputtering during the surface activation bonding process; the total thickness of the silicon intermediate layer is 1 nm to 100 nm; and the annealing temperature for low-temperature annealing is 100 °C to 400 °C.

[0091] In some embodiments of the present invention, the temporary corrosion protection carrier may be a sapphire sheet.

[0092] In some embodiments, the silicon layer in the temporary silicon carrier can be removed by a first wet etching method or a dry etching method, wherein the first wet etching method uses potassium hydroxide (KOH) solution or tetramethylammonium hydroxide (TMAH) solution.

[0093] Furthermore, the first and second dielectric barrier layers can be removed using a second wet etching method; the second wet etching method uses buffered oxide etching solution BOE or hydrofluoric acid HF solution.

[0094] The technical solution provided by this invention utilizes surface-activated bonding with a silicon interlayer to reduce interface contamination and thermal mismatch stress, thereby improving the stability of temporary bonding and target bonding. It utilizes a temporary silicon carrier and its SiO2 or SiN dielectric layer to provide rigid support and a controllable debonding interface for the thin film, reducing the risk of warping and cracking of submicron or micron-scale epitaxial films during transfer. It utilizes upper and lower double barrier layers to continuously protect the epitaxial functional layer during the removal of the original substrate, release of the temporary carrier, and final surface exposure, reducing corrosion damage. Finally, it utilizes low-temperature wax or temporary bonding adhesive to bond temporary corrosion protection carriers such as sapphire to isolate the corrosion solution and protect the target carrier.

[0095] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, and will not be described in detail here.

[0096] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for secondary transfer of compound semiconductor epitaxial thin films, characterized in that, include: Fabrication of compound semiconductor epitaxial wafers with double barrier layers; The compound semiconductor epitaxial wafer includes at least a bulk material substrate and an epitaxial functional layer, with a first barrier layer located above the epitaxial functional layer and a second barrier layer located between the epitaxial functional layer and the bulk material substrate. Preparation of temporary silicon carriers; The temporary silicon carrier includes a silicon layer, a first dielectric barrier layer above the silicon layer, and a second dielectric barrier layer below the silicon layer. The first barrier layer and the second dielectric barrier layer are subjected to a first surface activation bonding to obtain a wafer after the first bonding. Remove the bulk material substrate and the second barrier layer from the wafer after the first bonding to expose the surface of the epitaxial functional layer, and obtain the wafer after the first transfer. The epitaxial functional layer is then surface activated and bonded to the target carrier a second time to obtain a wafer after the second bonding. The target carrier in the wafer after the second bonding is attached to the temporary corrosion protection carrier using low-temperature wax or temporary bonding adhesive. The first dielectric barrier layer, silicon layer, second dielectric barrier layer and first barrier layer are removed sequentially, and the temporary corrosion protection carrier is removed by heating to obtain the compound semiconductor epitaxial film on the target carrier.

2. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, The compound semiconductor epitaxial wafer is a GaAs-based epitaxial wafer or an InP-based epitaxial wafer; Among them, GaAs-based epitaxial wafers include GaAs bulk material substrates and GaAs-based, AlGaAs-based, or InGaP-based epitaxial functional layers; InP-based epitaxial wafers include InP bulk material substrates and InP-based, InGaAs-based, or InGaAsP-based epitaxial functional layers. In response to the determination that the bulk material substrate is a GaAs substrate, the barrier layer is an InGaP layer; In response to the determination that the bulk material substrate is an InP substrate, the barrier layer is an InGaAs layer.

3. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, The thickness of the first barrier layer and the second barrier layer is 50 nanometers to 1 micrometer.

4. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, The first dielectric barrier layer and the second dielectric barrier layer are either SiO2 layers or SiN layers; The thickness of the first dielectric barrier layer and the second dielectric barrier layer is 100 nanometers to 1 micrometer. The overall thickness of the temporary silicon carrier ranges from 100 micrometers to 700 micrometers.

5. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, The surface activation bonding process includes: The surfaces to be bonded are sequentially subjected to surface activation, silicon intermediate layer sputtering, and lamination contact treatment to complete surface activation bonding; The bonding surfaces after the press-fit contact treatment are reinforced by low-temperature annealing. The bonding surfaces for the first surface activation bonding include the upper surface of the first barrier layer and the lower surface of the second dielectric barrier layer, while the bonding surfaces for the second surface activation bonding include the surface of the epitaxial functional layer and the upper surface of the target carrier.

6. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, Removing the bulk substrate and second barrier layer from the wafer after the first bonding includes: Mechanical thinning and polishing are performed on the bulk material substrate in the wafer after the first bonding. The remaining bulk material substrate and second barrier layer are removed by selective wet etching.

7. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 5, characterized in that, After the first bonding, the bulk material substrate in the wafer is mechanically thinned to 10 micrometers to 500 micrometers.

8. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 5, characterized in that, In response to the determination that the bulk material substrate is a GaAs substrate, the remaining bulk material substrate is removed by etching using an H3PO4:H2O2:H2O system; In response to the determination that the bulk material substrate is an InP substrate, the remaining bulk material substrate is removed by etching using an HCl:H2O system; In response to the determination that the second barrier layer material is an InP system, the second barrier layer is removed by etching using an H3PO4:H2O2:H2O system. In response to the determination that the second barrier layer material is GaAs system, the second barrier layer is removed by etching using HCl:H2O system; The process of using an H3PO4:H2O2:H2O system to etch and remove the remaining bulk substrate includes: The remaining bulk material substrate was rapidly etched using a high concentration ratio to obtain a remaining bulk material substrate that is close to the barrier layer. Selective etching of the remaining bulk material substrate near the barrier layer was performed using a low concentration ratio.

9. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 5, characterized in that, The silicon intermediate layer is an intermediate layer formed by sputtering during the surface activation bonding process; The total thickness of the silicon interlayer ranges from 1 nanometer to 100 nanometers; The annealing temperature for low-temperature annealing strengthening is 100℃ to 400℃.

10. The method for secondary transfer of compound semiconductor epitaxial thin films according to claim 1, characterized in that, The temporary corrosion protection carrier is a sapphire sheet; The silicon layer in the temporary silicon carrier is removed by a first wet etching method or a dry etching method. The first wet etching method uses potassium hydroxide (KOH) solution or tetramethylammonium hydroxide (TMAH) solution. The first dielectric barrier layer and the second dielectric barrier layer are removed by a second wet etching method; the second wet etching method uses buffer oxide etching solution BOE or hydrofluoric acid HF solution.

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