Method for manufacturing a metal film and semiconductor chip

Abstract

The present disclosure provides a preparation method of a metal film and a semiconductor chip, and belongs to the field of power electronics. The preparation method comprises: providing a semiconductor product; depositing a first aluminum-containing metal layer on the surface of the semiconductor product at a first deposition power and a first deposition rate; increasing the deposition power to a second deposition power and increasing the deposition rate to a second deposition rate to deposit a second aluminum-containing metal layer on the first aluminum-containing metal layer to form the metal film. The embodiments of the present disclosure can improve the coverage of metal materials on the step or recessed area and improve the reliability of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics, and in particular to a method for preparing a metal film and a semiconductor chip. Background Technology

[0002] A high electron mobility transistor (HEMT) in semiconductor chips is a field-effect transistor that uses a two-dimensional electron gas formed at a heterojunction interface as a conductive channel. Transistors have advantages such as high electron mobility, high operating frequency, and low noise, and are widely used in various electrical appliances.

[0003] In related technologies, power semiconductor devices typically consist of a substrate, a buffer layer, a channel layer, a barrier layer, multiple dielectric layers, and a metal layer stacked sequentially. During the preceding processes, the surface of the multiple dielectric layers is not perfectly smooth due to the multiple deposition and etching steps involved. Especially in the steps formed by the dielectric layers or the edges of contact holes, the cumulative effect of the multilayer structure often leads to microscopic height differences on the surface.

[0004] Since metal layers are typically fabricated using physical vapor deposition (PVD), and PVD has directional deposition characteristics, it is difficult to completely fill microscopic angles or recessed areas on the surface of the preceding layer. Areas with significant elevation differences are prone to forming deep recesses or internal voids, which not only cause localized current density concentration and increased interconnect resistance but may also induce stress concentration. In subsequent processes or device operation, these problems may further lead to metal layer fracture or electromigration failure, affecting the reliability of power semiconductor devices. Summary of the Invention

[0005] This disclosure provides a method for preparing a metal film and a semiconductor chip, which can improve the coverage of metal materials in stepped or recessed areas and improve the reliability of semiconductor devices. The technical solution is as follows: On one hand, embodiments of this disclosure provide a method for preparing a metal film, the method comprising: providing a semiconductor product; depositing a first aluminum-containing metal layer on the surface of the semiconductor product at a first deposition power and a first deposition rate; increasing the deposition power to a second deposition power and increasing the deposition rate to a second deposition rate to deposit a second aluminum-containing metal layer on the first aluminum-containing metal layer to form the metal film.

[0006] In one implementation of this disclosure, the first deposition power is 1 kW to 3 kW, and the first deposition rate is 0.18 μm / min to 0.54 μm / min.

[0007] In another implementation of this disclosure, the second deposition power is 8 kW to 10 kW, and the second deposition rate is 1.44 μm / min to 1.8 μm / min.

[0008] In another implementation of this disclosure, depositing a first aluminum-containing metal layer on the surface of the semiconductor article includes: depositing a first aluminum-containing metal layer with a thickness of 0.2 μm to 0.8 μm on the surface of the semiconductor article; depositing a second aluminum-containing metal layer on the first aluminum-containing metal layer includes: depositing a second aluminum-containing metal layer with a thickness of 2.2 μm to 2.8 μm on the first aluminum-containing metal layer.

[0009] In another implementation of this disclosure, both the first aluminum-containing metal layer and the second aluminum-containing metal layer include at least one of an Al layer, an AlSi layer, an AlCu layer, and an AlSiCu layer.

[0010] In another implementation of this disclosure, when depositing a first aluminum-containing metal layer on the surface of the semiconductor product, the deposition temperature is controlled to be between 250°C and 300°C; when depositing a second aluminum-containing metal layer on the first aluminum-containing metal layer, the deposition temperature is controlled to be between 250°C and 300°C.

[0011] In another implementation of this disclosure, before depositing a first aluminum-containing metal layer on the surface of the semiconductor article, the method further includes: depositing an adhesion layer on the surface of the semiconductor article, the adhesion layer comprising a Ti layer; and after depositing a second aluminum-containing metal layer on the first aluminum-containing metal layer, the method further includes: depositing a barrier layer on the surface of the second aluminum-containing metal layer, the barrier layer comprising a TiN layer.

[0012] On the other hand, this disclosure provides a semiconductor chip comprising an epitaxial layer, a dielectric film, and a metal film prepared by the preparation method described above, which are stacked sequentially.

[0013] Optionally, the metal film includes an adhesive layer, an aluminum-containing layer, and a barrier layer stacked sequentially, wherein the aluminum-containing layer includes at least one of an Al layer, an AlSi layer, an AlCu layer, and an AlSiCu layer.

[0014] Optionally, the thickness of the aluminum-containing layer is 2.5 μm to 3.5 μm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The metal film preparation method provided in this disclosure divides the metal film deposition into two steps. The first step employs low-power, slow-speed deposition, utilizing its excellent step coverage capability to fill the microscopic angles and recessed areas on the surface of semiconductor products, fundamentally eliminating the root cause of subsequent filling defects. In related technologies, the directional deposition characteristics of PVD processes make it difficult to completely fill the microscopic height differences on the surface of semiconductor products, easily forming voids or depressions at the edges of steps or recesses, leading to concentrated current density and increased interconnect resistance. The first-step deposition method of this disclosure, through lower deposition power and rate, allows aluminum atoms to cover and fill these microstructures more uniformly and non-directionally, thereby improving the step coverage effect.

[0016] Furthermore, by depositing only a portion of the metal film using a low-power, slow-speed mode, and increasing the deposition power and deposition rate to the second deposition rate for the main thickness portion, the deposition of the second aluminum-containing metal layer is completed. This solves the problem of filling the micro-regions and avoids the problem of reduced wafer throughput (WPH) caused by low-power deposition throughout the process. While ensuring the quality of metal layer filling, the impact of process adjustments on overall production efficiency is minimized.

[0017] Meanwhile, using an aluminum-containing metal layer as the metal film is advantageous because aluminum has a melting point of only 660℃, making it a low-melting-point metal. Under the high-temperature environment generated by the operation of power devices and the thermal effect brought about by power regulation during the deposition process, aluminum atoms are more likely to migrate at the microscopic level, exhibiting flow-like characteristics. This can further bridge the microstructural gaps that may occur during the deposition process, while avoiding current accumulation and stress concentration problems caused by incomplete metal filling. This effectively reduces interconnect resistance, improves the anti-electromigration ability of the metal layer, and ultimately extends the long-term operating life of the power devices.

[0018] Moreover, this disclosure does not require additional complex processes such as sacrificial layer deposition and chemical mechanical polishing, nor does it require the introduction of special materials or the addition of special equipment. It can be achieved simply by optimizing the deposition program of the existing standard PVD machine and adjusting parameters such as power and deposition rate. It is highly compatible with the existing back-end process flow of power devices, does not require major modifications to the existing production line, reduces the cost and threshold of technology iteration, and is easier to achieve large-scale integration and mass production promotion. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a method for preparing a metal film according to an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a transistor provided in an embodiment of this disclosure; Figure 4 It is an electron microscope image of a semiconductor chip provided by related technologies; Figure 5 This is an electron microscope image of a semiconductor chip provided in an embodiment of this disclosure.

[0021] The markings in the diagram are explained as follows: 10. Substrate; 20. Epitaxial layer; 30. Dielectric film; 31. First MOSiN layer; 32. AlN layer; 33. Second MOSiN layer; 34. LPSiN layer; 35. PESiN layer; 36. Dielectric layer; 40. Metal film; 41. Adhesive layer; 42. First aluminum-containing metal layer; 43. Second aluminum-containing metal layer; 44. Barrier layer; 50. Buffer layer; 60. Metal contact layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0023] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0024] Figure 1 This is a flowchart illustrating a method for preparing a metal film according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes: Step S11: Provide a semiconductor product.

[0025] In this process, the surface of the semiconductor product has a region where a metal film is to be deposited, and the region where the metal film is to be deposited has steps or pits, resulting in a microscopic height difference on the surface of the region where the metal film is to be deposited.

[0026] Step S12: Deposit a first aluminum-containing metal layer on the surface of the semiconductor product with a first deposition power and a first deposition rate.

[0027] Step S13: Increase the deposition power to the second deposition power and increase the deposition rate to the second deposition rate to deposit a second aluminum-containing metal layer on the first aluminum-containing metal layer to form a metal film.

[0028] The metal film preparation method provided in this disclosure divides the metal film deposition into two steps. The first step employs low-power, slow-speed deposition, utilizing its excellent step coverage capability to fill the microscopic angles and recessed areas on the surface of semiconductor products, fundamentally eliminating the root cause of subsequent filling defects. In related technologies, the directional deposition characteristics of PVD processes make it difficult to completely fill the microscopic height differences on the surface of semiconductor products, easily forming voids or depressions at the edges of steps or recesses, leading to concentrated current density and increased interconnect resistance. The first-step deposition method of this disclosure, through lower deposition power and rate, allows aluminum atoms to cover and fill these microstructures more uniformly and non-directionally, thereby improving the step coverage effect.

[0029] Furthermore, by depositing only a portion of the metal film using a low-power, slow-speed mode, and increasing the deposition power and deposition rate to the second deposition rate for the main thickness portion, the deposition of the second aluminum-containing metal layer is completed. This solves the problem of filling the micro-regions and avoids the problem of reduced wafer throughput (WPH) caused by low-power deposition throughout the process. While ensuring the quality of metal layer filling, the impact of process adjustments on overall production efficiency is minimized.

[0030] Meanwhile, using an aluminum-containing metal layer as the metal film is advantageous because aluminum has a melting point of only 660℃, making it a low-melting-point metal. Under the high-temperature environment generated by the operation of power devices and the thermal effect brought about by power regulation during the deposition process, aluminum atoms are more likely to migrate at the microscopic level, exhibiting flow-like characteristics. This can further bridge the microstructural gaps that may occur during the deposition process, while avoiding current accumulation and stress concentration problems caused by incomplete metal filling. This effectively reduces interconnect resistance, improves the anti-electromigration ability of the metal layer, and ultimately extends the long-term operating life of the power devices.

[0031] Moreover, this disclosure does not require additional complex processes such as sacrificial layer deposition and chemical mechanical polishing, nor does it require the introduction of special materials or the addition of special equipment. It can be achieved simply by optimizing the deposition program of the existing standard PVD machine and adjusting parameters such as power and deposition rate. It is highly compatible with the existing back-end process flow of power devices, does not require major modifications to the existing production line, reduces the cost and threshold of technology iteration, and is easier to achieve large-scale integration and mass production promotion.

[0032] The semiconductor chip provided in step S11 may include a light-emitting diode or a transistor.

[0033] Taking a transistor as an example, a semiconductor chip may include a substrate, a buffer layer, an epitaxial layer, and a dielectric film stacked sequentially. To achieve conductive communication with the epitaxial layer, holes need to be formed in the dielectric film, but the height difference on the surface of the dielectric film results in incomplete metal filling.

[0034] For example, the substrate may be a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.

[0035] For example, the buffer layer includes AlGaN layers and GaN layers stacked sequentially.

[0036] The thickness of the AlGaN layer ranges from 10 nm to 50 nm. The growth temperature of the AlGaN layer ranges from 500 °C to 700 °C.

[0037] The thickness of the GaN layer is 1 μm to 2 μm. The growth temperature of the GaN layer is 900℃ to 1100℃.

[0038] For example, the channel layer can be a GaN layer.

[0039] As an example, the thickness of the channel layer ranges from 100 nm to 500 nm.

[0040] For example, the barrier layer is an AlGaN layer.

[0041] As an example, the thickness of the barrier layer is 20 nm to 30 nm.

[0042] For example, the dielectric film may include at least one of a silicon oxide layer, a silicon nitride layer, and an aluminum nitride layer.

[0043] Prior to step S12, an adhesion layer is deposited on the surface of the semiconductor article.

[0044] For example, the adhesive layer includes a Ti layer.

[0045] In step S11, no adhesive structure is pre-set on the surface of the semiconductor product. Before depositing the first aluminum-containing metal layer, an adhesive layer needs to be deposited on the surface of the semiconductor product. The adhesive layer is a Ti layer, which can enhance the bonding force between the aluminum-containing metal layer and the underlying dielectric film and avoid interlayer peeling defects in subsequent processes.

[0046] Step S12 includes: depositing a first aluminum-containing metal layer on the surface of the semiconductor article at a first deposition power and a first deposition rate.

[0047] Step S12 is performed using a standard physical vapor deposition (Std PVD) chamber, with the deposition temperature controlled between 250°C and 300°C.

[0048] For example, the deposition temperature can be set to 275°C to ensure that aluminum atoms have basic thermal mobility while avoiding thermal damage to the preceding dielectric film structure.

[0049] Optionally, the first deposition power is 1 kW to 3 kW, and the first deposition rate is 0.18 μm / min to 0.54 μm / min.

[0050] The first deposition power is set to a low power mode of 1kW to 3kW, corresponding to a first deposition rate of 0.18μm / min to 0.54μm / min.

[0051] Low-power, slow-speed deposition sputtering particles have lower energy and weaker deposition directionality. The particles can cover the surface of semiconductor products with more uniform diffraction characteristics. In particular, they can penetrate into the microscopic angles and depressions in areas such as dielectric film steps and contact hole edges to achieve conformal filling, thereby avoiding the filling dead corner problem caused by excessive directionality during subsequent high-power deposition.

[0052] Optionally, the first aluminum-containing metal layer includes at least one of an Al layer, an AlSi layer, an AlCu layer, and an AlSiCu layer.

[0053] Among them, alloy systems such as AlSi and AlCu can further enhance the anti-electromigration ability of the metal layer, adapting to the high current density operating requirements of power devices.

[0054] Meanwhile, since aluminum has a melting point of only 660℃, it is a low-melting-point metal. Under the thermal effects of deposition at a deposition temperature of 250℃ to 300℃ and low-power deposition, aluminum atoms have the ability to migrate at the microscopic level, which can further bridge the tiny gaps that appear during the deposition process, making the filling structure more compact.

[0055] Optionally, the deposition thickness of the first aluminum-containing metal layer is controlled to be between 0.2 μm and 0.8 μm.

[0056] The thickness of the first aluminum-containing metal layer is set to be relatively thin, ranging from 0.2 μm to 0.8 μm. This ensures the filling effect in critical areas while avoiding excessive impact of low-power deposition on overall production capacity, thus reserving a process window for subsequent high-power rapid deposition.

[0057] Step S13 includes: increasing the deposition power to a second deposition power and increasing the deposition rate to a second deposition rate, depositing a second aluminum-containing metal layer on the first aluminum-containing metal layer to form a complete metal film.

[0058] Step S13 is carried out using a standard physical vapor deposition chamber, with the deposition temperature maintained in the same range of 250°C to 300°C as in step S12.

[0059] For example, the deposition temperature can be 275°C to ensure thermal compatibility between the two aluminum-containing metal layers and avoid thermal stress caused by temperature differences between the layers.

[0060] Optionally, the second deposition power is 8 kW to 10 kW, and the second deposition rate is 1.44 μm / min to 1.8 μm / min.

[0061] Optionally, the deposition thickness of the second aluminum-containing metal layer is 2.2 μm to 2.8 μm.

[0062] Among them, the second deposition power is increased to a high-power mode of 8kW to 10kW, corresponding to a second deposition rate of 1.44μm / min to 1.8μm / min, and the deposition thickness of the second aluminum-containing metal layer is controlled in the range of 2.2μm to 2.8μm, so that the total thickness of the first aluminum-containing metal layer and the second aluminum-containing metal layer reaches 2.5μm to 3.5μm, which meets the thickness requirements of the metal film of power semiconductor devices.

[0063] High-power sputtering particles have higher energy and stronger directionality, which can quickly stack on the surface of the first aluminum-containing metal layer that has filled the micro-depressions to form a flat metal host layer, greatly improving deposition efficiency.

[0064] Optionally, the second aluminum-containing metal layer includes at least one of an Al layer, an AlSi layer, an AlCu layer, and an AlSiCu layer.

[0065] For example, the second aluminum-containing metal layer is made of the same material as the first aluminum-containing metal layer to avoid introducing additional contact resistance and stress at the interface of different materials.

[0066] In the above implementation, the second aluminum-containing metal layer, which is deposited at high power and at high speed, undertakes the task of depositing the main thickness of the metal film. The high deposition rate of 1.44μm / min to 1.8μm / min can significantly shorten the thick film deposition time. Only a small amount of thickness (0.2μm to 0.8μm) is deposited in low power mode, while the main thickness is still deposited at high power and high speed. This has a minimal impact on the overall wafer throughput (WPH), achieving a balance between fill quality and production efficiency, and meeting the needs of large-scale mass production of power semiconductors.

[0067] Meanwhile, high-power deposition of 8kW to 10kW allows aluminum atoms to gain higher kinetic energy, resulting in denser grains and fewer defects in the deposited metal layer. Combined with the low melting point of aluminum, under the thermal effect of high-power deposition, aluminum atoms can further flow back to fill the tiny gaps between layers, allowing the two aluminum-containing metal layers to form a continuous, void-free overall structure, effectively reducing interconnect resistance and improving the electromigration resistance of the metal layer.

[0068] In addition, the design of maintaining the same deposition temperature for both layers avoids interlayer thermal mismatch caused by temperature fluctuations, reduces residual stress inside the metal layer, lowers the risk of metal layer fracture in subsequent processes or device operation, and ultimately improves the reliability of power semiconductor devices.

[0069] The process after step S13 further includes: depositing a barrier layer on the surface of the second aluminum-containing metal layer.

[0070] For example, the barrier layer includes a TiN layer.

[0071] By depositing a barrier layer on the surface of the second aluminum-containing metal layer, impurities can be prevented from diffusing into the metal layer during subsequent processes, thereby improving the metal layer's resistance to corrosion and electromigration, and also serving as an etching stop layer for subsequent processes.

[0072] Figure 2 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure. Figure 2 As shown, the semiconductor chip includes an epitaxial layer 20, a dielectric film 30, and a metal film 40 prepared by the method described above, which are stacked sequentially.

[0073] The metal film 40 prepared by the aforementioned method involves a two-step deposition process. The first step employs low-power, slow-speed deposition, utilizing its excellent step coverage capability to fill microscopic angles and recessed areas on the surface of the semiconductor product, fundamentally eliminating the root cause of subsequent filling defects. In related technologies, the directional deposition characteristics of PVD processes make it difficult to completely fill the microscopic height differences on the surface of semiconductor products, easily forming voids or depressions at the edges of steps or recesses, leading to concentrated current density and increased interconnect resistance. The first-step deposition method of this disclosure, through lower deposition power and rate, allows aluminum atoms to cover and fill these microstructures more uniformly and non-directionally, thereby improving the step coverage effect.

[0074] Furthermore, only a portion of the metal film 40 is deposited using a low-power, slow-speed mode. The main thickness portion is deposited by increasing the deposition power to the second deposition power and the deposition rate to the second deposition rate to complete the deposition of the second aluminum-containing metal layer 43. This solves the problem of filling the micro-regions and avoids the problem of reduced wafer productivity (WPH) caused by low-power deposition throughout the process. While ensuring the quality of metal layer filling, the impact of process adjustments on overall production efficiency is minimized.

[0075] Meanwhile, an aluminum-containing metal layer is used as the metal film 40 because aluminum has a melting point of only 660℃, which is a low-melting-point metal. Under the high-temperature environment generated by the operation of power devices and the thermal effect brought about by power regulation during the deposition process, aluminum atoms are more likely to migrate at the micro level, exhibiting flow-like characteristics. This can further bridge the micro-structural gaps that may occur during the deposition process, while avoiding current accumulation and stress concentration problems caused by incomplete metal filling. This effectively reduces interconnect resistance, improves the anti-electromigration ability of the metal layer, and ultimately extends the long-term operating life of the power devices.

[0076] Moreover, this disclosure does not require additional complex processes such as sacrificial layer deposition and chemical mechanical polishing, nor does it require the introduction of special materials or the addition of special equipment. It can be achieved simply by optimizing the deposition program of the existing standard PVD machine and adjusting parameters such as power and deposition rate. It is highly compatible with the existing back-end process flow of power devices, does not require major modifications to the existing production line, reduces the cost and threshold of technology iteration, and is easier to achieve large-scale integration and mass production promotion.

[0077] Optionally, such as Figure 2 As shown, the metal film 40 includes an adhesive layer 41, an aluminum-containing layer, and a barrier layer 44 stacked sequentially. The aluminum-containing layer includes at least one of an Al layer, an AlSi layer, an AlCu layer, and an AlSiCu layer.

[0078] For example, the adhesive layer 41 includes a Ti layer.

[0079] A Ti layer is placed between the first aluminum-containing metal layer 42 and the dielectric film 30 as an adhesion layer, which can enhance the bonding force between the aluminum-containing metal layer and the lower dielectric film 30 and avoid interlayer peeling defects in subsequent processes.

[0080] In this embodiment of the disclosure, an aluminum-containing layer is used as the main film structure of the metal film 40. Since aluminum has a melting point of only 660°C, it is a low-melting-point metal. Under the deposition temperature of 250°C to 300°C and the thermal effect of low-power deposition, aluminum atoms have the ability to migrate at the micro level, which can further bridge the tiny gaps that appear during the deposition process, making the filling structure more compact.

[0081] Among them, alloy systems such as AlSi and AlCu can further enhance the anti-electromigration ability of the metal layer, adapting to the high current density operating requirements of power devices.

[0082] For example, the thickness of the aluminum-containing layer is 2.5 μm to 3.5 μm.

[0083] For example, the adhesive layer 41 includes a TiN layer.

[0084] By depositing a barrier layer 44 on the surface of the aluminum-containing layer, impurities can be prevented from diffusing into the metal layer during subsequent processes, thereby improving the metal layer's resistance to corrosion and electromigration, and also serving as an etching stop layer for subsequent processes.

[0085] For example, a semiconductor chip can be a transistor or a light-emitting diode.

[0086] Taking transistors as an example, Figure 3 This is a schematic diagram of a transistor provided in an embodiment of this disclosure. (As shown...) Figure 3 As shown, the transistor may include a substrate 10, a buffer layer 50, an epitaxial layer 20, a first MOSiN layer 31, an AlN layer 32, a second MOSiN layer 33, an LPSiN layer 34, a PESiN layer 35, a metal contact layer 60, a dielectric layer 36, and a metal film 40 stacked sequentially.

[0087] In this embodiment of the disclosure, the area where the metal film is to be deposited is the area exposed after the transistor has completed the preceding dielectric layer and metal contact layer processes, where the source, drain, and gate interconnect metals need to be fabricated.

[0088] The area where the metal film is to be deposited is located on the surface of the uppermost dielectric layer 36 of the transistor and extends downward through the dielectric layer 36 to the metal contact layer 60. From the perspective of the transistor's vertical structure, after the substrate 10, buffer layer 50, and epitaxial layer 20 are stacked sequentially from bottom to top to complete the epitaxial fabrication, the first MOSiN layer 31 is deposited first, followed by the sequential stacking of the AlN layer 32, the second MOSiN layer 33, the LPSiN layer 34 prepared by LPCVD process, and the PESiN layer 35 prepared by PECVD process. The above multilayer structure together constitutes the insulating layer of the device.

[0089] After the dielectric layer 36 is deposited, an etching process is used to form contact holes in the dielectric layer 36 that extend to the metal contact layer 60, which are used to achieve ohmic contact between the device electrode and the epitaxial layer. At this time, the area to be deposited metal film 40 includes two parts: one is the planar area on the upper surface of the dielectric layer 36, and the other is the sidewall and bottom area inside the contact hole. Since the dielectric layer 36 contains multiple layers prepared by different processes, the cumulative effect of the multilayer structure causes microscopic height differences at the edge of the contact hole and the step position of the dielectric layer. At the same time, there are also small depressions at the junction of the bottom of the contact hole and the metal contact layer 60. These areas together constitute the area to be deposited metal film, which is also the area that the aluminum-containing metal layer needs to be filled in the aforementioned two deposition processes.

[0090] In step S12, during the low-power slow deposition of the first aluminum-containing metal layer, aluminum-containing metal particles preferentially fill the micro-depressions at the bottom of the contact hole and the micro-angle region between the edge of the contact hole and the step of the dielectric layer. Combined with the low melting point of aluminum at a deposition temperature of 250°C to 300°C, dense conformal filling is achieved. In step S13, the high-power rapid deposition of the second aluminum-containing metal layer quickly completes the deposition of the main thickness of the metal film 40 on the surface of the already filled first aluminum-containing metal layer. The final metal film 40 not only completely covers the upper surface of the dielectric layer 36, but also fully fills the contact hole region, achieving a high-quality electrical connection between the metal contact layer 60 and the subsequent interconnect structure. This avoids current accumulation and stress concentration problems caused by filling defects, and is suitable for the high-voltage and high-current operating scenarios of HEMT devices.

[0091] For example, the substrate may be a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate.

[0092] For example, the buffer layer 50 includes AlGaN layers and GaN layers stacked sequentially.

[0093] The thickness of the AlGaN layer ranges from 10 nm to 50 nm. The growth temperature of the AlGaN layer ranges from 500 °C to 700 °C.

[0094] The thickness of the GaN layer is 1 μm to 2 μm. The growth temperature of the GaN layer is 900℃ to 1100℃.

[0095] For example, the dielectric layer 36 includes one or more of a PESiN layer and a PESiO layer.

[0096] For example, the channel layer can be a GaN layer.

[0097] As an example, the thickness of the channel layer ranges from 100 nm to 500 nm.

[0098] For example, the barrier layer is an AlGaN layer.

[0099] As an example, the thickness of the barrier layer is 20 nm to 30 nm.

[0100] The MOSiN layer is a SiN layer prepared using a metal-organic chemical vapor deposition (MOCVD) process.

[0101] Among them, the PESiN layer 35 is a SiO layer prepared by plasma-enhanced chemical vapor deposition (PECVD) process.

[0102] Among them, the LPSiN layer 34 is a SiN layer prepared by low-pressure chemical vapor deposition (LPCVD) process.

[0103] Optionally, the metal contact layer 60 includes a Ti layer, an AlSi layer, and a TiN layer stacked sequentially.

[0104] Figure 4 This is an electron microscope image of a semiconductor chip provided by related technologies. Figure 5 This is an electron microscope image of a semiconductor chip provided in an embodiment of this disclosure.

[0105] like Figure 4 As shown, the metal film 40 prepared in the related technology has a lot of void defects X at the contact surface with the dielectric film 30 and at the location of the groove.

[0106] like Figure 5 As shown, the metal film 40 prepared in this embodiment is in close contact with the dielectric film 30, and there are no voids or defects in the groove. Therefore, the metal film 40 prepared in this embodiment can effectively cover and fill the microstructure on the surface of the dielectric film 30, improving the coverage effect of the metal film 40.

[0107] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for preparing a metal film (40), characterized in that, The preparation method includes: Provide a semiconductor product; A first aluminum-containing metal layer (42) is deposited on the surface of the semiconductor article with a first deposition power and a first deposition rate. The deposition power is increased to a second deposition power, and the deposition rate is increased to a second deposition rate to deposit a second aluminum-containing metal layer (43) on the first aluminum-containing metal layer (42) to form the metal film (40).

2. The preparation method according to claim 1, characterized in that, The first deposition power is 1 kW to 3 kW, and the first deposition rate is 0.18 μm / min to 0.54 μm / min.

3. The preparation method according to claim 1, characterized in that, The second deposition power is 8 kW to 10 kW, and the second deposition rate is 1.44 μm / min to 1.8 μm / min.

4. The preparation method according to any one of claims 1 to 3, characterized in that, Depositing a first aluminum-containing metal layer (42) on the surface of the semiconductor article includes: A first aluminum-containing metal layer (42) with a thickness of 0.2 μm to 0.8 μm is deposited on the surface of the semiconductor article. Depositing a second aluminum-containing metal layer (43) on the first aluminum-containing metal layer (42) includes: A second aluminum-containing metal layer (43) with a thickness of 2.2 μm to 2.8 μm is deposited on the first aluminum-containing metal layer (42).

5. The preparation method according to any one of claims 1 to 3, characterized in that, The first aluminum-containing metal layer (42) and the second aluminum-containing metal layer (43) each include at least one of Al layer, AlSi layer, AlCu layer and AlSiCu layer.

6. The preparation method according to any one of claims 1 to 3, characterized in that, When depositing the first aluminum-containing metal layer (42) on the surface of the semiconductor article, the deposition temperature is controlled to be 250°C to 300°C; A second aluminum-containing metal layer (43) is deposited on the first aluminum-containing metal layer (42), and the deposition temperature is controlled to be 250°C to 300°C.

7. The preparation method according to any one of claims 1 to 3, characterized in that, Before depositing the first aluminum-containing metal layer (42) on the surface of the semiconductor article, the method further includes: An adhesion layer (41) is deposited on the surface of the semiconductor article, the adhesion layer (41) comprising a Ti layer; After depositing the second aluminum-containing metal layer (43) on the first aluminum-containing metal layer (42), the process further includes: A barrier layer (44) is deposited on the surface of the second aluminum-containing metal layer (43), the barrier layer (44) comprising a TiN layer.

8. A semiconductor chip, characterized in that, The semiconductor chip includes an epitaxial layer (20), a dielectric film, and a metal film (40) prepared by the preparation method according to any one of claims 1 to 7, which are stacked sequentially.

9. The semiconductor chip according to claim 8, characterized in that, The metal film (40) comprises an adhesive layer (41), an aluminum-containing layer and a barrier layer (44) stacked sequentially, wherein the aluminum-containing layer comprises at least one of an Al layer, an AlSi layer, an AlCu layer and an AlSiCu layer.

10. The semiconductor chip according to claim 9, characterized in that, The thickness of the aluminum-containing layer is 2.5 μm to 3.5 μm.

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