Method for improving ion implantation uniformity

Abstract

The application provides a method for improving ion implantation uniformity, comprising: providing a semiconductor layer to be ion implanted, the semiconductor layer being formed with a photoresist pattern, the photoresist pattern being defined with a process window; performing additional baking on the photoresist pattern; performing ion implantation with a conductive type on the semiconductor layer by using the baked photoresist pattern as an implantation mask; removing the photoresist pattern from the semiconductor layer; and performing heat treatment on the semiconductor layer after ion implantation. The application adds a baking step on the photoresist pattern before performing ion implantation process based on the photoresist pattern. The chemical stability of the baked photoresist pattern is improved, so that the amount of gas released under the bombardment of the ion beam is reduced, and the divergence of the ion beam reaching the vicinity of the photoresist pattern is reduced, which is beneficial to improving the resistivity uniformity of the doped region in the semiconductor layer, and expanding the process margin of the parameter range of the ion implantation process, such as beam current intensity and beam current density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for improving ion implantation uniformity. Background Technology

[0002] Ion implantation is a material surface improvement technology that has flourished and gained widespread application internationally in recent years. Its principle is to use an ion beam with an energy of, for example, 100 keV to be incident on the material, so that the ion beam interacts with the atoms or molecules in the material in a series of physical and chemical ways. The incident ions gradually lose energy and eventually remain in the material, causing changes in the surface composition, structure and properties of the material, thereby optimizing the surface properties of the material or obtaining certain new superior properties.

[0003] Doping technology is fundamental to the fabrication of semiconductor devices, and ion implantation is one of the most commonly used doping methods. This process involves introducing a controllable number of impurities into a semiconductor substrate, thereby altering its electrical properties. Because ion implantation technology allows for repeated control of the concentration and depth of the doped impurities, most doping processes in current semiconductor device manufacturing technologies are implemented using ion implantation. In existing processes, after defining the implantation pattern on the material layer using photolithography, ion implantation is performed to achieve precise N-type or P-type doping. However, the uniformity of the ion implantation beam current density directly affects the on-chip consistency of the final wafer's electrical parameters. Currently, the problem of electrical inhomogeneity caused by ion implantation is generally addressed by tightening the range of beam current parameters such as beam current intensity and beam current density of the ion implanter. However, by tightening the limits of a single parameter, the ion beam will be frequently restarted due to the relevant parameters exceeding the limit range. This makes the ion implantation beam difficult to maintain, resulting in a waste of manpower and machine time, and ultimately leading to a loss of production capacity.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving ion implantation uniformity, which solves the problems of ion beam divergence and the resulting deterioration of chip electrical parameters when performing ion implantation processes based on implantation masks formed by photoresist, as well as the loss of production capacity caused by limiting the range of beam-related parameters.

[0006] To achieve the above and other related objectives, the present invention provides a method for improving ion implantation uniformity, comprising the following steps:

[0007] A semiconductor layer to be ion implanted is provided, wherein a photoresist pattern is formed on the semiconductor layer, and the photoresist pattern defines a process window;

[0008] The photoresist pattern is baked;

[0009] The semiconductor layer is implanted with ions of a conductive type using the baked photoresist pattern as an implantation mask.

[0010] Remove the photoresist pattern from the semiconductor layer;

[0011] The semiconductor layer after ion implantation is subjected to heat treatment.

[0012] Optionally, before baking the photoresist pattern, the process includes: hard baking the developed photoresist layer to obtain the photoresist pattern; and then inspecting the photoresist pattern after development.

[0013] Optionally, the photoresist pattern is baked at a temperature of 100°C-150°C; wherein the baking is performed at least once, and the duration of each baking is not less than 60 seconds.

[0014] Furthermore, the photoresist pattern is baked multiple times, with each baking session lasting 60 seconds.

[0015] Optionally, a rapid thermal annealing process is used to perform a thermal treatment step on the semiconductor layer after ion implantation, activating and advancing dopant ions to form a doped region; wherein the rapid thermal annealing process includes one or a combination of laser annealing and spike annealing.

[0016] Optionally, after the step of forming the photoresist pattern, the photoresist pattern may be additionally baked by vacuum heating.

[0017] Furthermore, the additional baking step for the photoresist pattern includes: the semiconductor layer on which the photoresist pattern is formed is transported to a load-locking chamber; subsequently, the vacuum level in the load-locking chamber is maintained at 10. -4 Pa to 10 -6Under the condition of Pa, the photoresist pattern is additionally baked using a heating component.

[0018] Furthermore, the load-locking chamber is equipped with cooling pipes, and the semiconductor layer is cooled using the cooling pipes before the step of ion implantation of the semiconductor layer.

[0019] Optionally, the ion implantation step may be performed using an ion beam with an ion beam current between 0.5 mA and 14.5 mA.

[0020] As described above, the method for improving ion implantation uniformity of the present invention adds a baking step to the photoresist pattern before performing the ion implantation process. Since the baked photoresist pattern has a smaller volume and improved chemical stability, the amount of gas released under the bombardment of the ion beam is reduced. This reduces the divergence of the ion beam reaching the vicinity of the photoresist pattern, which is beneficial to improving the resistivity uniformity of the doped region within the semiconductor layer. It also expands the process margin of parameters such as beam current intensity and beam current density in the ion implantation process, avoids frequent beam restarts that affect process stability, and can improve yield and product quality. In addition, by appropriately increasing the baking time or increasing the number of times it is performed, the electron beam divergence can be significantly reduced, improving the electrical uniformity of the resulting doped region, thereby improving the on-wafer uniformity of the final wafer electrical parameters. Attached Figure Description

[0021] Figures 1 to 3 The diagram shows a process of performing ion implantation using a photoresist pattern as an implantation mask.

[0022] Figure 4 Displayed as Figure 2 A partial schematic diagram of the ion beam used in step (2) is shown.

[0023] Figure 5 The flowchart shown is a comparative example and embodiment of the present invention, illustrating the formation of doped regions via ion implantation.

[0024] Figures 6 to 9 The diagram shows the structure after steps S1 to S3 in the method for improving ion implantation uniformity according to an embodiment of the present invention.

[0025] Figure 10 for Figure 9 A partial schematic diagram of the ion beam current used in step S3 is shown.

[0026] Figure 11A The diagram shows the transmission path within the terminal station of the ion implantation device in an embodiment of the present invention.

[0027] Figure 11BThe diagram shows an exemplary structural diagram of a load-locking chamber used to perform an additional baking step for photoresist patterning in an embodiment of the present invention.

[0028] Figure 12 The graphs are used to illustrate the average sheet resistance, standard deviation, and distribution of the doped regions in the comparative examples and experimental examples of this invention.

[0029] Explanation of reference numerals in the attached figures

[0030] 10 Semiconductor Layer

[0031] 20, 20b photoresist pattern

[0032] B ion beam

[0033] B1 and B2 diverging ion beams

[0034] G1 and G2 volatile gases

[0035] 30 Loading Port

[0036] 31 robotic arms

[0037] 32 Load Locking Chamber

[0038] 34 Processing Chamber

[0039] 322 storage space

[0040] 324 vacuum tube

[0041] 326 heating lamp

[0042] 328 Cooling Pipeline

[0043] Steps S1 to S6 Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] Figures 1 to 3This diagram illustrates the structure of an ion implantation process using a photoresist pattern as an implantation mask, showing the various steps involved.

[0047] (1) As Figure 1 As shown, a semiconductor layer 10 to be ion implanted is provided, and a photoresist pattern 20 is formed on the semiconductor layer 10. The photoresist pattern 20 defines a process window.

[0048] (2) Figure 2 As shown, the semiconductor layer 10 is implanted with ions of conductive type using the photoresist pattern 20 as an implantation mask;

[0049] (3) The surface of the photoresist pattern 20 is bombarded, releasing volatile gas G1. The volatile gas G1 causes the ion beam B to diverge, forming a diverging ion beam B1.

[0050] In the above steps, a process window is defined in the photoresist pattern 20. During the ion implantation process with conductivity type using the photoresist pattern 20 as an implantation mask, the ion beam is projected onto the semiconductor layer on which the photoresist pattern is formed. Although the photoresist pattern is formed through a series of processes such as spin coating, soft baking, exposure and development, the ion implantation process is usually performed at a low vacuum level (generally 10). -1 Pa to 10 -4 Even in a chamber environment within the Pa range, the bombardment of photoresist patterns by the ion beam still generates a large amount of volatile gases, causing severe ion beam divergence, such as... Figure 4 The ion beam B1 shown.

[0051] Furthermore, in order to suppress the aforementioned ion beam divergence, the range of beam current parameters such as beam current intensity and beam current density of the ion implanter is tightened. After tightening the parameter limit range, if the ion beam restarts multiple times during the single-wafer fabrication process, it will pose a challenge to the electrical stability of the wafer.

[0052] Through extensive analysis, research and experimentation, the inventors of this application have improved the process flow for forming ion-doped regions, which can help reduce the divergence of the ion beam, thereby improving the process stability of ion implantation and the resistivity uniformity of the resulting doped regions.

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0055] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0056] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0057] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0058] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] This invention provides a method for improving ion implantation uniformity; please refer to [link to relevant documentation]. Figure 5 The diagram shows the process flow of this method, which includes the following steps:

[0061] S1: Provide a semiconductor layer to be ion implanted, wherein a photoresist pattern is formed on the semiconductor layer, and the photoresist pattern defines a process window;

[0062] S2: Perform additional baking on the photoresist pattern;

[0063] S3: Using the baked photoresist pattern as an implantation mask, perform ion implantation of the semiconductor layer with a conductive type;

[0064] S4: Remove the photoresist pattern from the semiconductor layer;

[0065] S5: Perform heat treatment on the semiconductor layer after ion implantation;

[0066] S6: Perform electrical tests on the semiconductor layer after ion implantation.

[0067] The following section will detail each of the above steps in conjunction with the structural diagram.

[0068] First, perform step S1: provide a semiconductor layer 10 to be ion implanted, on which a photoresist pattern 20 is formed, and the photoresist pattern 20 defines a process window.

[0069] Specifically, the semiconductor layer 10 can be the semiconductor substrate itself, or a semiconductor layer formed on a substrate (not shown). The substrate can be a silicon substrate, germanium substrate, germanium-silicon substrate, silicon carbide substrate, III-V compound substrate (such as gallium nitride, gallium arsenide, etc.), or a composite substrate such as silicon-on-insulator (SOI), germanium-on-insulator (GOI), or germanium-silicon-on-insulator. The substrate 201 can be doped or undoped, and can also contain doped regions of various concentrations or electrical types to achieve different functions.

[0070] Please see Figure 6 The steps for forming the photoresist pattern 20 include: sequentially performing a series of processes such as spin coating of the photoresist layer, pre-baking, soft baking, exposure, development, and hard baking; the developed photoresist layer is then subjected to hard baking to obtain the photoresist pattern 20; that is, Figure 5 The process routes shown are ① and ②.

[0071] In some examples, the photoresist layer can be a chemically amplified photoresist. This chemically amplified photoresist uses a photoacid (PAG) as a photoinitiator. After the photoresist layer is soft-baked, it is selectively exposed using a deep ultraviolet or extreme ultraviolet light source. The photoacid (PAG) in the exposed area will generate an acid. This acid acts as a catalyst during the subsequent thermal baking process, removing the protective groups of the resin and making the resin easier to dissolve. As a result, this type of photoresist has better optical sensitivity and higher resolution.

[0072] Depending on the circumstances, after forming the photoresist pattern 20, the semiconductor layer is rinsed with deionized water to remove residual developer and residual photoresist.

[0073] Furthermore, after hard baking the developed photoresist layer, the resulting photoresist pattern 20 is subjected to after-development inspection (ADI). In this embodiment, a pattern distortion model of the photoresist pattern before and after baking can be established in advance, and the pattern judgment criteria for after-development inspection can be corrected, thereby ensuring the accuracy of the ion beam profile defined by the baked photoresist pattern.

[0074] Next, please refer to Figure 7 Then, perform step S2: perform additional baking on the photoresist pattern 20.

[0075] Specifically, the photoresist pattern 20 is subjected to additional baking to slightly shrink the photoresist pattern, wherein the baking temperature of the photoresist pattern 20 is selected to densify the interior of the photoresist pattern, for example, by increasing the degree of cross-linking, while the overall photoresist pattern does not deform or round the corners.

[0076] Figure 8 This is a schematic diagram of the photoresist pattern obtained after step S2. After additional baking, as shown... Figure 8 The top surface of the baked photoresist pattern 20b shown is significantly different from the top surface of the initially formed photoresist pattern 20 indicated by the dashed line, indicating that the volume of the baked photoresist pattern 20b has slightly decreased, while its geometry has not changed.

[0077] Compared to conventional ion implantation processes that use photoresist patterns as a barrier layer, the degree of cross-linking of the baked photoresist patterns is increased, and their chemical stability is further improved. When subjected to ion beam bombardment, the amount of volatile gases generated is significantly reduced.

[0078] In some examples, the photoresist pattern is additionally baked at a temperature of 100°C-150°C, wherein the duration of the baking is not less than 60 seconds.

[0079] By appropriately increasing the baking time or the number of times the baking process is performed, it is beneficial to improve the chemical stability of the photoresist pattern. In a preferred example, the additional baking is performed at least once, for example, once or twice, and the duration of each baking operation is preferably 60 seconds.

[0080] In some examples, the photoresist pattern is additionally baked using a vacuum heating method, and this additional baking step can be performed on the transport path of the ion-implanted processing chamber, such as a load-locking chamber. Figure 11A This diagram shows the transport path within the terminal station of the ion implantation device in an embodiment of the present invention. Figure 11AAs shown, after the photolithography process in step S1, the semiconductor layer with the photoresist pattern can be transported to the loading port 30. The additional baking can be performed in the load-locking chamber 32, which is equipped with a vacuum tube 324 (external vacuum device) to provide a chamber environment with the target vacuum level, serving as a transition region between a low-vacuum environment and a high-vacuum environment for ion implantation, thereby reducing the wafer's dwell time between different environments. In a preferred example, such as... Figure 11B As shown, the load-locking chamber 32 is also equipped with a heating component, such as a heating lamp 326. The additional baking step of the photoresist pattern includes: transporting the semiconductor layer with the photoresist pattern formed to the load-locking chamber 32 by a robotic arm 31, while maintaining the vacuum level of the load-locking chamber at 10. -3 Pa to 10 -6 Under the condition of Pa, the photoresist pattern is additionally baked using a heating assembly. Alternatively, a vacuum heating device is provided outside the processing chamber, and the additional baking of the photoresist pattern is performed using the vacuum heating device.

[0081] In some examples, after the additional baking step of the photoresist pattern, the semiconductor layer can be cooled. This additional baking and cooling process can be performed in the same chamber or in separate chambers. Unlike the soft and hard baking processes included in photolithography, where wafers are exposed to near-atmospheric pressure on the transport path after photolithography, reversible gas adsorption and desorption can easily occur. By introducing an additional baking step combined with cooling under vacuum conditions, better degassing can be achieved.

[0082] In a specific example, such as Figure 11B As shown, the load locking chamber is also equipped with a cooling pipe 328. The cooling medium of the cooling pipe 328 may include, for example, water. The semiconductor layer is cooled using the cooling pipe before the ion implantation step. As an additional implementation, the cooled semiconductor layer can be transported into the processing chamber 34 via the robotic arm for subsequent ion implantation processes.

[0083] Of course, additional baking of the photoresist pattern can also be performed using equipment or machines well known to those skilled in the art, including but not limited to: ovens, heating plates, and baking tables.

[0084] Next, please refer to Figure 9 Then, perform step S3: use the baked photoresist pattern 20b as an implantation mask to perform ion implantation of the semiconductor layer 10 with conductivity type.

[0085] Specifically, an ion implantation process is performed using the baked photoresist pattern 20b as an implantation mask. An implantation region is formed in the ion-implanted semiconductor layer, and this implantation region is configured to correspond one-to-one with the process windows defined in the photoresist pattern. In this case, the photoresist pattern 20b acts as a barrier layer, allowing the ion beam to enter the area of ​​the semiconductor layer not covered by the photoresist pattern. Alternatively, in an ion implantation process using a high-energy ion beam, in addition to the area of ​​the semiconductor layer not covered by the photoresist pattern, a portion of the high-energy ion beam can also penetrate the photoresist pattern and enter beneath it.

[0086] In step S3, using the baked photoresist pattern 20b as an implantation mask, an ion beam B bombards the side of the semiconductor layer where the photoresist pattern is formed, releasing volatile gas G2. In some examples, the ion implantation process is performed at a vacuum level of 10. -3 Pa to 10 -6 In the process chamber of Pa, such as Figure 9 As shown, after the photoresist pattern 20b is baked, the chemical stability of the photoresist pattern is improved, and the amount of gas generated by the ion beam bombardment is reduced, resulting in a significant improvement in the divergence of the ion beam. Figure 10 The diverging ion beam B2 is shown.

[0087] In this embodiment, an ion beam with an ion current between 0.5 mA and 14.5 mA is used to perform the ion implantation step. Compared to the conventional method of restricting the ion beam current parameters of the ion implantation equipment, introducing a photoresist pattern baking step before the ion implantation process can expand the process margin, such as the ion beam current density, and avoid multiple restarts in a single wafer fabrication process that could affect process stability.

[0088] It should be noted that the type of ions, implantation energy, angle, and similar process parameters can be flexibly adjusted according to the electrical properties of the desired doping region.

[0089] Next, step S4 is performed: the photoresist pattern is removed from the semiconductor layer.

[0090] After step S3, the photoresist remaining on the surface of the semiconductor layer is removed by dry or wet stripping.

[0091] Next, step S5 is performed: the semiconductor layer after ion implantation is subjected to heat treatment.

[0092] Specifically, the semiconductor layer after ion implantation is subjected to heat treatment to activate and propagate the doped ions to form a doped region; for example, a common rapid thermal annealing (RTA) process can be selected to perform the heat treatment. Preferably, laser annealing and / or peak annealing in the rapid thermal annealing process are selected, that is, laser annealing can be selected alone, peak annealing can be selected alone, or laser annealing and peak annealing can be performed together.

[0093] Next, step S6 is performed: electrical tests are conducted on the semiconductor layer after ion implantation to characterize the resistivity uniformity of the doped region.

[0094] Specifically, after the thermal treatment step of the semiconductor layer following ion implantation, electrical tests are performed on the doped region to characterize the resistivity uniformity of the doped region. In this embodiment, the parameters used to characterize the resistivity uniformity of the doped region include one or a combination of the average value, variance, and standard deviation of the sheet resistance.

[0095] In some examples, the sheet resistance of the doped region is measured using a four-point probe method and / or eddy current method. The doped region can be an N-type well region, a P-type well region, a source / drain extension region, or a polysilicon gate in a CMOS process. Here, we specifically illustrate the sheet resistance measurement method of the four-point probe method using an N-type well region formed in a substrate as an example: four probes arranged equidistantly and collinearly are contacted with the surface of the N-type well region for measurement. A direct current (DC) is driven between the two outer probes, while a voltage is measured between the two inner probes, thus obtaining the desired electrical parameter data.

[0096] Experimental Example

[0097] To verify the advantages of this invention in improving ion implantation uniformity, the following is an example. Figure 5 The doped regions fabricated using process routes ① and ② are used as comparative and experimental examples, respectively. The specific experimental conditions are as follows: The comparative doped region was fabricated by directly performing ion implantation along process route ① without a baking process; the doped regions in Experimental Examples 1, 2, and 3 were fabricated along process route ②. The doped region in Experimental Example 1 underwent one baking process at 110°C before ion implantation. The doped region in Experimental Example 2 underwent two baking processes at 110°C and 110°C before ion implantation, each baking process lasting 60 seconds. The doped region in Experimental Example 3 underwent one baking process in a vacuum environment at 110°C before ion implantation, each baking process lasting 60 seconds. Subsequently, the sheet resistance of the doped regions in the comparative, Experimental, Experimental, and Experimental Examples 1, 2, and 3 was measured using the eddy current method. The results are shown in [Figure / Table / Insert Table ...Insert Table / Table / Insert Table / Insert Table / Table / Insert Table / Insert Table / Table / Insert Table / Insert Table / Insert Table / Table / Insert Table / Insert Table / Insert Table / Insert Table / Insert Table / Insert Table / Insert Table / Insert Table / Figure 12 .

[0098] Figure 12 The standard deviation of sheet resistance is used to characterize the resistivity uniformity of the doped regions in the comparative examples, Experiment 1, Experiment 2, and Experiment 3. Figure 12 It can be seen that the average sheet resistance Rs of the doped regions of the comparative example, experimental example 1, experimental example 2 and experimental example 3 are not much different, and all fluctuate around 331.5 ohms. The doped regions of experimental example 1, experimental example 2 and experimental example 3 have a reduced sheet resistance standard deviation (Rs_STD) compared with the doped region of the comparative example.

[0099] Furthermore, by comparing the sheet resistance measurements of the doped regions in Experiment 1 and Experiment 2, it can be seen that the Rs_STD of the doped regions decreases with the increase of baking times. From one baking cycle in Experiment 1 to two baking cycles in Experiment 2, the standard deviation of sheet resistance Rs_STD decreased from 1.12 to 0.54. Comparing the sheet resistance measurements of the doped regions in Experiment 1 and Experiment 3, it is shown that under the same baking temperature and duration, reducing the vacuum level of the process environment, for example from a reduced pressure environment (1.33 x 10⁻⁶), reduces the sheet resistance. 3 Pa ～ 10 4 Pa) decreased to 10 -3 Below Pa, the standard deviation of sheet resistance, Rs_STD, decreased from 1.12 to 0.45. This is also reflected in the sheet resistance distribution plot; in Experiment 1 and Experiment 2, the distribution areas of the maxima and minima in the doped region decreased, while in Experiment 3, the maxima and minima in the doped region were only distributed at the edges, and the distribution area further decreased. Combined with... Figure 12 As shown, it can be seen that increasing the number of baking cycles and the vacuum conditions of the baking process can significantly narrow the fluctuation of sheet resistance. This indicates that appropriately increasing the baking time can significantly improve the sheet resistance uniformity of the resulting doped region. In particular, by introducing a baking process under vacuum conditions in the transport path, the sheet resistance uniformity of the doped region can be significantly improved without increasing the additional process time.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving ion implantation uniformity, characterized in that, Includes the following steps: A semiconductor layer to be ion implanted is provided, wherein a photoresist pattern is formed on the semiconductor layer, and the photoresist pattern defines a process window; Additional baking is performed on the photoresist pattern; The semiconductor layer is implanted with ions of a conductive type using the baked photoresist pattern as an implantation mask. Remove the photoresist pattern from the semiconductor layer; The semiconductor layer after ion implantation is subjected to heat treatment.

2. The method for improving ion implantation uniformity according to claim 1, characterized in that: Before performing additional baking on the photoresist pattern, the process includes: hard baking the developed photoresist layer to obtain the photoresist pattern; and then performing post-development inspection on the photoresist pattern.

3. The method for improving ion implantation uniformity according to claim 1, characterized in that: The photoresist pattern is additionally baked at a temperature of 100℃-150℃; wherein the baking is performed at least once, and the duration of each baking is not less than 60s.

4. The method for improving ion implantation uniformity according to claim 1, characterized in that: The photoresist pattern is subjected to multiple additional baking cycles, each lasting 60 seconds.

5. The method for improving ion implantation uniformity according to claim 1, characterized in that: A rapid thermal annealing process is used to perform a thermal treatment step on the semiconductor layer after ion implantation, activating and advancing dopant ions to form a doped region; wherein the rapid thermal annealing process includes one or a combination of laser annealing and spike annealing.

6. The method for improving ion implantation uniformity according to claim 1, characterized in that: Following the step of forming the photoresist pattern, the photoresist pattern is further baked using a vacuum heating method.

7. The method for improving ion implantation uniformity according to claim 6, characterized in that: The additional baking step for the photoresist pattern includes: conveying the semiconductor layer on which the photoresist pattern is formed to a load-locking chamber; subsequently, maintaining the vacuum level in the load-locking chamber at 10... -4 Pa to 10 -6 Under the condition of Pa, the photoresist pattern is additionally baked using a heating component.

8. The method for improving ion implantation uniformity according to claim 6, characterized in that: The load-locking chamber is equipped with cooling pipes, and the semiconductor layer is cooled using the cooling pipes before the step of ion implantation of the semiconductor layer.

9. The method for improving ion implantation uniformity according to claim 1, characterized in that: The ion implantation step is performed using an ion beam with an ion beam current between 0.5 mA and 14.5 mA.

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