Method of forming a semiconductor structure and laser annealing system

Abstract

This invention provides a method for forming a semiconductor structure, which involves obtaining a distribution map of the saturation current of a previous batch of wafers; obtaining the heat to be compensated for in different test areas of the previous batch of wafers based on the saturation current distribution map and converting it into equivalent temperature and equivalent time; performing a laser annealing process on a subsequent batch of wafers, where the laser spot size is smaller than the size of all test areas in the previous batch of wafers, determining the process temperature of the laser annealing process based on the equivalent temperature, and determining the moving speed of the subsequent batch of wafers and / or adjusting the path of the laser spot in the laser annealing process based on the equivalent time to compensate for the saturation current of the subsequent batch of wafers. An unexpected effect of this invention is that by changing the process temperature of the laser annealing process and / or the moving speed of the subsequent batch of wafers, the uniformity of the saturation current of the subsequent batch of wafers can be improved, and the laser spot size of the laser annealing process is smaller than the size of a single test area, precise compensation can be achieved for a single test area or different test areas of the subsequent batch of wafers.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for forming a semiconductor structure and a laser annealing system. Background Technology

[0002] Throughout the entire wafer, various films and photoresists cannot be made completely flat. The uneven film thickness affects the dose and depth of ion implantation and the degree of ion activation, causing deviations in threshold voltage and electrical properties at different locations on the entire wafer, leading to problems such as the uniformity of threshold voltage in a certain region.

[0003] Currently, the industry commonly uses zone-based ion implantation compensation and zone-based compensation via Rapid Thermal Processing (RTP) to compensate for the electrical properties of different locations on a wafer. Zone-based ion implantation compensation adjusts the ion implantation dose in different regions to change the threshold voltage of those regions. However, the ion beam size is too large, for example, with a diameter greater than 30 mm, and there are transition zones between compensation regions, making skip-type compensation impossible. Even after zone-based ion implantation compensation, issues such as uniformity of threshold voltage and electrical properties still exist across different locations on the wafer. Rapid thermal processing zone-based compensation changes the degree of ion activation, but in the rapid thermal processing process, the wafer is rotated and heated, allowing only zone-based compensation. Furthermore, the heating source is a light bulb, causing the compensation temperatures between regions to affect each other, resulting in low accuracy. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a semiconductor structure and a laser annealing system to solve the problem of threshold voltage and electrical properties at different locations on a wafer, which leads to the problem of threshold voltage uniformity in a certain region.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0006] Obtain the saturation current distribution map of the previous batch of wafers, wherein the saturation current distribution map of the previous batch of wafers includes saturation current information of multiple test areas of the previous batch of wafers;

[0007] Based on the distribution map of the saturation current of the previous batch of wafers, the heat that needs to be compensated in different test areas of the previous batch of wafers is obtained, and the equivalent temperature and equivalent time are obtained based on the heat that needs to be compensated.

[0008] A laser annealing process is performed on subsequent batches of wafers. The laser spot size of the laser annealing process on the subsequent batches of wafers is smaller than the size of all test areas in the preceding batches of wafers. The process temperature of the laser annealing process is determined based on the equivalent temperature. The moving speed of the subsequent batches of wafers is determined based on the equivalent time, and / or the path of the laser spot in the laser annealing process is adjusted to compensate for the saturation current of the subsequent batches of wafers.

[0009] Optionally, in the laser annealing process of the subsequent batch of wafers, the subsequent batch of wafers is located on a worktable, and the movement speed of the subsequent batch of wafers is changed by changing the movement speed of the worktable.

[0010] Optionally, in the laser annealing process of the subsequent batch of wafers, a multi-path compensation and / or multiple compensation method is adopted, wherein the multi-path compensation includes at least one of area compensation, diagonal compensation and cross compensation.

[0011] Optionally, the multipath compensation sets the compensation path based on the coordinates of each test area of ​​the previous batch of wafers.

[0012] Optionally, the laser annealing process for the subsequent batch of wafers includes compensation for different coordinate positions within each test area of ​​the subsequent batch of wafers and compensation for different test areas within the subsequent batch of wafers.

[0013] Optionally, during wafer acceptance testing, the saturation current parameters of the previous batch of wafers are tested to obtain a distribution map of the saturation current of the previous batch of wafers.

[0014] Optionally, in the laser annealing process, the relationship between the equivalent time and the laser spot width and the stage moving speed is as follows:

[0015] Dwell Time = Wbeam / Vstage

[0016] Where Wbeam is the width of the laser spot, Vstage is the stage moving speed, and Dwell Time is the heating time of a well region in the wafer.

[0017] Optionally, in the laser annealing process, the laser temperature settings are different for different test areas.

[0018] Optionally, the laser annealing process refers to a lightly doped annealing process, a stress annealing process, or an annealing process for the source / drain regions.

[0019] Based on the same inventive concept, the present invention also provides a laser annealing system for performing the semiconductor structure formation method described in any of the preceding claims, the laser annealing system comprising:

[0020] The laser unit is used to provide the laser beam.

[0021] Temperature control unit, used to set the process temperature for different laser annealing processes;

[0022] A worktable is used to carry subsequent batches of wafers and control the movement speed of the subsequent batches of wafers.

[0023] In a semiconductor structure formation method provided by the present invention, a saturation current distribution map of a previous batch of wafers is obtained, the saturation current distribution map of the previous batch of wafers includes saturation current information of multiple test areas of the previous batch of wafers; the heat to be compensated for different test areas of the previous batch of wafers is obtained according to the saturation current distribution map of the previous batch of wafers, and the equivalent temperature and equivalent time are obtained according to the heat to be compensated; a laser annealing process is performed on a subsequent batch of wafers, the laser spot size of the laser annealing process of the subsequent batch of wafers is smaller than the size of all test areas in the previous batch of wafers, and the process temperature of the laser annealing process is determined according to the equivalent temperature, and the moving speed of the subsequent batch of wafers is determined and / or the path of the laser spot in the laser annealing process is adjusted according to the equivalent time to compensate for the saturation current of the subsequent batch of wafers. An unexpected effect of this invention is that by changing the process temperature or the wafer's moving speed and path in the laser annealing process, i.e., by changing the algorithm settings of the laser annealing system, heat can be flexibly compensated for in subsequent batches of wafers, improving the uniformity of the saturation current in subsequent batches of wafers. Furthermore, the laser spot size in the laser annealing process is smaller than the size of a single test area. By changing the path of the laser spot, precise compensation can be made for a single test area or different test areas of a subsequent batch of wafers, improving the uniformity of the saturation current in a single test area or different test areas of a subsequent batch of wafers. Attached Figure Description

[0024] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0025] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0026] Figure 2 This is a distribution diagram of the saturation current of the first batch of wafers in an embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the saturation current of a batch of wafers after laser annealing process compensation according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram showing the positions of the laser unit and the subsequent batch of wafers in an embodiment of the present invention.

[0029] Figure 5 This is a graph showing the relationship between wafer movement speed, laser temperature, and wafer resistance in an embodiment of the present invention.

[0030] Figure 6This is a schematic diagram of a single test area according to an embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram of the laser spot according to an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram showing the position of the laser spot in a single test area according to an embodiment of the present invention.

[0033] Figure 9 This is a schematic diagram showing the position of the laser spot in a single test area during 100% area compensation in an embodiment of the present invention.

[0034] Figure 10 This is a schematic diagram showing the position of the laser spot in a single test area during 50% area compensation in an embodiment of the present invention.

[0035] Figure 11 This is a schematic diagram showing the position of the laser spot in a single test area during diagonal compensation in an embodiment of the present invention.

[0036] Figure 12 This is a schematic diagram showing the position of the laser spot in a single test area during cross-compensation in an embodiment of the present invention.

[0037] Figure 13 This is a schematic diagram showing the position of the laser spot in a single test area during multiple compensations in an embodiment of the present invention.

[0038] In the attached diagram: 10 - front batch wafers; 10a - back batch wafers; 20 - worktable; 20a - heating stage; 30 - laser unit; 11 - test area; 31 - laser spot. Detailed Implementation

[0039] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0040] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0041] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a semiconductor structure, including:

[0042] Step S10: Obtain the saturation current distribution map of the previous batch of wafers, wherein the saturation current distribution map of the previous batch of wafers includes saturation current information of multiple test areas of the previous batch of wafers.

[0043] Step S20: Obtain the heat to be compensated in different test areas of the previous batch of wafers according to the distribution map of the saturation current of the previous batch of wafers, and obtain the equivalent temperature and equivalent time according to the heat to be compensated.

[0044] Step S30: Perform laser annealing on the subsequent batch of wafers. The laser spot size of the laser annealing process on the subsequent batch of wafers is smaller than the size of all test areas in the previous batch of wafers. Determine the process temperature of the laser annealing process based on the equivalent temperature. Determine the moving speed of the subsequent batch of wafers based on the equivalent time and / or adjust the path of the laser spot in the laser annealing process to compensate for the saturation current of the subsequent batch of wafers.

[0045] Figure 2This is a distribution map of the saturation current of the first batch of wafers in this embodiment of the invention. WAT (Wafer Acceptance Test) is a measurement of the electrical parameters of a specific test structure after wafer fabrication and before quality inspection. The purpose of WAT is to detect the process status of each wafer by testing the electrical parameters of specific test structures on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specifications of the process technology platform. WAT data can serve as a quality certificate for wafer product delivery. Furthermore, WAT data can reflect the actual production status of the production line. By collecting and analyzing WAT data, the production line status can be monitored, trends in production line changes can be determined, and early warnings can be issued for potential problems. In this embodiment, by performing wafer acceptance testing on the first batch of wafers, a distribution map of the saturation current of the first batch of wafers is obtained to adjust the production process of the subsequent batch of wafers. Specifically, as shown... Figure 2 As shown, in wafer acceptance testing, parameters of the previous batch of wafers are tested, including the saturation current of the previous batch. In wafer acceptance testing, a "shot" is a physical point for a single test, i.e., a set of measurements completed after the probe card makes one contact with the wafer. Each shot is a test area 11, and each test wafer includes multiple shots. Each shot represents a saturation current, and different shots together form the saturation current distribution map of the wafer. That is, in wafer acceptance testing, the saturation current distribution map of the previous batch of wafers 10 is obtained. This distribution map includes the saturation current information of multiple test areas 11 of the previous batch of wafers, meaning the previous batch of wafers 10 includes multiple test areas 11. Figure 2 As shown, the saturation current varies in different test areas 11, represented by different colors. The darker the color, the greater the saturation current; the lighter the color, the smaller the saturation current. It can be seen that the saturation current distribution of the first batch of wafers 10 is uneven.

[0046] Figure 3This is a schematic diagram illustrating the compensation of saturation current in subsequent batches of wafers using the laser annealing process according to an embodiment of the present invention. Based on the distribution diagram of the saturation current of the preceding batch of wafers 10, the heat to be compensated for in different test areas 11 of the preceding batch of wafers is obtained, which is also the heat to be compensated for in the corresponding test areas of the subsequent batch of wafers. The test areas of the preceding batch of wafers and the test areas of the subsequent batch of wafers correspond one-to-one. During wafer manufacturing, the laser annealing process transfers heat to the wafer. After the wafer absorbs heat, its saturation current increases. The heat received by the wafer is adjusted by the temperature of the laser annealing process. Therefore, the equivalent temperature and equivalent time are calculated based on the heat to be compensated. The equivalent temperature is the temperature of the laser annealing process, and the equivalent time is the duration of the laser annealing process. In the laser annealing process, the heat received by the wafer is positively correlated with both the temperature and time of the laser annealing process; that is, the higher the temperature of the laser annealing process, the higher the heat received by the wafer, and the longer the laser annealing process, the higher the heat received by the wafer. In some embodiments, the equivalent temperature and equivalent time of the subsequent laser annealing process can be directly obtained from the saturation current distribution map of the previous batch of wafers. Those skilled in the art know how to obtain the equivalent temperature and equivalent time of the subsequent laser annealing process from the saturation current distribution map of the previous batch of wafers; generally, there are two methods: one is through physical principles and software calculations, and the other is based on experimental results. In this embodiment, the laser temperature settings are different for different test areas in the laser annealing process. That is, different shot idsatU% (exposure field uniformity) can be found based on the product WAT. Taking one shot (exposure field) as an example, if the overall temperature is low, a higher laser temperature is required for heating. The size and coordinates of the exposure field, as well as the area to be compensated, can be input into the machine parameters. The machine can then plan its route and adjust the beam size and stage speed in a specific area to complete the compensation. Figure 3 The x-axis is by shot. Figure 2 The different shots in AA' correspond to Figure 3 The horizontal axis of the shot. Figure 3 The vertical axis is Idsat, which is the saturation current corresponding to different shots. Figure 3The red curve represents the saturation current corresponding to different shots in the first batch of wafers 10. The blue curve represents the saturation current that needs to be compensated for in different shots of the subsequent batch of wafers. The green curve represents the saturation current corresponding to different shots in the subsequent batch of wafers that is expected to be achieved after laser annealing compensation, i.e., different shots of the subsequent batch of wafers have uniform saturation current. Similarly, the saturation current that needs to be compensated for in each test area 11 of the entire first batch of wafers is calculated and converted into compensating heat (thermal). The specific conversion method is as described above, using physical principles and software calculations or experimental results. Specifically, the shot coordinates of the first batch of wafers 10 and the shot coordinates of the subsequent batch of wafers are provided. The shot coordinates of the first batch of wafers 10 and the shot coordinates of the subsequent batch of wafers are the same. The LSA (Laser Spike Annealing) algorithm controls and changes the input quantities of the laser annealing process to adjust the compensating heat (thermal). The input quantities of the laser annealing process are, for example, the process temperature (temp) and / or the stage movement speed. The workpiece stage 20 drives the subsequent batch of wafers to move, and the moving speed of the workpiece stage 20 is also the moving speed of the subsequent batch of wafers.

[0047] Figure 4 This is a schematic diagram showing the positions of the laser unit and the subsequent batch of wafers in an embodiment of the present invention. Figure 4 As shown, a heating stage 20a is provided on the workpiece stage 20. The heating stage 20a is used to provide the required temperature to the wafer. The subsequent batch of wafers 10a is located on the heating stage 20a of the workpiece stage 20. The workpiece stage 20 can move along the X or Y direction to drive the movement of the subsequent batch of wafers 10a. Therefore, the movement speed of the subsequent batch of wafers 10a is changed by changing the movement speed of the workpiece stage 20. The movement speed of the subsequent batch of wafers 10a is inversely proportional to the heating time of the subsequent batch of wafers 10a. That is, the faster the movement speed of the subsequent batch of wafers 10a, the shorter the time that the subsequent batch of wafers 10a is irradiated by the laser spot in the laser unit 30, and the less heat it receives.

[0048] Figure 5 This is a graph showing the relationship between wafer movement speed, laser temperature, and wafer resistance in an embodiment of the present invention. Figure 5 The horizontal axis represents temperature, with the unit being °C. Figure 5 The vertical axis represents resistance (Rs), with the unit being ohms (Ω). Figure 5The relationship between laser temperature and wafer resistance is presented when the workpiece stage 20 moves at a speed of 375 mm / s, and when the workpiece stage 20 moves at a speed of 187.5 mm / s. It can be seen that the higher the laser temperature, the greater the compensation heat of the laser annealing process, the lower the wafer resistance, and the higher the wafer saturation current. Furthermore, at the same temperature, the faster the workpiece stage 20 moves and the faster the wafer 10 moves, the less compensation heat the laser annealing process requires, the higher the wafer resistance, and the lower the wafer saturation current.

[0049] Figure 6 This is a schematic diagram of a single test area according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the laser spot according to an embodiment of the present invention. Figure 8 This is a schematic diagram showing the position of the laser spot in a single test area according to an embodiment of the present invention. Figure 6 As shown, the length of a single test area 11 in the Y direction of a subsequent batch of wafers is, for example, 32 mm, and the length of a single test area 11 in the X direction of a subsequent batch of wafers is, for example, 25 mm. Figure 7 As shown, the laser beam size (LSA beam size) is also known as the laser spot 31. The length of the laser spot 31 in the Y direction is, for example, 5 mm to 10 mm, and the length of the laser spot 31 in the X direction is, for example, 55 μm to 150 μm. In the Y direction, the laser spot size of the laser annealing process is one-third to one-sixth of the size of the test area. That is, the LSA beam size is smaller than 1 shot in the WAT test of the previous batch of wafers, which can accurately compensate for each test area of ​​the subsequent batch of wafers.

[0050] Figure 9 This is a schematic diagram showing the position of the laser spot in a single test area during 100% area compensation in an embodiment of the present invention. Figure 10 This is a schematic diagram showing the position of the laser spot in a single test area during 50% area compensation in an embodiment of the present invention. Figure 11 This is a schematic diagram showing the position of the laser spot in a single test area during diagonal compensation in an embodiment of the present invention. Figure 12 This is a schematic diagram showing the position of the laser spot in a single test area during cross-compensation in an embodiment of the present invention. Figure 13This is a schematic diagram illustrating the position of the laser spot in a single test area during multiple compensation processes in an embodiment of the present invention. A laser annealing process is performed on subsequent batches of wafers. The laser spot size of the laser annealing process on these subsequent batches of wafers is smaller than the size of all test areas in the preceding batches of wafers. The process temperature of the laser annealing process is set according to the equivalent temperature, and the moving speed of the subsequent batches of wafers is determined according to the equivalent time, and / or the path of the laser spot in the laser annealing process is adjusted to compensate for the saturation current of the subsequent batches of wafers. Specifically, in the laser annealing process, the width of the laser spot Wbeam divided by the stage moving speed Vstage equals the heating time of a certain region (e.g., a well) in the wafer, i.e., Dwell Time = Wbeam / Vstage, where Wbeam is the width of the laser spot, Vstage is the stage moving speed, and Dwell Time is the heating time of a certain region (e.g., a well) in the wafer, with the unit of Dwell Time being seconds (sec). The laser annealing process includes heat compensation at different coordinate positions within each test area 11 of the subsequent batch of wafers and heat compensation for different test areas 11 within the subsequent batch of wafers. In one embodiment, heat compensation for a single test area (shot) 11 of the subsequent batch of wafers is calculated based on the saturation current of the previous batch of wafers 10, determining the equivalent temperature and equivalent time required for compensation in the subsequent batch of wafers. In the laser annealing process, the laser temperature is kept constant, and the moving speed of the workpiece stage 20 is changed, i.e., the moving speed of the subsequent batch of wafers, to accurately compensate for the saturation current at different positions within a single test area (shot) of the subsequent batch of wafers. In another embodiment, for heat compensation of a single test area (shot) 11 of the subsequent batch of wafers, the equivalent temperature and equivalent time required for compensation of the subsequent batch of wafers are calculated based on the saturation current of the preceding batch of wafers 10. During the laser annealing process, the moving speed of the workpiece stage 20 is kept constant, i.e., the moving speed of the subsequent batch of wafers remains constant, while the laser temperature is changed to accurately compensate for the saturation current at different locations within the single test area (shot) of the subsequent batch of wafers, enabling flexible heat compensation for the subsequent batch of wafers. In another embodiment, the laser annealing process is performed using multi-path compensation and / or multiple compensation methods to compensate for the saturation current at different locations within the single test area (shot) of the subsequent batch of wafers and the saturation current of different test areas 11 of the subsequent batch of wafers. The multi-path compensation includes area compensation, diagonal compensation, and cross compensation. The multi-path compensation sets the compensation path based on the coordinates of each test area of ​​the preceding batch of wafers. For example, the coordinates of the four vertices of a test area (shot) are (0, 0), (25, 0), (0, 35), and (25, 35), respectively. Area compensation can be 100% area compensation, such as... Figure 9As shown. The laser spot 31 moves from coordinates (0,35) along the X direction to coordinates (25,35), moving sequentially to each individual test area (shot) 11, thus compensating for each individual test area (shot). Area compensation can be 50% area compensation, such as... Figure 10 As shown, the laser spot 31 moves from coordinates (0,35) along the X direction to coordinates (25,35), sequentially moving half of the test area (shot), that is, the laser spot 31 moves to coordinates (25,17.5), compensating for half of the test area (shot). Those skilled in the art can also compensate for any area and coordinate region of a single test area (shot) of a subsequent batch of wafers based on the saturation current of the previous batch of wafers 10. For example... Figure 11 As shown, in diagonal compensation, the laser spot 31 moves from coordinates (0,35) to coordinates (25,0) along the diagonal direction. Figure 12 As shown, in the cross-compensation, the laser spot 31 first moves from coordinates (0,35) diagonally to coordinates (25,0), and then from coordinates (0,0) diagonally to coordinates (25,35). The multiple compensation method includes at least two compensations. For example... Figure 13 As shown, the laser spot 31 moves multiple times from coordinates (0,35) along the diagonal to coordinates (25,0). In another embodiment, the laser spot can be moved to any position within a single test area; for example, the laser spot can be moved to the center of a single test area before heating. Alternatively, the laser annealing process temperature can be set lower initially, the laser spot moved to the position requiring heat compensation, and then the laser annealing process temperature can be increased. These can all be algorithmically set within the laser annealing process. It is worth noting that in this embodiment, the laser spot movement is relative to the wafer's coordinate position; that is, the stage moves the wafer while the laser spot remains stationary.

[0051] In semiconductor structure formation methods, multiple processes employ laser annealing, such as lightly doped source / drain regions annealing (S / D Extension & Halo), stress annealing (SMT process), or source / drain region annealing (S / D spike RTP). In these laser annealing processes, the process temperature, the moving speed of the subsequent wafers, and / or the path of the laser spot are varied to precisely compensate for the saturation current of the subsequent wafers, thereby improving the uniformity of the saturation current in a single test area and between different test areas of the subsequent wafers.

[0052] like Figure 4 As shown, this embodiment also provides a laser annealing system, including:

[0053] Laser unit 30 is used to provide laser spot 31;

[0054] The temperature control unit is used to set the process temperature for different laser annealing processes; the process temperature of the laser annealing process is changed multiple times during the movement of subsequent batches of wafers.

[0055] The worktable 20 is used to carry subsequent batches of wafers and control the movement speed of the subsequent batches of wafers. The worktable 20 drives the subsequent batches of wafers to move along the X and Y directions.

[0056] In summary, in the semiconductor structure formation method provided by this invention, a saturation current distribution map of the previous batch of wafers is obtained, which includes saturation current information of multiple test areas of the previous batch of wafers; the heat to be compensated for in different test areas of the previous batch of wafers is obtained based on the saturation current distribution map of the previous batch of wafers, and the equivalent temperature and equivalent time are obtained based on the heat to be compensated; a laser annealing process is performed on the subsequent batch of wafers, where the laser spot size of the laser annealing process of the subsequent batch of wafers is smaller than the size of all test areas in the previous batch of wafers, and the process temperature of the laser annealing process is determined based on the equivalent temperature; the moving speed of the subsequent batch of wafers is determined based on the equivalent time, and / or the path of the laser spot in the laser annealing process is adjusted to compensate for the saturation current of the subsequent batch of wafers. An unexpected effect of this invention is that by changing the process temperature or the wafer's moving speed and path in the laser annealing process, which also changes the algorithm settings of the laser annealing system, heat can be flexibly compensated for in subsequent batches of wafers, improving the uniformity of the saturation current in subsequent batches of wafers. Furthermore, the laser spot size in the laser annealing process is smaller than the size of a single test area. By changing the path of the laser spot, precise compensation can be made for a single test area or different test areas of a subsequent batch of wafers, improving the uniformity of the saturation current in a single test area or different test areas of a subsequent batch of wafers.

[0057] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0058] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Obtain the saturation current distribution map of the previous batch of wafers, wherein the saturation current distribution map of the previous batch of wafers includes saturation current information of multiple test areas of the previous batch of wafers; Based on the distribution map of the saturation current of the previous batch of wafers, the heat that needs to be compensated in different test areas of the previous batch of wafers is obtained, and the equivalent temperature and equivalent time are obtained based on the heat that needs to be compensated. A laser annealing process is performed on subsequent batches of wafers. The laser spot size of the laser annealing process on the subsequent batches of wafers is smaller than the size of all test areas in the preceding batches of wafers. The process temperature of the laser annealing process is determined based on the equivalent temperature. The moving speed of the subsequent batches of wafers is determined based on the equivalent time, and / or the path of the laser spot in the laser annealing process is adjusted to compensate for the saturation current of the subsequent batches of wafers.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, In the laser annealing process of the subsequent batch of wafers, the subsequent batch of wafers is located on a worktable, and the movement speed of the subsequent batch of wafers is changed by changing the movement speed of the worktable.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, In the laser annealing process of the subsequent batch of wafers, multi-path compensation and / or multiple compensation methods are adopted. The multi-path compensation includes at least one of area compensation, diagonal compensation and cross compensation.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The multipath compensation is set according to the coordinates of each test area of ​​the previous batch of wafers to determine the compensation path.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The laser annealing process for the subsequent batch of wafers includes compensation for different coordinate positions within each test area of ​​the subsequent batch of wafers and compensation for different test areas within the subsequent batch of wafers.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, During wafer acceptance testing, the saturation current parameters of the previous batch of wafers are tested to obtain a distribution map of the saturation current of the previous batch of wafers.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, In the laser annealing process, the equivalent time is related to the laser spot width and the stage moving speed as follows: Dwell Time = Wbeam / Vstage Where Wbeam is the width of the laser spot, Vstage is the stage moving speed, and Dwell Time is the heating time of a well region in the wafer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, In the laser annealing process, the laser temperature is set differently in different test areas.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The laser annealing process refers to a lightly doped annealing process, a stress annealing process, or an annealing process for the source / drain regions.

10. A laser annealing system, characterized in that, For performing a method of forming a semiconductor structure as described in any one of claims 1 to 9, the laser annealing system comprises: The laser unit is used to provide the laser beam. Temperature control unit, used to set the process temperature for different laser annealing processes; A worktable is used to carry subsequent batches of wafers and control the movement speed of the subsequent batches of wafers.

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