A wafer deep trench etching method and wafer

Abstract

This invention provides a wafer deep trench etching method that defines a pattern on a thin photoresist (0.5~1.5μm) using only one photolithography exposure; subsequently, the pattern is transferred to a hard mask through a first etching step; after removing the photoresist, a second deep trench etching is performed using the hard mask. No secondary photolithography is required throughout the process. This simplifies the process flow and reduces costs: compared to the traditional hard mask approach (which requires hard mask deposition, photolithography, hard mask etching, photoresist removal, secondary photolithography, secondary alignment, and deep trench etching), this application omits the second photolithography step and the corresponding photoresist coating, alignment, and development steps, reducing equipment downtime, material consumption, and manual operation. The single-batch process cycle can be shortened by 20%~30%.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor etching technology, specifically relating to a wafer deep trench etching method and a wafer. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, has been widely used in radio frequency / microwave power amplifier devices due to its excellent properties such as wide bandgap, high breakdown electric field, and high electron saturation velocity. To balance heat dissipation performance and lattice matching, the current mainstream technology typically uses silicon carbide (SiC) as the substrate material to form a SiC on GaN heterojunction structure. In the fabrication of such devices, deep trench etching is a key process, mainly used to form mesa isolation trenches between active regions, deep trench capacitor structures, or to provide high aspect ratio pattern transfer for back-side via grounding.

[0003] For SiC on GaN RF devices, deep trench etching faces the following stringent requirements: ① It is necessary to minimize the consumption of mask material while etching GaN / SiC material, i.e., a high selectivity ratio is required; ② The sidewall angle is usually required to be greater than 80° to ensure the continuity of subsequent dielectric layer coverage and the stability of electrical parameters, i.e., high steepness is required; ③ The critical dimension changes of the pattern before and after etching need to be controlled at the nanometer level to ensure the accuracy of the RF matching network, i.e., precise control of the critical dimension (CD) is required.

[0004] Currently, the two most similar existing implementation schemes to this scheme are as follows.

[0005] Option 1: Direct etching using a pure photoresist mask. This is the most common process route in the industry. The process flow includes: spin-coating photoresist directly onto the GaN epitaxial layer; defining the pattern to be etched through exposure and development; then using inductively coupled plasma (ICP) etching equipment with gases such as Cl2 / Ar or BCl3 to etch the exposed GaN / SiC material; and finally removing the remaining photoresist after etching.

[0006] Option 2: Traditional Hard Mask-Assisted Etching Solution. To address the low selectivity of photoresist masks, existing technologies employ hard masks. The typical process is as follows: First, a hard mask material (such as SiO2, SiN, or metallic Ni) is deposited on the GaN epitaxial layer using chemical vapor deposition (CVD) or physical vapor deposition (PVD). Then, photoresist is spin-coated onto the hard mask. After defining the pattern using photolithography, the pattern is transferred to the hard mask layer using etching. After removing the photoresist, deep trench etching is performed on the GaN / SiC using the hard mask as a barrier layer. Finally, the hard mask is removed.

[0007] However, the existing solutions mentioned above still have the following obvious drawbacks in practical applications: 1. The process is complex and the manufacturing cost is high. When using the traditional hard mask-assisted etching scheme, multiple additional steps are required, such as hard mask deposition, hard mask etching, photoresist removal, and hard mask stripping after etching. Each additional step introduces extra equipment downtime, material consumption, and the risk of particle contamination, leading to increased manufacturing costs, extended production cycles, and the accumulated alignment errors from multiple steps directly affecting the yield of the final device.

[0008] 2. Insufficient precision in critical dimension control. In pure photoresist mask solutions, due to the relatively low etching ratio of organic photoresist to GaN / SiC material (typically 3:1~5:1), carbonization and shrinkage occur at the edges of the photoresist during long-term high-power etching. This results in a significant enlargement of the critical dimension at the top of the etched pattern compared to the photolithographic pattern, forming a "trumpet mouth" shape, and the sidewall steepness is insufficient to meet the requirements of RF devices. In traditional hard mask solutions, the hard mask etching step itself involves lateral etching during the transfer of the pattern from photoresist to the hard mask, causing secondary loss of critical dimensions. The cumulative error of the two pattern transfers makes it difficult to control the final critical dimension within the sub-micron precision range.

[0009] 3. Poor compatibility with the warpage characteristics of SiC on GaN heterostructures. There is approximately 3.5% lattice mismatch and significant thermal mismatch between the SiC substrate and the GaN epitaxial layer, resulting in substantial intrinsic warpage of the wafer itself. Traditional hard masks often employ high-temperature (typically 300-400℃) chemical vapor deposition processes (such as PECVD deposition of SiO2). This high-temperature process introduces additional thermal stress into the heterojunction, exacerbating wafer warpage. Increased warpage makes it difficult for the alignment system in the photolithography process to stably grasp the alignment marks, deteriorating the consistency of the exposure focal plane, leading to out-of-tolerance overlay accuracy, and in severe cases, even causing the lithography machine to malfunction.

[0010] 4. Poor etching morphology consistency. Existing methods generally exhibit significant micro-loading effects during deep trench etching. As the photoresist mask gradually thins during etching, its protection capability for regions with different pattern densities varies, leading to inconsistent etching depths between densely patterned and isolated patterned regions. This depth difference directly affects the uniformity of breakdown voltage in mesa isolation and the consistency of capacitance values ​​in deep trench capacitors, reducing the performance yield of RF chips. Summary of the Invention

[0011] In view of this, this application provides a wafer deep trench etching method, which aims to solve the technical problems in existing solutions that make it difficult to balance etching selectivity, critical dimension accuracy, process complexity and wafer warpage compatibility.

[0012] To solve the above problems, this application adopts the following technical solution: In a first aspect, this application provides a wafer deep trench etching method, comprising the following steps: S1: A substrate is provided, on which a SiC layer and a GaN layer are formed to form a GaN / SiC material layer; S2: Deposit an inorganic hard mask layer on the GaN / SiC material layer at a temperature below 300°C to ensure that the inorganic hard mask layer is in a low-stress state and to avoid introducing additional thermal stress into the SiC / GaN heterojunction. S3: A photoresist layer is formed on the inorganic hard mask layer, and the desired pattern is defined in the photoresist layer through a single photolithography process; S4: Using the photoresist layer as a mask, perform a first etching on the inorganic hard mask layer to transfer the pattern to the inorganic hard mask layer. The first etching uses a low bias power to reduce physical bombardment of the photoresist. S5: Remove the photoresist layer; S6: Using the patterned inorganic hard mask layer as a mask, the GaN / SiC material layer is etched a second time to form a deep trench. The second etching utilizes the high etching selectivity between the inorganic hard mask layer and the GaN / SiC material layer to keep the mask window size constant. S7: Remove the inorganic hard mask layer to obtain a wafer with mesa isolation trenches.

[0013] In some embodiments, in step S2, the inorganic hard mask layer is formed by plasma-enhanced atomic layer deposition or plasma-enhanced chemical vapor deposition at a deposition temperature of 150°C to 200°C; and / or, the material of the inorganic hard mask layer is selected from one or more of silicon oxynitride, silicon oxide, or silicon nitride.

[0014] In some embodiments, in step S2, by adjusting the deposition process parameters, the inorganic hard mask layer is made to exhibit micro-compressive stress, so as to partially offset the original tensile stress of the GaN / SiC material layer and improve the wafer flatness.

[0015] In some embodiments, the microcompressive stress ranges from -100 MPa to -200 MPa.

[0016] In some embodiments, in step S3, the thickness of the photoresist layer is 0.5-1.5 μm, and the first photolithography process uses KrF deep ultraviolet lithography, and the photoresist is a positive photoresist.

[0017] In some embodiments, in step S4, the first etching is performed using inductively coupled plasma etching, the etching gas contains a fluorine-based gas, and the etching power is lower than that of the second etching; preferably, the fluorine-based gas includes CF4, CHF3, or a combination thereof, the ICP power of the first etching is 200W to 400W, and the bias power is 30W to 80W.

[0018] In some embodiments, in step S6, the second etching is performed using inductively coupled plasma etching, the etching gas contains a chlorine-based gas, and the etching power is higher than that of the first etching; preferably, the chlorine-based gas includes Cl2, BCl3, or a combination thereof, the ICP power of the second etching is 600W to 1000W, and the bias power is 150W to 250W.

[0019] In some embodiments, in step S6, the etching selectivity ratio of the inorganic hard mask layer to the GaN / SiC material layer in the second etching is ≥10:1, so that the thickness loss of the inorganic hard mask layer during the etching process is less than 20% of the initial thickness, thereby maintaining the constant size of the mask window.

[0020] In some embodiments, step S5 involves removing the photoresist layer using an O2 plasma ashing process, and optionally includes a wet cleaning step to remove ashing residues; step S7 involves removing the inorganic hard mask layer using wet etching with diluted hydrofluoric acid as the etching solution.

[0021] In some embodiments, the deep groove is a mesa isolation groove with an etching depth of 1μm to 2μm and a sidewall angle greater than 80°.

[0022] In some embodiments, the substrate is a silicon carbide substrate, and the GaN / SiC material layer includes a GaN buffer layer, an undoped GaN channel layer, an AlGaN barrier layer, and a GaN cap layer sequentially formed on the silicon carbide substrate.

[0023] In some embodiments, step S8 is also included: after completing the deep trench etching and removing the inorganic hard mask layer, performing subsequent processes, the subsequent processes including at least one of depositing an isolation dielectric layer, fabricating source / drain / gate electrodes, metal interconnects, back-side thinning, and fabricating back-side vias.

[0024] Secondly, this application also provides a wafer prepared by any of the methods described in the previous application.

[0025] Compared with the prior art, the present invention has the following significant advantages: The wafer deep trench etching method provided by this invention requires only one photolithography exposure to complete the pattern definition. The deep trench is then directly formed through a two-step pattern transfer process involving first and second etching. This eliminates the need for secondary photolithography, alignment, and development steps required in traditional methods to prepare the hard mask pattern, significantly reducing equipment usage time and material consumption. Each step removed reduces the chance of particulate matter introduction, thereby lowering defect density and improving manufacturing yield. By removing the photoresist before the main deep trench etching, and using only the hard mask as the final etching barrier layer, the carbonization and shrinkage problem of the photoresist during long-term etching is avoided. Simultaneously, the one-step transfer method of "directly defining the hard mask pattern with photoresist" reduces the number of pattern transfers, eliminating critical dimensional deviations caused by lateral losses during hard mask etching in traditional hard mask solutions, and achieving high-fidelity transfer of the photolithographic pattern to the GaN / SiC material. The hard mask layer is prepared using a low-temperature (<200℃) deposition process, significantly reducing the thermal stress introduced during hard mask deposition and preventing exacerbation of intrinsic wafer warpage. By controlling the stress characteristics of the hard mask, it can compensate for or buffer the original warpage of the heterojunction to a certain extent, thereby ensuring the alignment accuracy and focal plane control capability of the subsequent photolithography process. The inorganic hard mask is used to replace the organic photoresist as the main mask for deep trench etching. Taking advantage of the almost zero loss of the hard mask during the etching process, the mask window size is kept constant throughout the etching process, thereby effectively suppressing the micro-load effect and achieving consistent etching depth between dense and isolated pattern areas. This results in a deep trench morphology with high steepness (sidewall angle > 80°) and controllable deviation between the top and bottom critical dimensions. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 The following is a flowchart of the wafer deep trench etching method provided in this application. Detailed Implementation

[0028] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. In the description of this application, it should be understood that the terms "upper", "lower", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0030] Please see Figure 1 This application provides a schematic flowchart of a wafer deep trench etching method, which includes the following steps: S1: A substrate is provided, on which a SiC layer and a GaN layer are formed to form a GaN / SiC material layer.

[0031] In this embodiment, the substrate is a silicon carbide substrate, and the GaN / SiC material layer includes a GaN buffer layer, an undoped GaN channel layer, an AlGaN barrier layer, and a GaN cap layer sequentially formed on the silicon carbide substrate.

[0032] S2: Deposit an inorganic hard mask layer on the GaN / SiC material layer at a temperature below 300°C to ensure that the inorganic hard mask layer is in a low-stress state and to avoid introducing additional thermal stress into the SiC / GaN heterojunction.

[0033] In this embodiment, in step S2, the inorganic hard mask layer is formed by plasma-enhanced atomic layer deposition or plasma-enhanced chemical vapor deposition, and the deposition temperature is 150℃~200℃; and / or, the material of the inorganic hard mask layer is selected from one or more of silicon oxynitride, silicon oxide or silicon nitride.

[0034] It is understandable that plasma-enhanced atomic layer deposition (PEALD) can achieve dense, uniformly thick films at low temperatures; plasma-enhanced chemical vapor deposition (PECVD) is a mature process that facilitates mass production. The deposition temperature of 150–200°C further reduces thermal stress, making it highly compatible with the stress characteristics of SiC on GaN heterojunctions. SiON, SiO2, and SiN are all commonly used hard mask materials in semiconductor processes, exhibiting high selectivity with GaN / SiC in chlorine-based etching (SiON is particularly outstanding, reaching over 15:1), and all can be removed by wet hydrofluoric acid dilution without damaging GaN / SiC.

[0035] Furthermore, in step S2, by adjusting the deposition process parameters, the inorganic hard mask layer is made to exhibit micro-compressive stress, so as to partially offset the original tensile stress of the GaN / SiC material layer and improve the wafer flatness.

[0036] Furthermore, the range of the micro-compressive stress is -100MPa to -200MPa.

[0037] It is understandable that lattice and thermal mismatches between the SiC substrate and the GaN epitaxial layer lead to intrinsic tensile stress in the wafer, causing warpage. A hard mask introducing micro-compressive stress provides reverse stress compensation, resulting in minimal overall wafer warpage variation (bore variation < ±5μm in this example). A flat wafer surface is a prerequisite for high-precision alignment and focal plane control in lithography; this design ensures a single-pass photolithography process window from the outset.

[0038] It should be noted that the hard mask deposition temperature is below 300℃ (preferably 150~200℃), and PE is used. ALD or PECVD processes, by adjusting parameters such as gas flow ratio and RF power, can make the hard mask layer exhibit low stress or even micro-compressive stress (-100MPa~-200MPa), achieving the following technical effects: Significantly Reduced Wafer Warpage: Approximately 3.5% lattice and thermal mismatch exists between the SiC substrate and the GaN epitaxial layer, resulting in significant intrinsic wafer warpage. Traditional high-temperature hard masks (300~400℃) introduce additional thermal stress, increasing warpage by 20~30μm. This solution controls the deposition temperature at 150~200℃, achieving warpage variations of less than ±5μm, thus avoiding issues such as lithography machine autofocus failure or out-of-tolerance overlay accuracy caused by warpage.

[0039] Ensuring the lithography process window: The flat wafer surface enables the lithography machine alignment system to stably grasp the alignment marks, ensuring the consistency of the exposure focal plane, thereby achieving excellent pattern uniformity and critical dimension uniformity (CDU<3%) in a single photolithography process.

[0040] Actively improve flatness: By controlling the hard mask to micro compressive stress, the original tensile stress of GaN / SiC heterojunction can be partially offset, upgrading the hard mask from "passively avoiding damage" to "actively controlling stress", further optimizing wafer flatness.

[0041] By adjusting PE The process parameters of ALD (Plasma Enhanced Atomic Layer Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) (such as SiH4 / N2O flow ratio, RF power, etc.) can cause the deposited hard mask layer to exhibit precisely controllable micro-compressive stress (-100MPa ~ -200MPa), rather than traditional neutral stress or tensile stress, which can achieve the following technical effects: Active compensation for intrinsic warpage: Due to lattice mismatch and thermal mismatch, SiC on GaN heterojunctions typically exhibit tensile stress, causing the wafer to warp into a "bowl shape". A hard mask layer with micro-compressive stress is equivalent to applying a "reverse stress film" to the wafer surface. After the two are combined, the overall warpage of the wafer is significantly reduced or even approaches zero.

[0042] Enhancing photolithography capabilities: A flat wafer ensures that the focal plane undulation of the stepper lithography machine is less than the depth of focus range throughout the entire exposure field, guaranteeing the uniformity of critical dimensions of the pattern across the entire wafer. At the same time, the distortion of alignment marks is reduced, and the alignment accuracy can be improved to ≤30nm (3σ), meeting the stringent overlay requirements of RF devices.

[0043] Reducing the risk of wafer breakage: Excessive wafer warpage can easily lead to wafer breakage during subsequent processes (such as vacuum adsorption, transfer, and annealing). This solution uses a hard mask as a stress control layer to keep the wafer flat throughout the overall wafer fabrication process, significantly reducing the risk of breakage and improving mass production yield.

[0044] S3: A photoresist layer is formed on the inorganic hard mask layer, and the desired pattern is defined in the photoresist layer through a single photolithography process.

[0045] In this embodiment, in step S3, the thickness of the photoresist layer is 0.5-1.5 μm, and the first photolithography process uses KrF deep ultraviolet lithography, and the photoresist is a positive photoresist.

[0046] Understandably, thin resist avoids the scattering and diffraction effects of thick resist during exposure, significantly improving pattern resolution and supporting critical size definitions of 0.35μm and below. KrF deep ultraviolet lithography (248nm wavelength) balances resolution and depth of focus, making it suitable for the production of 4-inch and larger wafers. The sidewall angle of the pattern after positive resist development is controllable (approximately 85°), which is beneficial for subsequent pattern transfer.

[0047] Furthermore, photoresist can also include variations in type and thickness.

[0048] S4: Using the photoresist layer as a mask, perform a first etching on the inorganic hard mask layer to transfer the pattern to the inorganic hard mask layer. The first etching uses a low bias power to reduce physical bombardment of the photoresist.

[0049] In this embodiment, in step S4, the first etching is performed using inductively coupled plasma etching, the etching gas contains a fluorine-based gas, and the etching power is lower than that of the second etching. Preferably, the fluorine-based gas includes CF4, CHF3, or a combination thereof, and the ICP power of the first etching is 200W to 400W, and the bias power is 30W to 80W.

[0050] Understandably, low bias power reduces the physical bombardment of photoresist by high-energy ions, preventing photoresist morphology deformation or premature carbonization, and ensuring complete pattern transfer. Fluorine-based gases have a moderate etching rate for hard masks such as SiON and SiO2, allowing for complete etching through the hard mask while leaving some photoresist remaining, thus preserving an operating window for subsequent ashing and resist removal.

[0051] It should be noted that the first etching (transferring the pattern from the photoresist to the hard mask) uses low-bias power (30~80W) fluorine-based plasma etching, with an ICP power of 200~400W, and etching gases such as CF4 / CHF3 / Ar, which has the following technical effects: Protecting the integrity of photoresist morphology: Low bias power significantly reduces the physical bombardment intensity of high-energy ions on organic photoresist, preventing deformation, wrinkling, or premature carbonization of the photoresist during etching. The sidewall angles (approximately 85°) and critical dimensions of the photoresist pattern are fully preserved.

[0052] Ensuring pattern transfer accuracy: As the mask for the first etching step, the integrity of the photoresist pattern directly determines the fidelity of the hard mask pattern. Low-damage control allows the dimensional deviation of the final hard mask opening to be controlled within +2% relative to the photoresist pattern.

[0053] Maintaining a process operation window: A suitable etching ratio (moderate etching rate of SiON with fluorine-based materials) ensures that the hard mask is completely etched through while the photoresist still has a remaining thickness (e.g., 0.1~0.2μm). The remaining photoresist can be easily removed by a subsequent standard O2 ashing process, avoiding over-etching of the hard mask or damage to the substrate due to photoresist depletion.

[0054] S5: Remove the photoresist layer.

[0055] In this embodiment, in step S5, the photoresist layer is removed using an O2 plasma ashing process, and optionally includes a wet cleaning step to remove ashing residue; in step S7, the inorganic hard mask layer is removed using wet etching, and the etching solution is diluted hydrofluoric acid.

[0056] It is understandable that O2 plasma ashing is a standard residue-free method for resist removal. Combined with SPM cleaning, it can thoroughly remove polymer residues and ensure subsequent interface cleanliness. DHF has an extremely high etching rate for SiON, SiO2, and SiN, but an extremely low etching rate for GaN / SiC materials (selectivity ratio >1000:1). Therefore, removing the hard mask will not damage the etched deep trench sidewalls and bottom, nor will it change critical dimensions.

[0057] S6: Using the patterned inorganic hard mask layer as a mask, the GaN / SiC material layer is etched a second time to form a deep trench. This second etching utilizes the high etching selectivity between the inorganic hard mask layer and the GaN / SiC material layer to maintain a constant mask window size.

[0058] In this embodiment, in step S6, the second etching is performed using inductively coupled plasma etching, the etching gas contains chlorine-based gas, and the etching power is higher than that of the first etching. Preferably, the chlorine-based gas includes Cl2, BCl3, or a combination thereof, the ICP power of the second etching is 600W to 1000W, and the bias power is 150W to 250W.

[0059] It is understandable that high power generates high-density plasma and high-energy ion bombardment, providing sufficient anisotropic etching capability to achieve high aspect ratio etching of deep trenches (1~2μm). Increased bias power enhances the perpendicular incidence directionality of ions, resulting in steep sidewalls (>80°). Chlorine-based gases exhibit high etching rates for GaN / SiC while exhibiting low etching rates for inorganic hard masks, which is the basis for achieving high selectivity.

[0060] Furthermore, in step S6, the etching selectivity ratio of the inorganic hard mask layer to the GaN / SiC material layer in the second etching is ≥10:1, so that the thickness loss of the inorganic hard mask layer during the etching process is less than 20% of the initial thickness, thereby maintaining the constant size of the mask window.

[0061] Understandably, a high selectivity ensures that the hard mask retains sufficient remaining thickness after prolonged etching, preventing the underlying material from being exposed due to mask wear. A constant window size means that the actual etching opening area remains unchanged during etching, which is the fundamental reason for suppressing micro-load effects. Ultimately, the uniformity of etching depth (intra-wafer and inter-wafer) is significantly improved, which is beneficial for increasing the yield of RF chips.

[0062] Furthermore, the deep groove is a mesa isolation groove with an etching depth of 1μm to 2μm and a sidewall angle greater than 80°.

[0063] It is understandable that this depth range is sufficient to cut through the GaN buffer layer, achieving electrical isolation between adjacent devices (breakdown voltage >100V). A sidewall angle >80° ensures the continuity of step coverage when subsequently depositing the isolation medium (such as SiN), avoiding voids or thin spots at the root of the sidewall, thereby ensuring the long-term reliability and leakage current suppression capability of the device.

[0064] It should be noted that the photoresist was removed before the second etching (deep trench etching), and an inorganic hard mask (SiON, SiO2, etc.) was used as the barrier layer. High-power chlorine-based etching was employed (ICP power 600~1000W, bias power 150~250W), with a hard mask to GaN / SiC etching selectivity ratio ≥10:1 and hard mask thickness loss <20%. The achieved technical effects are as follows: The mask window size remains constant, eliminating the "trumpet mouth" effect: Organic photoresist rapidly carbonizes, shrinks, and curls at the edges in chlorine-based high-power plasma, leading to a significant expansion of the mask window size in the later stages of etching, forming a "trumpet mouth" shape that is wider at the top and narrower at the bottom. In this solution, the photoresist is removed before the second etching, leaving only the inorganic hard mask. Its high selectivity ensures that the window size remains almost unchanged throughout the etching process, and the deviation between the top CD and bottom CD of the deep trench after etching is less than 50nm.

[0065] Effectively suppressing micro-load effects: In traditional photoresist mask solutions, the photoresist consumption rate differs across regions with different pattern densities (faster consumption in dense areas and slower consumption in isolated areas), resulting in shallower etching depths in dense areas and deeper etching depths in isolated areas. This solution employs an almost "zero-loss" inorganic hard mask, providing the same blocking capability for both dense and isolated areas. The uniformity of on-chip etching depth can be controlled within ±3%, significantly improving the consistency of mesa isolation breakdown voltage.

[0066] Obtaining steep sidewalls: High bias power enhances the vertical orientation of ions. Combined with a constant window size, a deep trench morphology with a sidewall angle greater than 80° and a smooth surface without microgrooves can be obtained, providing an ideal interface for subsequent dielectric layer coverage and electrical isolation.

[0067] S7: Remove the inorganic hard mask layer to obtain a wafer with mesa isolation trenches.

[0068] Specifically, a wet etching process was used to remove the remaining SiON hard mask layer. The etching solution was diluted hydrofluoric acid (DHF, HF:H2O=1:100), and the wafer was immersed at room temperature for 60 seconds. DHF has an extremely high selectivity for GaN / SiC materials (>1000:1), therefore it will not damage the already etched mesa isolation trench sidewalls and bottom. After removing the hard mask, the wafer was rinsed with deionized water and spun dry to obtain a wafer with mesa isolation trenches.

[0069] Furthermore, it also includes step S8: after completing the deep trench etching and removing the inorganic hard mask layer, performing subsequent processes, the subsequent processes including at least one of depositing an isolation dielectric layer, fabricating source / drain / gate electrodes, metal interconnects, back-side thinning, and fabricating back-side vias.

[0070] Specifically, after completing the deep trench etching and removing the hard mask, subsequent processes include depositing isolation dielectric, fabricating source / drain / gate electrodes, metal interconnects, back-side thinning, and back-side vias. This demonstrates that the deep trench etching method provided by this invention is highly compatible with the complete RF device manufacturing process and can be directly integrated into mass production lines. The mesa isolation trenches fabricated using this method have precise CD, steep sidewalls, and uniform depth, laying a solid foundation for subsequent electrode fabrication and dielectric filling, ultimately improving the frequency characteristics, output power, and yield of RF HEMT devices.

[0071] The wafer deep trench etching method provided by this invention defines a pattern on a thin photoresist (0.5~1.5μm) using only one photolithography exposure; subsequently, the pattern is transferred to a hard mask through a first etching; after removing the photoresist, a second deep trench etching is performed using the hard mask. No secondary photolithography is required throughout the process. This simplifies the process flow and reduces costs: compared to the traditional hard mask solution (which requires hard mask deposition, photolithography, hard mask etching, photoresist removal, secondary photolithography, secondary alignment, and deep trench etching), this application omits the second photolithography and the corresponding photoresist coating, alignment, and development processes, reducing equipment downtime, material consumption, and manual operation. The single-batch process cycle can be shortened by 20%~30%.

[0072] Furthermore, to avoid the accumulation of alignment errors, traditional solutions require secondary photolithography alignment between the hard mask pattern and subsequent deep trench etching. Any misalignment will directly lead to device performance degradation (such as increased leakage current caused by misalignment of the mesa isolation trench). This solution uses only one photolithography step, fundamentally eliminating multi-layer alignment errors.

[0073] In addition, it supports high-resolution patterns. Since the photoresist no longer serves as a barrier to deep trench etching, thin photoresist (<1μm) can be used. Thin photoresist greatly reduces light scattering and standing wave effects during exposure, improving the resolution to 0.35μm and below, which can meet the increasingly smaller feature size requirements of RF devices.

[0074] This application also provides a wafer prepared by any of the methods described herein.

[0075] The wafer deep trench etching method described in this invention is not only applicable to the fabrication of mesa isolation trenches for SiC on GaN RF HEMT devices, but can also be extended to the following multiple application scenarios. The process requirements and applicability of this invention for each scenario are described below.

[0076] 1. Application scenarios for grounding via the back hole Process requirements: Back-side vias need to be etched through the SiC substrate from the back of the wafer, with a typical thickness of 50~100μm and an aspect ratio usually greater than 10:1. The etching process requires high selectivity and high etching rate, while maintaining steep sidewalls of the vias to facilitate subsequent metal filling and low ground inductance. The hard mask material must withstand long-term, high-power deep SiC etching and must not damage the front-side devices during removal.

[0077] Specific applicability includes: Low-temperature hard masks can support ultra-deep etching: The inorganic hard masks (such as SiON and SiO2) selected in this invention have an extremely high selectivity (>20:1) in fluorine-based or chlorine-based deep SiC etching. Even if the etching depth reaches 50~100μm, the hard mask thickness only needs to be a few micrometers to meet the blocking requirements (for example, 1.5μm SiON can withstand about 30μm SiC etching, and the thickness can be adjusted by stacking).

[0078] High-precision via patterning defined in a single photolithography step: The alignment accuracy of the vias on the back side directly affects the connection resistance between the front electrode and the back metal. This invention requires only one photolithography step, avoiding the cumulative error of multiple alignments, and ensuring that the alignment deviation between the via position and the front pad is less than ±1μm.

[0079] Low-temperature process compatible with wafer-level packaging: Backside via fabrication is typically performed after the front-side processing of the device is complete. The wafer already has a front-side metal layer and dielectric layer. High-temperature hard mask deposition may damage the front-side structure or exacerbate warpage. The low-temperature (150~200°C) deposition process of this invention is fully compatible with the thermal budget requirements of already processed wafers.

[0080] 2. Application scenarios of deep trench capacitors Process requirements: Deep trench capacitors require etching deep trenches of 2-5 μm in the GaN / SiC material layer, with high sidewall steepness (typically >80°) to ensure vertical structure and capacitance consistency between capacitor plates. The trench bottom and sidewalls must be smooth and free of micro-grooves to avoid breakdown voltage drop caused by electric field concentration. The deep trench array includes both dense and isolated regions, requiring uniform etching depth to suppress micro-load effects.

[0081] Specific applicability includes: Sidewall angle > 80°, meeting the perpendicularity requirement: The second etching of this invention uses high bias power (150~250W) chlorine-based plasma, which has strong ion vertical incidence directionality. Combined with the constant window of the inorganic hard mask, the measured sidewall angle can reach 85°~89°, which fully meets the perpendicularity requirement of deep trench capacitors.

[0082] Suppressing micro-load effects and ensuring depth uniformity: The hard mask has almost zero loss during the etching process (selectivity ratio ≥10:1, thickness loss <20%), providing the same blocking ability for regions with different pattern densities, so that the on-chip depth uniformity of 2~5μm deep trenches can be controlled within ±3%, and the capacitance value consistency is significantly improved.

[0083] High-fidelity pattern transfer: The lateral dimension (CD) of a deep trench capacitor directly affects the capacitance per unit area. This invention employs thin photoresist (<1μm) and low-damage first etching, controlling the pattern transfer deviation within +2%, thus ensuring the accuracy of capacitor design.

[0084] 3. Gate Trench Etching Application Scenarios (MIS-HEMT) Process Requirements: For metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs), gate trench etching requires precise control of the etching depth within the AlGaN barrier layer or GaN cap layer, typically only 20-50 nm, which is considered extremely shallow trench etching. Critical dimension (CD) accuracy is extremely critical because the gate length directly affects the device's cutoff frequency (fT) and maximum oscillation frequency (fmax). Etching stop must be precise to avoid penetrating the barrier layer, which could lead to threshold voltage drift or increased leakage current.

[0085] Specific applicability includes: Thin-film and high-fidelity transfer enable submicron-level CD control: This invention allows the use of photoresist with a thickness of <1μm, combined with KrF deep ultraviolet lithography, to define gate patterns of 0.35μm and below. After a low-damage transfer to a hard mask, followed by extremely shallow etching with the hard mask, the final gate CD deviation can be controlled within ±20nm.

[0086] Hard masks provide precise etching endpoints: Inorganic hard masks are almost consumed in shallow trench etching, avoiding the opening enlargement problem caused by the gradual thinning of photoresist masks during etching. Combined with endpoint detection techniques (such as photoemission spectroscopy), precise stopping at depths of 20–50 nm can be achieved.

[0087] Low-temperature processing does not affect gate interface quality: Source / drain ohmic contacts and passivation layer deposition are usually completed before gate trench etching, and high-temperature hard masks may introduce interface states or thermal stress. The low-temperature deposition of this invention avoids damage to sensitive gate regions.

[0088] 4. Other extended fields of compound semiconductors A. SiC-based power devices (MOSFET, JFET) SiC-based power devices (such as silicon carbide MOSFETs and JFETs) also face the challenge of deep trench etching of SiC substrates or epitaxial layers. For example, trench gate structures typically require etching SiC trenches 1-5 μm deep. SiC materials have high hardness and strong chemical inertness, resulting in low etching selectivity and extremely high requirements for the durability of the mask material. The low-temperature inorganic hard mask (SiON, SiO2) in this invention exhibits a high selectivity (typically 10:1-15:1) with SiC in fluorine-based etching, allowing for direct transfer. Simultaneously, the one-step photolithography two-step transfer architecture simplifies the process, making it particularly suitable for power MOSFETs requiring high-precision trench CD control.

[0089] B. GaN-on-Si RF devices Although the GaN-on-Si heterojunction uses a different substrate (silicon substrate instead of SiC), it still faces the same wafer warpage problem: the thermal mismatch between silicon and GaN is greater, and the wafer warpage is more significant.

[0090] One of the core advantages of this invention is the low-temperature, low-stress hard mask, which is also effective for GaN-on-Si. The deposition temperature of 150~200℃ is far below the plastic deformation temperature of the silicon substrate, avoiding the introduction of additional stress. During deep trench etching (mesa isolation or back-side vias), the high selectivity of the hard mask to GaN remains unchanged; the only adjustment is to pay attention to the etching rate of the silicon substrate by DHF when removing the hard mask (a thin oxide layer can be added for protection). The entire method can be directly ported.

[0091] C. Other III-V devices (InP, GaAs) Indium phosphide (InP), gallium arsenide (GaAs), and other III-V group semiconductors are widely used in optoelectronics and high-frequency devices. They also require deep trench etching for mesa isolation, channel definition, or back-side vias.

[0092] The "one-step photolithography + hard mask" architecture of this invention is versatile: by selecting a suitable hard mask (such as SiO2, SiN, SiON) and etching gas (such as Cl2 / Ar, CH4 / H2, etc.) according to the material to be etched, the low-temperature deposition principle and one-step photolithography strategy can remain unchanged. For example, the mesa isolation etching of InP-based HEMTs can use low-temperature PECVD SiO2 as a hard mask, and the pattern can be defined by one-step photolithography, which can also avoid the problem of photoresist carbonization and micro-loading effect, and obtain steep sidewalls.

[0093] To more clearly illustrate the technical solution and expected effects of the present invention, the present invention will be described in detail below with reference to specific embodiments and experimental data. It should be understood that these embodiments are for illustrative purposes only and do not constitute any limitation on the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0094] Example The first step is to select a substrate, a 4-inch silicon carbide (SiC) substrate, which is semi-insulating and 350 μm thick. On the SiC substrate, an epitaxial structure is grown sequentially by metal-organic chemical vapor deposition (MOCVD): a GaN buffer layer with a thickness of approximately 2 μm, an undoped GaN channel layer with a thickness of approximately 300 nm, an AlGaN barrier layer with a thickness of approximately 25 nm and an Al composition of 25%, and a GaN cap layer with a thickness of approximately 3 nm. The second step involves using plasma-enhanced atomic layer deposition (PE-ALD) equipment to deposit a silicon oxynitride (SiON) hard mask layer on the surface of the GaN / SiC material layer at a deposition temperature of 150°C. This temperature is much lower than the 300-400°C temperature range of traditional PECVD deposition of SiO2, which can effectively avoid introducing additional thermal stress into the SiC / GaN heterojunction. Testing showed that the wafer warpage variation after deposition in this embodiment was less than ±5μm, while the warpage increase after deposition of traditional high-temperature hard masks can reach 20~30μm. The deposition thickness was 200nm, which is sufficient to withstand the subsequent GaN etching consumption of about 1.5μm (the etching selectivity ratio of SiON to GaN is about 15:1), while avoiding the decrease in pattern transfer accuracy caused by excessive thickness. Stress control was achieved by adjusting the RF power and gas flow ratio (SiH4 / N2O) in the PE-ALD process to make the SiON hard mask layer exhibit micro compressive stress (-100MPa~-200MPa), which can partially offset the original tensile stress of the SiC / GaN heterojunction and further improve wafer flatness. The third step involves spin-coating a positive photoresist layer onto the SiON hard mask layer. This embodiment uses KrF deep ultraviolet photoresist (such as the JSR AR series) with a thickness of 0.8 μm. After coating, a pre-baking process is performed at 110°C for 90 seconds. This method uses a relatively thin photoresist (0.8 μm), which significantly improves pattern resolution compared to traditional pure photoresist methods (typically requiring 3-5 μm thick photoresist), supporting critical dimension definitions of 0.35 μm and below. The fourth step involves exposure using a KrF stepper lithography machine. The exposure energy is 25 mJ / cm², and the numerical aperture (NA) is 0.65. Post-exposure baking (PEB) is performed at 115°C for 90 seconds. Development is then performed using tetramethylammonium hydroxide (TMAH) developer (2.38%) for 60 seconds, resulting in a photoresist pattern corresponding to the mesa isolation trench. The critical dimension (CD) of the photoresist pattern opening is 1.0 μm, and the sidewall angle is approximately 85°. In this step, the critical dimension uniformity (CDU) of the photoresist pattern is controlled within 3%, meeting the requirements for RF devices. The fifth step involves etching the exposed SiON hard mask layer using the photoresist pattern as a mask, transferring the pattern to the hard mask layer. The etching equipment is an inductively coupled plasma (ICP) etching machine. The etching gas is a CF4 / CHF3 / Ar mixture with a flow rate ratio of CF4:CHF3:Ar = 30:15:100 sccm. The process parameters are as follows: chamber pressure 30 mTorr, ICP power 300 W, bias power 50 W, and etching time approximately 45 seconds. Step 6: Remove the remaining photoresist layer using O2 plasma ashing. Process conditions: O2 flow rate 500 sccm, chamber pressure 500 mTorr, RF power 200 W, temperature 120℃, time 120 seconds. After ashing, remove ashing residue using a wet cleaning step: clean with SPM solution (H2SO4:H2O2=4:1) at 120℃ for 10 minutes, then rinse with deionized water and spin dry. At this point, the pattern of the area to be etched has been completely transferred to the SiON hard mask layer, with a hard mask window size of 1.02 μm (a deviation of only +2% compared to the photolithographic pattern size of 1.0 μm). Step 7: Using the SiON hard mask layer as a mask, deep trench etching is performed on the exposed GaN / SiC material layer to form mesa isolation trenches. An ICP etching machine is used. The etching gas is a Cl2 / BCl3 / Ar mixture with a flow ratio of Cl2:BCl3:Ar = 50:20:10 sccm. The process parameters are as follows: chamber pressure 15 mTorr, ICP power 800 W, bias power 200 W, and etching time approximately 8 minutes. Step 8: Remove the remaining SiON hard mask layer using a wet etching process. The etching solution is diluted hydrofluoric acid (DHF, HF:H2O=1:100), and the wafer is immersed at room temperature for 60 seconds. DHF has an extremely high selectivity for GaN / SiC materials (>1000:1), therefore it will not damage the etched mesa isolation trench sidewalls and bottom. After removing the hard mask, the wafer is rinsed with deionized water and spun dry to obtain a wafer with mesa isolation trenches. Step 9: After completing the above steps, the wafer enters the subsequent processes, including: depositing an isolation dielectric layer (such as SiN or SiO2), fabricating source / drain / gate electrodes, metal interconnects, back-side thinning, and fabricating back-side vias, etc.

[0095] Compared with existing technologies, the wafer deep trench etching method provided in the above embodiments of the present invention simultaneously solves the inherent contradictions of traditional solutions in five dimensions: critical dimension control, sidewall morphology, warpage compatibility, process complexity, and etching uniformity. The comparison is as follows: I. Improvement of Critical Dimension (CD) Control Precision

[0096] II. Significant Improvement in the Morphology of Deep Trench Sidewalls

[0097] III. Perfect compatibility with SiC on GaN heterojunction warpage

[0098] IV. Significant simplification of process flow and cost reduction

[0099] V. Significantly improved etching uniformity and wider process window

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0101] It is understood that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above are merely preferred embodiments of this application, and only specifically describe the technical principles of this application. These descriptions are only for explaining the principles of this application and should not be construed as limiting the scope of protection of this application in any way. Based on this explanation, any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application, as well as other specific embodiments of this application that can be conceived by those skilled in the art without creative effort, should be included within the scope of protection of this application.

Claims

1. A method for deep trench etching of a wafer, characterized in that, Includes the following steps: S1: A substrate is provided, on which a SiC layer and a GaN layer are formed to form a GaN / SiC material layer; S2: Deposit an inorganic hard mask layer on the GaN / SiC material layer at a temperature below 300°C to ensure that the inorganic hard mask layer is in a low-stress state and to avoid introducing additional thermal stress into the SiC / GaN heterojunction. S3: A photoresist layer is formed on the inorganic hard mask layer, and the desired pattern is defined in the photoresist layer through a single photolithography process; S4: Using the photoresist layer as a mask, perform a first etching on the inorganic hard mask layer to transfer the pattern to the inorganic hard mask layer. The first etching uses a low bias power to reduce physical bombardment of the photoresist. S5: Remove the photoresist layer; S6: Using the patterned inorganic hard mask layer as a mask, the GaN / SiC material layer is etched a second time to form a deep trench. The second etching utilizes the high etching selectivity between the inorganic hard mask layer and the GaN / SiC material layer to keep the mask window size constant. S7: Remove the inorganic hard mask layer to obtain a wafer with mesa isolation trenches.

2. The method according to claim 1, characterized in that, In step S2, the inorganic hard mask layer is formed by plasma-enhanced atomic layer deposition or plasma-enhanced chemical vapor deposition at a deposition temperature of 150°C to 200°C; and / or, the material of the inorganic hard mask layer is selected from one or more of silicon oxynitride, silicon oxide, or silicon nitride.

3. The method according to claim 1, characterized in that, In step S2, by adjusting the deposition process parameters, the inorganic hard mask layer is made to exhibit micro-compressive stress, which partially offsets the original tensile stress of the GaN / SiC material layer and improves the wafer flatness.

4. The method according to claim 3, characterized in that, The range of the micro-compressive stress is -100MPa to -200MPa.

5. The method according to claim 1, characterized in that, In step S3, the thickness of the photoresist layer is 0.5-1.5μm, and the first photolithography process uses KrF deep ultraviolet lithography, and the photoresist is a positive photoresist.

6. The method according to claim 1, characterized in that, In step S4, the first etching is performed using inductively coupled plasma etching, the etching gas contains fluorine-based gas, and the etching power is lower than that of the second etching. The fluorine-based gas includes CF4, CHF3, or a combination thereof. The ICP power of the first etching is 200W to 400W, and the bias power is 30W to 80W.

7. The method according to claim 1, characterized in that, In step S6, the second etching is performed using inductively coupled plasma etching, the etching gas contains chlorine-based gas, and the etching power is higher than that of the first etching. The chlorine-based gas includes Cl2, BCl3, or a combination thereof. The ICP power of the second etching is 600W to 1000W, and the bias power is 150W to 250W.

8. The method according to claim 1, characterized in that, In step S6, the etching selectivity ratio of the inorganic hard mask layer to the GaN / SiC material layer in the second etching is ≥10:1, so that the thickness loss of the inorganic hard mask layer during the etching process is less than 20% of the initial thickness, thereby maintaining the constant size of the mask window.

9. The method according to claim 1, characterized in that, In step S5, the photoresist layer is removed using an O2 plasma ashing process, and optionally includes a wet cleaning step to remove ashing residue; in step S7, the inorganic hard mask layer is removed using wet etching, and the etching solution is diluted hydrofluoric acid.

10. The method according to claim 1, characterized in that, The deep groove is a mesa isolation groove with an etching depth of 1μm to 2μm and a sidewall angle greater than 80°.

11. The method according to claim 1, characterized in that, The substrate is a silicon carbide substrate, and the GaN / SiC material layer includes a GaN buffer layer, an undoped GaN channel layer, an AlGaN barrier layer, and a GaN cap layer formed sequentially on the silicon carbide substrate.

12. The method according to claim 1, characterized in that, It also includes step S8: after completing the deep trench etching and removing the inorganic hard mask layer, performing subsequent processes, the subsequent processes including at least one of depositing an isolation dielectric layer, fabricating source / drain / gate electrodes, metal interconnects, back-side thinning, and fabricating back-side vias.

13. A wafer, characterized in that, It is prepared by the method according to any one of claims 1 to 12.

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