Semiconductor device and method of manufacturing a semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device, the method comprising forming a first etch stop layer over a substrate; forming an interlayer dielectric over the etch stop layer; patterning the interlayer dielectric to form a first opening and a second opening; forming a second etch stop layer over the patterned interlayer dielectric; forming an antireflective layer over the first etch stop layer, the antireflective layer having a first thickness over the first opening and a second thickness greater than the first thickness over the second opening; etching the antireflective layer to expose a bottom surface of the second opening, the antireflective layer covering the bottom surface of the first opening.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor device structures and methods for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a substrate, and using photolithography to pattern these material layers to form circuit components and elements. As the semiconductor industry has progressed to nanotechnology process nodes in pursuit of higher device density, improved performance, and lower costs, challenges from both manufacturing and design issues have led to the development of stacked substrates, such as in the case of wafer or die bonding. Accordingly, various components of a circuit can be distributed between substrates. Alignment marks provide a fiducial indication to identify a relative lateral portion of a device. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first etch stop layer over a substrate; forming an interlayer dielectric over the first etch stop layer; patterning the interlayer dielectric to form a patterned layer including a first opening and a second opening; forming a second etch stop layer over the patterned layer; forming an antireflective layer over the second etch stop layer, the antireflective layer having a first thickness over the first opening and a second thickness less than the first thickness over the second opening; and etching the antireflective layer to expose a bottom surface of the second opening, the antireflective layer covering the bottom surface of the first opening.

[0004] According to some embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate comprising a plurality of memory cells; forming a first capping layer over the substrate; forming a patterned layer over the first capping layer, the patterned layer comprising a plurality of first openings spaced apart over the plurality of memory cells and a plurality of second openings laterally spaced apart from the plurality of first openings; forming a second capping layer over the patterned layer; forming an antireflective layer over the second capping layer, the antireflective layer having a first thickness over the plurality of first openings and a second thickness greater than the first thickness over the plurality of second openings; and etching the antireflective layer in the plurality of second openings to expose at least one of the first capping layer and the second capping layer.

[0005] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a plurality of memory cells; alignment marks provided for the memory cells, which are laterally offset from the plurality of memory cells, wherein the alignment marks have a thickness of more than about 800 angstroms and abut along the sidewalls; an interlayer dielectric formed in the memory cells; a silicon-based layer formed in the interlayer dielectric; a first etch stop layer formed in the silicon-based layer; and a low-k dielectric layer formed in the silicon-based layer, which perpendicularly spaces the memory cells from each other. Attached Figure Description

[0006] The nature of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 An exemplary flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown.

[0008] Figure 2-7 Examples according to some embodiments Figure 1 An example cross-sectional view of a semiconductor device during various manufacturing stages of the method.

[0009] Figure 8 Examples according to some embodiments include those that can Figure 1 An example cross-sectional view of a semiconductor device with stacked layers formed during the method. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided objectives. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, a first feature formed on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of explanation, this document may use spatial relative terms such as “under,” “below,” “below,” “above,” “on,” “top,” “bottom,” and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted accordingly. Reference to “or” may be interpreted inclusively, such that any term described using “or” may indicate any one, more than one, or all of the terms described. Reference to at least one of the combined terms may be interpreted as an inclusive OR, indicating any one, more than one, or all of the terms described. For example, a reference to "at least one of 'A' and 'B'" can include only "A", only "B", or both "A" and "B". Such references, when used in conjunction with "includes" or other open-ended terms, can include additional items.

[0012] Typically, alignment marks (sometimes called reference marks) are provided to identify an edge or other portion of a semiconductor device. For example, a semiconductor device, including a stacked memory device, may include alignment marks to assist in its stacking or bonding, maintaining a position of stacked components that can be thermally or electrically connected to each other. Such stacking may refer to the stacking of two or more substrates, such as back-side or front-side bonding, or providing additional layers on top of a semiconductor device. Thicker alignment marks are easier to identify and can aid in the alignment of the various layers above each other.

[0013] According to this disclosure, alignment marks can be formed based on a non-uniform distribution of an anti-reflective coating, rather than defining the openings for the alignment marks using a lithographic mask. For example, a spin-coating process can accumulate a larger thickness of organic back-side anti-reflective coating (oBARC) over a portion of a semiconductor device including fewer or smaller openings, relative to a larger opening. Accordingly, the larger opening associated with the alignment mark can receive an oBARC thickness less than the thickness of other portions of the semiconductor device (e.g., a portion formed over a memory cell or device logic). This greater thickness protects the memory cell or device logic from removal processes used to form or extend the openings for the alignment marks, thereby avoiding the need for a separate mask to define the alignment mark. This technique eliminates the need for a separate mask to define the alignment mark openings and can further define deeper openings, allowing for the formation of thicker alignment marks, thus facilitating alignment mark identification compared to other methods.

[0014] Figure 1A flowchart illustrating a method 100 for manufacturing a semiconductor device according to some embodiments is provided. For example, at least some of the operations (or steps) of method 100 can be used to form a semiconductor device including an alignment mark. It should be noted that method 100 is merely an example and is not intended to limit the scope of this disclosure. Accordingly, it should be understood that... Figure 1 Additional operations are provided before, during, or after Method 100, and some other operations may be briefly described in this document only.

[0015] In short, method 100 begins with operation 102 of providing a substrate. Then, method 100 continues to operation 104 of forming an etch stop layer over the substrate. Next, method 100 continues to operation 106 of forming a patterned layer over the etch stop layer. Next, method 100 continues to operation 108 of forming a second etch stop layer over the patterned layer. Next, method 100 continues to operation 110 of forming an anti-reflective layer over the second etch stop layer. Next, method 100 proceeds to operation 112 of etching the anti-reflective layer to expose at least one etch stop layer.

[0016] Corresponding to Figure 1 Operation 102, Figure 2 An example is a semiconductor device 200 including a substrate 202. The substrate 202 may include an active surface on which various components may be formed. For example, the active surface may include transistors, diodes, resistors, or capacitors, which are electrically interconnected to form a circuit. The active surface of the semiconductor device 200 may include various regions depending on a function of the circuit. For example, a first region 206 of the semiconductor device 200 may include a memory cell. A second region 208 of the semiconductor device 200 may include circuitry for a processor or other logic for processing a circuit system. A third region 210 of the semiconductor device 200 may be reserved for an alignment mark, which may aid in the positioning of the semiconductor device 200. For example, the alignment mark may serve as a reference mark to aid in the formation of additional layers stacked on top of the semiconductor device.

[0017] Although depicted in this figure as approximately equal in lateral dimensions, the third zone 210 is... Figure 3-8 The areas are depicted more prominently, but the areas associated with the corresponding regions can vary considerably. For example, the area dedicated to alignment marks is typically small (e.g., one percent of the device area). Accordingly, the first region 206 and the second region 208 can constitute the majority of a device, which can vary depending on the type of device. For example, in an exemplary example, the first region 206 may occupy approximately five percent of the device area, and the second region 208 may occupy approximately ninety-five percent.

[0018] The illustrated substrate 202 may be provided with any number of stacked layers, which may include additional functional surfaces coupled to each other via via structures 214. The via structures 214 may provide as back-side or other through-substrate vias (sometimes referred to as through-silicon vias). An interlayer dielectric that may include a low-k dielectric 212 may provide electrical separation of various components of the layers to reduce crosstalk or other electromagnetic coupling / interference between the layers. In some embodiments, the low-k dielectric 212 is provided as an extremely low-k dielectric (having a k value less than 2.5). For example, silicate glass (OSG), fluorinated silicon oxide (SiOF), spin-coated polymers, or various porous materials may be used. The low-k dielectric 212 may be formed over a surface of the semiconductor device (e.g., a back side opposite a front functional surface).

[0019] Some of the via structures 214 are illustrated as extending vertically through the first region 206, which can be configured to couple with various additional memory cells stacked thereon, or form interconnects between various memory cells. Other via structures 214 are illustrated as extending through the second region 208, which can be configured to couple with various additional devices or logic, or form interconnects. According to various exemplary examples of this disclosure, the via structures 214 can be configured as back-side vias. However, such references should not be construed as limiting. The patterns of this disclosure can be applied to front-side bonding or stacking, or other procedures.

[0020] Corresponding to Figure 1 Operations 104-106 Figure 3 A cross-sectional view of a semiconductor device 200 is shown, which includes a patterned layer 304 formed in operation 106. The patterned layer 304 is formed over a first etch stop layer 302 formed in operation 104.

[0021] Referring to a first etch stop layer 302 (sometimes referred to as a capping layer), the first etch stop layer 302 may be provided as an alumina layer. The alumina layer may be formed according to an atomic layer deposition (ALD) process, which provides sufficient process control for a relatively thin layer, such as about 40 angstroms. For example, 40 cycles of an ALD process may be repeated to form the first etch stop layer. Some embodiments may apply the alumina layer according to other processes, such as chemical vapor deposition or physical vapor deposition (CVD / PVD). These processes can provide a bulk layer with fewer cycles (e.g., a single cycle). However, these approaches provide reduced process control compared to the ALD process. In some embodiments, an etch stop layer (e.g., the first etch stop layer 302) may comprise another material. For example, an etch stop layer may comprise hafnium oxide or zirconium oxide, among others.

[0022] The first etch stop layer 302 can be directly formed on a substrate (e.g., ...). Figure 2 It can be deposited on top of the depicted substrate, or on top of another layer. For example, various first etch stop layers 302 can be formed on... Figure 2-7 The illustrated layers are stacked repeatedly to form a stacked memory device. The stacked memory device may include a silicon-based layer that may include a semiconductor material for forming an active surface, or various hard masks 312 or stress-compensating layers. For example, this silicon-based layer may include a hard mask 312 comprising silicon oxynitride, silicon carbide, or silicon carbonitride having a thickness of approximately 150 angstroms.

[0023] Referring to patterned layer 304, patterned layer 304 may include an interlayer dielectric (ILD). The interlayer dielectric may include, for example, undoped silicate glass (USG), formed according to a CVD process, such as plasma-enhanced CVD or low-pressure CVD. In some embodiments, the ILD may be formed to have a thickness of about 650 angstroms. Various openings may be formed to generate patterned layer 304 according to various positive or negative lithography processes. Patterned layer 304 may include one or more constituent layers, which may include a body layer for assisting process control in lithography. For example, patterned layer 304 may include a first layer 308 of the ILD and a second layer 310 of an antireflective coating. The antireflective coating may include a negative tone bottom antireflective coating (NFARC) having a thickness of about 330 angstroms.

[0024] The openings can be formed with varying lateral widths according to a lithography process. For example, one or more first openings 314 may be formed over a first region 206 of the substrate, over a memory cell or logic element. The first opening 314 may be formed to receive additional via structures or other interconnects. At least one second opening 316 may be formed over a third region 210. The second opening 316 may be formed to receive an alignment mark. The second opening 316 may exhibit a larger lateral width than the first opening (e.g., at least an order of magnitude larger). The widths of the various openings may be defined according to a mask used for patterning the positive or negative lithography process of the patterned layer 304.

[0025] Corresponding to Figure 1 Operation 108, Figure 4An example is a semiconductor device 200 having a second etch stop layer 402 formed above a patterned layer 304. The second etch stop layer 402 may be made of the same material as the first etch stop layer (e.g., aluminum oxide), or it may be made of a different material. The thickness of the second etch stop layer 402 may differ from the thickness of the first etch stop layer. For example, the second etch stop layer 402 may be about half the thickness of the first etch stop layer 302 (e.g., about 20 angstroms of aluminum oxide). A total etch stop thickness may vary between the bottom surface of the opening and an upper surface of the patterned layer 304. For example, at the bottom surface of the opening, the second etch stop layer 402 may additionally form above the first etch stop layer 302 (although some portions of the first etch stop layer 302 may be affected by the patterning of the patterned layer 304). Conversely, the portion of the second etch stop layer 402 formed above the upper surface of the patterned layer 304 should not include any contribution from the first etch stop layer 302. Accordingly, the etch stop structure formed above the patterned layer can be configured according to the deposition thickness of the second etch stop layer 402, at least in the case where the patterned layer itself does not include a constitutive etch stop structure along an upper surface.

[0026] Corresponding to Figure 1 Operation 110, Figure 5 An example is a semiconductor device 200 having an anti-reflective layer 502 formed over a second etch stop layer 402. For example, the anti-reflective layer 502 may be formed as an organic back-side anti-reflective coating oBARC deposited according to a spin coating process, or an inorganic back-side anti-reflective coating iBARC deposited according to a CVD deposition process.

[0027] As illustrated, the antireflective layer 502 exhibits a shallower taper than the patterned layer 304. That is, the sidewalls 503 of the antireflective layer 502 are shallower than the sidewalls of the first opening 314 or the second opening 316. Accordingly, the antireflective layer 502 can form a relatively flat upper surface above the (later smaller) first opening 314 and exhibit a larger pull above the (later larger) second opening 316, wherein the lateral dimension of the second opening 316 exceeds the lateral dimension of the pull sidewall of the antireflective layer 502. For example, a dimension of a lateral surface at the bottom of a second opening 316 formed between corresponding sidewalls 503 can exceed the lateral dimension of a bottom of the antireflective layer 502 (the bottom of the antireflective layer 502 formed above the bottom of the second opening 316). A first distance 504 (or thickness) extending from one side of a first opening 314 toward a bottom surface towards the center may exceed a second thickness 506 (or distance) extending from one side of a second opening 316 toward a bottom surface towards the center. This difference may approximately correspond to the thickness of the patterned layer 304. For example, for a patterned layer 304 having an ILD of 650 angstroms and an NFARC of 330 angstroms, the difference between the first distance 504 and the second distance 506 may deviate by approximately 980 angstroms (~100 nm). Accordingly, a third distance 508 (or thickness), measured along one sidewall of the second opening 316, may be approximately equal to the first distance 504.

[0028] For the application of the antireflective layer 502, particularly for spin coating processes used to apply oBARC, the antireflective layer 502 can be clumped over an existing high point of the patterned layer 304 near the first opening 314. This clumping can result in a slightly larger accumulation of material above the first region 206 (or the second region 208) relative to the third region 210. This effect can be amplified by reducing the spin speed (e.g., to about 1k-2k RPM) or by using a multi-step spin profile that starts at less than about 1k RPM (e.g., about 500 RPM) and ramps up to about 2k RPM. Additionally, increased BARC viscosity from a solvent used to remove BARC, or reduced baking time or temperature, can contribute to the clumping process to increase the asymmetry of the deposition thickness. This clumping effect can result in a slightly larger BARC thickness above an upper surface of the patterned layer 304 relative to the bottom of the second opening 316. For example, the first distance 504 may be approximately 1400 angstroms, including a patterned layer of approximately 1000 angstroms and a fourth thickness 510 (or distance) of approximately 400 angstroms of BARC deposited on the patterned layer 304. The second thickness 506 may be equal to or slightly less than the fourth thickness 510 (e.g., approximately 300 angstroms). The difference in thickness of the antireflective layer 502 can be used to replace a mask (e.g., the first region 206 or the second region 208) by providing greater protection against removal for the portion of the semiconductor device 200 covered by the thicker portion relative to the thinner portion. This approach can therefore omit a mask used to define the features of an alignment mark in the third region 210.

[0029] Corresponding to Figure 1 Operation 112, Figure 6An example is a semiconductor device 200 in which the antireflective layer 502 has been removed (e.g., etched). Depending on time, the number of cycles, the etchant composition, or chamber conditions, the removal can be configured to remove a selected thickness of the antireflective layer 502. For example, the removal can be configured to remove at least a second thickness 506 (above the second opening 316), but less than a fourth thickness 510 (above the patterned layer 304 near the first opening 314). This removal can expose a second etch stop layer 402 in the bottom of the second opening 316. In some cases, a build-up effect can further result in a greater thickness of the antireflective layer 502 above the portion of the patterned layer 304 near the second opening 316, which can protect this upper surface. However, these areas can be configured as clearance areas for electrical connections so that some damage to the patterned layer 304 in these areas is acceptable. A fifth thickness 602 (or distance) of approximately 50-100 angstroms of antireflective layer 502 may be maintained above the etch stop layer 402 formed above the patterned layer 304 defining the first opening 314. Furthermore, a portion of the antireflective layer 502 may be retained along the sidewall of the second opening 316 (and covering the first opening to at least an upper surface of the second etch stop layer 402 formed above the patterned layer 304). This remaining portion of the antireflective layer 502 may reduce the effects of under-etching, a wet process used to remove any of the hard mask 312, low-k dielectric 212, or the etch stop layer.

[0030] In continuing to correspond Figure 1 In the case of operation 112, Figure 7 This example illustrates another removal (e.g., etching) operation, thereby removing... Figure 6 The exposed second etch stop layer 402 and a first etch stop layer 302 formed thereunder. For example, a dry etching process can be applied to remove the second etch stop layer 402 and the first etch stop layer 302 (which may form a single combined layer 704). The operation may further remove a portion of the anti-reflective layer 502 above the first region 206. However, the fifth thickness 602 of the remaining anti-reflective layer 502, combined with the thickness of the second etch stop layer 402 formed thereover the anti-reflective layer 502, can protect the patterned layer 304 (e.g., at least the ILD of the patterned layer 304) during an etching process used to remove the first etch stop layer 302 and the second etch stop layer 402 at the bottom of the second opening 316.

[0031] The same etching process (or another removal process) can remove all or part of the silicon-based layer or other hard mask 312, extending into the low-k dielectric 212. For example, approximately 300 angstroms can be removed (e.g., Figure 7The low-k dielectric 212 (shown in 702) is removed. In some embodiments, removal may be performed according to a multi-step procedure. For example, a first sub-operation of dry etching may break through the first etch stop layer 302 and the second etch stop layer 402, and a second sub-operation may extend the opening into the hard mask 312 and the low-k dielectric 212. The second sub-operation may include a slightly isotropic etching that may etch the hard mask 312 such that a sidewall of the second opening 316 for alignment marks extends laterally under the hard mask 312 (e.g., under a silicon-based layer).

[0032] After the first etch stop layer 302 and the second etch stop layer 402 are breached, any remaining portion of the antireflective layer 502 can be removed. For example, an oxygen, nitrogen, or ammonia-based plasma can be used to remove the remaining portion of the antireflective layer 502 (sometimes referred to as a plasma stripping process). Because alignment marks will form over the exposed low-k dielectric 212 at the bottom of the second opening, carbon loss, porosity collapse, or other damage to the exposed low-k dielectric 212 should not affect circuit operation. In fact, such operations can further extend the etchant depth into the exposed low-k dielectric 212, thereby increasing the final thickness of the alignment marks. Etching can be selective for other portions of the semiconductor device 200 (e.g., USG or other ILDs) to minimize removal or damage to these portions.

[0033] Figure 8 An exemplary cross-sectional view of a semiconductor device 200 including stacked layers is shown. For example, the illustrated semiconductor device 200 can be based on... Figure 1 Method 100 is used to form the memory device. In some embodiments, method 100 may form one or more alignment marks 802 on the same layer of a semiconductor device 200. In some embodiments, method 100 may be repeated to form a plurality of stacked layers, each having at least one alignment mark 802. For example, method 100 may be repeated to form a stack of memory devices comprising tens, hundreds or thousands of layers.

[0034] Vertically extending through the via structure 214 of the first region 206, it couples with other via structures or other interconnects 804. The interconnect 804 is illustrated as a single interconnect 804 extending along one sidewall, abutting, as with alignment marks 802, an interlayer dielectric of the patterned layer 304, a silicon-based body or other hard mask 312, a first etch stop layer 302 (e.g., an aluminum oxide layer), and a low-k dielectric layer 212. However, the interconnect structure may be formed according to multiple metallization layers, including conductive lines interconnected by other via structures or other interlayer via structures. For example, the via structure 214 vertically extending through the first region 206 is illustrated in the cut plane as not having interconnects 804. This illustration may correspond to interconnects 804 provided on another plane, or for at least some portions of the circuitry in the second region 208, the lack of interconnects 804 extending through the interlayer dielectric of the patterned layer 304.

[0035] Additional layers may be stacked over the upper surface of the illustrated semiconductor device 200 (e.g., the back side of the substrate 202). For example, alternating dielectric layers 806 and active layers 808 may be stacked over each other. Figure 2-7 Similar to the interlayer dielectric provided in the exemplary example of the low-k dielectric 212, dielectric layer 806 may include various dielectrics, including silicon dioxide or low-k dielectrics (e.g., very low-k dielectrics). The active layer 808 may include additional substrates, such as in the case of die or wafer bonding, or thin-film based layers, such as those used to provide additional memory cells or logic functions to couple with an active surface of the first substrate 202. For example, a thin-film based layer may be applied over a surface (e.g., a back side) of the substrate 202 to form a stacked memory device. The substrate or thin-film based layer may include a patterning layer 304, an etch stop layer, or a hard mask 312 such that openings for alignment marks 802 formed in the stacked layers can be configured according to the requirements of the alignment marks 802 formed in the stacked layers. Figure 2-7 The second opening 316 is formed using a similar technique.

[0036] Alignment marks 802 may be formed above each other in a uniform, lateral arrangement, as illustrated with respect to the two uppermost active layers 808, or may be staggered or otherwise offset, as illustrated with respect to the three lowermost layers of alignment marks 802. Alignment marks 802 may comprise various materials from a marking layer configured to be detectable by contrast with another part of the semiconductor device. Accordingly, alignment marks 802 may exhibit a discernible contrast under optical inspection (in the visible or IR spectrum) by a scanning electron beam or otherwise. For example, alignment marks 802 may comprise high-Z metals such as tungsten or molybdenum, and may also provide a contrast against antireflective coatings, mask layers, dielectric stacks, or other metals in extreme ultraviolet (EUV) processes. Alignment marks 802 may comprise titanium nitride, tungsten, or etched silicon nitride to provide a contrast against various dielectric layers in a chemical mechanical polishing (CMP / G) process. Various other materials can be conceived, which can be conceived in accordance with other procedures, or in accordance with the alignment mark 802 to compare with a base layer.

[0037] The upper surface of the alignment mark can be set to be relatively flat by a CMP / G or other program used to level the upper surface. This is based on an isotropic program for etching the opening according to operation 112, or according to... Figure 6 The remaining portion of the illustrated antireflective coating 502 exhibits a shadow effect, and the lower surface of the alignment mark may display significant irregularities. However, the thickness of the alignment mark 802 (e.g., an average, maximum, or minimum total thickness) exceeds approximately 800 angstroms, which may exceed the thickness achieved according to other schemes. This dimension improves the detectability of the alignment mark and enhances stack alignment based on the adjusted positioning for improved detection accuracy.

[0038] In one embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming a first etch stop layer over a substrate. The method includes forming an interlayer dielectric over the first etch stop layer. The method includes patterning the interlayer dielectric to form a first opening and a second opening. The method includes forming a second etch stop layer over the patterned interlayer dielectric. The method includes forming an anti-reflective layer over the first etch stop layer, the anti-reflective layer having a first thickness over the first opening and a second thickness greater than the first thickness over the second opening. The method includes etching the anti-reflective layer to expose a bottom surface of the second opening, without exposing a bottom surface of the first opening, and without masking the first opening.

[0039] In another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes providing a substrate comprising a plurality of memory cells. The method includes forming a first alumina layer over the substrate. The method includes forming a patterned layer over the first alumina layer, the patterned layer including a plurality of first openings spaced apart over the memory cells and a plurality of second openings laterally spaced apart from the plurality of first openings. The method includes forming a second alumina layer over the patterned layer. The method includes forming an anti-reflective layer over the second alumina layer, the anti-reflective layer having a first thickness over the plurality of first openings and a second thickness greater than the first thickness over the plurality of second openings. The method includes etching the anti-reflective layer in the plurality of second openings to expose at least one of the alumina layers.

[0040] As will be understood from the foregoing discussion, this invention can be embodied in various forms, including but not limited to the following:

[0041] Example 1. A method of manufacturing a semiconductor device, comprising: forming a first etch stop layer over a substrate; forming an interlayer dielectric over the first etch stop layer; patterning the interlayer dielectric to form a patterned layer including a first opening and a second opening; forming a second etch stop layer over the patterned layer; forming an antireflective layer over the second etch stop layer, the antireflective layer having a first thickness over the first opening and a second thickness less than the first thickness over the second opening; and etching the antireflective layer to expose a bottom surface of the second opening, the antireflective layer covering the bottom surface of the first opening.

[0042] Example 2. The method of Example 1, wherein forming the antireflective layer comprises: forming the antireflective layer having a third thickness that is less than the first thickness and greater than the second thickness above an upper surface of the patterned layer.

[0043] Example 3. The method of Example 1, wherein an etched anti-reflective layer covers an upper surface of the patterned layer that abuts the first opening.

[0044] Example 4. The method of Example 1, wherein etching the anti-reflective layer involves removing the anti-reflective layer from a bottom surface of the second opening and leaving the anti-reflective layer on at least a portion of the sidewall of the second opening.

[0045] Example 5. The method of Example 4 further includes: removing, according to an isotropic procedure, the remaining portion of the antireflective layer from the sidewall of the second opening; a silicon-based layer under the first etch stop layer and the second etch stop layer; and a low-k dielectric layer under the silicon-based layer.

[0046] Example 6. The method of Example 1 further includes: forming a plurality of layers of a memory device above the first opening.

[0047] Example 7. The method of Example 1 further includes: removing the antireflective layer from the first opening using a plasma stripping process; and removing the first etch stop layer and the second etch stop layer from a lower surface of the first opening.

[0048] Example 8. A method of manufacturing a semiconductor device, comprising: providing a substrate comprising a plurality of memory cells; forming a first capping layer over the substrate; forming a patterned layer over the first capping layer, the patterned layer comprising a plurality of first openings spaced apart over the plurality of memory cells and a plurality of second openings laterally spaced apart from the plurality of first openings; forming a second capping layer over the patterned layer; forming an antireflective layer over the second capping layer, the antireflective layer having a first thickness over the plurality of first openings and a second thickness greater than the first thickness over the plurality of second openings; and etching the antireflective layer in the plurality of second openings to expose at least one of the capping layers.

[0049] Example 9. The method of Example 8, wherein the plurality of second openings have a larger lateral dimension than the plurality of first openings.

[0050] Example 10. The method of Example 9, wherein the antireflective layer is an organic back-side antireflective coating (oBARC) formed according to a spin coating process to form the second thickness to be greater than the first thickness.

[0051] Example 11. The method of Example 8, wherein the first capping layer is an aluminum oxide layer that is thicker than the aluminum oxide layer of the second capping layer.

[0052] Example 12. The method of Example 8, wherein the anti-reflective layer etched in the plurality of second openings is left in the plurality of first openings.

[0053] Example 13. The method of Example 8, wherein the anti-reflective layer etched in the plurality of second openings is left on an upper surface of the patterned layer.

[0054] Example 14. The method of Example 13, wherein the antireflective layer is further etched through a low-k dielectric layer.

[0055] Example 15. The method of Example 8 further includes: forming a via structure in the plurality of first openings to interconnect the plurality of memory cells with a plurality of second memory cells of a second layer of the semiconductor device; and forming a marker layer in the plurality of second openings.

[0056] Example 16. The method of Example 15, wherein the via structure is a back-side via structure of the semiconductor device.

[0057] Example 17. The method of Example 15, wherein the marking layer has a thickness of more than 800 angstroms.

[0058] Example 18. The method of Example 8 further includes: after etching the antireflective layer in the plurality of second openings, removing the antireflective layer, the first cap layer and the second cap layer from the patterned layer.

[0059] Example 19. A semiconductor device comprising: a plurality of memory cells; and an alignment mark laterally offset from the plurality of memory cells, wherein the alignment mark has a thickness of more than about 800 angstroms and abuts along a sidewall: an interlayer dielectric; a silicon-based body; a first etch stop layer; and a low-k dielectric layer that perpendicularly spaces the memory cells apart from each other.

[0060] Example 20. A semiconductor device as described in Example 19, wherein the sidewall extends laterally beneath the silicon-based layer.

[0061] In another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device includes a plurality of memory cells (e.g., stacked memory cells). The semiconductor device includes an alignment mark laterally offset from the plurality of memory cells. The alignment mark abuts along a sidewall an interlayer dielectric, a silicon-based layer, a first aluminum oxide layer, and a low-k dielectric layer that spaces the stacked memory cells apart from each other. The memory cells can be stacked according to the alignment mark.

[0062] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the main semiconductor device. Based on a particular technology node, the term “about” may indicate a value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0063] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes: A first etch stop layer is formed above the substrate; An interlayer dielectric is formed above the first etch stop layer; The interlayer dielectric is patterned to form a patterned layer including a first opening and a second opening; A second etch stop layer is formed above the patterned layer; An anti-reflective layer is formed above the second etch stop layer, the anti-reflective layer having a first thickness above the first opening and a second thickness less than the first thickness above the second opening; and The anti-reflective layer is etched to expose the bottom surface of the second opening, which covers the bottom surface of the first opening.

2. The method according to claim 1, characterized in that, The formation of this anti-reflective layer includes: An anti-reflective layer with a third thickness that is less than the first thickness and greater than the second thickness is formed above the upper surface of the patterned layer.

3. The method according to claim 1, characterized in that, The etched anti-reflective layer covers the upper surface of the patterned layer that abuts the first opening.

4. The method according to claim 1, characterized in that, Etching the anti-reflective layer involves removing the anti-reflective layer from the bottom surface of the second opening and leaving the anti-reflective layer on at least a portion of the sidewall of the second opening.

5. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes: Provides a substrate containing multiple memory cells; A first capping layer is formed on top of the substrate; A patterned layer is formed above the first cap layer, the patterned layer including a plurality of first openings spaced apart above the plurality of memory cells and a plurality of second openings laterally spaced apart from the plurality of first openings; A second capping layer is formed above the patterned layer; An anti-reflective layer is formed above the second cap layer, the anti-reflective layer having a first thickness above the plurality of first openings and a second thickness greater than the first thickness above the plurality of second openings; as well as The anti-reflective layer is etched into the plurality of second openings to expose at least one of the first cap layer and the second cap layer.

6. The method according to claim 5, characterized in that, The plurality of second openings have a larger lateral dimension than the plurality of first openings.

7. The method according to claim 5, characterized in that, The first capping layer is an aluminum oxide layer that is thicker than the aluminum oxide layer of the second capping layer.

8. The method according to claim 5, characterized in that, It further includes: Through-hole structures are formed in the plurality of first openings to interconnect the plurality of memory cells with a plurality of second memory cells in the second layer of the semiconductor device; and A marking layer is formed in the plurality of second openings.

9. A semiconductor device, characterized in that, The semiconductor device includes: Multiple memory cells; and Alignment marks are provided to the memory cells, the alignment marks being laterally offset from the plurality of memory cells, wherein the alignment marks have a thickness of more than 800 angstroms and abut along the sidewalls; Interlayer dielectric is formed in the memory cell; Silicon-based layers are formed in the interlayer dielectric; The first etch stop layer is formed in the silicon-based layer; as well as A low-k dielectric layer is formed on the silicon-based layer, which perpendicularly spaces the memory cells apart from each other.

10. The semiconductor device according to claim 9, characterized in that, The sidewall extends laterally beneath the silicon-based layer.

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