Semiconductor device and method of forming the same

Abstract

This application provides a semiconductor device and a method for forming the same. The method includes: forming a plurality of chip structures, each chip structure including a chip and a temporary planarization layer; the chip including a chip bonding surface and a chip back side, the temporary planarization layer being located on the chip back side; providing a second wafer, the second wafer including a second wafer bonding surface; and bonding the chip bonding surfaces of the plurality of chip structures to the second wafer bonding surface of the second wafer. During the bonding process between the chip structures and the second wafer, the temporary planarization layer provides temporary rigid support for the chip, thereby achieving a planarization effect and improving the problem of misaligned bonding caused by chip warpage and other deformation issues during the bonding process with the second wafer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] Chip-wafer stacking technology is favored by global semiconductor giants because it is not limited by chip size matching. Currently, in order to package a larger number of chips during the packaging process, the chips need to be thinned before being bonded to the wafer. However, when bonding the thinned chips to the wafer, the thinned chips are prone to warping, resulting in misalignment bonding problems. Summary of the Invention

[0003] This application provides a semiconductor device and a method for forming the same, which improves the problem of misaligned bonding caused by chip warping during the chip-wafer bonding process.

[0004] In a first aspect, embodiments of this application provide a method for forming a semiconductor device, comprising:

[0005] Multiple chip structures are formed, each chip structure including a chip and a temporary planarization layer, the chip including opposing chip bonding surfaces and a chip back surface, and the temporary planarization layer being located on the chip back surface;

[0006] A second wafer is provided, the second wafer including a second wafer bonding surface;

[0007] The chip bonding surfaces of the plurality of chip structures are bonded to the second wafer bonding surface of the second wafer.

[0008] Secondly, embodiments of this application also provide a semiconductor device, which is prepared by the above-described semiconductor device formation method.

[0009] In the semiconductor device and its formation method according to embodiments of this application, the chip structure includes a chip and a temporary planarization layer located on the back side of the chip. During the bonding process between the chip structure and the second wafer, the temporary planarization layer provides temporary mechanical support for the chip to play a planarization role, thereby reducing the risk of misaligned bonding caused by chip warpage and other deformation problems during the bonding process with the second wafer. Attached Figure Description

[0010] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor device according to an embodiment of this application;

[0011] Figures 2 to 13 A schematic diagram of the formation process of a semiconductor device provided in an embodiment of this application;

[0012] Figure 14This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0013] The attached figures are labeled as follows:

[0014] 10. Temporary bonding structure; 11. Chip structure;

[0015] 12. First wafer; 12A. Bonding surface of the first wafer; 12B. Back side of the first wafer;

[0016] 121. First substrate; 122. First bonding layer; 1221. First bonding insulating layer; 1222. First bonding metal layer; 123. Chip; 123A. Chip bonding surface; 123B. Chip back side;

[0017] 13. First initial dielectric layer; 131. First dielectric layer;

[0018] 14. Initial inorganic peeling layer; 141. Inorganic peeling layer;

[0019] 15. Second initial dielectric layer; 151. Second dielectric layer;

[0020] 16. Initial temporary leveling layer; 161. Temporary leveling layer;

[0021] 171. First cutting groove; 172. Second cutting groove;

[0022] 18. Temporary bonding adhesive;

[0023] 191. First substrate; 192. Support membrane; 193. Fixing structure;

[0024] 21. Second wafer; 21A. Bonding surface of the second wafer; 21B. Back side of the second wafer; 211. Second substrate; 212. Second bonding layer; 2121. Second bonding insulating layer; 2122. Second bonding metal layer;

[0025] 303, Second substrate; 304, Adhesive layer;

[0026] 40. Initial filling medium; 401. Filling medium; 40A. First planarization surface;

[0027] 50. Protective layer;

[0028] L, laser. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0030] Chip-wafer stacking technology is favored by global semiconductor giants because it is not limited by chip size matching. However, thinned chips have weaker stress resistance, which makes them prone to cracking during the bonding process with the wafer, as well as bonding misalignment due to excessive deformation of the thinned chip.

[0031] To address the problem of bonding deviations that can easily occur during the bonding process between thinned chips and wafers due to excessive deformation of the thinned chips, this application provides a method for forming a semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor device according to an embodiment of this application. The method for forming a semiconductor device includes:

[0032] Step S101: Form multiple chip structures, each chip structure including a chip and a temporary planarization layer. The chip includes a chip bonding surface and a chip back surface, and the temporary planarization layer is located on the chip back surface.

[0033] Step S102: Provide a second wafer, the second wafer including a second wafer bonding surface;

[0034] Step S103: Bond the chip bonding surfaces of the multiple chip structures to the second wafer bonding surfaces of the second wafer.

[0035] In some embodiments of this application, the chip structure includes a chip and a temporary planarization layer located on the back of the chip. During the bonding process between the chip structure and the second wafer, the temporary planarization layer provides temporary rigid support for the chip, thereby flattening the chip and reducing the risk of misalignment bonding due to chip warpage or other deformation issues during bonding with the second wafer. Furthermore, during chip transfer, the temporary planarization layer also thickens the chip, mitigating the problem of cracks caused by uneven density distribution during chip pick-up.

[0036] It should be noted that the temporary planarization layer is effective both before and during the bonding process between the chip and the second wafer. The temporary planarization layer can be removed after permanent bonding is achieved between the chip and the second wafer.

[0037] The following combination Figures 2 to 13 The formation process of the semiconductor device according to the embodiments of this application will be described in detail.

[0038] See Figures 2 to 6 As shown, perform the above step S101.

[0039] In some embodiments, see Figure 2 As shown, the formation of multiple chip structures 11 includes:

[0040] Step S1011: Provide the first wafer 12 and the first carrier 191;

[0041] Step S1012: Temporarily bond the first wafer bonding surface 12A to the first carrier 191;

[0042] Step S1013: Thin the back side 12B of the first wafer to obtain a temporary bonding structure 10.

[0043] After the first wafer 12 is temporarily bonded to the first carrier 191, the back side 12B of the first wafer is thinned to obtain the thinned first wafer 12, which facilitates the obtaining of the thinner chip 123 described below.

[0044] In some embodiments, see Figure 2 As shown, in step S1011, the first wafer 12 includes a first substrate 121 and a first bonding layer 122, with the first bonding layer 122 located on the first substrate 121. The surface of the first bonding layer 122 facing away from the first substrate 121 is the first wafer bonding surface 12A of the first wafer 12. The surface of the first substrate 121 facing away from the first bonding layer 122 is the first wafer back surface 12B of the first wafer 12. The first wafer back surface 12B is opposite to the first wafer bonding surface 12A. The first substrate 121 includes a first substrate and a device layer (not shown in the figure). The device layer is located on the first substrate, and the first bonding layer 122 is located on the side of the device layer facing away from the first substrate. The device layer includes device structures, such as memory devices, MOS transistors, image sensors, etc. The first bonding layer 122 includes a first bonding insulating layer 1221 and a first bonding metal layer 1222, with the first bonding metal layer 1222 embedded in the first bonding insulating layer 1221.

[0045] In some embodiments, in step S1011, the first carrier 191 may include at least one of a metal carrier, a semiconductor carrier, a glass carrier, and an organic carrier. Exemplarily, the first carrier 191 is a wafer carrier.

[0046] In some embodiments, see Figure 2 As shown, in step S1012, temporarily bonding the first wafer bonding surface 12A to the first carrier 191 includes: using temporary bonding adhesive 18 to temporarily bond the first wafer bonding surface 12A to the first carrier 191. The temporary bonding adhesive 18 can be made of conventional materials, which will not be described in detail here.

[0047] In some embodiments, in step S1013, the back surface 12B of the first wafer may be thinned using processes such as grinding. The thickness of the first wafer 12 before thinning may be 600 micrometers to 800 micrometers. The thickness of the first wafer 12 after thinning may be 5 micrometers to 200 micrometers, 10 micrometers to 100 micrometers, 5 micrometers to 80 micrometers, or 2 micrometers to 18 micrometers. For example, the thickness of the first wafer 12 after thinning is 5 micrometers to 80 micrometers.

[0048] In some embodiments, see Figure 3 As shown, after forming the temporary bonding structure 10, multiple chip structures 11 are formed, and the process also includes step S1014, which involves forming a first initial dielectric layer 13 on the side of the back surface 12B of the first wafer that is away from the first carrier 191.

[0049] The first initial dielectric layer 13 not only protects the back side 12B of the first wafer after thinning, but the design of the first initial dielectric layer 13 also helps to increase the process window for subsequent planarization.

[0050] In some embodiments, the thickness of the first initial dielectric layer 13 can be 1000 angstroms to 3000 angstroms, which reduces the manufacturing difficulty of the first initial dielectric layer 13 while ensuring an increased process window for subsequent planarization processing.

[0051] In some embodiments, the first initial dielectric layer 13 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first initial dielectric layer 13 may be a single layer or multiple layers. Exemplarily, the first initial dielectric layer 13 includes silicon oxide.

[0052] In some embodiments, continue reading Figure 3 As shown, after the first initial dielectric layer 13 is formed, a plurality of chip structures 11 are formed, and the process also includes step S1015, namely forming an initial inorganic release layer 14 on the side of the back surface 12B of the first wafer that is away from the first carrier 191.

[0053] The initial inorganic release layer 14 not only has peelability but also high temperature resistance. Compared to organic release layers such as organic temporary bonding adhesives, the initial inorganic release layer 14 is more suitable for high-temperature process environments. In this embodiment, by adding the initial inorganic release layer 14, the initial inorganic release layer 14 is cut to obtain the inorganic release layer 141 (hereinafter referred to as the inorganic release layer), so that the temporary smoothing layer 161 (hereinafter referred to as the temporary smoothing layer) can be removed by peeling off the inorganic release layer 141.

[0054] In one exemplary embodiment, an initial inorganic release layer 14 is formed on the side of the back surface 12B of the first wafer opposite to the first substrate 191, including forming the initial inorganic release layer 14 on the surface of the first initial dielectric layer 13 opposite to the first wafer 12. Thus, when the inorganic release layer 141 cut from the initial inorganic release layer 14 is peeled off, the first dielectric layer 131 cut from the first initial dielectric layer 13 (hereinafter referred to as the first dielectric layer 13) remains on the chip, facilitating a larger process window for planarization.

[0055] In another exemplary embodiment, an initial inorganic release layer 14 is formed on the side of the back surface 12B of the first wafer that is opposite to the first substrate 191, including: forming the initial inorganic release layer 14 on the back surface 12B of the first wafer, wherein the initial inorganic release layer 14 is in direct contact with the back surface 12B of the first wafer.

[0056] In some embodiments, the thickness of the initial inorganic release layer 14 can be 100 angstroms to 3000 angstroms, so as to reduce the manufacturing difficulty of the initial inorganic release layer 14 and the peeling difficulty of the inorganic release layer 141 obtained by cutting the initial inorganic release layer 14.

[0057] In some embodiments, the material of the initial inorganic release layer 14 may include, but is not limited to, the inorganic release material of Nano Cleave, which can be released by infrared laser irradiation.

[0058] In some embodiments, see Figure 3 As shown, after the initial inorganic release layer 14 is formed, a plurality of chip structures 11 are formed, and the process also includes step S1016, forming a second initial dielectric layer 15 on the side of the initial inorganic release layer 14 opposite to the first substrate 191.

[0059] The second initial dielectric layer 15 serves to connect the initial inorganic stripping layer 14 with the initial temporary planarization layer 16 (hereinafter referred to as the initial temporary planarization layer 16), so as to securely fix the initial temporary planarization layer 16 to the back surface 12B of the first wafer.

[0060] In some embodiments, the thickness of the second initial dielectric layer 15 is 100 angstroms to 3000 angstroms, which reduces the manufacturing difficulty of the second initial dielectric layer 15 while ensuring the connection effect of the second initial dielectric layer 15.

[0061] In some embodiments, the second initial dielectric layer 15 may include an inorganic insulating material, including but not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second initial dielectric layer 15 may be a single layer or multiple layers. Exemplarily, the second initial dielectric layer 15 includes silicon oxide.

[0062] In some embodiments, see Figure 4As shown, after forming the initial inorganic release layer 14, multiple chip structures 11 are formed. The process also includes step S1017, where an initial temporary planarization layer 16 is formed on the back side 12B of the first wafer. The initial temporary planarization layer 16 is located on the side of the initial inorganic release layer 14 opposite to the first wafer 12. Thus, the initial temporary planarization layer 16 provides temporary rigid support for the thinned first wafer 12, thereby flattening the thinned first wafer 12 and reducing the risk of warping and breakage during processing.

[0063] In one exemplary embodiment, forming an initial temporary planarization layer 16 on the back side 12B of the first wafer includes forming the initial temporary planarization layer 16 on the surface of the second initial dielectric layer 15 facing away from the first wafer 12. Since the second initial dielectric layer 15 has good adhesion to both the initial temporary planarization layer 16 and the initial inorganic release layer 14, the firmness of the initial temporary planarization layer 16 fixed to the back side of the first wafer is improved. The initial temporary planarization layer 16 can be formed on the surface of the second initial dielectric layer 15 facing away from the first wafer 12 using bonding processes such as fusion bonding.

[0064] In another exemplary embodiment, forming an initial temporary planarization layer 16 on the back side 12B of the first wafer includes forming an initial temporary planarization layer 16 on the surface of the initial inorganic release layer 14 opposite to the first wafer 12, wherein the initial temporary planarization layer 16 is in direct contact with the initial inorganic release layer 14.

[0065] In some embodiments, the thickness of the initial temporary planarization layer 16 may be the same as the thickness of the first wafer 191. In some embodiments, the thickness of the initial temporary planarization layer 16 is greater than the thickness of the first initial dielectric layer 13, the initial inorganic release layer 14, and the second initial dielectric layer 15, to ensure the planarization effect of the initial temporary planarization layer 16 on the thinned first wafer 12 and reduce the risk of warping of the first wafer 12.

[0066] In some embodiments, the initial temporary planarization layer 16 may be a rigid substrate that provides sufficient rigid support for the thinned first wafer 12. The rigid substrate includes at least one of a metal substrate, a semiconductor substrate, a glass substrate, and a rigid organic substrate. Exemplarily, the initial temporary planarization layer 16 is a wafer substrate.

[0067] In some embodiments, forming a plurality of chip structures 11 further includes thinning the surface of the initial temporary planarization layer 16 away from the first wafer 12. This ensures the planarization effect of the initial temporary planarization layer 16 while reducing the thickness of the chip structures 11.

[0068] In some embodiments, see Figure 5As shown, multiple chip structures 11 are formed, and the process also includes step S1018, which involves fixing the surface of the initial temporary planarization layer 16 away from the first wafer 12 onto the first support film 192.

[0069] The first support film 192 serves to support and fix the initial temporary planarization layer 16. The first support film 192 is also fixed by the fixing structure 193 to facilitate the cutting of the first wafer 12, the initial temporary planarization layer 16, and other structures. The first support film 192 may include support tape.

[0070] In some embodiments, see Figure 5 and Figure 6 As shown, after the initial temporary planarization layer 16 is formed, multiple chip structures 11 are formed, including:

[0071] Step S1019, namely, removing the first carrier 191 and cutting the first wafer 12 and the initial temporary planarization layer 16 to obtain the chip 123 and the temporary planarization layer 161 of the chip structure 11. The chip 123 includes a chip bonding surface 123A and a chip back surface 123B, and the temporary planarization layer 161 is located on the chip back surface 123B.

[0072] In some embodiments, removing the first carrier 191 includes debonding the first carrier 191 to the first wafer bonding surface 12A. The debonding process can be achieved by laser treatment of the temporary bonding adhesive 18.

[0073] In some embodiments, see Figure 5 As shown, multiple first dicing grooves 171 can be formed using at least one process, namely laser cutting and etching. The multiple first dicing grooves 171 extend from the back surface 12B of the first wafer to the bonding surface 12A of the first wafer, thereby cutting the first wafer 12 into multiple chips 123. The chip bonding surface 123A is obtained by cutting the first wafer bonding surface 12A. The back surface 123B of the chips is obtained by cutting the back surface 12B of the first wafer.

[0074] In one exemplary embodiment, the first bonding layer 122 of the first wafer 12 is cut using a laser cutting process, and the first substrate 121 of the first wafer 12 is cut using an etching process to form a first dicing groove 171.

[0075] In some embodiments, see Figure 6 As shown, after removing the first carrier 191, multiple chip structures 11 are formed, including:

[0076] The initial inorganic stripping layer 14 is cut to obtain multiple inorganic stripping layers 141 of chip structures 11. The inorganic stripping layer 141 is located between the temporary flattening layer 161 and the back surface of the chip 123B.

[0077] In some embodiments, continue reading Figure 6 As shown, after removing the first carrier 191, multiple chip structures 11 are formed, including:

[0078] The first initial dielectric layer 13 is cut to obtain a first dielectric layer 131 of multiple chip structures 11. The first dielectric layer 131 is located between the inorganic stripping layer 141 and the back surface of the chip 123B.

[0079] In some embodiments, see again Figure 6 As shown, after removing the first carrier 191, multiple chip structures 11 are formed, including:

[0080] The second initial dielectric layer 15 is cut to obtain a second dielectric layer 151 of multiple chip structures 11. The second dielectric layer 151 is located between the temporary planarization layer 161 and the inorganic stripping layer 141.

[0081] In some embodiments, see Figure 6 As shown, after forming multiple first cutting grooves 171, multiple second cutting grooves 172 are formed using at least one process selected from laser cutting and etching. The multiple second cutting grooves 172 are respectively connected to the multiple first cutting grooves 171. Each second cutting groove 172 penetrates the first initial dielectric layer 13, the initial inorganic stripping layer 14, the second initial dielectric layer 15, and the initial temporary planarization layer 16.

[0082] In one exemplary example, after sequentially cutting the first initial dielectric layer 13, the initial inorganic stripping layer 14, and the second initial dielectric layer 15 using at least one of laser cutting and etching processes, the initial temporary planarization layer 16 is then cut using an etching process to form a second cutting groove 172, resulting in a plurality of chip structures 11.

[0083] The chip structure 11 prepared by the above method includes a chip 123, a first dielectric layer 131, an inorganic release layer 141, a second dielectric layer 151, and a temporary planarization layer 161. The temporary planarization layer 161 temporarily planarizes the chip 123, reducing the risk of warping. The inorganic release layer 141 is located between the temporary planarization layer 161 and the back surface of the chip 123B, facilitating the removal of the temporary planarization layer 161 from the back surface of the chip 123B. After the inorganic release layer 141 is removed, the first dielectric layer 131 remains on the back surface of the chip 123B, increasing the process window for subsequent planarization processing. The second dielectric layer 151 connects the inorganic release layer 141 and the temporary planarization layer 161. Furthermore, the first dielectric layer 131, the inorganic release layer 141, the second dielectric layer 151, and the temporary planarization layer 161 all thicken the thinned chip 123, reducing the risk of cracks in the chip 123 due to uneven density distribution during pick-up.

[0084] See Figure 7 As shown, perform step S102 as described above.

[0085] In some embodiments, the second wafer 21 includes a second substrate 211 and a second bonding layer 212. The second bonding layer 212 is located on the second substrate 211. The surface of the second bonding layer 212 facing away from the second substrate 211 is the second wafer bonding surface 21A of the second wafer 21. The surface of the second substrate 211 facing away from the second bonding layer 212 is the second wafer back surface 21B of the second wafer 21, which is opposite to the second wafer bonding surface 21A. The second substrate 211 may include a second substrate and a device layer (not shown in the figure). The device layer is located on the second substrate, and the second bonding layer 212 is located on the side of the device layer facing away from the second substrate. The device layer includes device structures, such as memory devices, MOSFETs, image sensors, etc. The second bonding layer 212 includes a second bonding insulating layer 2121 and a second bonding metal layer 2122, with the second bonding metal layer 2122 embedded in the second bonding insulating layer 2121.

[0086] In some embodiments, the function of the second wafer 21 may differ from that of the first wafer 12. For example, the second wafer 21 and the first wafer 12 may be a logic wafer and a memory wafer, respectively. In some embodiments, the function of the second wafer 21 may also be the same as that of the first wafer 12. For example, both may be memory wafers.

[0087] Continue reading Figure 7 As shown, perform step S103 as described above.

[0088] In some embodiments, permanent bonding processes such as hybrid bonding can be used to bond the chip bonding surfaces 123A of multiple chip structures 11 to the second wafer bonding surface 21A of the second wafer 21 to obtain a permanent bonding structure.

[0089] In some embodiments, the chips 123 in the plurality of chip structures 11 may have the same function, for example, all of them may be memory chips. In other embodiments, the chips 123 in the plurality of chip structures 11 may have different functions from each other, for example, including memory chips and logic chips. Each of the plurality of chip structures 11 can be fabricated by the above-described chip structure 11 fabrication process.

[0090] It should be noted that after the chip structure 11 is fabricated, it needs to be picked up to achieve permanent bonding. During the picking up of the chip structure 11, the temporary planarization layer 161 provides temporary rigid support and thickens the chip 123, reducing the risk of cracks in the chip 123 due to its thinness and uneven density distribution. Furthermore, during the bonding process between each chip structure 11 and the second wafer 21, the temporary planarization layer 161 provides temporary rigid support for the chip 123, ensuring its planarization and preventing poor bonding accuracy and issues such as misalignment and bubbles caused by chip warpage or deformation during bonding with the second wafer 21.

[0091] It should also be noted that since the temporary planarization layer 161 provides temporary rigid support for the chip 123 during both the pick-up and bonding processes, the thickness of the chip 123 can be very thin. In other words, the thickness of the first wafer 12 can be reduced to a very small amount, for example, less than 20 micrometers.

[0092] In some embodiments, see Figures 7 to 9 As shown, after step S103, the method further includes:

[0093] Step S104: The multiple inorganic stripping layers 141 are peeled off from the multiple chips 123 to remove the temporary planarization layer 161 of the multiple chip structures 11.

[0094] After permanent bonding is completed between the multiple chips 123 and the second wafer 21 in step S104, the thickness of the permanent bonding structure is reduced by peeling off the inorganic release layer 141 to remove the temporary planarization layer 161 and the second dielectric layer 151.

[0095] In some embodiments, see Figure 7 and Figure 8 As shown, the process of peeling multiple inorganic stripping layers 141 from multiple chips 123 includes: irradiating the inorganic stripping layers 141 of the multiple chip structures 11 with a laser L.

[0096] After the inorganic release layer 141 is irradiated by laser, the inorganic release layer 141 loses its adhesive properties, which facilitates the separation between the inorganic release layer 141 and the chip 123.

[0097] for Figure 7 In the structure shown, after the inorganic release layer 141 loses its adhesive properties, a peeling force is applied to the temporary flattening layer 161 of the multiple chip structures 11 using tape or the like, so as to peel the inorganic release layer 141 of the multiple chip structures 11 from the first dielectric layer 131, with the remaining first dielectric layer 131 located on the back side 123B of the chip.

[0098] In one exemplary embodiment, a laser is used to irradiate the inorganic release layer 141 of a plurality of chip structures 11 from the side of the temporary planarization layer 161 facing away from the chip 123. Where the initial inorganic release layer 14 comprises an inorganic release material of Nano Cleave, the laser can be an infrared laser, which can penetrate the temporary planarization layer 161, etc.

[0099] In some embodiments, the wavelength of the infrared laser can be 760 nm to 1 mm.

[0100] In some embodiments, see Figure 8 As shown, removing the inorganic peeling layer 141 of multiple chip structures 11 also includes: fixing the temporary planarization layer 161 of multiple chip structures 11 onto the second carrier 303, and applying a peeling force to the second carrier 303.

[0101] When the inorganic release layer 141 loses its adhesive properties by irradiating it with a laser, a second carrier 303 is also used to simultaneously apply the release to the temporary planarization layer 161 of multiple chip structures 11, so as to simultaneously remove multiple inorganic release layers 141 and simplify the release process of multiple inorganic release layers 141.

[0102] In some embodiments, the second carrier 303 may include at least one of a metal carrier, a semiconductor carrier, a glass carrier, and an organic carrier. Exemplarily, the second carrier 303 is a wafer carrier.

[0103] In some embodiments, continue reading Figure 8 As shown, multiple temporary flattening layers 161 can be fixed to the second carrier 303 using an adhesive layer 304.

[0104] In some embodiments, see Figure 10 As shown, after step S104, the forming method further includes: forming a protective layer 50, which covers the side surface of the chip, located between the back surface 123B and the bonding surface 123A of the chip. By forming the protective layer 50 on the side surface of the chip, the chip side surface of the chip 123 is protected.

[0105] In some embodiments, the protective layer 50 includes an inorganic insulating material. The inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0106] In some embodiments, see Figures 11 to 13 As shown, after step S104, the forming method further includes:

[0107] Step S105: An initial filling medium 40 is formed. The initial filling medium 40 fills the space between adjacent chips 123 and covers the first dielectric layer 131. The material of the initial filling medium 40 is the same as the material of the first dielectric layer 131.

[0108] Step S106: Planarize the initial filling medium 40 to obtain filling medium 401, which is located between adjacent chips 123.

[0109] During the formation of the initial filling medium 40, the initial filling medium 40 can serve to fix the chip 123. When the initial filling medium 40 and the first dielectric layer 131 are planarized, the material of the initial filling medium 40 is the same as the material of the first dielectric layer 131, which not only expands the process window of the planarization process, but also improves process compatibility.

[0110] It should be noted that if the first dielectric layer 131 is not provided on the back side 123B of the chip, the planarization process may simultaneously process both the initial filling medium 40 and the semiconductor substrate of the chip 123. Since the initial filling medium 40 and the semiconductor substrate are made of different materials, an uneven planarization surface is easily formed during the planarization process. For example, when chemical mechanical polishing is used to process both the initial filling medium 40 and the semiconductor substrate simultaneously, the selectivity of the polishing slurry for the initial filling medium 40 and the semiconductor substrate differs, easily resulting in an uneven planarization surface.

[0111] It should also be noted that the design of the temporary planarization layer 161 combined with the inorganic release layer 141 allows for a thinner chip 123, resulting in a smaller height difference between the back side 123B of the chip and the second wafer 21. This reduces the risk of stress causing cracks on the sidewalls of the chip 123 during the initial filling process 40.

[0112] In some embodiments, see Figure 11 As shown, in step S105, an initial filling medium 40 can be formed using a thin film deposition process. The thin film deposition process may include at least one of physical vapor deposition, chemical vapor deposition, solution deposition, and atomic layer deposition.

[0113] In some embodiments, the initial filling medium 40 may include an inorganic insulating material. The inorganic insulating material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Exemplarily, the initial filling medium 40 includes silicon oxide.

[0114] In some embodiments, see Figure 11 As shown, the thickness D1 of the initial filling medium 40 located between chips 123 is greater than the thickness D2 of chips 123 in order to improve the planarization effect.

[0115] In some embodiments, see Figure 12 As shown, the initial filling medium 40 is planarized, including:

[0116] The initial filling medium 40 is subjected to a first planarization process, and the remaining initial filling medium 40 on the surface away from the second wafer 21 forms a first planarization surface 40A. At least a portion of the first planarization surface 40A is located on the side of the first dielectric layer 131 away from the first chip 123.

[0117] At least a portion of the first planarization surface 40A is located on the side of the first dielectric layer 131 away from the first chip 123, so as to leave a portion of the initial filling dielectric 40 above the chip 123, which facilitates the repair of damage caused by the first planarization process through subsequent planarization processes and reduces the impact on the performance of the semiconductor device.

[0118] In some embodiments, the distance D3 between at least a portion of the first planarized surface 40A and the first dielectric layer 131 is 2 to 3 micrometers, so as to leave an initial filling medium 40 of sufficient thickness to facilitate subsequent repair while shortening the time required for subsequent repair.

[0119] In some embodiments, the first planarization process includes at least one of grinding and etching processes, i.e., the first planarization process is a coarse planarization process.

[0120] In some embodiments, see Figure 13 As shown, the planarization process for the initial filling medium 40 also includes:

[0121] The first planarized surface is subjected to a second planarization process to remove the remaining initial filling medium 40 on the first dielectric layer 131.

[0122] After the first planarization process, a second planarization process is used to repair the defects of the first planarization process, so as to form a flat second planarization surface, reduce the grooves on the second planarization surface, and facilitate the improvement of the quality of subsequent bonding processes.

[0123] In some embodiments, the second planarization process can be a chemical mechanical polishing process, i.e., a refined planarization process.

[0124] In some embodiments, the second planarization process is stopped at the first dielectric layer 131 to avoid the second planarization process causing grooves on the planarized surface that may affect subsequent bonding.

[0125] In some embodiments, after step S106, other structures may be bonded to the first dielectric layer 131 of chip 123.

[0126] Based on the same inventive concept, see [reference] Figure 14As shown, this application embodiment also provides a semiconductor device 100, which is prepared by the above-described semiconductor device forming method.

[0127] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0128] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0129] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0130] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Multiple chip structures are formed, each chip structure including a chip and a temporary planarization layer. The chip includes opposing chip bonding surfaces and a chip back surface, and the temporary planarization layer is located on the chip back surface. A second wafer is provided, the second wafer including a second wafer bonding surface; The chip bonding surfaces of the plurality of chip structures are bonded to the second wafer bonding surface of the second wafer.

2. The method for forming a semiconductor device according to claim 1, characterized in that, The formation of multiple chip structures includes: A temporary bonding structure is formed, the temporary bonding structure including a first substrate and a first wafer, the first wafer including a first wafer bonding surface and a first wafer back surface, the first wafer bonding surface being temporarily bonded to the first substrate; An initial temporary planarization layer is formed on the back side of the first wafer; Remove the first carrier and cut the first wafer and the initial temporary planarization layer to obtain the chip and the temporary planarization layer of the chip structure.

3. The method for forming a semiconductor device according to claim 2, characterized in that, The formation of multiple chip structures also includes: Before forming the initial temporary planarization layer, an initial inorganic release layer is formed on the back side of the first wafer opposite to the first substrate. After removing the first substrate, the initial inorganic release layer is cut to obtain multiple inorganic release layers of the chip structure, wherein the inorganic release layer is located between the temporary planarization layer and the back side of the chip.

4. The method for forming a semiconductor device according to claim 3, characterized in that, After bonding the chip bonding surfaces of the plurality of chip structures to the second wafer bonding surface of the second wafer, the process further includes: The inorganic stripping layers are peeled off from the chips to remove the temporary planarization layer of the chip structure.

5. The method for forming a semiconductor device according to claim 4, characterized in that, The step of peeling the plurality of inorganic release layers from the plurality of chips includes: The inorganic release layer of multiple chip structures is irradiated with a laser.

6. The method for forming a semiconductor device according to claim 5, characterized in that, The removal of the inorganic stripping layer from the plurality of chip structures further includes: The temporary planarization layer of the plurality of chip structures is fixed onto the second substrate, and a peeling force is applied to the second substrate.

7. The method for forming a semiconductor device according to claim 4, characterized in that, The formation of multiple chip structures also includes: Before forming the initial inorganic release layer, a first initial dielectric layer is formed on the back side of the first wafer away from the first substrate. After removing the first substrate, the first initial dielectric layer is cut to obtain a plurality of first dielectric layers of the chip structure, wherein the first dielectric layer is located between the inorganic stripping layer and the back side of the chip.

8. The method for forming a semiconductor device according to claim 7, characterized in that, After removing the temporary planarization layers of the plurality of said chip structures, the method further includes: An initial filling medium is formed, which fills the space between adjacent chips and covers the first dielectric layer. The material of the initial filling medium is the same as that of the first dielectric layer. The initial filling medium is planarized to obtain a filling medium located between adjacent chips.

9. The method for forming a semiconductor device according to claim 8, characterized in that, The planarization process for the initial filling medium includes: The initial filling medium is subjected to a first planarization process, and the remaining surface of the initial filling medium facing away from the second wafer constitutes a first planarization surface, at least a portion of which is located on the side of the first dielectric layer facing away from the first chip.

10. The method for forming a semiconductor device according to claim 9, characterized in that, The planarization process for the initial filling medium further includes: The first planarized surface is subjected to a second planarization process to remove the remaining initial filling medium on the first medium layer.

11. The method for forming a semiconductor device according to claim 3, characterized in that, The formation of multiple chip structures also includes: After the initial inorganic release layer is formed and before the initial temporary planarization layer is formed, a second initial dielectric layer is formed on the side of the initial inorganic release layer opposite to the first substrate. After removing the first substrate, the second initial dielectric layer is cut to obtain a plurality of second dielectric layers of the chip structure, the second dielectric layers being located between the temporary planarization layer and the inorganic stripping layer.

12. The method for forming a semiconductor device according to any one of claims 2 to 11, characterized in that, The formation of the temporary bond structure includes: Provide the first wafer and the first carrier; The first wafer bonding face is temporarily bonded to the first carrier; The back side of the first wafer is thinned to obtain the temporary bonding structure.

13. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for forming the semiconductor device according to any one of claims 1 to 12.

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