WAT test structure and method of manufacturing the same, and test method for overlay of contact holes
Patent Information
- Application Number
- CN202510319048.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2026-09-22
AI Technical Summary
[0005]本发明的目的在于提供一种WAT测试结构及其制造方法、接触孔的套刻偏移量测试方法，以解决常规WAT测试也检查不出接触孔偏移的问题
[0025]在本发明提供的WAT测试结构中，通过在薄膜堆栈结构上形成叉指状的多晶硅图形，并在各多晶硅条上设置接触孔，由于接触孔和多晶硅条之间存在交叠，在接触孔偏移时，两者之间的交叠总长度改变，那么接触孔处电阻也随之改变，从共接区处和多晶硅条顶部的接触孔施加电压所得到的电流也随之变化，在生产线上通过互连金属施加电压测试电流变化来表征接触孔套刻对准偏移量，从而分析数据监控产线工艺是否异常波动。
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Figure CN122803679A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, and in particular to a WAT test structure and its manufacturing method, and a method for testing the overlay offset of contact holes. Background Technology
[0002] In semiconductor manufacturing, a Wafer Acceptance Test (WAT) structure is typically fabricated on the wafer. The WAT structure verifies whether the semiconductor manufacturing process is performed according to established technical specifications, ensuring that the circuitry on the wafer meets expected electrical performance. This is a crucial step in ensuring product quality and reliability. By analyzing WAT data, engineers can monitor and evaluate the production line's operational status, such as detecting equipment performance deviations and changes in process conditions, thereby adjusting process parameters and optimizing the production process in a timely manner. The data provided by WAT supports the early identification and warning of potential problems in the production process.
[0003] During chip manufacturing, devices need to be brought out through contact holes (CTs) for subsequent wiring connections. The alignment deviation between the CT and the underlying pattern needs to be controlled within a certain range. If the offset is too large, it will seriously affect manufacturing performance and reliability, leading to chip failure. However, in actual production, there will be a problem where the lithography station cannot detect it, and subsequent routine WAT testing cannot detect it either, but the chip is seriously misaligned.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a WAT test structure and its manufacturing method, as well as a method for testing the offset of contact holes, so as to solve the problem that conventional WAT testing cannot detect contact hole offset.
[0006] To address the aforementioned technical problems, this invention provides a WAT test structure, comprising:
[0007] Thin-film stack structure;
[0008] A polysilicon pattern is formed on the thin film stack structure. The polysilicon pattern is an interdigitated pattern comprising a plurality of polysilicon strips, which are interconnected by a common junction region.
[0009] Multiple contact holes, at least some of which overlap on the corresponding polysilicon strip;
[0010] An interconnecting metal is disposed on top of the contact hole for applying voltage to the contact hole for testing.
[0011] Preferably, the thin film stack structure includes a substrate, an epitaxial layer, and a field oxide layer stacked sequentially from bottom to top.
[0012] Preferably, an interlayer dielectric is further disposed on the polysilicon pattern, and the interlayer dielectric surrounds the contact hole to isolate the interconnect metal and the polysilicon pattern.
[0013] Preferably, the interconnecting metal includes a first interconnecting region and a second interconnecting region, the second interconnecting region being disposed on top of at least a portion of the contact hole, and the first interconnecting region being disposed on top of the common contact area.
[0014] Preferably, the top of the common connection area is further provided with a contact hole to connect with the first interconnection area through the contact hole.
[0015] Preferably, the first interconnect region and the second interconnect region are further covered with a passivation layer, the passivation layer having two openings to expose the first interconnect region and the second interconnect region respectively to form a first needle puncture region and a second needle puncture region.
[0016] A method for manufacturing a WAT test structure, comprising:
[0017] Provides thin-film stack structures;
[0018] Polysilicon is deposited on the thin film stack structure and etched to form a polysilicon pattern, wherein the polysilicon pattern is an interdigitated pattern comprising a plurality of polysilicon strips, and the polysilicon strips are interconnected by a common junction region.
[0019] An interlayer dielectric is deposited on the polysilicon pattern;
[0020] The interlayer dielectric is etched to form a plurality of holes, and metal is deposited in the holes to form contact holes, and at least a portion of the contact holes overlap on the corresponding polysilicon strips;
[0021] Interconnect metal is deposited on top of the contact hole to apply voltage to the contact hole for testing.
[0022] Preferably, the interlayer dielectric is etched to form holes on the top of the polysilicon strip and the common junction area, respectively, and then metal is deposited in the holes to form contact holes.
[0023] Preferably, depositing interconnect metal on top of the contact hole includes: forming a second interconnect region on top of at least a portion of the contact hole, and forming a first interconnect region on the contact hole on top of the common interconnect region.
[0024] A method for testing the offset of a contact hole using the WAT test structure described above.
[0025] In the WAT test structure provided by this invention, interdigitated polysilicon patterns are formed on a thin-film stack structure, and contact holes are provided on each polysilicon strip. Since there is an overlap between the contact holes and the polysilicon strips, the total length of the overlap changes when the contact holes are offset, and the resistance at the contact holes also changes accordingly. The current obtained by applying voltage from the contact holes at the common junction area and the top of the polysilicon strips also changes accordingly. On the production line, the current change is tested by applying voltage to the interconnect metal to characterize the contact hole overlay alignment offset, thereby analyzing data to monitor whether there are abnormal fluctuations in the production line process.
[0026] The manufacturing method of the WAT test structure and the method for testing the overlay offset of the contact hole provided by this invention belong to the same inventive concept as the WAT test structure provided by this invention. Therefore, the manufacturing method of the WAT test structure and the method for testing the overlay offset of the contact hole provided by this invention have at least all the advantages of the WAT test structure provided by this invention, and will not be repeated here. Attached Figure Description
[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0028] Figure 1 This is a top view of an embodiment of the present invention;
[0029] Figure 2 This is a schematic diagram of the structure of a polycrystalline silicon layer and a contact Y metal according to an embodiment of the present invention;
[0030] Figure 3 This is a partial cross-sectional structural schematic diagram of an embodiment of the present invention.
[0031] In the attached image:
[0032] 1. Substrate; 2. Epitaxial layer; 3. Field oxide layer; 4. Polysilicon pattern; 41. Common junction region; 42. Polysilicon strip; 5. Interlayer dielectric; 6. Interconnect metal; 61. First interconnect region; 62. Second interconnect region; 7. Contact hole; 8. First pin area; 9. Second pin area. Detailed Implementation
[0033] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0034] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0035] The inventors discovered that conventional WAT test structures have difficulty obtaining the offset of contact holes.
[0036] Based on this, the core idea of the present invention is to characterize the overlay offset by setting the polysilicon pattern into an interdigitated pattern, forming contact holes that overlap with the polysilicon strip, and leading them out through interconnect metal, thereby applying voltage to the contact holes and testing the change in current.
[0037] Example 1
[0038] For details, please refer to Figures 1-3 This is a schematic diagram of an embodiment of the present invention. Figure 1 As shown, a WAT test structure includes:
[0039] Thin-film stack structure;
[0040] A polysilicon pattern 4 is formed on the thin film stack structure. The polysilicon pattern 4 is an interdigitated pattern including a plurality of polysilicon strips 42, which are interconnected by a common junction area 41.
[0041] Multiple contact holes 7, at least some of which overlap on the corresponding polysilicon strip 42;
[0042] Interconnecting metal 6 is disposed on top of the contact hole 7 for applying voltage to the contact hole 7 for testing.
[0043] In one embodiment, an interdigitated polysilicon pattern 4 is formed on a thin-film stack structure, and contact holes 7 are provided on each polysilicon strip 42. Since there is an overlap between the contact holes 7 and the polysilicon strip 42, when the contact holes 7 are offset, the total length of the overlap between the two changes, and the resistance at the contact holes 7 also changes accordingly. The current obtained by applying voltage from the common junction area 41 and the contact holes 7 at the top of the polysilicon strip 42 also changes accordingly. On the production line, the current change is tested by applying voltage to the interconnect metal 6 to characterize the offset of the contact hole 7 overlay, thereby analyzing the data to monitor whether there are abnormal fluctuations in the production line process.
[0044] Understandably, the length, width, and number of polysilicon strips 42 are adjusted according to the specific processes and materials used in the chip factory, thereby controlling the overlap area between the ends of the polysilicon strips 42 and the landing points of the contact holes 7. Specifically, during the manufacturing of the contact holes 7, the contact resistance of the polysilicon strips 42 can be made lower than the contact resistance of the contact holes 7, thus improving test sensitivity.
[0045] When forming the contact hole 7, the cross-section at the top of the contact hole 7 is often larger than that at the bottom. Therefore, the larger cross-section at the top of the contact hole 7 can reduce the contact resistance between the contact hole 7 and the interconnect metal 6, making the contact resistance at that point small enough to be negligible and not affecting the measurement results. The smaller cross-section at the bottom of the contact hole 7 can form a larger contact resistance. When the contact hole 7 is offset, the overlapping area of the polysilicon strip 42 and the contact hole 7 changes, and the contact resistance changes. The change in the applied voltage and test current can characterize the offset of the contact hole 7.
[0046] like Figure 3 As shown, the thin film stack structure includes a substrate 1, an epitaxial layer 2, and a field oxide layer 3 stacked sequentially from bottom to top. The substrate 1 is, for example, an N-type substrate made of silicon or silicon carbide, and the epitaxial layer 2 is, for example, an N-type epitaxial layer made of silicon or silicon carbide.
[0047] like Figure 3 As shown, an interlayer dielectric 5 is further disposed on the polysilicon pattern 4, and the interlayer dielectric 5 surrounds the contact hole 7 to isolate the interconnect metal 6 and the polysilicon pattern 4. The interconnect metal 6 is made of aluminum. The polysilicon pattern 4 and the interconnect metal 6 are connected through the contact hole 7. The interconnect metal 6 includes a first interconnect region 61 and a second interconnect region 62. The second interconnect region 62 is disposed on top of at least a portion of the contact hole 7, and the first interconnect region 61 is disposed on top of the common connection region 41.
[0048] like Figure 1 and Figure 2 As shown, both the common junction area 41 and the polysilicon strip 42 are provided with contact holes 7. The contact holes 7 are overlaid in a predetermined position according to the layout. The polysilicon strips 42 are arranged in an array with a certain spacing according to the layout, and the ends of the polysilicon strips 42 are in contact with the contact holes 7. There is an overlap between the two, and the contact holes 7 are connected through the second interconnection area 62. For testing, the polysilicon strips 42 are interconnected through the common junction area 41 to connect voltage and form a test circuit. The common junction area 41 is also provided with contact holes 7, and they are connected through the first interconnection area 61.
[0049] Specifically, the top of the common connection area 41 is also provided with a contact hole 7 to connect with the first interconnect area 61 through the contact hole 7. The first interconnect area 61 and the second interconnect area 62 are also covered with a passivation layer (not shown), which has two openings to expose the first interconnect area 61 and the second interconnect area 62 to form the first needle piercing area 8 and the second needle piercing area 9, respectively.
[0050] The common connection area 41 is used to connect voltage. The top of the common connection area 41 can also be provided with a contact hole 7 to form a test circuit with the contact hole 7 on the top of the polysilicon strip 42. The shape of the common connection area 41 can also be set according to the position of the contact hole 7, so that the common connection area 41 and the contact hole 7 overlap and contact, and the overlay offset of the contact hole 7 is measured.
[0051] like Figure 2As shown, for example, there are 6 polysilicon strips 42. Typically, the standard offset for the contact holes 7 in a chip manufacturing plant is 100nm. Therefore, according to the established layout, the overlap length between the smaller contact holes 7 and the polysilicon strips 42 increases sequentially from left to right: 0nm, 10nm, 20nm, 30nm, 40nm, and 50nm, for a total overlap length of 150nm. If the contact holes 7 are shifted 10nm to the right, the overlap length becomes 10nm, 20nm, 30nm, 40nm, 50nm, and 60nm, for a total overlap length of 210nm. This total overlap length increases by 210 / 150 = 140% compared to before the shift, theoretically reducing the contact resistance by 40%. This sensitivity is sufficient to meet testing requirements. The number of polysilicon strips 42 and the increment of the overlap length can be adjusted according to actual conditions.
[0052]
Example 2
[0053] Please refer to Figures 1 to 3 Based on the same technical concept, this disclosure also provides a method for manufacturing a WAT test structure, including:
[0054] S1 provides a thin-film stack structure. For example... Figure 3 As shown, the thin film stack structure includes a substrate 1, an epitaxial layer 2, and a field oxide layer 3 stacked sequentially from bottom to top. The substrate 1 is, for example, an N-type substrate made of silicon or silicon carbide, and the epitaxial layer 2 is, for example, an N-type epitaxial layer made of silicon or silicon carbide.
[0055] S2, polysilicon is deposited on the thin film stack structure and etched to form a polysilicon pattern 4. The polysilicon pattern 4 is an interdigitated pattern including a plurality of polysilicon strips 42, one end of which is interconnected through a common junction area 41.
[0056] Understandably, the length, width, and number of polysilicon strips 42 are adjusted according to the specific processes and materials used in the chip factory, thereby controlling the overlap area between the ends of the polysilicon strips 42 and the landing points of the contact holes 7. Specifically, during the manufacturing of the contact holes 7, the contact resistance of the polysilicon strips 42 can be made lower than the contact resistance of the contact holes 7, thus improving test sensitivity.
[0057] S3, depositing interlayer dielectric 5 on the polysilicon pattern 4.
[0058] S4, etch the interlayer medium 5 to form a plurality of holes, and deposit metal in the holes to form contact holes 7, and at least a portion of the contact holes 7 overlap on the corresponding polysilicon strip 42.
[0059] In one embodiment, the interlayer dielectric 5 is etched to form holes on the top of the polysilicon strip 42 and the common junction region 41, respectively, and then metal is deposited in the holes to form contact holes 7.
[0060] The common connection area 41 is used to connect voltage. The top of the common connection area 41 can also be provided with a contact hole 7 to form a test circuit with the contact hole 7 on the top of the polysilicon strip 42. The shape of the common connection area 41 can also be set according to the position of the contact hole 7, so that the common connection area 41 and the contact hole 7 overlap and contact, and the overlay offset of the contact hole 7 is measured.
[0061] S5, an interconnect metal 6 is deposited on top of the contact hole 7 to apply a voltage to the contact hole 7 for testing. Depositing the interconnect metal 6 on top of the contact hole 7 includes forming a second interconnect region 62 on top of at least a portion of the contact hole 7, and forming a first interconnect region 61 on the contact hole 7 above the common connection region 41. The interconnect metal 6 is made of aluminum. The polysilicon pattern 4 and the interconnect metal 6 are connected through the contact hole 7.
[0062] After forming the first interconnect region 61 and the second interconnect region 62, a passivation layer (not shown) is also covered on the first interconnect region 61 and the second interconnect region 62. The passivation layer has two openings to expose the first interconnect region 61 and the second interconnect region 62 to form the first needle puncture region 8 and the second needle puncture region 9, respectively.
[0063] In one embodiment, an interdigitated polysilicon pattern 4 is formed on a thin-film stack structure, and contact holes 7 are provided on each polysilicon strip 42. Since there is an overlap between the contact holes 7 and the polysilicon strip 42, when the contact holes 7 are offset, the total length of the overlap between the two changes, and the resistance at the contact holes 7 also changes accordingly. The current obtained by applying voltage from the common junction area 41 and the contact holes 7 at the top of the polysilicon strip 42 also changes accordingly. On the production line, the current change is tested by applying voltage to the interconnect metal 6 to characterize the offset of the contact hole 7 overlay, thereby analyzing the data to monitor whether there are abnormal fluctuations in the production line process.
[0064]
Example 3
[0065] Based on the same technical concept, this disclosure also provides a method for testing the overlay offset of a contact hole, employing the WAT test structure described above. Figure 1 As shown, voltage is supplied to the WAT test structure through the first pin piercing area 8 and the second pin piercing area 9. When the contact hole 7 is offset, the overlapping area of the polysilicon strip 42 and the contact hole 7 changes, and the contact resistance changes. On the production line, the contact hole 7 offset is characterized by applying voltage to the first pin piercing area 8 and the second pin piercing area 9 to test the change in current. Data analysis can be used to monitor whether there are abnormal fluctuations in the production line process, thereby analyzing the offset of the contact hole 7 and monitoring whether there are abnormal fluctuations in the production line process.
[0066] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A WAT test structure, characterized in that, include: Thin-film stack structure; A polysilicon pattern is formed on the thin film stack structure. The polysilicon pattern is an interdigitated pattern comprising a plurality of polysilicon strips, which are interconnected by a common junction region. Multiple contact holes, at least some of which overlap on the corresponding polysilicon strip; An interconnecting metal is disposed on top of the contact hole for applying voltage to the contact hole for testing.
2. The WAT test structure according to claim 1, characterized in that, The thin film stack structure includes a substrate, an epitaxial layer, and a field oxide layer stacked sequentially from bottom to top.
3. The WAT test structure according to claim 1, characterized in that, An interlayer dielectric is also disposed on the polysilicon pattern, and the interlayer dielectric surrounds the contact hole to isolate the interconnect metal and the polysilicon pattern.
4. The WAT test structure according to claim 1, characterized in that, The interconnecting metal includes a first interconnecting region and a second interconnecting region, the second interconnecting region being disposed on top of at least a portion of the contact hole, and the first interconnecting region being disposed on top of the common contact area.
5. The WAT test structure according to claim 4, characterized in that, The top of the common connection area is also provided with a contact hole to connect with the first interconnection area through the contact hole.
6. The WAT test structure according to claim 4, characterized in that, The first interconnect region and the second interconnect region are also covered with a passivation layer, which has two openings to expose the first interconnect region and the second interconnect region to form the first needle puncture region and the second needle puncture region, respectively.
7. A method for manufacturing a WAT test structure, characterized in that, include: Provides thin-film stack structures; Polysilicon is deposited on the thin film stack structure and etched to form a polysilicon pattern, wherein the polysilicon pattern is an interdigitated pattern comprising a plurality of polysilicon strips, and the polysilicon strips are interconnected by a common junction region. An interlayer dielectric is deposited on the polysilicon pattern; The interlayer dielectric is etched to form a plurality of holes, and metal is deposited in the holes to form contact holes, and at least a portion of the contact holes overlap on the corresponding polysilicon strips; Interconnect metal is deposited on top of the contact hole to apply voltage to the contact hole for testing.
8. The method for manufacturing the WAT test structure according to claim 7, characterized in that, The interlayer dielectric is etched to form holes on the top of the polysilicon strip and the common junction area, respectively, and then metal is deposited in the holes to form contact holes.
9. The method for manufacturing the WAT test structure according to claim 8, characterized in that, Depositing interconnect metal on top of the contact hole includes: forming a second interconnect region on top of at least a portion of the contact hole, and forming a first interconnect region on the contact hole on top of the common interconnect region.
10. A method for testing the overlay offset of a contact hole, characterized in that, The WAT test structure described in any one of claims 1-6 is adopted.