Chip sorting method

Abstract

The present disclosure provides a chip sorting method, and belongs to the technical field of semiconductor device manufacturing. The sorting method comprises: providing a wafer, the wafer has a first region and a second region, the first region is connected with the second region, the first region comprises a plurality of first type chips, and the second region comprises a plurality of second type chips; removing a plurality of boundary chips at the junction of the first region and the second region to form a physical isolation strip without chips between the first region and the second region; and removing the second type chips remaining in the second region. The present disclosure can improve the sorting efficiency.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor device manufacturing technology, and specifically relates to a chip sorting method. Background Technology

[0002] In the manufacturing process of light-emitting diode (LED) chips, after the wafer completes the front-end and mid-end processes, it needs to be sorted in the back-end process to separate qualified chips that meet the photoelectric performance and appearance specifications, in order to prepare for subsequent shipment.

[0003] In related technologies, the chip sorting process is as follows: First, the sorting equipment uses nozzles to pick up chips from the wafer that fail to meet photoelectric performance or appearance standards one by one and transfer them to a dedicated carrier blue film. These chips are typically defined as scrap, defective, or off-standard products and are not delivered to the customer. Subsequently, a casting process is used to transfer the remaining qualified chips from the wafer onto one or more blue films. These chips, carried on new blue films, are the final qualified products shipped to the customer.

[0004] However, due to limitations in manufacturing processes, chips with substandard optoelectronic performance or appearance often account for more than 20% of the wafers, and are highly concentrated in the edge areas. This means that the sorting equipment must perform a massive amount of picking, resulting in long sorting times. Furthermore, when picking these substandard chips, the picker nozzles wear down rapidly due to frequent contact with chips with surface defects such as burrs and protrusions, leading to frequent air leakage alarms during pickup. Moreover, air leakage from the nozzles can cause substandard chips that should have been rejected to remain on the wafer due to pickup failures, and then be mixed with qualified chips in subsequent casting processes, resulting in abnormal chip quality. Summary of the Invention

[0005] This disclosure provides a chip sorting method that can improve sorting efficiency. The technical solution is as follows: This disclosure provides a chip sorting method, the sorting method comprising: providing a wafer having a first region and a second region, the first region being adjacent to the second region, the first region including a plurality of first type chips, and the second region including a plurality of second type chips; removing a plurality of boundary chips at the junction of the first region and the second region to form a chip-free physical isolation zone between the first region and the second region; and removing the remaining second type chips in the second region.

[0006] In another implementation of this disclosure, at least one parameter of the first type of chip and the second type of chip belongs to different parameter ranges.

[0007] In another implementation of this disclosure, removing the plurality of chips at the boundary between the first region and the second region includes: In the test data file of the wafer, a predefined isolation mark value is assigned to the boundary chip; the boundary chip with the isolation mark value is sorted out from the wafer.

[0008] In yet another implementation of this disclosure, the method further includes: Based on the coordinates of each chip, it is determined whether a second type of chip appears around each first type of chip; the second type of chip located in a first neighborhood of each first type of chip is identified as the boundary chip, where the first neighborhood is the area occupied by the chip adjacent to the first type of chip along multiple different directions around the outer periphery of the first type of chip.

[0009] In yet another implementation of this disclosure, the method further includes: Based on the coordinates of each chip, it is determined whether a first type of chip appears around each second type of chip; if a first type of chip exists in the second neighborhood of a second type of chip, then the second type of chip in the second neighborhood of the second type of chip is determined as a boundary chip, and the second neighborhood is the area occupied by chips that are directly adjacent to the second type of chip along multiple different directions along the outer periphery of the second type of chip.

[0010] In another implementation of this disclosure, the chips included in the first neighborhood are arranged in a triangular, square, rectangular, pentagonal or hexagonal pattern on the wafer.

[0011] In another implementation of this disclosure, after determining the boundary chip, the sorting method further includes: verifying whether the boundary chip forms a continuous path in space; if there is a discontinuity, then determining the second type of chip connected to the discontinuity position as the boundary chip.

[0012] In another implementation of this disclosure, the method further includes: classifying the chip into a first type of chip and a second type of chip according to one or more of the parameters; and determining the area occupied by the chips that are spatially continuous and belong to the first type of chip as the first area, and the area occupied by the chips that are spatially continuous and belong to the second type of chip as the second area, based on the coordinates of the chips on the wafer.

[0013] In another implementation of this disclosure, the physical isolation zone is a closed loop surrounding the first region.

[0014] In another implementation of this disclosure, removing the remaining second type of chips in the second region includes: manually sorting out the second type of chips outside the physical isolation strip using a suction pen or vacuum suction tool.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: This sorting method removes multiple boundary chips at the boundary between the first and second regions based on the location of different types of chips (first-type chips and second-type chips). This creates a chip-free physical isolation zone between the first and second regions. The existence of this physical isolation zone provides a clear and unambiguous reference boundary for subsequent sorting operations. Based on this physical isolation zone, chips other than boundary chips within the second region can be sorted and removed in batches. This method fundamentally avoids errors such as mis-picking and omissions that are prone to occur when sorting in complex boundary areas. It also frees up the sorting workload from the original arduous task of picking each chip individually, requiring only a small amount of precise positioning work, while transforming most of the workload into simple, batch-processable operations. This significantly improves sorting efficiency and reliably guarantees sorting quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a chip sorting method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another chip sorting method provided in this embodiment of the disclosure; Figure 3 This is a wafer grade diagram showing a wafer after photoelectric testing and visual inspection in a certain production line; Figure 4 This is a schematic diagram of the formation of physical isolation bands in a wafer; Figure 5 This is a schematic diagram of the boundary chip obtained when the moving window moves along the second path; Figure 6 This is a schematic diagram of a wafer after physical isolation bands have been formed. Figure 7 This is a schematic diagram of the supplied chips remaining on the wafer.

[0018] The markings in the diagram are explained as follows: 1. First Zone; 2. Second Zone; 3. Physical Barrier. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] This disclosure provides a chip sorting method, such as... Figure 1 As shown, the sorting methods include: S101: Provides wafers.

[0021] The wafer has a first region and a second region, the first region being adjacent to the second region. The first region includes multiple first-type chips, and the second region includes multiple second-type chips.

[0022] S102: Remove multiple boundary chips at the junction of the first region and the second region to form a chip-free physical isolation band between the first region and the second region.

[0023] S103: Remove the remaining second-type chips in the second region.

[0024] This sorting method removes multiple boundary chips at the boundary between the first and second regions based on the location of different types of chips (first-type chips and second-type chips). This creates a chip-free physical isolation zone between the first and second regions. The existence of this physical isolation zone provides a clear and unambiguous reference boundary for subsequent sorting operations. Based on this physical isolation zone, chips other than boundary chips within the second region can be sorted and removed in batches. This method fundamentally avoids errors such as mis-picking and omissions that are prone to occur when sorting in complex boundary areas. It also frees up the sorting workload from the original arduous task of picking each chip individually, requiring only a small amount of precise positioning work, while transforming most of the workload into simple, batch-processable operations. This significantly improves sorting efficiency and reliably guarantees sorting quality.

[0025] In this embodiment, the first area is a concentrated area for supplied chips, and the second area is a concentrated area for non-supplied chips. The first type of chip consists of supplied chips. The second type consists of scrapped or recycled chips.

[0026] The first and second regions simply represent the areas where different chips belong. In other examples, the roles can be reversed; for instance, the first region could be a concentrated area for supplied chips, and the second region for non-supplied chips. The second type of chip represents supplied chips, while the first type represents scrapped or recycled chips. When determining the physical isolation zone, simply remove the scrapped or recycled chips and retain the supplied chips.

[0027] This disclosure also provides another chip sorting method, such as... Figure 2 As shown, the sorting methods include: S201: Provides wafers.

[0028] The wafer is covered with hundreds or even tens of thousands of individual chips.

[0029] The wafer has a first region and a second region, the first region being adjacent to the second region. The first region includes multiple first-type chips, and the second region includes multiple second-type chips.

[0030] The wafers provided above have already undergone the dicing process.

[0031] The dicing process involves placing the wafer face up and attaching a dicing protective film to the back. Then, using a laser or diamond wheel, the wafer is diced along the dicing grooves (grooves 90%-95% thick) into individual, physically separated chip units. A small amount of material remains connecting the chips, and they are not completely separated. The wafer transforms from a single unit into a collection of smaller pieces that are still attached to the original thin film.

[0032] After dicing, a new blue film is applied to the front side of the wafer and bonded to it. The wafer is then flipped over, and the protective film on the back side is removed. The new blue film is stretched outwards, flattening and expanding it, resulting in increased spacing between the chip cells bonded to it. This prevents the chips from colliding with each other during subsequent pick-up, facilitating the operation of sorting machines or pick-up equipment.

[0033] S202: Obtain at least one parameter of each chip on the wafer.

[0034] In this embodiment, the wafer can be tested to obtain a test data file. The test data file includes the unique coordinates of each chip on the wafer and at least one parameter reflecting the chip's performance or appearance.

[0035] Testing refers to the electrical performance testing of each chip unit on a wafer using a wafer tester and probes. This test, also known as full testing, is mainly used to screen out chips that are fully functional and meet the required parameters, while rejecting chips that are faulty or do not meet the performance standards.

[0036] During testing, the tester applies a series of pre-programmed electrical signals (voltage, current, pulses) to the chip cell via probes and measures its response (output current, brightness, wavelength, switching speed, leakage current, etc.). After testing one chip cell, the wafer stage or probes move one chip cell pitch to the next chip cell, repeating the test until the entire wafer is covered.

[0037] The test data file includes the coordinates of each chip on the wafer and at least one parameter corresponding to the chip.

[0038] The coordinates included in the test data file represent the unique location of the chip on the wafer.

[0039] Coordinates include values ​​along the x-axis and along the y-axis, and can be denoted as (x, y).

[0040] In this embodiment, the parameters can be electrical performance parameters, including forward voltage, emission wavelength, brightness, etc., used to evaluate chip performance and quality, or appearance parameters, including cracks, chipping, contamination, electrode defects, etc.

[0041] In other examples, the parameter can be any one type, as long as it reflects the chip level.

[0042] S203: Based on one or more parameters, divide the multiple chips arranged in an array on the wafer into a first region and a second region.

[0043] Optionally, step S203 includes: 2031: Based on one or more of the parameters, the chips are divided into a first type of chip and a second type of chip.

[0044] The first type of chip is the supplied chip, and the second type of chip is the scrapped or recycled chip. At least one parameter of the first type of chip and the second type of chip belongs to different parameter ranges.

[0045] In this embodiment, the chip can be assigned different grade codes according to one or more of the parameters; then, the chips are divided into first-class chips and second-class chips according to the grade codes.

[0046] For example, a chip must meet the following criteria: forward voltage of 2.8V - 3.2V, wavelength of 450nm - 455nm, brightness greater than 100 mcd, and no chipping or cracks. Chips that meet all these criteria are classified under one grade code (e.g., 1). Chips that do not meet at least one of these criteria are classified under another grade code (e.g., 2). Based on these grade codes, chips with grade code 1 are identified as Category 1 chips (i.e., supplied chips), and chips with grade code 2 are identified as Category 2 chips (i.e., non-supplied chips). Thus, each chip has a coordinate, and each coordinate corresponds to a grade code.

[0047] In other examples, the grade codes are also represented by other symbols, such as letters.

[0048] 2032: Based on the coordinates of the chips on the wafer, the area occupied by chips that are spatially continuous and belong to the first type of chips is defined as the first region, and the area occupied by chips that are spatially continuous and belong to the second type of chips is defined as the second region.

[0049] Based on chip coordinates, spatially adjacent chips are identified; chips of the first category that are adjacent to each other and have a level code of 1 are merged into the same region to obtain the first region; chips of the second category that are adjacent to each other and have a level code of 2 are merged into the same region to obtain the second region.

[0050] In this embodiment, by analyzing the chip's position coordinates, it was found that the second type of chips are mainly concentrated at the edge of the wafer, and therefore this area can be defined as the second region, i.e., the edge defective product region. The first type of chips, on the other hand, are concentrated in the center of the wafer, and can be defined as the central good product region, i.e., the first region.

[0051] S204: Determine the boundary chip based on the coordinates of each chip.

[0052] Optionally, step S204 can be implemented as follows: 2041: Based on the coordinates of each chip, determine whether a second type of chip appears around each first type of chip.

[0053] 2042: The second type of chip located in the first neighborhood of each first type of chip is identified as the boundary chip.

[0054] The first neighborhood is the area occupied by chips that are directly adjacent to the first type of chip in multiple different directions along the outer periphery of the first type of chip.

[0055] When the first neighborhood contains both type 1 and type 2 chips, it crosses the boundary between the first and second regions. In this case, the type 2 chips within the first neighborhood are considered boundary chips because they are both type 2 and adjacent to type 1 chips. This means these chips can serve as a physical isolation zone for positioning, or they can be discarded. Discarding these type 2 chips and establishing a physical isolation zone allows for the efficient removal of large quantities of defective products without losing any good ones.

[0056] In this embodiment, the chips included in the first neighborhood can be arranged on the wafer in the form of triangles, regular polygons, rectangles, pentagons, and hexagons.

[0057] In the two-dimensional coordinate system of a wafer, for a first type of chip with coordinates (x, y), the chips in its first neighborhood refer to the set of chips that are spatially adjacent to the first type of chip; or include the first type of chip itself and the chips that are spatially adjacent to the first type of chip.

[0058] For example, the set of chips in the first neighborhood, when the chips form a triangle on the wafer, includes adjacent chips in the top, bottom, left, or right directions of the first type of chip, with coordinates (x, y+1), (x-1, y), and (x+1, y), respectively; or (x, y-1), (x-1, y), and (x+1, y). Alternatively, when including itself, the coordinates could be (x, y), (x, y+1), and (x-1, y).

[0059] The first neighborhood includes the set of chips that form a square on the wafer, including adjacent chips in the four directions (up, down, left, right) of the first type of chip, including chips with coordinates (x, y+1), (x, y-1), (x-1, y), and (x+1, y). Alternatively, it may include itself, for example, chips with coordinates (x, y), (x-1, y), (x, y+1), and (x-1, y+1), etc.

[0060] When the chips in the first neighborhood are rectangular on the wafer, the chip set includes the first type of chips, as well as the chips above, below, to the left or right of the first type of chips, and the adjacent chips in the two diagonal directions. For example, the coordinates can be (x, y), (x, y+1), (x, y-1), (x+1, y), (x+1, y+1), (x+1, y-1).

[0061] The first neighborhood includes a set of chips that are pentagonal on the wafer. This set of chips can include adjacent chips in the directions of the top, bottom, left, right and one of the diagonals of the first type of chip. For example, chips with coordinates of (x, y+1), (x, y-1), (x-1, y), (x+1, y) and (x-1, y-1).

[0062] The first neighborhood includes a set of chips that are hexagonal on the wafer. This set of chips can include adjacent chips in the directions of the top, bottom, left, right and two diagonals of the first type of chip, such as chips with coordinates of (x, y+1), (x, y-1), (x-1, y), (x+1, y), (x-1, y-1), and (x+1, y-1).

[0063] In other examples, the chips contained in the first neighborhood can be any other shape on the wafer, such as octagons, circles, etc. If it is an octagon, the set of chips in the first neighborhood that are octagonal on the wafer can include adjacent chips in the four directions of up, down, left, and right, as well as adjacent chips in the four diagonal directions, for example, including (x, y+1), (x, y-1), (x-1, y), (x+1, y), (x-1, y-1), (x+1, y-1), (x-1, y+1), and (x+1, y+1), etc.

[0064] In step 2041, the first neighborhood of each first type of chip can be determined. In this embodiment, when a second type of chip appears in the first neighborhood, the first neighborhood can be determined to be the intersection of the first region and the second region.

[0065] Optionally, in step 2041, during the determination, a sliding window can be moved along a preset first path, using the first neighborhood of one of the first-type chips as a sliding window, and the chip spacing as the unit of movement. During the movement, it is confirmed whether both first-type and second-type chips exist within the sliding window. For example, the first path is a path from the first region to the second region. The first neighborhood of a first-type chip located on the side of the first region away from the second region is used as the sliding window. Then, following the first path, the sliding window is moved to check whether it contains a second-type chip, until it is detected that both first-type and second-type chips are present within the sliding window. At this point, the boundary between the first and second regions can be located.

[0066] In this embodiment, since the second region is located at the edge of the wafer and the first region is located in the middle of the wafer, the first path is actually a path from the center of the wafer to the edge.

[0067] In another example, step S204 can be implemented as follows: 2043: Based on the coordinates of each chip, determine whether a first-type chip appears around each second-type chip.

[0068] 2044: If a first-type chip exists in the second neighborhood of a second-type chip, then the second-type chip in the second neighborhood of the second-type chip is determined as a boundary chip.

[0069] The second neighborhood is the area occupied by chips that are directly adjacent to the first type of chip along multiple different directions around the outer periphery of the second type of chip.

[0070] At this point, the second neighborhood encompasses both the first and second type of chips, and it precisely crosses the boundary between the first and second regions. The second type of chips within this second neighborhood are considered boundary chips because they are both second type chips and adjacent to the first type chips. This means these chips can serve as a physical isolation zone for positioning, and can also be discarded. Discarding these second type chips and establishing a physical isolation zone allows for the efficient removal of large quantities of defective products without any loss of good products.

[0071] In this embodiment, the chips included in the second neighborhood can be arranged on the wafer in the form of triangles, regular polygons, pentagons, and hexagons.

[0072] The set of chips contained in the second neighborhood is similar to that in the first neighborhood mentioned above, so it will not be repeated here.

[0073] In step 2043, the second neighborhood of each second type of chip can be determined. In this embodiment, when a first type of chip appears in the second neighborhood, the second neighborhood can be determined to be the intersection of the first region and the second region.

[0074] Optionally, in step 2043, during the determination, a second neighboring region of one of the second-type chips can be used as a sliding window, moving the sliding window in units of chip spacing, following a preset second path. During the movement, it is confirmed whether both first-type and second-type chips exist simultaneously within the sliding window. For example, the second path can be a path from the second region to the first region. The second neighboring region of a second-type chip located on the side of the second region furthest from the first region can be used as the sliding window. Then, following the second path, the sliding window is moved to check whether it contains a first-type chip, until it is detected that both first-type and second-type chips are present within the sliding window. At this point, the boundary between the first and second regions can be located.

[0075] For example, there can be multiple first paths and multiple second paths, with multiple first paths evenly distributed radially on the wafer, and multiple second paths also evenly distributed radially on the wafer. For example, there can be 24 first paths (one every 15°) or 36 second paths (one every 10°).

[0076] By setting multiple first paths or multiple second paths to cover different angular directions of the wafer, the defined boundary chips form a closed loop in space, providing a basis for the subsequent formation of continuous physical isolation zones. Simultaneously, multiple first paths or multiple second paths can simultaneously identify chips at different angular directions on the wafer, thereby improving the efficiency of boundary chip identification.

[0077] When determining the first and second paths, the geometric center of the wafer can be used as a reference point. Multiple radially distributed paths are set along the radial direction of the wafer, where the first path is radially outward and the second path is radially inward.

[0078] The number of first and second paths can be flexibly adjusted according to wafer size, chip layout, and other factors.

[0079] S205: Verify whether the boundary chip forms a continuous path in space.

[0080] If a discontinuity exists, the second type of chip connected to the discontinuity location will be identified as a boundary chip.

[0081] S206: In the wafer's test data file, assign a predefined isolation flag value to the boundary chip.

[0082] Optionally, step S206 can be achieved through the following steps: Modify at least one of the original parameter values ​​of the boundary chip to a predefined isolation flag value.

[0083] For example, the original grade code of the boundary chip (e.g., 2) can be directly modified to a dedicated isolation mark code (e.g., 3), and the sorting equipment can identify and pick out the boundary chips based on this code.

[0084] Alternatively, add a marker field to the test data of the boundary chip and set the value of the marker field to a predefined isolation marker value.

[0085] For example, without changing the original grade code, an additional marker field can be added to the boundary chip. For instance, a column "isolation marker" can be added to the test data file and its value can be set to "3". When the sorting device reads the data, it will prioritize identifying this marker for picking.

[0086] Whether modified or added, the essence is to distinguish boundary chips from other chips so that sorting equipment can accurately perform picking operations and form a physical isolation zone. Therefore, any data marking method that can achieve this distinguishing function is an equivalent implementation of the embodiments of this disclosure, and the embodiments of this disclosure do not limit it.

[0087] In other examples, the isolation marker value can be represented by letters or other symbols, as long as they can be recognized by the sorting device.

[0088] S207: Separate the boundary chips with isolation mark values ​​from the wafer to form a chip-free physical isolation band between the first region and the second region.

[0089] After the sorting equipment removes the boundary chips from the wafer based on the isolation mark values, the areas previously occupied by these boundary chips become blank areas. Since these boundary chips are located precisely at the junction of the first and second regions, their removal directly creates a continuous chip-free zone between the two previously connected areas—a physical isolation zone. This physical isolation zone acts as a "dividing line," completely separating the first region (the supplied chip area) and the second region (the non-supplied chip area) spatially. With this clearly visible physical isolation zone, subsequent manual operations or automated equipment processing of the remaining non-supplied chips in the second region can clearly use the isolation zone as the boundary, ensuring that the operation is limited to the area outside the physical isolation zone and that the supplied chips inside are never accidentally touched or damaged, thereby improving sorting efficiency.

[0090] In this embodiment, since the first region is located in the center of the wafer and the second region is located in the edge region of the wafer, the physical isolation band formed is a closed ring band surrounding the first region.

[0091] S208: Remove the remaining Type II chips in the second region.

[0092] The remaining chips, except for the first artificial chip, are manually separated from the wafer using a suction pen or vacuum suction tool.

[0093] Once the physical isolation zone is formed, the first area (the area for supplied chips) and the second area (the area for non-supplied chips) are clearly separated. At this point, operators can use a suction pen or vacuum suction tool to manually or semi-automatically remove the remaining chips (i.e., large, continuous sheets of non-supplied chips) from the wafer in batches, excluding the boundary chips, within the second area. Due to the physical isolation zone, operators can operate precisely within its boundaries, eliminating the need for high-precision visual positioning equipment and the risk of accidentally sucking up supplied chips from the first area. This design transforms the previously arduous task of picking millions of chips at a time into a rapid, one-time manual batch operation, significantly improving overall sorting efficiency and fundamentally eliminating the loss of good products or the omission of defective products due to misoperation, achieving optimal division of labor between humans and machines.

[0094] The sorting method provided in this embodiment first forms a physical isolation zone between the first region and the second region, and then sorts the chips according to the physical isolation zone. This can reduce the sorting of chips at the edge of the wafer and also reduce the sorting of chips that do not meet the appearance requirements. By reducing the sorting of chips that affect the wear of the nozzle, wear is reduced and sorting efficiency is improved.

[0095] The following specific example further illustrates the detailed process of the above sorting method: Figure 3 This is a wafer grade diagram showing a wafer after photoelectric testing and visual inspection in a production line. (Refer to...) Figure 3 The area containing the inner ring is the first region 1, where the first type of chip of level 1 is located, and the area outside the first region 1 is the second region 2, where the second type of chip of level 2 is located. To clearly show the levels, the first region 1 and the second region 2 can also be distinguished by different colors on the diagram, or by other different labeling methods, such as patterns, as long as the different regions of the chip level can be shown.

[0096] against Figure 3For simplicity, only two areas are shown. The chips in Area 1 (represented by number 1) do not require sorting and are the remaining chips on the wafer, i.e., the supply chips. These chips need to be flipped onto new blue film and shipped to the customer. The chips in Area 2 are non-supply chips, which need to be scrapped or otherwise processed, and require a pick-and-place process.

[0097] In other examples, the wafer-level map may include multiple regions, such as a first region 1 located at the center of the wafer, multiple second regions 2 surrounding the first region 1 in the circumferential direction, or multiple second regions 2 arranged radially around the first region 1 in the periphery of the first region 1.

[0098] exist Figure 3 As can be seen from the data, non-supply chips are mostly concentrated at the outer edge of the wafer. The outer edge contains many chips with poor appearance and those whose optoelectronic performance does not meet requirements. These poorly appearing chips accelerate nozzle damage during sorting by the picker. Moreover, non-supply chips account for approximately 30% of such a wafer, resulting in a huge number of chips that the sorting equipment must pick, leading to significant inefficiency. Therefore, the sorting method described earlier is used for this purpose.

[0099] Figure 4 This is a schematic diagram illustrating the formation of physical isolation bands in a wafer. (See also...) Figure 4 During sorting, the second type of chips at the junction of the first region 1 and the second region 2 are first removed, forming an empty physical isolation zone 3 between the two regions. Chips outside the physical isolation zone 3 are those that need to be scrapped, while chips inside the zone are those that can be shipped to customers. This reduces the actual sorting percentage from about 30% to about 5%, and eliminates the need to sort chips with poor edge appearance.

[0100] For specific sorting, please follow the steps below: The first step, based on the wafer's test data file, is to divide the multiple chips arrayed on the wafer into a first region 1 and a second region 2, that is, to divide the chips on the wafer into... Figure 3 The first region 1 and the second region 2 are shown.

[0101] For example, chips that meet the threshold range for forward voltage, wavelength, and brightness, and have no chipping or cracks in their appearance, are classified as Category 1 chips, while the remaining chips are classified as Category 2 chips. Then, the area containing consecutively arranged Category 1 chips is designated as Region 1, and the area containing consecutively arranged Category 2 chips is designated as Region 2. Here, the chip grade code for Region 1 is Grade 1, and the chip grade code for Region 2 is Grade 2.

[0102] The second step is to determine the boundary chip.

[0103] Figure 5 This is a schematic diagram showing the boundary chip obtained when the moving window moves along the second path. See also... Figure 5 Multiple second paths are defined from the edge of the wafer towards the center (the direction of the second paths is...). Figure 5 (As indicated by the arrow in the image), using the second neighborhood of a second-type chip located on the edge of the wafer as a moving window, the system checks whether a first-type chip appears within this moving window. The moving window is defined as follows (…). Figure 5 The black box in the middle contains 6 adjacent chips. Figure 5 Each vertex of the black box represents a chip. The black dot filled with shading (the bottom left dot) represents the second type of chip itself, and the other five are chips adjacent to it. The dashed box indicates the next position the moving window will move to.

[0104] The moving window is moved until a first-type chip appears within it, and the number of first-type chips reaches a preset threshold (e.g., when moved to the far right). At this point, the position of the moving window is the intersection of the first and second regions. The second-type chips contained within the moving window at this intersection are then identified as boundary chips. This provides the coordinates of the boundary chips located within the physical isolation zone at the intersection of the first and second regions.

[0105] The third step is to modify the grade code corresponding to the coordinates of the boundary chip obtained in the second step to a different code than the original code, and also different from the grade code of the first type of chip.

[0106] The fourth step involves the sorting equipment picking out boundary chips based on the modified grade codes.

[0107] Figure 6 This is a schematic diagram showing the wafer after physical isolation bands have been formed. See also... Figure 6 After a wafer is sorted by the sorting equipment, a physical isolation zone 3 without chips is formed. The outer part of the physical isolation zone 3 contains the chips that need to be scrapped, and the inner part of the physical isolation zone contains the chips that the customer will ship.

[0108] The fifth step involves manually sorting out the non-supply chips located outside the physical isolation zone.

[0109] Since the chips in the second region cannot be shipped to the customer, a suction pen is used to remove the chips in the second region outside the physical isolation zone of the wafer. Because of the physical isolation zone, the suction process allows for precise control, removing only the outer second region without touching the chips in the inner first region.

[0110] The sixth step is to remove the chips from the outer perimeter of the isolation zone in the fifth step.

[0111] Figure 7 This is a schematic diagram of the supplied chips remaining on the wafer. See also... Figure 7 Only the first region 1 of the supplied chip remains on the wafer. The supplied chip is then cast onto a new blue film (either one new blue film or multiple new blue films) using a casting process, and then shipped to the customer.

[0112] The above methods can reduce chip picking at wafer edges, reduce picking of chips that do not meet appearance requirements, and reduce chip picking that affects nozzle wear, thereby reducing wear and improving sorting efficiency.

[0113] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0114] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A chip sorting method, characterized in that, The sorting method includes: A wafer is provided, the wafer having a first region and a second region, the first region being adjacent to the second region, the first region including a plurality of first type chips, and the second region including a plurality of second type chips; Multiple boundary chips at the junction of the first region and the second region are removed to form a chip-free physical isolation band between the first region and the second region; Remove the remaining second-type chips in the second region.

2. The sorting method according to claim 1, characterized in that, At least one parameter of the first type of chip and the second type of chip belongs to different parameter ranges.

3. The sorting method according to claim 2, characterized in that, The removal of multiple boundary chips at the junction of the first region and the second region includes: In the test data file of the wafer, a predefined isolation marker value is assigned to the boundary chip; The boundary chip with the isolation mark value is sorted out from the wafer.

4. The sorting method according to claim 3, characterized in that, The method further includes: Based on the coordinates of each chip, determine whether a second type of chip appears around each first type of chip; The second type of chip located within a first neighborhood of each first type of chip is defined as the boundary chip, where the first neighborhood is the area occupied by the chip adjacent to the first type of chip along multiple different directions around the periphery of the first type of chip.

5. The sorting method according to claim 3, characterized in that, The method further includes: Based on the coordinates of each chip, determine whether a first type of chip appears around each second type of chip; If a chip of the first type exists within the second neighborhood of a chip of the second type, then the chip of the second type within the second neighborhood of the second type is defined as a boundary chip. The second neighborhood is the area occupied by chips that are directly adjacent to the chip of the second type along multiple different directions around the outer periphery of the chip of the second type.

6. The sorting method according to claim 4, characterized in that, The chips contained in the first neighborhood are arranged in a triangular, square, rectangular, pentagonal or hexagonal pattern on the wafer.

7. The sorting method according to claim 4 or 5, characterized in that, After determining the boundary chip, the sorting method further includes: Verify whether the boundary chip forms a continuous path in space. If there is a discontinuity, then the second type of chip connected to the discontinuity is identified as the boundary chip.

8. The sorting method according to claim 2, characterized in that, The method further includes: Based on one or more of the parameters, the chips are divided into a first type of chip and a second type of chip; Based on the coordinates of the chips on the wafer, the area occupied by the chips that are spatially continuous and belong to the first type of chips is determined as the first region, and the area occupied by the chips that are spatially continuous and belong to the second type of chips is determined as the second region.

9. The sorting method according to any one of claims 1-8, characterized in that, The physical isolation zone is a closed ring surrounding the first area.

10. The sorting method according to any one of claims 1-8, characterized in that, The removal of the remaining second type of chips in the second region includes: The second type of chip outside the physical isolation strip is manually sorted out using a suction pen or vacuum suction tool.

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