Wafer test pattern parameter validity verification and adaptive rotation compensation method

Abstract

This invention discloses a method for validating the validity of wafer test pattern parameters and adaptive rotation compensation. It acquires a wafer test dataset and receives configured rotation angles, rotation center coordinates, and marker point coordinates. The method performs range verification on the rotation angle and deviation verification on the marker point coordinates from the geometric center of the dataset. When the deviation exceeds a threshold, the final rotation center is determined. A single-pass traversal method is used to calculate the coordinates after rotation and synchronously update extreme values ​​to store the mapping relationship. Based on the extreme values, the minimum bounding rectangle is determined and memory is allocated. Multi-core block parallel processing is employed, selecting either lock-free direct writing or thread-local buffer merging based on the rotation angle type to write the test results into the minimum bounding rectangle. This method solves the technical problems of lacking synchronous verification of marker point positions and rotation parameter validity before rotation, the disconnect between rotation compensation and parameter verification, and performance bottlenecks caused by multiple data traversals. It improves the accuracy of wafer test pattern rotation compensation and the efficiency of automated processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a method for validating the validity of wafer test pattern parameters and adaptive rotation compensation. Background Technology

[0002] In semiconductor wafer manufacturing and testing processes, the large amount of test data generated by testing equipment is typically organized in the form of coordinate arrays. After data parsing and processing, a wafer test result image is generated. Due to inconsistent wafer placement orientation on the probe station, the wafer image generated from the test data will have a rotational deviation from the actual wafer orientation. User-defined marker points will differ from the actual center point of the wafer, and the relative positional relationship of the marker points will be disrupted after rotation. Pre-conversion warnings and confirmations are necessary. Traditional rotation processing requires multiple data traversals, resulting in performance bottlenecks and low algorithm efficiency.

[0003] In existing technologies, most rotation compensation methods for wafer test patterns employ fixed-angle rotation or coarse-grained correction strategies based on template matching. These methods struggle to simultaneously verify the legitimacy of marker positions and rotation parameters before rotation, leading to deviations in coordinate mapping after rotation and impacting the accuracy of subsequent defect localization. Furthermore, existing solutions lack dynamic verification methods for the consistency of marker topological relationships during rotation. The rotation compensation and parameter verification processes are disconnected, making it difficult to establish an effective early warning mechanism before data conversion. This restricts the overall efficiency and reliability of automated wafer test data processing.

[0004] Therefore, there is an urgent need to provide a technical solution to address the above problems. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for validating the validity of wafer test pattern parameters and for adaptive rotation compensation.

[0006] In a first aspect, the present invention provides a method for validating the legality of wafer test pattern parameters and adaptive rotation compensation, the technical solution of which is as follows: Obtain a wafer test dataset containing the original coordinates and test results of each die, and receive the user-configured rotation angle, rotation center coordinates, and marker point coordinates; The rotation angle is checked for range, and the consistency deviation between the coordinates of the marked point and the geometric center of the wafer test dataset is checked. When the deviation exceeds a preset threshold, an confirmation signal is generated. The final rotation center is determined based on the rotation angle, the coordinates of the rotation center, and the response result of the confirmation signal. Using a single traversal method, the rotation formula is applied to each grain to calculate the rotated coordinates based on the final rotation center. During the traversal, the extreme values ​​of the rotated coordinates are updated synchronously, and the mapping relationship between the original coordinates, test results and the rotated coordinates of each grain is stored. Determine the minimum bounding rectangle that can contain all rotated coordinates based on the extreme value, and allocate memory for the minimum bounding rectangle; A multi-core block parallel processing method is adopted. Depending on whether the rotation angle is an integer multiple of the rotation, the lock-free direct write method or the thread local buffer merging method is selected to write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory. Based on the minimum bounding rectangle after writing the test results, output the rotated wafer test result image.

[0007] The beneficial effects of the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention are as follows: The method of this invention acquires a wafer test dataset and receives user-configured rotation angle, rotation center coordinates, and marker point coordinates. It performs range verification on the rotation angle and consistency deviation verification on the marker point coordinates and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated to determine the final rotation center. The method calculates the coordinates after rotation using a single traversal method and synchronously updates the extreme values ​​to store the mapping relationship. Based on the extreme values, the minimum bounding rectangle is determined and memory is allocated. Multi-core block parallel processing is used to select lock-free direct writing or thread-local buffer merging method according to the rotation angle type to write the test results into the minimum bounding rectangle. This method solves the problems of lack of synchronous verification of marker point position and rotation parameter validity before rotation, the disconnect between rotation compensation and parameter verification, and performance bottlenecks caused by multiple data traversals in the prior art. It improves the accuracy of wafer test pattern rotation compensation and the efficiency of automated processing.

[0008] Based on the above scheme, the wafer test pattern parameter legality verification and adaptive rotation compensation method of the present invention can be further improved as follows.

[0009] In an alternative approach, when the rotation angle is 90°, 180°, or 270°, the rotation formula does not use trigonometric functions, wherein: The formula for rotating 90° is: ; The formula for rotating 180° is: ; The transformation formula for rotating 270° is: ; and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center.

[0010] The advantages of adopting the above optional method are as follows: For rotation scenarios of integer multiples of 90°, 180° and 270°, the coordinates after rotation are directly calculated using coordinate transformation formulas without trigonometric functions, avoiding the precision loss and performance overhead caused by floating-point operations, and improving the calculation speed and coordinate mapping accuracy of integer multiple rotations.

[0011] In one alternative approach, when the final rotation center is a half-integer coordinate, the rotated coordinates are rounded to the nearest integer and mapped to discrete grain grid positions.

[0012] The advantages of adopting the above optional method are as follows: under the condition of half-integer rotation center, the rotated coordinates are mapped to discrete grain grid positions by rounding, which solves the alignment problem between non-integer coordinates and grain grids, and ensures the uniqueness and accuracy of the rotated grain positions in the grid coordinate system.

[0013] In an alternative approach, when the rotation angle is a non-integer multiple of the angle, the rotation formula is: in, and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center. The rotation angle is denoted as .

[0014] The advantages of adopting the above optional method are as follows: for non-integer multiple rotation angles, the standard rotation formula based on trigonometric functions is used to calculate the coordinates after rotation, which expands the applicable range of rotation compensation, so that accurate coordinate transformation results can be obtained for any angle rotation, and meets the correction needs of diverse wafer placement angles.

[0015] In one alternative approach, when multiple raw dies are mapped to the same target location, the test results are merged according to a preset priority rule; wherein the preset priority rule is that Pass is higher than Fail, Fail is higher than untested, or a conflict marker character is used to fill the target location.

[0016] The advantages of using the above optional method are: when multiple original dies are mapped to the same target position, the test results are merged by processing the preset priority rules or conflict marker characters, which avoids information loss caused by data overwriting and ensures the correctness and integrity of the test results at each position in the wafer test diagram after rotation.

[0017] In one alternative approach, the step of outputting the rotated wafer test result image includes: Output the character matrix and header information of the rotated wafer test result image. The header information includes the total number of chips, the number of Pass chips, and the number of Fail chips in the original wafer test dataset.

[0018] The advantages of using the above-mentioned optional method are: when outputting the wafer test result image after rotation, additional header information is added, including the total number of chips, the number of passed chips, and the number of failed chips, which facilitates subsequent quality statistical analysis and data traceability, and improves the readability and management convenience of wafer test data.

[0019] In one alternative approach, a multi-core block parallel processing method is employed. The step of writing the test results from the mapping relationship into the minimum bounding rectangle of the allocated memory, based on whether the rotation angle is an integer multiple of the rotation angle, includes either a lock-free direct write method or a thread-local buffer merging method. For integer multiple rotations, a lock-free direct write method is adopted, where different calculation threads directly write the test results to the corresponding coordinate positions of the minimum bounding rectangle; For rotations that are not integer multiples, a thread-local buffer merging method is adopted. Each calculation thread first writes the test results into the thread-local buffer, and then merges them into the minimum bounding rectangle after all threads have completed.

[0020] The advantages of adopting the above optional methods are as follows: further distinguishing the parallel write strategy according to the rotation angle type, using lock-free direct writing for integer multiple rotations, and using thread-local buffer merging for non-integer multiple rotations, avoiding thread conflicts and write competition, giving full play to the advantages of multi-core parallel processing, and improving data writing efficiency.

[0021] In one alternative approach, a single-pass traversal method is employed, where the rotation formula is applied to each grain based on the final rotation center to calculate the rotated coordinates, and the extreme values ​​of the rotated coordinates are updated synchronously during the traversal process. This includes: initialization , , , The rotation formula is applied to each grain to obtain the rotated coordinates. and Updated later: The width of the minimum bounding rectangle is The height is .

[0022] The advantages of adopting the above optional method are: further updating the extreme values ​​of the rotated coordinates synchronously during a single traversal, directly determining the size of the minimum bounding rectangle through dynamic maintenance of the minimum and maximum values, avoiding independent extreme value scanning traversal, reducing the number of data processing times, and improving the overall execution efficiency of rotation compensation.

[0023] Secondly, this invention provides a wafer test pattern parameter validity verification and adaptive rotation compensation system, the technical solution of which is as follows: The acquisition module is used to acquire a wafer test dataset containing the original coordinates and test results of each die, and to receive the rotation angle, rotation center coordinates and marker point coordinates configured by the user; The verification module is used to verify the range of the rotation angle and to verify the consistency deviation between the coordinates of the marker point and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated. The determining module is used to determine the final rotation center based on the rotation angle, the coordinates of the rotation center, and the response result of the confirmation signal; The traversal module is used to calculate the rotated coordinates of each grain by applying the rotation formula to each grain according to the final rotation center in a single traversal. During the traversal, the extreme values ​​of the rotated coordinates are updated synchronously, and the mapping relationship between the original coordinates of each grain, the test results and the rotated coordinates is stored. The allocation module is used to determine the minimum bounding rectangle that can contain all the rotated coordinates based on the extreme value, and to allocate memory for the minimum bounding rectangle; The writing module is used to write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory by adopting a multi-core block parallel processing method and selecting either a lock-free direct writing method or a thread-local buffer merging method according to whether the rotation angle is an integer multiple of the rotation. The output module is used to output the rotated wafer test result image based on the minimum bounding rectangle after the test results are written.

[0024] The beneficial effects of the wafer test pattern parameter validity verification and adaptive rotation compensation system of the present invention are as follows: The system of this invention acquires a wafer test dataset and receives user-configured rotation angle, rotation center coordinates, and marker point coordinates. It performs range verification on the rotation angle and consistency deviation verification on the marker point coordinates and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated to determine the final rotation center. The system calculates the coordinates after rotation using a single traversal method and synchronously updates the extreme values ​​to store the mapping relationship. Based on the extreme values, it determines the minimum bounding rectangle and allocates memory. It uses multi-core block parallel processing and selects either lock-free direct writing or thread-local buffer merging method according to the rotation angle type to write the test results into the minimum bounding rectangle. This solves the problems of lack of synchronous verification of marker point positions and rotation parameter validity before rotation, the disconnect between rotation compensation and parameter verification, and performance bottlenecks caused by multiple data traversals in the prior art. It improves the accuracy of wafer test pattern rotation compensation and the efficiency of automated processing.

[0025] Thirdly, the technical solution of an electronic device according to the present invention is as follows: It includes a memory, a processor, and a program stored in the memory and running on the processor, wherein the processor executes the program to implement the steps of the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention.

[0026] Fourthly, the technical solution of a computer-readable storage medium provided by the present invention is as follows: The computer-readable storage medium stores instructions that, when read, cause the computer-readable storage medium to perform the steps of the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention.

[0027] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0028] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a flowchart illustrating an embodiment of a wafer test pattern parameter validity verification and adaptive rotation compensation method according to the present invention. Figure 2 A schematic diagram of the dialog box for confirming the deviation between the user's marked point and the center point; Figure 3 A diagram illustrating the configuration file parameter settings; Figure 4This is a schematic diagram of an embodiment of the wafer test pattern parameter validity verification and adaptive rotation compensation system of the present invention; Figure 5 This is a schematic diagram of an embodiment of an electronic device according to the present invention. Detailed Implementation

[0029] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0030] Figure 1 This diagram illustrates a flowchart of an embodiment of a wafer test pattern parameter validity verification and adaptive rotation compensation method provided by the present invention. This method can be executed by electronic devices such as terminal devices or servers. The terminal device can be any fixed or mobile terminal, such as user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, vehicle-mounted device, or wearable device. The server can be a single server or a server cluster consisting of multiple servers. Any electronic device can implement the wafer test pattern parameter validity verification and adaptive rotation compensation method by having its processor call computer-readable instructions stored in its memory. Figure 1 As shown, it includes the following steps: S1. Obtain the wafer test dataset containing the original coordinates and test results of each die, and receive the user-configured rotation angle, rotation center coordinates, and marker point coordinates.

[0031] The original coordinates of a die refer to the x-coordinate and y-coordinate values ​​of each die in the original test data coordinate system within the wafer test dataset. For example, the original coordinates of a die are (100, 120), indicating that the die is located in the 100th column and 120th row of the original wafer diagram. The test result refers to the test status identifier obtained by each die during the test, used to indicate whether the die belongs to the category of pass, fail, or not tested. For example, a test result of "P" for a die indicates that the die passed the test.

[0032] The wafer test dataset refers to a complete set of data containing the original coordinates and corresponding test results of all valid dies on the wafer. For example, a test dataset of a 150 mm diameter wafer contains 52,921 dies, and each die records a set of original coordinates and a test result.

[0033] Here, rotation angle refers to the degree configured by the user for rotating and compensating the original wafer image; for example, configuring a rotation angle of 90° means rotating the original wafer image 90° clockwise. Rotation center coordinates refer to the x and y coordinates of the center point around which the rotation operation is performed in the original coordinate system; for example, configuring the rotation center coordinates as (139, 128) means that the rotation is centered on this point. Marker point coordinates refer to the position of a specific die used for auxiliary calibration in the original coordinate system; for example, defining the marker point coordinates as (251, 250) means that this marker point is located in column 251 and row 250 of the original wafer image.

[0034] S2. Perform range verification on the rotation angle and perform consistency deviation verification on the coordinates of the marked point and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, generate a confirmation signal.

[0035] The range check refers to checking whether the rotation angle configured by the user is a valid angle value between 0 degrees and 360 degrees. For example, if the user configures the rotation angle to be 90 degrees, the range check will pass; if it is configured to be 370 degrees, the range check will fail.

[0036] The geometric center refers to the coordinates of the center point of the region occupied by all valid dies in the wafer test dataset. For example, if the X-coordinate range of the original die is 0 to 278 and the Y-coordinate range is 0 to 256, the geometric center is (139, 128). Consistency deviation verification refers to calculating the positional difference between the marker point coordinates and the geometric center coordinates, and determining whether this difference exceeds the allowable range. For example, if the geometric center is (250, 250), the marker point coordinates are (251, 250), and the deviation is (1, 0), then if the preset threshold is 0, the deviation exceeds the threshold.

[0037] The preset threshold refers to the maximum allowable deviation between the coordinates of the marker point and the geometric center. For example, a preset threshold of 0 means that the marker point coordinates must be perfectly aligned with the geometric center to pass the verification. The confirmation signal is an instruction generated by the system to prompt the user to confirm whether to continue the rotation operation when the deviation between the marker point coordinates and the geometric center exceeds the preset threshold. For example, when the deviation exceeds the threshold, the system will display a dialog box and generate a confirmation signal.

[0038] S3. Determine the final rotation center based on the rotation angle, the coordinates of the rotation center, and the response result of the confirmation signal.

[0039] The response result refers to the user's choice in response to the confirmation signal, including confirming to continue or canceling the operation; for example, if the user clicks the "OK" button, the response result is confirmation; if the user clicks the "Cancel" button, the response result is cancellation. The final rotation center refers to the coordinates of the rotation center point used for calculating the rotation formula, which are finally determined based on the rotation center coordinates configured by the user and the response result of the confirmation signal; for example, if the user configures the rotation center coordinates as (139, 128) and the response result is confirmation, the final rotation center is (139, 128).

[0040] S4. Using a single traversal method, apply the rotation formula to each grain according to the final rotation center to calculate the rotated coordinates. During the traversal, update the extreme values ​​of the rotated coordinates synchronously, and store the original coordinates of each grain, the mapping relationship between the test results and the rotated coordinates.

[0041] The single-pass traversal method refers to accessing each die in the wafer test dataset only once, and completing coordinate transformation, extreme value update and mapping relationship storage operations simultaneously in a single loop; for example, processing each of the 52921 dies sequentially, with each die being processed only once.

[0042] The rotation formula refers to the mathematical expression used to calculate the new coordinates of a grain after rotating its original coordinates by a specified angle around the rotation center; for example, for rotations that are not integer multiples, the rotation formula is: The rotated coordinates refer to the new x-coordinate and y-coordinate values ​​obtained by calculating the original coordinates of the grain using the rotation formula; for example, the original coordinates (100, 120) are rotated 90 degrees around the center (139, 128), and the rotated coordinates are (147, 91).

[0043] The extreme values ​​refer to the minimum, maximum, minimum, and maximum x-coordinates, y-coordinates, and y-coordinates among all rotated coordinates during a single traversal; for example, after the traversal is completed, we get... , , , The mapping relationship refers to the corresponding record between the original coordinates, test results and the corresponding rotated coordinates of each grain; for example, the mapping relationship of a grain is the original coordinates (100, 120), test result "P", and rotated coordinates (147, 91).

[0044] S5. Determine the smallest bounding rectangle that can contain all the rotated coordinates based on the extreme value, and allocate memory for the smallest bounding rectangle.

[0045] The minimum bounding rectangle refers to the smallest rectangular region that can contain all the rotated coordinate points, with a width of [missing value]. The height is For example, based on the extreme values ​​-128, 149, -139, and 138, the minimum bounding rectangle width is... The height is .

[0046] S6. Using a multi-core block parallel processing method, depending on whether the rotation angle is an integer multiple of the rotation, select either lock-free direct write method or thread-local buffer merging method, and write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory.

[0047] The multi-core block parallel processing method refers to a parallel computing method that utilizes multiple computing threads of a multi-core CPU to divide the wafer test dataset into multiple contiguous data blocks, with each thread independently processing one data block. For example, 52,921 dies can be divided into 10 data blocks by row, with each block processed by an independent CPU thread. Integer multiple rotation refers to rotation operations with angles that are integer multiples of 90 degrees, such as 90 degrees, 180 degrees, or 270 degrees. For example, a user-configured rotation angle of 90 degrees is considered an integer multiple rotation.

[0048] The lock-free direct write method refers to a write strategy where, during integer multiple rotations, multiple threads directly write test results to the corresponding location in the target memory without the need for locking synchronization, since there are no multiple source dies mapped to the same target location. For example, during a 90° rotation, each thread directly writes the "P" or "F" character to the specified position in the character matrix. The thread-local buffer merging method refers to a write strategy where, during non-integer multiple rotations, each thread first writes its calculation results to its own independent temporary buffer. After all threads have completed their work, the results from each buffer are merged into the final memory according to conflict resolution rules. For example, during a 2° rotation, each thread maintains a local character matrix, which is then merged uniformly.

[0049] S7. Based on the minimum bounding rectangle after writing the test results, output the rotated wafer test result diagram.

[0050] The rotated wafer test result image refers to the wafer image data file output after filling all the test results of all the dies into the smallest bounding rectangle according to the rotated coordinates and adding header information; for example, outputting a character matrix of 278 rows and 278 columns, with each position filled with the character "P", "F" or a space.

[0051] The technical solution of this embodiment acquires a wafer test dataset and receives user-configured rotation angle, rotation center coordinates, and marker point coordinates. It performs range verification on the rotation angle and consistency deviation verification on the marker point coordinates and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated to determine the final rotation center. The coordinates after rotation are calculated using a single traversal method, and extreme values ​​are updated synchronously to store the mapping relationship. The minimum bounding rectangle is determined based on the extreme values ​​and memory is allocated. Multi-core block parallel processing is used to select lock-free direct writing or thread-local buffer merging method according to the rotation angle type to write the test results into the minimum bounding rectangle. This solves the problems of lack of synchronous verification of marker point position and rotation parameter validity before rotation, the disconnect between rotation compensation and parameter verification, and performance bottlenecks caused by multiple data traversals in the prior art. It improves the accuracy of wafer test pattern rotation compensation and the efficiency of automated processing.

[0052] Compared with existing fixed-angle rotation or template matching strategies, this embodiment completes parameter validity warning through consistency deviation verification and confirmation signals before rotation, avoiding mapping deviation caused by misalignment of marker points after rotation; at the same time, it adopts single traversal and dynamic minimum bounding rectangle allocation, eliminating the performance loss caused by multiple traversals, and realizing integrated processing of rotation compensation and parameter verification.

[0053] In an alternative approach, when the rotation angle is 90°, 180°, or 270°, the rotation formula does not use trigonometric functions, wherein: The formula for rotating 90° is: ; The formula for rotating 180° is: ; The transformation formula for rotating 270° is: ; and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center.

[0054] Among the above optional methods, for rotation scenarios of integer multiples of 90°, 180° and 270°, a coordinate transformation formula without trigonometric functions is used to directly calculate the coordinates after rotation, avoiding the precision loss and performance overhead caused by floating-point operations, and improving the calculation speed and coordinate mapping accuracy of integer multiple rotations.

[0055] In one alternative approach, when the final rotation center is a half-integer coordinate, the rotated coordinates are rounded to the nearest integer and mapped to discrete grain grid positions.

[0056] In this context, half-integer coordinates refer to coordinates that are integers plus 0.5, such as 139.5 or 128.5. When the wafer size is even, the geometric center may be located between two grains, forming half-integer coordinates. Discrete grain grid positions refer to the location units of each grain in the wafer diagram, represented by integer coordinates. For example, after rotation, the coordinates (147.2, 91.7) are rounded to the nearest integer and mapped to the discrete grain grid position (147, 92).

[0057] In the above-mentioned optional methods, under the condition of a half-integer rotation center, the rotated coordinates are mapped to discrete grain grid positions by rounding, which solves the alignment problem between non-integer coordinates and grain grids and ensures the uniqueness and accuracy of the rotated grain positions in the grid coordinate system.

[0058] In an alternative approach, when the rotation angle is a non-integer multiple of the angle, the rotation formula is: in, and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center. The rotation angle is denoted as .

[0059] Among the above optional methods, for non-integer multiple rotation angles, the standard rotation formula based on trigonometric functions is used to calculate the coordinates after rotation, which expands the applicability of rotation compensation and enables accurate coordinate transformation results to be obtained for any angle rotation, meeting the correction needs of diverse wafer placement angles.

[0060] In one alternative approach, when multiple raw dies are mapped to the same target location, the test results are merged according to a preset priority rule; wherein the preset priority rule is that Pass is higher than Fail, Fail is higher than untested, or a conflict marker character is used to fill the target location.

[0061] The target position refers to the unique grid cell within the smallest bounding rectangle after rotation, determined by the rounding of a certain rotated coordinate. For example, the target position corresponding to the rotated coordinates (147, 91) is the 91st row and 147th column of the character matrix.

[0062] The preset priority rule refers to the rule that when multiple original dies are mapped to the same target location, the result to be retained is determined according to the predefined test result level. For example, the preset priority rule is that "P" is higher than "F" and "F" is higher than untested. If two dies are mapped to the same location, the die with the test result "P" will cover the die with the test result "F".

[0063] In the above-mentioned optional methods, when multiple original dies are mapped to the same target position, the test results are merged by processing the data through preset priority rules or conflict marker characters, which avoids information loss caused by data overwriting and ensures the correctness and integrity of the test results at each position in the wafer test diagram after rotation.

[0064] In one alternative approach, the step of outputting the rotated wafer test result image includes: Output the character matrix and header information of the rotated wafer test result image. The header information includes the total number of chips, the number of Pass chips, and the number of Fail chips in the original wafer test dataset.

[0065] The character matrix refers to character data stored as a two-dimensional array. Each array element corresponds to a grid position in the rotated wafer image, storing the test result character for the die at that position. For example, a 278-row, 278-column character matrix where each element is "P", "F", or a space. The header information refers to the descriptive data lines in the output file preceding the character matrix, used to explain the statistical information and coordinate range of the wafer test dataset. For example, the header information includes the maximum die coordinates, the total number of tested dies, the number of passed dies, and the number of failed dies.

[0066] The total number of chips refers to the number of all valid chips in the wafer test dataset; for example, in a test dataset for a 150 mm diameter wafer, the total number of chips is 52921. The number of Pass chips refers to the number of chips whose test result is marked "P" (indicating pass); for example, out of 52921 chips, the number of Pass chips is 52407. The number of Fail chips refers to the number of chips whose test result is marked "F" (indicating failure); for example, out of 52921 chips, the number of Fail chips is 514.

[0067] In the above-mentioned optional methods, header information is further added when outputting the wafer test result diagram after rotation, including the total number of chips, the number of passed chips, and the number of failed chips, which facilitates subsequent quality statistical analysis and data traceability, and improves the readability and management convenience of wafer test data.

[0068] In one alternative approach, a multi-core block parallel processing method is employed. The step of writing the test results from the mapping relationship into the minimum bounding rectangle of the allocated memory, based on whether the rotation angle is an integer multiple of the rotation angle, includes either a lock-free direct write method or a thread-local buffer merging method. For rotations that are multiples of an integer, a lock-free direct write method is used, where different calculation threads directly write the test results to the corresponding coordinate positions of the minimum bounding rectangle.

[0069] For rotations that are not integer multiples, a thread-local buffer merging method is adopted. Each calculation thread first writes the test results into the thread-local buffer, and then merges them into the minimum bounding rectangle after all threads have completed.

[0070] Among the above optional methods, the parallel write strategy is further differentiated according to the rotation angle type. Integer multiple rotations adopt lock-free direct write, while non-integer multiple rotations adopt thread-local buffer merging, which avoids thread conflicts and write competition, fully leverages the advantages of multi-core parallel processing, and improves data writing efficiency.

[0071] In one alternative approach, a single-pass traversal method is employed, where the rotation formula is applied to each grain based on the final rotation center to calculate the rotated coordinates, and the extreme values ​​of the rotated coordinates are updated synchronously during the traversal process. This includes: initialization , , , The rotation formula is applied to each grain to obtain the rotated coordinates. and Updated later: The width of the minimum bounding rectangle is The height is .

[0072] In the above-mentioned optional methods, the extreme values ​​of the rotated coordinates are updated synchronously during a single traversal. The minimum bounding rectangle size is directly determined by dynamically maintaining the minimum and maximum values, avoiding independent extreme value scanning traversal, reducing the number of data processing operations, and improving the overall execution efficiency of rotation compensation.

[0073] In another embodiment of the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention, the following are included: like Figure 2As shown, when the deviation between the user-defined marker point coordinates and the geometric center of the wafer test dataset exceeds a preset threshold, a confirmation signal is generated and a confirmation dialog box pops up. The dialog box displays the message "Map location point coordinates (250, 250) are inconsistent with the default Mark point (251, 250)," and provides three options: use custom Mark coordinates (251, 250), use Map file Mark coordinates (250, 250), or specify other coordinates. "OK" and "Cancel" buttons are located at the bottom of the dialog box. Clicking "OK" continues the rotation compensation process based on the selected marker point coordinates; clicking "Cancel" terminates the conversion and outputs a log message. The left side of the dialog box lists the Map directories and files to be converted, such as "001.AS4FN6.1-01" to "013.AS4FN6.1-13," allowing users to select the wafer test data files to be processed.

[0074] like Figure 3 As shown, users set rotation parameters and other related parameters in the configuration file. The configuration file contains the following: DefaultPath=D:\mapout specifies the output path, RotationAngle=2.0 sets the rotation angle to 2.0 degrees, DisplayType=2 sets the display type, SpecialBinMark=$ defines a special Bin marker symbol, SkipDie=: defines a skipped die symbol, Bin0Symbol=. defines the Bin0 symbol, Bin35Symbol=@ defines the Bin35 symbol, PassMode_PassSym=P defines the pass die symbol as "P", PassMode_FailSym=F defines the fail die symbol as "F", PassBinandFailDieFlag=F sets the pass and fail die flags, MarkFlag=* defines the marker symbol, CheckSpecilSymbol=True enables special symbol checking, SkipDieFlag=: defines the skipped die flag, and NullDieFlag=. defines the null die symbol.

[0075] After reading the configuration file, the rotation angle is first validated within a certain range: 2.0° falls within the range of 0° to 360°, so the validation passes. Since the user did not define the marker point coordinates in the configuration file, the consistency deviation check between the marker point coordinates and the geometric center is skipped. This embodiment also checks whether the number of valid dies matches the system configuration. If the number of dies is inconsistent or empty, the conversion is aborted and an error log is output. The rotation center uses an automatic geometric center mode, which calculates the geometric center based on the coordinate range of all valid dies in the wafer test dataset. The calculation formula is as follows: , .

[0076] Subsequently, adaptive coordinate mapping is performed. Using a single-pass approach, the rotation formula is applied to each die in the wafer test dataset to calculate the rotated coordinates. For a non-integer multiple of the rotation angle 2.0°, the rotation formula is: in, and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center. The rotation angle is 2.0°. During the traversal, the extreme values ​​of the rotated coordinates, i.e., the minimum x-coordinate, are updated synchronously. Maximum x-coordinate Minimum y-coordinate and maximum ordinate It also stores the mapping relationship between the original coordinates of each grain, the test results, and the coordinates after rotation.

[0077] Based on the extreme values ​​obtained through traversal, determine the minimum bounding rectangle that can contain all rotated coordinates. The width of the minimum bounding rectangle is... The height is The system dynamically allocates memory for this minimum bounding rectangle.

[0078] The data writing phase employs a multi-core block parallel processing approach. Since 2.0° is not an integer multiple of rotation (i.e., not 90°, 180°, or 270°), a thread-local buffer merging method is chosen. The raw die list is divided into multiple data blocks according to continuous coordinate intervals, with each computation thread processing one data block independently. Each thread first writes the calculated test results into its own independent thread-local buffer. After all threads have finished processing, the results from each buffer are merged into the final minimum bounding rectangle according to preset conflict resolution rules. When multiple raw dies map to the same target location, the test results are merged according to preset priority rules. The preset priority rule is that "P" (pass) is higher than "F" (failure), and "F" is higher than untested. Users can also define conflict marker characters, such as filling conflict locations with "X". If there is no die mapping at the target location, an empty symbol is used.

[0079] Finally, the rotated wafer test results are output. The output file includes a character matrix and header information. The header information contains the total number of dies in the original wafer test dataset, the number of passed dies, and the number of failed dies. Each position in the character matrix stores the test result character for the corresponding die, such as "P", "F", or a space.

[0080] The entire processing, from user execution to result output, takes only 2 seconds. For rotations that are multiples of 90°, 180°, or 270°, a coordinate transformation formula without trigonometric functions is used. For example, the formula for rotating 90° is... , The processing time can be reduced to 0.2 seconds. Compared to the traditional method (which requires 2 to 3 full data traversals and takes about 6 seconds for 52,921 chips), the processing speed of this embodiment is improved by about 7 times, and memory usage is reduced by about 30% to 50%.

[0081] Figure 4 This diagram illustrates a structural schematic of an embodiment of a wafer test pattern parameter validity verification and adaptive rotation compensation system 200 provided by the present invention. Figure 4 As shown, the wafer test pattern parameter validity verification and adaptive rotation compensation system 200 includes: The acquisition module 201 is used to acquire a wafer test dataset containing the original coordinates and test results of each die, and to receive the rotation angle, rotation center coordinates and marker point coordinates configured by the user. The verification module 202 is used to perform range verification on the rotation angle and to perform consistency deviation verification on the coordinates of the marker point and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated. The determining module 203 is used to determine the final rotation center based on the rotation angle, the rotation center coordinates, and the response result of the confirmation signal; The traversal module 204 is used to calculate the rotated coordinates of each grain by applying the rotation formula according to the final rotation center in a single traversal method. During the traversal, the extreme values ​​of the rotated coordinates are updated synchronously, and the mapping relationship between the original coordinates of each grain, the test results and the rotated coordinates is stored. The allocation module 205 is used to determine the minimum bounding rectangle that can contain all the rotated coordinates based on the extreme value, and to allocate memory for the minimum bounding rectangle; The writing module 206 is used to write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory by adopting a multi-core block parallel processing method and selecting either a lock-free direct writing method or a thread-local buffer merging method according to whether the rotation angle is an integer multiple of the rotation. The output module 207 is used to output a rotated wafer test result image based on the minimum bounding rectangle after the test results are written.

[0082] In an alternative approach, when the rotation angle is 90°, 180°, or 270°, the rotation formula does not use trigonometric functions, wherein: The formula for rotating 90° is: ; The formula for rotating 180° is: ; The transformation formula for rotating 270° is: ; and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center.

[0083] In one alternative approach, when the final rotation center is a half-integer coordinate, the rotated coordinates are rounded to the nearest integer and mapped to discrete grain grid positions.

[0084] In an alternative approach, when the rotation angle is a non-integer multiple of the angle, the rotation formula is: in, and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center. The rotation angle is denoted as .

[0085] In one alternative approach, when multiple raw dies are mapped to the same target location, the test results are merged according to a preset priority rule; wherein the preset priority rule is that Pass is higher than Fail, Fail is higher than untested, or a conflict marker character is used to fill the target location.

[0086] In an alternative embodiment, the output module 207 is specifically used for: Output the character matrix and header information of the rotated wafer test result image. The header information includes the total number of chips, the number of Pass chips, and the number of Fail chips in the original wafer test dataset.

[0087] In an alternative embodiment, the writing module 206 is specifically used for: For integer multiple rotations, a lock-free direct write method is adopted, where different calculation threads directly write the test results to the corresponding coordinate positions of the minimum bounding rectangle; For rotations that are not integer multiples, a thread-local buffer merging method is adopted. Each calculation thread first writes the test results into the thread-local buffer, and then merges them into the minimum bounding rectangle after all threads have completed.

[0088] In one alternative approach, a single-pass traversal method is employed, where the rotation formula is applied to each grain based on the final rotation center to calculate the rotated coordinates, and the extreme values ​​of the rotated coordinates are updated synchronously during the traversal process. This includes: initialization , , , The rotation formula is applied to each grain to obtain the rotated coordinates. and Updated later: The width of the minimum bounding rectangle is The height is .

[0089] It should be noted that the beneficial effects of the wafer test pattern parameter validity verification and adaptive rotation compensation system 200 provided in the above embodiments are the same as those of the wafer test pattern parameter validity verification and adaptive rotation compensation method described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0090] The wafer test pattern parameter validity verification and adaptive rotation compensation system 200 of the present invention can be a computer program (including program code) running on a computer device. For example, the wafer test pattern parameter validity verification and adaptive rotation compensation system 200 of the present invention is an application software that can be used to execute the corresponding steps in the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention.

[0091] In some embodiments, the wafer test pattern parameter validity verification and adaptive rotation compensation system 200 of the present invention can be implemented in a combination of hardware and software. As an example, the wafer test pattern parameter validity verification and adaptive rotation compensation system 200 of the present invention can be a processor in the form of a hardware decoding processor, which is programmed to execute the wafer test pattern parameter validity verification and adaptive rotation compensation method of the present invention. For example, the processor in the form of a hardware decoding processor can be one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0092] The modules described in the embodiments of this invention can be implemented in software or hardware. The names of the modules are not, in some cases, limiting the scope of the module itself.

[0093] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the above-mentioned wafer test pattern parameter validity verification and adaptive rotation compensation methods. That is, an electronic device according to an embodiment of the present invention may include, but is not limited to: a processor and a memory; the memory is used to store the computer program; the processor is used to execute the wafer test pattern parameter validity verification and adaptive rotation compensation method shown in any embodiment of the present invention by calling the computer program.

[0094] In one alternative embodiment, an electronic device is provided, such as Figure 5 As shown, Figure 5 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0095] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0096] Bus 4002 may include a path for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus 4002 is represented by only one thick line, but this does not mean that there is only one bus or one type of bus.

[0097] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0098] The memory 4003 stores application code (computer program) for executing the present invention, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0099] Among them, electronic devices can also be terminal devices. A terminal device can be any terminal device that can install applications and access web pages through applications, including at least one of smartphones, tablets, laptops, desktop computers, smart speakers, smartwatches, smart TVs, and smart in-vehicle devices.

[0100] It should be noted that, Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0101] An embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-mentioned wafer test pattern parameter validity verification and adaptive rotation compensation methods.

[0102] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0103] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the aforementioned wafer test pattern parameter validity verification and adaptive rotation compensation method.

[0104] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] It should be understood that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0106] The computer-readable storage medium provided in this invention can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0107] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the method shown in the above embodiments.

[0108] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0109] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0110] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this invention can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, this invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0111] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for validating the validity of wafer test pattern parameters and adaptive rotation compensation, characterized in that, include: Obtain a wafer test dataset containing the original coordinates and test results of each die, and receive the user-configured rotation angle, rotation center coordinates, and marker point coordinates; The rotation angle is checked for range, and the consistency deviation between the coordinates of the marked point and the geometric center of the wafer test dataset is checked. When the deviation exceeds a preset threshold, an confirmation signal is generated. The final rotation center is determined based on the rotation angle, the coordinates of the rotation center, and the response result of the confirmation signal. Using a single traversal method, the rotation formula is applied to each grain to calculate the rotated coordinates based on the final rotation center. During the traversal, the extreme values ​​of the rotated coordinates are updated synchronously, and the mapping relationship between the original coordinates, test results and the rotated coordinates of each grain is stored. Determine the minimum bounding rectangle that can contain all rotated coordinates based on the extreme value, and allocate memory for the minimum bounding rectangle; A multi-core block parallel processing method is adopted. Depending on whether the rotation angle is an integer multiple of the rotation, the lock-free direct write method or the thread local buffer merging method is selected to write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory. Based on the minimum bounding rectangle after writing the test results, output the rotated wafer test result image.

2. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, When the rotation angle is 90°, 180°, or 270°, the rotation formula does not use trigonometric functions, where: The formula for rotating 90° is: ; The formula for rotating 180° is: ; The transformation formula for rotating 270° is: ; and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center.

3. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, When the final rotation center is a half-integer coordinate, the rotated coordinates are rounded to the nearest integer and mapped to discrete grain grid positions.

4. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, When the rotation angle is not an integer multiple of the angle, the rotation formula is: in, and These are the original coordinates of the grain. and The coordinates are after rotation. and Let x and y be the x and y coordinates of the final rotation center. The rotation angle is denoted as .

5. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 4, characterized in that, When multiple original dies are mapped to the same target location, the test results are merged according to a preset priority rule; wherein, the preset priority rule is that Pass is higher than Fail, Fail is higher than untested, or, conflict marker characters are used to fill the target location.

6. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, The steps for outputting the test results image of the rotated wafer include: Output the character matrix and header information of the rotated wafer test result image. The header information includes the total number of chips, the number of Pass chips, and the number of Fail chips in the original wafer test dataset.

7. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, The step of writing the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory, using a multi-core block parallel processing approach and selecting either a lock-free direct write method or a thread-local buffer merging method based on whether the rotation angle is an integer multiple of the rotation angle, includes: For integer multiple rotations, a lock-free direct write method is adopted, where different calculation threads directly write the test results to the corresponding coordinate positions of the minimum bounding rectangle; For rotations that are not integer multiples, a thread-local buffer merging method is adopted. Each calculation thread first writes the test results into the thread-local buffer, and then merges them into the minimum bounding rectangle after all threads have completed.

8. The wafer test pattern parameter validity verification and adaptive rotation compensation method according to claim 1, characterized in that, The method employs a single traversal approach, calculating the rotated coordinates of each grain using the rotation formula based on the final rotation center, and synchronously updating the extreme values ​​of the rotated coordinates during the traversal process, including: initialization , , , The rotation formula is applied to each grain to obtain the rotated coordinates. and Updated later: The width of the minimum bounding rectangle is The height is .

9. A wafer test pattern parameter validity verification and adaptive rotation compensation system, characterized in that, include: The acquisition module is used to acquire a wafer test dataset containing the original coordinates and test results of each die, and to receive the rotation angle, rotation center coordinates and marker point coordinates configured by the user; The verification module is used to verify the range of the rotation angle and to verify the consistency deviation between the coordinates of the marker point and the geometric center of the wafer test dataset. When the deviation exceeds a preset threshold, a confirmation signal is generated. The determining module is used to determine the final rotation center based on the rotation angle, the coordinates of the rotation center, and the response result of the confirmation signal; The traversal module is used to calculate the rotated coordinates of each grain by applying the rotation formula to each grain according to the final rotation center in a single traversal. During the traversal, the extreme values ​​of the rotated coordinates are updated synchronously, and the mapping relationship between the original coordinates of each grain, the test results and the rotated coordinates is stored. The allocation module is used to determine the minimum bounding rectangle that can contain all the rotated coordinates based on the extreme value, and to allocate memory for the minimum bounding rectangle; The writing module is used to write the test results in the mapping relationship into the minimum bounding rectangle of the allocated memory by adopting a multi-core block parallel processing method and selecting either a lock-free direct writing method or a thread-local buffer merging method according to whether the rotation angle is an integer multiple of the rotation. The output module is used to output the rotated wafer test result image based on the minimum bounding rectangle after the test results are written.

10. An electronic device, characterized in that, The electronic device includes a processor coupled to a memory, the memory storing at least one computer program, which is loaded and executed by the processor to enable the electronic device to implement the wafer test pattern parameter validity verification and adaptive rotation compensation method as described in any one of claims 1 to 8.

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