Semiconductor inspection apparatus and method

Abstract

Embodiments of the present application relate to a semiconductor inspection apparatus and an inspection method. A semiconductor inspection apparatus and an inspection method that grasp the inclination of a dislocation line within a wafer over a wide range are provided. The semiconductor inspection apparatus of the embodiments includes an acquisition unit, a detection unit, an analysis unit, and a classification unit. The acquisition unit acquires an image of a wafer by photographing the wafer. The detection unit detects a first coordinate of a threading dislocation appearing on the back surface of the wafer and a second coordinate of the threading dislocation appearing on the surface of the wafer based on the image. The analysis unit analyzes the inclination of a dislocation line of the threading dislocation with respect to the thickness direction of the wafer based on the first coordinate and the second coordinate and the thickness of the wafer. The classification unit classifies the threading dislocation based on the analysis result.

Description

[0001] This application is based on Japanese Patent Application 2025-045766 (filed on March 19, 2025), and enjoys priority benefits from that application. The entire contents of that application are incorporated herein by reference. Technical Field

[0002] The implementation methods relate to semiconductor inspection apparatus and inspection methods. Background Technology

[0003] During the crystal growth of a semiconductor single-crystal ingot, multiple dislocation lines propagate in a roughly linear fashion from the seed crystal side at various angles of inclination. Some of these dislocation lines are through-screw dislocations (TSDs), and some are mixed dislocations (TMDs). These various through-dislocations are contained within the wafer diced from the single-crystal ingot. These through-dislocations affect the quality of the semiconductor device formed on the wafer and can potentially have adverse effects. Therefore, in semiconductor inspection equipment, the distribution and density of through-dislocations on the wafer are inspected before forming the semiconductor device on the wafer.

[0004] While the semiconductor inspection apparatus described above has no particular problems, according to the inventors' research, from the viewpoint of classifying through dislocations that are highly likely to adversely affect semiconductor devices, it is desirable to be able to determine the inclination of the dislocation line of through dislocations. Here, methods for determining the inclination of the dislocation line include, for example, cross-sectional TEM (Transmission Electron Microscope) and multiphoton-excitation photoluminescence (MPPL). Cross-sectional TEM is a method that obtains a cross-sectional image of a sample by incident an electron beam onto the sample and analyzing the electron beam transmitted through the sample. Multiphoton-excitation photoluminescence is a method that obtains a fluorescence image deep within the sample by incident a pulsed laser onto the sample while controlling the focal position, and analyzing the fluorescence emitted from the sample.

[0005] However, these methods all measure deep within the sample, resulting in a narrow measurement range, making it difficult to determine the tilt of dislocation lines within a wafer over a large area. Summary of the Invention

[0006] The problem to be solved by the present invention is to provide a semiconductor inspection device and inspection method that can measure the tilt of dislocation lines within a wafer over a wide range.

[0007] The semiconductor inspection apparatus of this embodiment includes an acquisition unit, a detection unit, an analysis unit, and a classification unit. The acquisition unit acquires an image of the wafer by photographing it. Based on the image, the detection unit detects a first coordinate of a through-dislocation occurring on the back side of the wafer and a second coordinate of a through-dislocation occurring on the surface of the wafer. The analysis unit analyzes the inclination of the dislocation line of the through-dislocation relative to the thickness direction of the wafer based on the first and second coordinates and the thickness of the wafer. The classification unit classifies the through-dislocations based on the analysis results.

[0008] The semiconductor inspection device with the above structure can determine the tilt of dislocation lines within a wafer over a wide range. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a configuration example of the semiconductor inspection apparatus according to the first embodiment.

[0010] Figure 2 This is a schematic diagram representing an example of an ingot.

[0011] Figure 3 This is a schematic diagram representing an example of a wafer.

[0012] Figure 4 This is a schematic diagram used to illustrate the orientation of a wafer.

[0013] Figure 5 It means Figure 1 A block diagram illustrating the configuration of a shooting device.

[0014] Figure 6 It means Figure 1 A block diagram illustrating the configuration of a computer.

[0015] Figure 7 It means Figure 1 A block diagram illustrating the structure of a database.

[0016] Figure 8 This is a flowchart used to illustrate an example of an action in the first embodiment.

[0017] Figure 9 This is a schematic diagram used to illustrate an example of operation in the first embodiment.

[0018] Figure 10 This is a schematic diagram used to illustrate an example of operation in the first embodiment.

[0019] Figure 11 This is a schematic diagram used to illustrate an example of operation in the first embodiment.

[0020] Figure 12 This is a schematic diagram used to illustrate an example of operation in the first embodiment.

[0021] Figure 13 This is a schematic diagram used to illustrate an example of operation in the first embodiment.

[0022] Figure 14 This is a block diagram illustrating the configuration of the imaging device in a first variation of the first embodiment.

[0023] Figure 15 This is a block diagram illustrating the configuration of the imaging device in a second variation of the first embodiment.

[0024] Figure 16A This is a block diagram illustrating an example of the configuration of the imaging device included in the semiconductor inspection apparatus of the second embodiment.

[0025] Figure 16B This is a block diagram illustrating other configuration examples of the imaging device included in the semiconductor inspection apparatus of the second embodiment.

[0026] Figure 17 This is a schematic diagram used to illustrate an example of operation in the second embodiment.

[0027] Figure 18 This is a schematic diagram used to illustrate an example of operation in the second embodiment.

[0028] Figure 19 This is a schematic diagram illustrating a first variation of the operation in the second embodiment.

[0029] Figure 20 This is a schematic diagram illustrating a second variation of the operation in the second embodiment.

[0030] Figure 21 This is a schematic diagram illustrating a second variation of the operation in the second embodiment.

[0031] Figure 22 This is a schematic diagram illustrating a third variation of the operation in the second embodiment.

[0032] Figure 23 This is a schematic diagram illustrating a fourth variation of the operation in the second embodiment.

[0033] Figure 24 This is a schematic diagram illustrating a fifth variation of the operation in the second embodiment. Detailed Implementation

[0034] Hereinafter, illustrative descriptions of various embodiments will be provided with reference to the accompanying drawings. In the following description, elements having the same function and structure will be labeled with the same reference numerals. In addition, in the following embodiments, for components labeled with reference numerals / letters at the end for distinction (e.g., imaging device, wafer, etc.), where they can be used without distinction, descriptions with the numerals / letters at the end will be used (refer to the reference numerals).

[0035] <First Implementation Method> Figure 1 This is a block diagram illustrating a configuration example of the semiconductor inspection apparatus according to the first embodiment. The semiconductor inspection apparatus 100 includes an imaging device 1, a computer 2, and a database 3.

[0036] The imaging device 1 captures an image of the wafer 9 being non-destructively inspected, generating an image of the wafer 9. The wafer 9 is a semiconductor wafer obtained from a single-crystal ingot of semiconductors, such as a silicon carbide (SiC) wafer that transmits visible light. However, the wafer 9 can also be a gallium nitride (GaN) or diamond (C) wafer. Furthermore, the wafer 9 can be a silicon (Si) wafer.

[0037] Here, use in advance Figures 2 to 4 The description of wafer 9 and ingot is provided. Figure 2 In the ingot 900, a semiconductor crystal 90 is formed by growing a semiconductor crystal 90 on a seed crystal 99. The ingot 900 contains multiple through dislocations 999. These through dislocations 999 originate from defects in the seed crystal 99. As the semiconductor crystal 90 grows, the through dislocations 999 extend substantially linearly from the seed crystal 99 side toward the growth end of the ingot 900 at an angle relative to the surface of the seed crystal 99, according to the diameter of the ingot 900 (the diameter of the wafer). Multiple wafers 9 (9A, 9B) are cut from the ingot 900 by slicing it.

[0038] For example, to determine the position of wafer 9 within ingot 900, wafer 9 has an identification number corresponding to its distance from seed crystal 99. For example, wafer 9A has an identification number ID. <m>Wafer 9B has an identification number ID. <n>m and n are integers greater than or equal to 1. m has a value different from n.

[0039] Identification ID <m>Wafer 9A was used to inspect for through-dislocation 999 within the wafer. Furthermore, within ingot 900, from which multiple wafers 9 were cut, a certain identification number ID... <m>Wafers other than wafer 9A may also be exempt from being photographed by imaging device 1. The identification number ID in ingot 900... <m>The portion outside the corresponding location is called the uninspected area 910. Wafers 9 cut from the uninspected area 910 are excluded from the imaging targets of the imaging device 1.

[0040] Figure 3 This is a schematic diagram used to illustrate wafer 9. Figure 3 The image shows the upper surface (XY plane) of wafer 9 as viewed from the growth direction (Z direction) of the ingot (wafer). Wafer 9 can be either a bulk wafer (semiconductor substrate) cut and ground from ingot 900, or an epitaxial wafer obtained by epitaxial growth on the bulk wafer to form a semiconductor layer as part of a semiconductor device. Figure 3 The diagram hypothetically illustrates a chip region 950 based on chip layout information and an orientation plane 9f representing a specified orientation. An orientation plane is an abbreviation for an orientation plane. A wafer 9 includes multiple chip regions 950. A dicing region 959 is disposed within the wafer 9 to surround the chip regions 950. By dicing the wafer 9 along the dicing region 959, each chip region 950 is made an independent semiconductor chip (semiconductor device). Furthermore, through-dislocations 999 directly below or near the active region where semiconductor devices (MOSFETs, IGBTs, etc.) are formed within the chip region 950 have a higher risk of becoming a cause of semiconductor device defects. In contrast, through-dislocations 999 within regions of the wafer 9 that do not contribute to the characteristics of power devices (e.g., component isolation regions or dicing regions 959) have a lower risk of becoming a cause of semiconductor device defects.

[0041] Figure 4 This is a schematic diagram used to illustrate the orientation of wafer 9. Figure 4 In (a), with Figure 3 Similarly, for wafer 9, the upper surface (XY plane) is shown as viewed from the growth direction (Z direction). In SiC wafer 9, an X direction perpendicular to the Z direction is [11-20], and a Y direction perpendicular to both the Z and X directions is [-1100]. In this case, the angles relative to the X direction in the XY plane and the directions in wafer 9 can be labeled correspondingly. For example, an angle of 0° relative to the X direction in the XY plane can be labeled as the [11-20] direction. Furthermore, in Figure 4 In the [11-20] direction, the "-" symbol indicates a horizontal bar above the number "2" immediately following the "-". The same applies to the markings for other directions.

[0042] Furthermore, an angle of 30° relative to the X direction in the XY plane can be labeled as the [01-10] direction. Similarly, angles of 60°, 90°, 120°, 150°, 180°, 210°, 240°, 270°, 300°, and 330° relative to the X direction in the XY plane can be labeled as the [-12-10] direction, [-1100] direction, "-2110" direction, "-1010" direction, "-1-120" direction, "0-110" direction, "1-210" direction, "1-100" direction, "2-1-10" direction, and "10-10" direction, respectively. The "1-100" direction corresponding to the angle 270° is the direction shown on orientation surface 9f. Additionally, the angle 360° is the same as the angle 0° and can be labeled as the [11-20] direction. Such angles and directions can be appropriately changed, for example, by pre-establishing associations in the storage device 24.

[0043] Furthermore, the [2-1-10] direction corresponding to this angle of 300° can also be called the a1 axis direction. Similarly, the [-12-10] direction corresponding to this angle of 60° can also be called the a2 axis direction. The [-1-120] direction corresponding to this angle of 180° can also be called the a3 axis direction. The a1, a2, and a3 axes intersect each other at an angle of 120 degrees on the same plane. In addition, there exists an unillustrated c-axis that is orthogonal to the intersection point of the a1, a2, and a3 axes. Figure 4 In (a), the a1 axis, a2 axis, a3 axis and the hexagonal markings correspond to the case where SiC is a hexagonal crystal.

[0044] Figure 4 In (b), the

[0001] direction is a direction that is tilted at an angle from the Z direction to the side opposite to the [11-20] direction. Since the angle is about 4°, the

[0001] direction is actually along the Z direction. The above is an explanation of wafer 9 and ingot 900.

[0045] return Figure 1 Computer 2 performs various computational processes based on the captured image of wafer 9. Computer 2 uses various information in database 3 to inspect wafer 9 based on the image. Computer 2 is capable of controlling the imaging device 1 and database 3.

[0046] Database 3 stores various types of information. For example, database 3 can store information related to the shooting by the shooting device 1 and data related to the calculations by the computer 2. Database 3 is accessed by the computer 2 for analysis and calculation. Database 3 is, for example, an external storage device of the computer 2. Database 3 can also be provided from a server.

[0047] Figure 5 This is a schematic diagram illustrating an example of the configuration of the imaging device 1.

[0048] In this embodiment, the imaging apparatus 1 includes a reflective X-ray topography (XRT) device 1xrt. This X-ray topography device 1xrt includes two X-ray sources 10, two sensors 12, two slits 15, a vacuum chuck 17, and a control unit 19. Of the two X-ray sources 10, two sensors 12, and two slits 15, the X-ray source 10, sensors 12, and slits 15 positioned above the wafer 9 are used for reflective X-ray topography measurement of the surface of the wafer 9. The X-ray source 10, sensors 12, and slits 15 positioned below the wafer 9 are used for reflective X-ray topography measurement of the back surface of the wafer 9.

[0049] The wafer 9 is placed on the vacuum chuck 17 and held in place by suction. The vacuum chuck 17 is controlled by the control unit 19 to maintain the holding state of the wafer 9 until the imaging of the front and back sides of the wafer 9 is completed.

[0050] Two slits 15 are respectively positioned between the two X-ray sources 10 and the vacuum chuck 17. Each slit 15 converges the X-rays from each X-ray source 10 into a sheet shape.

[0051] Two X-ray sources 10 irradiate the wafer 9 on the vacuum chuck 17 through respective slits 15. The X-rays are incident on the wafer 9 at Bragg diffraction angles. The X-rays diffract in the wafer 9 in a manner that satisfies the Bragg diffraction conditions.

[0052] Each of the two sensors 12 detects diffracted X-rays from wafer 9. For example, an X-ray CCD camera is used as one of the sensors 12. CCD is an abbreviation for charge-coupled device.

[0053] The control unit 19, controlled by the computer 2, controls two X-ray sources 10, two sensors 12, two slits 15, and a vacuum chuck 17. The control unit 19 scans the entire area of ​​the wafer 9 or a representative portion of the wafer 9 by controlling each component. Based on the output of the sensors 12 associated with the area scanned on the back side of the wafer 9, the control unit 19 generates an X-ray topographic image of the back side of the wafer 9. Additionally, based on the output of the sensors 12 associated with the area scanned on the surface of the wafer 9, the control unit 19 generates an X-ray topographic image of the surface of the wafer 9. Each X-ray topographic image represents the result of defect inspection on the X-ray reflecting surfaces (surface and back side) of the wafer 9. Furthermore, X-ray topographic images can also be generated by the computer 2, which receives inspection results from the imaging device 1.

[0054] Through the photographing apparatus 1, threading dislocations 999 included in a SiC wafer 9 are detected based on an X-ray topography image. The threading dislocations 999 include various defects such as threading screw dislocations (TSD) and threading mixed dislocations (TMD). A mixed dislocation is a dislocation formed by mixing a threading screw dislocation (TSD) with another dislocation. Examples of such other dislocations include threading edge dislocations (TED) and basal plane dislocations (BPD).

[0055] In addition, the photographing apparatus 1 may also photograph the wafer 9 through destructive inspection, as long as it can detect defects (for example, threading dislocations) in the wafer 9. For example, the photographing apparatus 1 may also photograph the wafer 9 by using an etch pit method (Japanese: エッチピット法) in which the wafer 9 is pre-etched before photographing. Alternatively, instead of the etch pit method, the photographing apparatus 1 may use an optical microscope instead of the X-ray topography apparatus 1xrt to photograph the wafer 9.

[0056] Figure 6 is a block diagram showing a configuration example of the computer 2 of the semiconductor inspection apparatus 100. The computer 2 includes a processing circuit 21, a ROM (Read Only Memory) 22, a RAM (Random Access Memory) 23, a storage device 24, an input interface 25, a display 26, and a communication interface 27.

[0057] The processing circuit 21 is a processor capable of executing various programs (software, applications). The processing circuit 21 executes calculation processing using various information, various data, various signals, and various parameters. The processing circuit 21 controls the operations of the ROM 22, the RAM 23, the storage device 24, the input interface 25, the display 26, and the communication interface 27. The processing circuit 21 includes, for example, a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). Such a processing circuit 21 executes processing of each function such as an acquisition function 211, a detection function 212, an analysis function 213, a classification function 214, and a management function 215 by executing a program. In addition, the division of processing for each function is an example, and may be appropriately changed. For example, part or all of the classification function 214 may be included in the analysis function 213 or the management function 215. That is, since there is no difference in that the processing of each function is executed by the processing circuit 21, the division may be appropriately changed.

[0058] Here, the acquisition function 211 acquires an image of the wafer 9 by photographing it using the imaging device 1. The image of the wafer 9 includes an X-ray topography image of the back side of the wafer 9 and an X-ray topography image of the surface of the wafer 9. The acquisition function 211 can acquire images of the back side and the surface of the wafer 9 by photographing it separately using the imaging device 1 while maintaining the wafer 9 in a holding state. The imaging device 1 and the acquisition function 211 are an example of an acquisition unit. The acquisition unit mentioned here includes an X-ray topography device 1xrt, and is configured to acquire an image of the wafer 9 by photographing it using the X-ray topography device 1xrt. In addition, the acquisition function 211 can appropriately store the acquired image of the wafer 9 in a memory such as RAM 23 or a storage device 24, or it can be stored in a database 3.

[0059] The detection function 212 detects, based on the image acquired by the acquisition function 211, a first coordinate of a through-hole dislocation occurring on the back side of wafer 9 and a second coordinate of a through-hole dislocation occurring on the surface of wafer 9. The detection function 212 can detect the first coordinate based on an image of the surface of wafer 9 and can detect the second coordinate based on an image of the back side of wafer 9.

[0060] Detection function 212 is an example from the detection department.

[0061] Analysis function 213 analyzes the tilt of the dislocation line penetrating dislocation 999 relative to the thickness direction of wafer 9 based on the first and second coordinates detected by detection function 212 and the thickness of wafer 9. Analysis function 213 can further analyze the extension direction of the dislocation line based on the first and second coordinates. Analysis function 213 can predict, based on the first and second coordinates and the extension direction of the dislocation line, the third coordinate of the penetrating dislocation 999 appearing on the back side of a wafer 9 different from wafer 9, cut from the same ingot 900 from which wafer 9 was cut, and the fourth coordinate of the penetrating dislocation 999 appearing on the surface of this different wafer 9. Analysis function 213 is an example of an analysis unit.

[0062] Classification function 214 classifies through-dislocations 999 based on the analysis results of analysis function 213. Classification function 214 can classify through-dislocations based on whether the tilt indicated by the analysis results is within a threshold range. Classification function 214 can further classify through-dislocations 999 based on which of multiple directional ranges the extension direction indicated by the analysis results enters. Classification function 214 can classify through-dislocations 999 as mixed dislocations based on the image of wafer 9, and combine the classification result representing the mixed dislocation with the classification result based on the analysis results to further classify through-dislocations 999. Classification function 214 can identify abnormal regions within wafer 9 based on the classification results of each through-dislocation 999 within wafer 9. Classification function 214 can classify through-dislocations 999 with third and fourth coordinates according to the classification results of through-dislocations 999 with first and second coordinates. Classification function 214 is an example of a classification unit.

[0063] Management function 215 manages information related to wafer 9 by storing the detection results of detection function 212, the analysis results of analysis function 213, and the classification results of classification function 214—information related to through-dislocation 999—in database 3. Furthermore, management function 215 can manage the distribution and density of through-dislocation 999 on wafer 9 by performing statistical processing on the information related to through-dislocation 999 in database 3.

[0064] ROM22 is a non-volatile semiconductor memory. ROM22 stores programs and control data used to control computer 2.

[0065] RAM23 is a volatile semiconductor memory. RAM23 is used as the working area of ​​the processing circuit 21. RAM23 temporarily stores various data and parameters used in the processing of the processing circuit 21.

[0066] Storage device 24 is a non-volatile storage device such as HDD (Hard disc drive), SSD (Solid state), or memory card. Storage device 24 stores various information, data, and parameters. Storage device 24 has a database consisting of a collection of data of a certain type. Program and control data can also be stored in storage device 24. For example, storage device 24 stores a program PG related to the inspection method performed by semiconductor inspection apparatus 100. The inspection method mentioned here includes, for example, acquiring an image of wafer 9 by photographing wafer 9; detecting a first coordinate of a through dislocation 999 appearing on the back side of wafer 9 and a second coordinate of a through dislocation 999 appearing on the surface of wafer 9 based on the image; analyzing the tilt of the dislocation line of the through dislocation 999 relative to the thickness direction of wafer 9 based on the first and second coordinates and the thickness of wafer 9; and classifying the through dislocation 999 based on the analysis results. Program PG can be stored in ROM 22. In summary, program PG is stored in a non-transitory computer-readable storage medium.

[0067] Input interface 25 accepts various operation inputs from the user. Input interface 25 can be a keyboard, mouse, various switches, touchpad, touch panel display, etc. The electrical signal corresponding to the accepted operation input (hereinafter referred to as the operation signal) is supplied to processing circuit 21.

[0068] The display 26 displays various data, including images, of the wafer 9 under the control of the processing circuit 21. The display 26 can be a CRT (Cathode-Ray Tube) display, a liquid crystal display, an organic EL (ElectroLuminescence) display, an LED (Light-Emitting Diode) display, a plasma display, or any other arbitrary display.

[0069] The communication interface 27 includes various connectors, ports, signal processing circuits, and communication modules. The communication interface 27 connects the computer 2 to the imaging device 1 and the database 3. The communication interface 27 sends control signals from the processing circuit 21 to the imaging device 1 and the database 3. The communication interface 27 also sends information from the imaging device 1 (e.g., an image of the wafer 9) and information from the database 3 to the processing circuit 21.

[0070] Figure 7 This is a diagram illustrating an example of the configuration of the database 3 in the semiconductor inspection apparatus 100. The database 3 includes chip layout information 31, pattern layout information 32, process information 33, distance information 34, and wafer information 35.

[0071] Chip layout information 31 is information related to the layout of chip regions within wafer 9. A chip region is a region within wafer 9 arranged in a manner corresponding to a single chip formed by dicing wafer 9.

[0072] The pattern layout information 32 includes information related to the layout (coordinates) of various patterns disposed within the chip region of the wafer 9. For example, the pattern layout information 32 includes information related to the layout of active regions (e.g., diffusion layer patterns or sludge semiconductor region patterns), information related to the layout of gate patterns, and information related to the layout of wiring patterns, etc.

[0073] Process information 33 includes information related to manufacturing processes such as ion implantation, film formation, and etching. The information on various manufacturing processes contained in the process information is related to the layout of the patterns contained in the pattern layout information.

[0074] Distance information 34 is information related to the distance from the end of the ingot on the seed crystal side to the target wafer 9 in the growth direction of the ingot. For example, the distance from the end of the ingot to the target wafer 9 is determined based on the thickness of the wafer 9 and the position of the wafer 9 in the ingot.

[0075] Wafer information 35 includes ingot number, wafer 9 identification number, dislocation coordinates on the back side, dislocation coordinates on the surface, tilt of the dislocation line, direction of dislocation line extension, grouping information for each feature, distribution of fatal TSDs, and density of fatal TSDs. The ingot number is a number used to identify the ingot cut from wafer 9. The wafer 9 identification number is a number used to identify each wafer 9 cut from the ingot. The dislocation coordinates on the back side are the coordinates (first coordinates) indicating the location of through dislocations appearing on the back side of wafer 9. The dislocation coordinates on the surface are the coordinates (second coordinates) indicating the location of through dislocations appearing on the surface of wafer 9. Furthermore, the back side of wafer 9 is the side of wafer 9 opposite to the seed crystal side within the ingot. The surface of wafer 9 is the side opposite to the back side of wafer 9, formed after the back side of wafer 9 through crystal growth. Therefore, through dislocations within wafer 9 propagate approximately linearly from the back side of wafer 9 towards the surface at various tilt angles. The tilt of the dislocation line is the tilt of the penetrating dislocation relative to the thickness direction of wafer 9. The thickness direction of wafer 9 is the direction of crystal growth of the ingot, which is the direction of the shortest distance connecting the back side and the surface of wafer 9 to the same coordinate. The extension direction of the dislocation line can be the direction in which the dislocation line extends within the ingot. In this embodiment, the direction in which the dislocation line extends within the ingot is managed as the direction projected onto the surface of wafer 9. The grouping information under each feature is information that groups penetrating dislocations into specific patterns according to each feature, such as specific patterns representing the magnitude of the tilt of the dislocation line, specific patterns representing the extension direction, etc. A fatal TSD is a penetrating spiral dislocation (TSD) that has a fatal adverse effect on the semiconductor device formed on wafer 9. Examples of fatal adverse effects include malfunctions or operational failures caused by current leakage. According to the inventors' research, the location where current leakage occurs tends to have a tilt of approximately the same range relative to the thickness direction of wafer 9. In other words, through-dislocations propagating from the vertical direction with a tilt range of +θ1 to -θ2 relative to the surface and back of wafer 9 tend to be associated with current leakage. Therefore, from the viewpoint of identifying fatal TSDs among various through-dislocations, it is preferable, for example, to classify through-dislocations whose dislocation line tilt is within a specific threshold range. The distribution of fatal TSDs is information representing a region within wafer 9 or the entire wafer surface where fatal TSDs are distributed. The density of fatal TSDs is the density of fatal TSDs (cm³). ^ -2) represents the value ( ^ (This is a symbol representing an exponentiation), representing the number of fatal TSDs per square centimeter on wafer 9. Furthermore, the density of fatal TSDs can also be included in the distribution of fatal TSDs. In this case, the distribution of fatal TSDs is information representing the density of fatal TSDs in a certain region within wafer 9 or across the entire surface of the wafer. Additionally, the distribution of fatal TSDs can, for example, be combined with chip layout information 31 to... Figure 3 The distribution and density of fatal TSDs are represented on wafer 9 as shown. The distribution and density of fatal TSDs are generated by the management function 215 of the processing circuit 21 through the database 3 by statistically processing information related to the number and coordinates of through dislocations 999 representing a specific pattern of fatal TSDs.

[0076] In addition, database 3 can be stored in storage device 24 inside computer 2.

[0077] Next, use Figure 8 Flowchart and Figures 9 to 13 The schematic diagram illustrates an example of the operation of the semiconductor inspection device 100 configured as described above.

[0078] (Step ST10) The imaging device 1 of the semiconductor inspection apparatus 100 begins imaging the wafer 9 upon receiving a control signal from the computer. The control unit 19 of the imaging device 1 scans the entire area or a representative portion of the wafer 9 held in the vacuum chuck 17 by controlling two X-ray sources 10, two sensors 12, and two slits 15. Furthermore, the vacuum chuck 17 maintains the wafer 9 in a holding state until imaging of both the front and back surfaces of the wafer 9 is completed.

[0079] After scanning, such as Figure 9 As shown, the control unit 19 generates an image g1 of the back side of wafer 9 based on the output of sensor 12 related to the area scanned on the back side of wafer 9. Additionally, the control unit 19 generates an image g2 of the surface of wafer 9 based on the output of sensor 12 related to the area scanned on the surface of wafer 9. Furthermore, the control unit 19 sends the generated images g1 and g2 to computer 2. The processing circuit 21 of computer 2 acquires the image of wafer 9. Moreover, the back side image g1 and the surface image g2 are in a relationship where the Y-direction is the same and the X-direction is opposite to each other in the XY plane.

[0080] (Step ST20) Based on the images g1 and g2 acquired in step ST10, processing circuit 21 detects the coordinates of through dislocations 999 on both sides of wafer 9. For example, processing circuit 21 flips the back image g1 around the Y-axis along the Y direction to make the coordinate systems of images g1 and g2 consistent. Then, based on image g1, processing circuit 21 detects the first coordinate P1 (x1, y1) of the through dislocation 999 appearing on the back side of wafer 9. Additionally, based on image g2, processing circuit 21 detects the second coordinate P2 (x2, y2) of the through dislocation 999 appearing on the surface of wafer 9. Then, processing circuit 21 generates a composite image g3 obtained by combining images g1 and g2 in the same coordinate system. Furthermore, since the processing below step ST30 can be performed based on the first and second coordinates, it is not necessarily necessary to generate the composite image g3. The following explanation of the composite image g3 is provided from an easily understandable point of view. Additionally, processing circuit 21 stores the detection results of step ST20 in the wafer information 35 of database 3.

[0081] (Step ST30) Based on the detection results of step ST20, processing circuit 21 analyzes the tilt and extension direction of the dislocation lines penetrating dislocations within wafer 9. For example, as Figure 10 As shown in the figure above and Equation (1), the processing circuit 21 calculates the length L between the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2) on the XY plane of the wafer 9.

[0082] L = {(x2-x1)} ^ 2 + (y2 - y1) ^ 2} ^ (1 / 2)...(1) In addition, the processing circuit 21 is based on the length L and the thickness d of the wafer 9, such as Figure 10 As shown in the figure below and Equation (2), the tilt θ of the dislocation line penetrating dislocation 999 relative to the thickness direction Td of wafer 9 is calculated.

[0083] θ=tan ^ -1 (L / d)…(2) Furthermore, the processing circuit 21 is based on the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2), such as Figure 11 As shown in equation (3), the angle of the penetrating dislocation relative to the X direction in the XY plane is calculated. .

[0084] =tan ^ -1{(y2-y1) / (x2-x1)}…(3) The angle of the through dislocation corresponds to the direction of its extension, which can be denoted as the [01-10] direction within wafer 9. Therefore, the processing circuit 21 determines the angle of the through dislocation 999 projected onto the XY plane. The extension direction of the through dislocation 999 projected onto the XY plane is analyzed. Furthermore, the processing circuit 21 can first analyze either the tilt θ of the dislocation line or either the extension direction. Additionally, the analysis of the extension direction is not necessarily required and can be omitted. The processing circuit 21 then saves the analysis results of step ST30 to the wafer information 35 of the database 3.

[0085] (Step ST40) Based on the analysis results of step ST30, processing circuit 21 classifies the through-hole dislocations 999 within wafer 9. For example, as Figure 12 As shown, the processing circuit 21 can classify through dislocations 999a to 999d based on whether the tilt θ indicated by the analysis results is within a threshold range. In this case, the processing circuit 21 classifies the through dislocations 999b and 999c, which have small tilt θ, into a specific pattern Pt1. The processing circuit 21 can also classify the remaining through dislocations 999a and 999d into other specific patterns, or it can choose not to classify them.

[0086] Furthermore, processing circuit 21 can further classify the through-dislocation 999 based on which of the multiple directional ranges it enters according to the extension direction indicated by the analysis results. Additionally, processing circuit 21 can classify whether the through-dislocation 999 is a mixed dislocation based on the image of wafer 9, and combine the classification result indicating the mixed dislocation with the classification result based on the analysis results to further classify the through-dislocation 999. Furthermore, processing circuit 21 can identify abnormal regions within wafer 9 based on the classification results of each through-dislocation 999 within wafer 9. Finally, processing circuit 21 saves the classification results of step ST40 in the wafer information 35 of database 3.

[0087] (Step ST50) Based on the results of steps ST20 and ST30 in a certain wafer 9, the processing circuit 21 predicts the coordinates of the through dislocation 999 in other wafers 9. For example, based on the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2) of the through dislocation 999 in a certain wafer 9 and the extension direction of the dislocation line of the through dislocation 999, the processing circuit 21 predicts the third coordinate P3 (x3, y3) of the through dislocation 999 appearing on the back side of other wafers 9 and the fourth coordinate P4 (x4, y4) of the through dislocation 999 appearing on the surface of other wafers 9.

[0088] For example, such as Figure 13 As shown on the left, assume that a certain wafer 9 is wafer 9A, and the other wafers 9 are wafers 9B. In addition, in ingot 900, the distance D between the surface of wafer 9A and the back surface of other wafers 9B is n times the thickness d of wafer 9A.

[0089] On the other hand, when the thickness d of wafer 9A is such that... Figure 13 As shown on the right, the length between the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2) on the XY plane of wafer 9A is L. That is, the following relationship exists: when the thickness of wafer 9 is d, the penetrating dislocation 999 propagates with a length L. Accompanying this, the following relationship exists: when the distance between wafers 9A and 9B is D (=d·n), the penetrating dislocation 999 extends with a length E. At this time, since d∶L=D∶E, the extended length E is expressed as equation (4).

[0090] E=L·n…(4) Here, length E represents the extension direction [01-10] or angle along wafer 9. The length between the second coordinate P2(x2, y2) on the surface of wafer 9A when extending through dislocation 999 and the third coordinate P3(x3, y3) on the back side of wafer 9B. That is, the third coordinate P3(x3, y3) on the back side of other wafers 9B is predicted as the position after extending from the second coordinate P2(x2, y2) on the surface of a certain wafer 9A along the extension direction by a length E. Specifically, for example, the third coordinate P3(x3, y3) can be represented as x3 = x2 + E·cos y3=y2+E·sin To find it. Or, from the perspective of reducing and angle. From the perspective of related calculation errors, the third coordinate P3(x3, y3) can also be obtained as shown in equation (5).

[0091] x3 = (x2 - x1)·n + x2 y3=(y2-y1)·n+y2…(5) Additionally, the fourth coordinate P4(x4, y4) of the surface of wafer 9B is predicted as the position after extending along the extension direction by a length L from the third coordinate P3(x3, y3). The fourth coordinate P4(x4, y4) can also be obtained as shown in equation (6).

[0092] x4 = (x2 - x1) + x3 y4 = (y2 - y1) + y3…(6) Furthermore, processing circuit 21 stores the prediction results (third coordinate, fourth coordinate) of step ST50 in the wafer information 35 of database 3, associating them with the identification numbers of other wafers 9B. Moreover, the tilt and extension direction of the dislocation lines associated with the third and fourth coordinates in other wafers 9B are the same as those associated with the first and second coordinates in a certain wafer 9A, therefore no analysis is required. Thus, processing circuit 21 stores the analysis results associated with other wafers 9B in wafer information 35 by copying the analysis results associated with a certain wafer 9A. Then, processing circuit 21 terminates the processing.

[0093] As described above, according to the first embodiment, the processing circuit 21 acquires images g1 and g2 of the wafer 9 by photographing the wafer 9 with the imaging device 1. Based on the images g1 and g2, the processing circuit 21 detects the first coordinates P1 (x1, y1) of a through-dislocation 999 appearing on the back side of the wafer 9 and the second coordinates P2 (x2, y2) of a through-dislocation 999 appearing on the surface of the wafer 9. Based on the first and second coordinates and the thickness d of the wafer 9, the processing circuit 21 analyzes the inclination of the dislocation line of the through-dislocation 999 relative to the thickness direction Td of the wafer 9. The processing circuit 21 classifies the through dislocations 999 based on the analysis results. In this way, by analyzing the structure of the tilt of the dislocation line based on the first coordinate of the through dislocation appearing on the back side of the wafer and the second coordinate of the through dislocation appearing on the surface of the wafer based on the image obtained by photographing the wafer, the tilt of the dislocation line within the wafer can be determined over a large range without measuring the depth of the sample.

[0094] Furthermore, according to the first embodiment, the processing circuit 21 can classify through dislocations based on whether the tilt θ indicated by the analysis result is within the range of thresholds θ1 to θ2. In this case, for example, through dislocations with a tilt θ within the threshold range can be classified as highly lethal specific patterns that have a fatal impact on the semiconductor device. In addition, since through dislocations within the threshold range can be classified, the distribution of highly lethal specific through dislocations can be managed, rather than the distribution of all through dislocations. As a result, by flexibly applying it to quality evaluation, defect inspection, etc. during the manufacturing of semiconductor devices, the yield can be improved. For example, by discarding semiconductor devices that use chip areas containing highly lethal through dislocations during pre-shipment inspection, the generation of defective semiconductor devices can be reduced. This is not limited to classification results based on analysis results indicating that the tilt θ is within the threshold range; any analysis result corresponding to the classification result of highly lethal specific patterns is acceptable, and the same applies to other analysis results.

[0095] Furthermore, according to the first embodiment, the processing circuit 21 can further analyze the extension direction of the dislocation line based on the first coordinate and the second coordinate. In this case, through dislocations can be classified according to the extension direction of the dislocation line. In addition, through dislocations can be classified according to the combination of the tilt of the dislocation line and the extension direction of the dislocation line.

[0096] Furthermore, according to the first embodiment, the processing circuit 21 can further classify through dislocations based on which of the multiple directional ranges the extension direction indicated by the analysis result enters. In this case, through dislocations can be managed according to each of the multiple directional ranges.

[0097] Furthermore, according to the first embodiment, the processing circuit 21 can classify whether a through-hole dislocation is a mixed dislocation based on the image, and combine the classification result representing the mixed dislocation with the classification result based on the analysis result, thereby further classifying the through-hole dislocation. In this case, for example, by combining the classification result representing a mixed dislocation with the classification result representing that the tilt of the dislocation line is within a threshold range, it is possible to classify the through-hole dislocation into a specific pattern that is extremely lethal.

[0098] Furthermore, according to the first embodiment, the processing circuit 21 can identify abnormal regions within the wafer based on the classification results of each through-dislocation within the wafer. In this case, for example, regions with a higher number of through-dislocations with a high catastrophic classification result than a threshold can be identified as abnormal regions.

[0099] Furthermore, according to the first embodiment, the processing circuit 21 can predict, based on the first and second coordinates and the extension direction of the dislocation line, the third coordinate of a penetrating dislocation appearing on the back side of another wafer 9B, which is different from wafer 9A and cut from the same ingot 900 from which wafer 9A was cut, and the fourth coordinate of a penetrating dislocation appearing on the surface of the other wafer 9B. In this case, the burden of photographing and analyzing the target wafers in all wafers 9 can be reduced. In addition, the photographed wafer 9 is not limited to non-destructive inspection, but can also be destructive inspection. In addition, wafer 9A is not limited to the side closer to the seed crystal 99, but can also be the side farther from the seed crystal 99. In this case, the other wafers 9B are the side closer to the seed crystal 99. That is, the third and fourth coordinates of a penetrating dislocation 999 in the other wafers 9B on the side closer to the seed crystal 99 can be predicted based on the first and second coordinates of the penetrating dislocation 999 in the wafer 9A on the side farther from the seed crystal 99. In addition, based on the first and second coordinates of the through dislocation 999 of the two wafers 9A and 9B cut from their respective separated positions, the third and fourth coordinates of the through dislocation 999 of the other wafers between the two wafers 9A and 9B can be predicted.

[0100] Furthermore, according to the first embodiment, the processing circuit 21 can classify through-dislocations with third and fourth coordinates in other wafers 9B based on the classification results of through-dislocations with first and second coordinates in a certain wafer 9A. In this case, the analysis of the tilt and extension direction of dislocation lines based on the third and fourth coordinates can be omitted. In addition, based on the property that through-dislocations propagate in a roughly linear manner, it can be inferred that the tilt and extension direction of through-dislocations with predicted third and fourth coordinates are approximately the same as those of through-dislocations with predicted first and second coordinates. Therefore, the tilt and extension direction of dislocation lines related to the predicted third and fourth coordinates do not need to be analyzed, and this analysis can be omitted.

[0101] Furthermore, according to the first embodiment, by capturing images of the back side and surface of the wafer 9 while maintaining the wafer 9 in a holding state, the processing circuit 21 acquires images of the back side and surface of the wafer 9. The processing circuit 21 can detect a first coordinate based on the back side image and a second coordinate based on the surface image. In this case, the wafer 9 is not released and re-held during the capturing process, thus reducing the positional offset of the coordinate system between the back side image and the surface image. In addition, by measuring both sides of the wafer using reflective XRT while the wafer 9 is held in a holding state, the coordinate accuracy required for calculating the tilt of dislocation lines can be maintained. For example, the positional offset of the coordinate system between the back side image and the surface image is expected to be less than 10 μm, preferably less than 1 μm. In contrast, in conventional reflective XRT, when the holding is released after measuring the surface of the holding wafer, the wafer is transported, flipped, and then held in a holding state again to measure the surface of the wafer, the positional offset of the coordinate system is approximately 100 μm. That is, in the existing XRT of reflection, the position offset of the coordinate system is large, which makes it impossible to maintain the coordinate accuracy required to calculate the inclination of the dislocation line.

[0102] Furthermore, according to the first embodiment, the acquisition unit, which includes the imaging device 1 and the acquisition function 211, may include an X-ray topography device 1xrt, and images g1 and g2 of the wafer 9 are acquired by imaging the wafer 9 using the X-ray topography device 1xrt. In this case, the X-ray topography device in any imaging device capable of imaging wafers can be used to image and acquire images of the wafer.

[0103] <First Variation of the First Embodiment> In the first embodiment, the X-ray topography device 1xrt includes two X-ray sources 10, two sensors 12, and two slits 15, but is not limited to these. For example, as Figure 14 As shown, the X-ray topology apparatus 1xrt can also be configured to include an X-ray source 10, a sensor 12, and a slit 15. In this case, the control unit 19 can also rotate the X-ray source 10, sensor 12, and slit 15 around a rotation axis Ry along the Y direction within the wafer 9 via a drive unit (not shown), thereby switching between a first configuration and a second configuration. Here, the first configuration is for performing reflective X-ray topology measurement on the surface of the wafer 9 using the X-ray source 10, sensor 12, and slit 15 positioned above the wafer 9. The second configuration is for performing reflective X-ray topology measurement on the back side of the wafer 9 using the X-ray source 10, sensor 12, and slit 15 positioned below the wafer 9. Furthermore, the control unit 19 can appropriately raise or lower the vacuum chuck 17 as the configuration is switched. According to the first variation, only one X-ray source 10, sensor 12, and slit 15 are needed, thus enabling cost reduction of the X-ray topology apparatus 1xrt.

[0104] <Second variation of the first embodiment> In the first embodiment, the X-ray topography device 1xrt includes two X-ray sources 10, two sensors 12, and two slits 15, but is not limited to these. For example, as Figure 15 As shown, the X-ray topology apparatus 1xrt can also be configured to include an X-ray source 10, a sensor 12, and a slit 15. In this case, the control unit 19 can also switch between imaging the surface and back of the wafer 9 by rotating the vacuum chuck 17 around a rotation axis Ry along the Y direction within the wafer 9 via a drive unit (not shown), thereby switching between imaging the surface and back of the wafer 9. Furthermore, the control unit 19 can appropriately raise or lower the vacuum chuck 17 as the imaging surface is switched. According to the second modification, the X-ray source 10, sensor 12, and slit 15 can be a single unit, thus achieving cost reduction of the X-ray topology apparatus 1xrt. Furthermore, the second modification envisions a case where the X-rays output by the X-ray source 10 are radiation, but it is not limited to this. For example, the X-rays output by the X-ray source 10 can also be radiation. In this case, a large-scale radiation facility SPring-8 can be appropriately used as the X-ray topology apparatus 1xrt. Accordingly, the acquisition function 211 is a structure that does not include the imaging device 1, and it is installed as a function of the processing circuit 21, which performs the process of reading the image from the RAM 23 or the storage device 24 that stores the image obtained from the photographed wafer 9. Even with this modification, the same effect as the first embodiment can be obtained. Furthermore, the structure of the acquisition function 211 that does not include the imaging device 1 can also be applied to the first embodiment and its first modification, as well as the following embodiments and modifications.

[0105] <Second Implementation Method> Next, the semiconductor inspection apparatus of the second embodiment will be described.

[0106] The second embodiment is a variation of the wafer image and imaging device, which is a method of imaging a wafer 9 with etch pits (Japanese: エッチピット) formed on its surface by an etching pit method using an optical microscope device.

[0107] Figure 16A This is a block diagram illustrating an example of the configuration of the imaging apparatus in the semiconductor inspection apparatus of the second embodiment. Instead of the X-ray topology apparatus 1xrt, the imaging apparatus 1 is equipped with an incident illumination type optical microscope apparatus 1pm. The optical microscope apparatus 1pm includes a light source unit 41, a semi-transparent mirror 42, a light receiving unit 44, a sample stage 45, and a control unit 46. The sample stage 45 holds the wafer 9 that has undergone chemical treatment using the etch pit method.

[0108] The light source unit 41 outputs light generated by the light source and transmitted through the lens to the semi-transparent mirror 42. The light, whose optical path is changed at the semi-transparent mirror, illuminates the wafer 9 on the sample stage 45. The light reflected from the wafer 9 passes through the semi-transparent mirror 42 and enters the light receiving unit 44. The light receiving unit 44 focuses the incident light through the objective lens, detects the transmitted light through the image sensor, and outputs the detection result to the control unit 46.

[0109] In addition, such as Figure 16B As shown, the optical microscope 1pm can also be a transmitted illumination type. In this case, the optical microscope apparatus 1pm includes a light source unit 43, a light receiving unit 44, a sample stage 45, and a control unit 46. The light source unit 43 outputs parallel light generated by the light source and transmitted through a condenser lens, illuminating the wafer 9 on the sample stage 45. The parallel light transmitted through the wafer 9 is incident on the light receiving unit 44. The light receiving unit 44 focuses the incident light through an objective lens, detects the obtained transmitted light through an image sensor, and outputs the detection result to the control unit 46. However, in this embodiment, as... Figure 16A As shown, the example is the case of using a spotlight type.

[0110] The control unit 46, controlled by the computer 2, controls the light source unit 41 (or 43), the light receiving unit 44, and the sample stage 45. The control unit 46 scans the entire area of ​​the wafer 9 or a representative portion of the wafer 9 by controlling each unit. The control unit 46 generates an optical image of the wafer 9 based on the output of the light receiving unit 44 related to the scanned area within the wafer 9. The optical image represents the results of defect inspection on the back and surface of the wafer 9. Furthermore, an X-ray topography image can also be generated by the computer 2, which receives the inspection results from the imaging device 1.

[0111] On the other hand, the acquisition function 211 of the processing circuit 21 acquires an image of the wafer 9 by photographing the wafer 9 with the optical microscope device 1pm. The imaging device 1 and the acquisition function 211 are an example of an acquisition unit. The acquisition unit mentioned here includes the optical microscope device 1pm and is configured to acquire an image of the wafer 9 by photographing the wafer 9 with the optical microscope device 1pm.

[0112] Here, wafer 9 has a state where a first etch pit with a dot-shaped shape corresponding to a through dislocation 999 is formed on the back side by etching based on the etch pit method, and a second etch pit with a hexagonal shape corresponding to a through dislocation 999 is formed on the surface. The first etch pit and the second etch pit are crystal defects expanded by the solution treatment of the etch pit method. The hexagonal shape of the second etch pit represents the outline of the second etch pit produced by anisotropic etching. Accordingly, the optical image of wafer 9 is an image representing the first etch pit with a dot-shaped shape and the second etch pit with a hexagonal shape based on the through dislocation 999. In addition, the X-ray topography image of wafer 9 in the first embodiment consists of two images: an image representing the surface and an image representing the back side, both within the same scanning area. In contrast, the optical image of wafer 9 in the second embodiment is a single image that overlays the surface and back side in the same scanning area. That is, the optical image of wafer 9 is an image taken by summing the surface and back side of wafer 9 using the same coordinates into a single image.

[0113] Detection function 212 detects the position of the first etch pit represented by the image of wafer 9 and uses it as the first coordinate, and detects the position of the second etch pit represented by the image and uses it as the second coordinate. For example, detection function 212 detects the position of the midpoint of the diagonal of a hexagonal shape and uses it as the second coordinate, and detects the position of a dotted shape and uses it as the first coordinate. In addition, detection function 212 can also output a detection result that includes the second coordinate but not the first coordinate if the second coordinate is detected but the first coordinate is not detected.

[0114] In addition to the functions mentioned above, analysis function 213, upon receiving a detection result that includes the second coordinate but not the first coordinate, outputs an analysis result that does not include the tilt θ of the dislocation line based on the detection result.

[0115] In addition to the functions described above, classification function 214 classifies dislocations that penetrate the dislocation line as insufficiently etched if the analysis results do not include the tilt angle θ of the dislocation line. Furthermore, management function 215 can adjust observation conditions such as the focal point of the optical microscope device within a specified range based on the classification result of insufficient etching, and output the adjustment results to control unit 46. Control unit 46 controls each part according to the observation conditions.

[0116] The other structures are the same as in the first embodiment.

[0117] Next, using the aforementioned Figure 8 Flowchart and Figures 17 to 24 The schematic diagram illustrates an example of the operation of the semiconductor inspection apparatus 100 configured as described above. The following explanation omits repetitive details.

[0118] (Step ST10) In the imaging device 1 of the semiconductor inspection apparatus 100, the control unit 19 scans the entire area or a representative portion of the wafer 9 held on the sample stage 45 by controlling the light source unit 41, the light receiving unit 44, and the sample stage 45. Furthermore, the sample stage 45 maintains the state of holding the wafer 9 until the imaging of the wafer 9 is completed.

[0119] After scanning, the control unit 46 generates an image of the wafer 9 based on the output of the light-receiving unit 44, and sends the image to the computer 2. The processing circuit 21 of the computer 2 acquires the image of the wafer 9.

[0120] (Step ST20) Based on the image acquired in step ST10, processing circuit 21 detects the coordinates of through dislocations 999 on both sides of wafer 9. For example, as Figure 17 As shown, the processing circuit 21 detects the position of the first etch pit represented by image g4 of wafer 9 and uses it as the first coordinate, and detects the position of the second etch pit represented by the same image and uses it as the second coordinate. For example, one etch pit region in image g4 is magnified and displayed in image g41, and another etch pit region is magnified and displayed in image g42. For images g41 and g42, the processing circuit 21 detects the position of the midpoint of the diagonal of the hexagonal shape and uses it as the second coordinate P2 (x2, y2), and detects the position of the dotted shape and uses it as the first coordinate P1 (x1, y1). The first and second coordinates are also detected similarly for other etch pits in image g4. In addition, the processing circuit 21 saves the detection results of step ST20 in the wafer information 35 of database 3.

[0121] (Step ST30) Based on the detection results of step ST20, the processing circuit 21 analyzes the tilt and extension direction of the dislocation line that penetrates the dislocation within the wafer 9. For example, the processing circuit 21 calculates the length L between the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2) on the XY plane of the wafer 9 using the aforementioned equation (1).

[0122] Similarly, the processing circuit 21, based on the length L and the thickness d of the wafer 9, through... Figure 18 And using the aforementioned equation (2), the tilt θ of the dislocation line penetrating dislocation 999 relative to the thickness direction Td of wafer 9 is calculated.

[0123] That is, in the case where there are etch pits on the surface of wafer 9, such as Figure 18 As shown, similarly to the above, the tilt θ of the dislocation line is calculated based on the first coordinate P1 (x1, y1), the second coordinate P2 (x2, y2), and the thickness d of wafer 9. Furthermore, it is not limited to this, such as... Figure 19 As shown in Equation (2a), the tilt θ of the dislocation line can also be calculated based on the value (d-Δe) obtained by subtracting the depth Δe of the etch pit from the thickness d of the wafer 9.

[0124] θ=tan ^ -1(L / (d-Δe))…(2a) The depth Δe of the etch pit is the value obtained by multiplying the etch rate by the etch time.

[0125] Next, processing circuit 21 analyzes the extension direction of the dislocation 999 based on the first coordinate P1 (x1, y1) and the second coordinate P2 (x2, y2), in the same manner as described above. Furthermore, processing circuit 21 saves the analysis results of step ST30 in the wafer information 35 of database 3.

[0126] (Step ST40) Based on the analysis results of step ST30, processing circuit 21 classifies the through-hole dislocations 999 within wafer 9. For example, processing circuit 21 can classify them as follows: Figure 20 and Figure 21 As shown, in image g5 of wafer 9, through dislocations are classified based on whether the tilt angle θ indicated by the analysis results is within a threshold range. In this case, processing circuit 21 classifies through dislocations 999 with small tilt angle θ as specific pattern Pt1, and through dislocations 999 with large tilt angle θ as specific pattern Pt2. Furthermore, based on the detection results including the second coordinate but not the first coordinate, processing circuit 21 classifies through dislocations with dislocation lines as specific pattern Pt3 when the analysis results do not include the tilt angle θ of the dislocation line. Specific pattern Pt3 is a pattern without etch pits on the back side, indicating insufficient etching.

[0127] Furthermore, processing circuit 21 can further classify the through dislocation 999 based on which of the multiple directional ranges the extension direction indicated by the analysis results falls into. For example, processing circuit 21... Figure 22 As shown, in image g51, which is a magnified version of a portion of image g5, the angle of the penetrating dislocation from the first coordinate P1 (x1, y1) to the second coordinate P2 (x2, y2) is calculated using the aforementioned equation (3). Additionally, due to this angle The corresponding extension direction [11-20] enters the range between the a1 axis direction and the a2 axis direction, therefore the processing circuit 21 classifies the through dislocation as a specific pattern Pt12. Furthermore, the processing circuit 21 at this angle... When the corresponding extension direction enters the range between the a2-axis direction and the a3-axis direction, the through dislocation is classified as a specific pattern Pt23. Similarly, the processing circuit 21, in relation to this angle... When the corresponding extension direction enters the range between the a3 axis direction and the a1 axis direction, the through dislocation is classified as a specific pattern Pt31.

[0128] In addition, such as Figure 23 As shown, the processing circuit 21 can combine specific patterns Pt12 and Pt23 of the classification results related to the extension direction and specific pattern Pt2 of the classification results related to the aforementioned tilt θ.

[0129] Additionally, processing circuit 21 classifies whether the through-dislocation 999 is a mixed dislocation based on the image of wafer 9. For example, as Figure 24 As shown, in image g61 obtained by magnifying a portion of image g6, processing circuit 21 determines, based on the shape of the etch pits, that the through-hole dislocation is a mixed dislocation TMD, namely a through-hole edge dislocation (TED) and a through-hole spiral dislocation (TSD), and classifies the through-hole dislocation as a specific pattern Pt30. Furthermore, Figure 24 The etched pit shown has a contour shape formed by blending a portion of a roughly hexagonal shape with a roughly semi-circular shape. Then, processing circuit 21 further classifies the through-dislocation 999 by combining the classification result representing this mixed dislocation with a classification result based on the analysis results. Additionally, processing circuit 21 can identify abnormal regions within wafer 9 based on the classification results of each through-dislocation 999 within wafer 9. Furthermore, processing circuit 21 stores the classification results of step ST40 in wafer information 35 of database 3.

[0130] (Step ST50) After step ST40, the processing circuit 21 performs step ST50 in the same manner as described above and ends the processing.

[0131] As described above, according to the second embodiment, the wafer 9 has a state in which a first etch pit with a dot-shaped shape corresponding to a through dislocation 999 is formed on the back side by etching based on the etch pit method, and a second etch pit with a hexagonal shape corresponding to a through dislocation 999 is formed on the surface. The processing circuit 21 detects the position of the first etch pit represented by the image and uses it as the first coordinate P1 (x1, y1), and detects the position of the second etch pit represented by the image and uses it as the second coordinate P2 (x2, y2). Therefore, even when using the etch pit method, by having a structure that can detect the first and second coordinates of the through dislocation based on the image of the wafer, the same effect as in the first embodiment can be obtained.

[0132] Furthermore, according to the second embodiment, the processing circuit 21 detects the position of the midpoint of the diagonal in the hexagonal shape and uses it as the second coordinate, and detects the position of the point shape and uses it as the first coordinate. Therefore, when using the etch pit method, by using the same method to detect the second coordinate of each etch pit, the detection deviation of the second coordinate relative to the etch pit can be reduced.

[0133] Furthermore, according to the second embodiment, when the second coordinate is detected but the first coordinate is not detected, the processing circuit 21 outputs a detection result that includes the second coordinate but not the first coordinate. Based on this detection result, the processing circuit 21 outputs an analysis result that does not include the tilt θ of the dislocation line. When the analysis result does not include the tilt θ, the processing circuit 21 classifies the through dislocation as insufficient etching. Therefore, in the etch pit method, insufficient etching can be detected when it exists.

[0134] Furthermore, according to the second embodiment, the acquisition unit, which includes the imaging device 1 and the acquisition function 211, may include an optical microscope device 1pm, and images g4, g5, and g6 of the wafer 9 are acquired by imaging the wafer 9 using the optical microscope device 1pm. In this case, the optical microscope device in any imaging device capable of imaging wafers can be used to image and acquire images of the wafer.

[0135] <Modifications of the Second Embodiment> The second embodiment uses the etch pit method and an optical microscope device 1pm, but is not limited to this. For example, the second embodiment can also be modified to use the etch pit method and use an X-ray topology device 1xrt instead of the optical microscope device 1pm. Other structures are the same as the second embodiment. In this case, the processing circuit 21 detects the position of the midpoint of the diagonal in the hexagonal shape based on the image of the surface of the wafer 9 and uses it as the second coordinate. In addition, the processing circuit 21 detects the position of the dot-shaped shape based on the image of the back side of the wafer 9 and uses it as the first coordinate. Even with this modification, the same effect as the second embodiment can be obtained. In addition, similarly, if the processing circuit 21 detects the second coordinate but not the first coordinate, it outputs an analysis result that does not include the tilt θ of the dislocation line based on the detection result, and classifies the penetrating dislocation as insufficient etching. Therefore, as described above, insufficient etching in the etch pit method can be detected.

[0136] According to at least one embodiment described above, the tilt of dislocation lines within a wafer can be controlled over a wide range. This is also true in at least one of the modifications described above.

[0137] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as set forth in the claims and its equivalents.< / m> < / m> < / m> < / n> < / m>

Claims

1. A semiconductor inspection device, characterized in that, have: The acquisition unit acquires images of the wafer by photographing it; The detection unit, based on the image, detects a first coordinate of a through-hole dislocation appearing on the back side of the wafer and a second coordinate of a through-hole dislocation appearing on the surface of the wafer; The analysis unit analyzes the inclination of the dislocation line penetrating the dislocation relative to the thickness direction of the wafer based on the first coordinate, the second coordinate, and the thickness of the wafer. as well as The classification department classifies the penetrating dislocations based on the analysis results.

2. The semiconductor inspection apparatus according to claim 1, characterized in that, The classification department classifies the penetrating dislocations based on whether the tilt indicated by the analysis results is within a threshold range.

3. The semiconductor inspection apparatus according to claim 1 or 2, characterized in that, The analysis unit further analyzes the extension direction of the dislocation line based on the first coordinate and the second coordinate.

4. The semiconductor inspection apparatus according to claim 3, characterized in that, The classification department further classifies the penetrating dislocation based on which of the multiple directional ranges the extension direction indicates in the analysis results.

5. The semiconductor inspection apparatus according to claim 3, characterized in that, The classification unit classifies whether the through dislocation is a mixed dislocation based on the image, and combines the classification result representing the mixed dislocation with the classification result based on the analysis result, thereby further classifying the through dislocation.

6. The semiconductor inspection apparatus according to claim 3, characterized in that, The classification unit identifies abnormal regions within the wafer based on the classification results of each through dislocation within the wafer.

7. The semiconductor inspection apparatus according to claim 3, characterized in that, The analysis unit predicts, based on the first coordinate, the second coordinate, and the extension direction of the dislocation line, the third coordinate of a penetrating dislocation appearing on the back side of another wafer, which is different from the wafer and cut from the same ingot from which the wafer was cut, and the fourth coordinate of a penetrating dislocation appearing on the surface of the other wafer.

8. The semiconductor inspection apparatus according to claim 7, characterized in that, The classification department classifies through dislocations having the third coordinate and the fourth coordinate according to the classification results of through dislocations having the first coordinate and the second coordinate.

9. The semiconductor inspection apparatus according to claim 1, characterized in that, The acquisition unit acquires images of the back side and the surface side of the wafer by maintaining a holding state of the wafer. The detection unit detects the first coordinate based on the image of the back side and detects the second coordinate based on the image of the surface.

10. The semiconductor inspection apparatus according to claim 1, characterized in that, The wafer has a state in which a first etch pit with a dot-shaped shape corresponding to the through dislocation is formed on the back side by etching based on the etch pit method, and a second etch pit with a hexagonal shape corresponding to the through dislocation is formed on the surface. The detection unit detects the position of the first etch pit represented by the image and uses that position as the first coordinate; it also detects the position of the second etch pit represented by the image and uses that position as the second coordinate.

11. The semiconductor inspection apparatus according to claim 10, characterized in that, The detection unit detects the position of the midpoint of the diagonal in the hexagonal shape and uses this position as the second coordinate, and detects the position of the dotted shape and uses this position as the first coordinate.

12. The semiconductor inspection apparatus according to claim 10, characterized in that, If the detection unit detects the second coordinate but not the first coordinate, it outputs a detection result that includes the second coordinate but not the first coordinate. Based on the detection results, the analysis unit outputs analysis results that do not include the tilt angle. If the analysis results do not include the tilt, the classification unit classifies the through dislocation as insufficiently etched.

13. The semiconductor inspection apparatus according to any one of claims 9 to 12, characterized in that, The acquisition unit includes an X-ray topology device, which acquires an image of the wafer by taking a picture of the wafer using the X-ray topology device.

14. The semiconductor inspection apparatus according to any one of claims 10 to 12, characterized in that, The acquisition unit includes an optical microscope, which captures images of the wafer by photographing the wafer with the optical microscope.

15. An inspection method performed by a semiconductor inspection apparatus, characterized in that, have: Images of the wafer are obtained by photographing the wafer; Based on the image, the first coordinates of the through dislocations appearing on the back side of the wafer and the second coordinates of the through dislocations appearing on the surface of the wafer are detected. The inclination of the dislocation line penetrating the dislocation relative to the thickness direction of the wafer is analyzed based on the first coordinate, the second coordinate, and the thickness of the wafer. as well as The penetrating dislocations are classified based on the analysis results.

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