A method for manufacturing a semiconductor structure

Abstract

The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a buffer layer on the substrate, and forming a hard mask layer on the buffer layer; forming a groove penetrating through the hard mask layer and the buffer layer and extending into the substrate, wherein the groove is enclosed into a closed pattern; removing the hard mask layer and the buffer layer in the region enclosed by the groove to form an opening, wherein the substrate exposed by the groove and the opening presents a top-high-and-bottom-low pattern; performing local thermal oxidation on the substrate exposed by the groove and the opening to form an oxidation layer; and flattening the upper surface of the oxidation layer and the hard mask layer by a CMP process. The technical scheme of the application can effectively reduce the generation of scratches in the CMP process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor structure. Background Technology

[0002] Low-voltage IGBT (Insulated Gate Bipolar Transistor) devices typically employ a planar LOCOS (Local Oxidation of Silicon) structure, while high-voltage IGBT devices typically employ a trench LOCOS structure. The trench LOCOS structure effectively improves the device's breakdown voltage and increases device density.

[0003] Because the LOCOS process produces a bird's beak, and the impact of the beak on subsequent processes is significant, CMP (Chemical Mechanical Polishing) is used for planarization. However, the hard mask layer (such as a silicon nitride layer) protrudes much higher than other areas at the beak location, causing the hard mask layer to peel off during CMP polishing, resulting in severe scratches.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, the present invention provides a method for fabricating a semiconductor structure, comprising: A substrate is provided, a buffer layer is formed on the substrate, and a hard mask layer is formed on the buffer layer; A trench is formed that penetrates the hard mask layer and the buffer layer and extends into the substrate, wherein the trench forms a closed pattern; The hard mask layer and the buffer layer within the area enclosed by the trench are removed to form an opening, wherein the substrate exposed by the trench and the opening has a morphology that is high in the middle and low around the edges; The substrate exposed by the trenches and openings is subjected to localized thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process. The removal of the hard mask layer and the buffer layer within the area enclosed by the trench to form an opening includes: A protective layer is formed within the trench, and a patterned first photoresist layer is formed on the hard mask layer; Using the patterned first photoresist layer as a mask, the hard mask layer and the buffer layer in the area enclosed by the trench are removed by an etching process to form the opening; Remove the first photoresist layer and the protective layer.

[0007] For example, the protective layer is a spin-coated carbon layer.

[0008] For example, the protective layer is a photoresist layer.

[0009] For example, when removing the hard mask layer and the buffer layer within the area enclosed by the trench, a portion of the substrate within the area enclosed by the trench is also removed; The bottom wall of the opening is higher than the bottom wall of the trench and lower than the lower surface of the buffer layer.

[0010] For example, the buffer layer is a silicon oxide layer.

[0011] For example, the substrate is a silicon substrate; The buffer layer is formed on the substrate by an ISSG process or a thermal oxidation process.

[0012] For example, the hard mask layer is a silicon nitride layer.

[0013] For example, the hard mask layer is formed on the buffer layer by an LPCVD process.

[0014] For example, before planarizing the upper surfaces of the oxide layer and the hard mask layer using a CMP process, the fabrication method further includes: Remove the silicon oxynitride layer on the upper surface of the hard mask layer.

[0015] According to the semiconductor structure fabrication method of the present invention, by first forming a trench that penetrates the hard mask layer and the buffer layer and extends into the substrate, and then removing the hard mask layer and the buffer layer in the area enclosed by the trench to form an opening, the substrate exposed by the trench and the opening can exhibit a morphology that is high in the middle and low around the edges. As a result, the oxide layer formed by local thermal oxidation will also exhibit a morphology that is high in the middle and low around the edges. The oxide layer protruding in the middle can share the grinding stress together with the hard mask layer protruding at the bird's beak, thereby effectively reducing the risk of peeling off the hard mask layer in the CMP process and reducing the generation of scratches. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings, Figures 1A-1D These are cross-sectional schematic diagrams of the structures corresponding to each step of the semiconductor structure fabrication method in related technologies; Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 3A-3I This is a cross-sectional schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0017] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0018] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0020] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0023] See attached document Figures 1A-1D An exemplary method for fabricating semiconductor structures in related technologies is provided. This fabrication method includes the following steps: First, see appendix Figure 1A A substrate 10 is provided, and a buffer layer 20 is formed on the substrate 10 by a process such as thermal oxidation, and then a hard mask layer 30 is formed on the buffer layer 20 by a deposition process such as CVD (Chemical Vapor Deposition).

[0024] Then, see appendix. Figure 1B An opening 40 is formed through the hard mask layer 30 and the buffer layer 20 by photolithography and etching processes. For example, the opening 40 may extend into the substrate 10.

[0025] Then, see appendix. Figure 1C The substrate 10 on the inner wall of the opening 40 is locally thermally oxidized to form an oxide layer 50. In this step, a bird's beak is formed at the edge of the opening 40. Figure 1C The protrusion of the hard mask layer 30 at point A is much higher than at other locations.

[0026] Then, see appendix. Figure 1DThe upper surfaces of the oxide layer 50 and the hard mask layer 30 are planarized using a CMP process. During this process, because the protrusion of the hard mask layer 30 at the beak position is much higher than other positions, the protruding hard mask layer 30 will be subjected to greater stress during CMP polishing, which can easily lead to the hard mask layer 30 peeling off and producing severe scratches, especially arc scratches, during polishing.

[0027] The following is a reference to the appendix. Figure 2 An exemplary method for fabricating a semiconductor structure according to an embodiment of this application will be described, the method comprising the following steps: S10: Provide a substrate, form a buffer layer on the substrate, and form a hard mask layer on the buffer layer.

[0028] S20: Forming trenches that penetrate the hard mask layer and the buffer layer and extend into the substrate, wherein the trenches form a closed pattern.

[0029] S30: Remove the hard mask layer and buffer layer in the area enclosed by the trench to form an opening, wherein the substrate exposed by the trench and the opening has a morphology that is high in the middle and low around the edges.

[0030] S40: Local thermal oxidation of the substrate exposed by trenches and openings to form an oxide layer.

[0031] S50: The upper surfaces of the oxide layer and hard mask layer are planarized using CMP process; The process of removing the hard mask layer and buffer layer within the area enclosed by the trench to form an opening includes: A protective layer is formed within the trench, and a patterned first photoresist layer is formed on the hard mask layer; Using a patterned first photoresist layer as a mask, the hard mask layer and buffer layer in the area enclosed by the trench are removed by an etching process to form an opening; Remove the first photoresist layer and the protective layer.

[0032] According to the semiconductor structure fabrication method of the present application embodiment, by first forming a trench that penetrates the hard mask layer and the buffer layer and extends into the substrate, and then removing the hard mask layer and the buffer layer in the area enclosed by the trench to form an opening, the substrate exposed by the trench and the opening can present a morphology that is high in the middle and low around the edges. As a result, the oxide layer formed by local thermal oxidation will also present a morphology that is high in the middle and low around the edges. The oxide layer protruding in the middle can share the grinding stress together with the hard mask layer protruding at the bird's beak, thereby effectively reducing the risk of peeling off the hard mask layer in the CMP process and reducing the generation of scratches.

[0033] The following is a reference to the appendix. Figures 3A-3IA method for fabricating a semiconductor structure according to an embodiment of this application (including the steps S10-S50 described above) will be described in detail.

[0034] In step S10, see Appendix Figure 3A A substrate 100 is provided, a buffer layer 200 is formed on the substrate 100, and a hard mask layer 300 is formed on the buffer layer 200.

[0035] In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may also be a substrate of other suitable materials that can be locally thermally oxidized to form an oxide layer 900.

[0036] The buffer layer 200 serves as a transition layer, providing stress buffering between the substrate 100 and the hard mask layer 300, and improving the stress mismatch problem between the substrate 100 and the hard mask layer 300. In this embodiment, the buffer layer 200 is a silicon oxide layer, formed on the substrate 100 by ISSG (In Situ Steam Generation) or thermal oxidation processes. The buffer layer 200 formed by these processes has good quality and small thickness, and can effectively buffer the stress in the subsequently formed hard mask layer 300.

[0037] The ISSG process uses oxygen mixed with a small amount of hydrogen as the reaction atmosphere. Under high temperature and low pressure, a large number of oxygen free radicals with strong oxidizing properties are generated, resulting in fewer defects in the oxide film obtained from the reaction and a lower interface state density.

[0038] In this embodiment, the hard mask layer 300 is a silicon nitride layer, but it can also be any other suitable hard mask material known to those skilled in the art. The hard mask layer 300 can be formed on the buffer layer 200 using a deposition process such as CVD. For example, the hard mask layer 300 is formed on the buffer layer 200 using LPCVD (Low Pressure Chemical Vapor Deposition). The LPCVD process can reduce the stress in the hard mask layer 300 by adjusting process parameters such as the ratio of reactant gases and the pressure in the reaction chamber, thereby reducing the thickness of the buffer layer 200. In other words, a thinner buffer layer 200 can effectively buffer the stress in the hard mask layer 300. In some embodiments, the hard mask layer 300 can also be formed on the buffer layer 200 using PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0039] In step S20, see Appendix Figures 3B-3CThis forms trenches 500 that penetrate the hard mask layer 300 and the buffer layer 200 and extend into the substrate 100, wherein the trenches 500 form a closed pattern. The trenches 500 forming a closed pattern means that, from a top-view perspective (…), Figure 3C From a top-down perspective, the extension path of the groove 500 closes, forming a closed outline. For example, the closed shape formed by the groove 500 can be a rectangle (the groove 500 appears as a rectangle from a top-down perspective), a circle (the groove 500 appears as a rectangle from a top-down perspective), etc.

[0040] For details, please refer to the appendix. Figure 3B A patterned second photoresist layer 400 is formed on the hard mask layer 300. The second photoresist layer 400 can be formed on the hard mask layer 300 by spin coating and patterned by photolithography.

[0041] Then, see appendix. Figure 3C Using a patterned second photoresist layer 400 as a mask, an anisotropic dry etching process is used to etch the hard mask layer 300, the buffer layer 200, and the substrate 100 to form trenches 500. After the trenches 500 are formed, the second photoresist layer 400 is removed.

[0042] In step S30, see Appendix Figure 3D - Figure 3G The hard mask layer 300 and buffer layer 200 within the area enclosed by the trench 500 are removed to form an opening 800, wherein the substrate 100 exposed by the trench 500 and the opening 800 exhibits a morphology that is high in the middle and low around the edges.

[0043] In this embodiment, in step S30, please refer to the appendix first. Figure 3D A protective layer 600 is formed within the trench 500. The protective layer 600 protects the hard mask layer 300, buffer layer 200, and substrate 100 outside the area enclosed by the trench 500 to prevent them from being etched in subsequent steps. For example, the protective layer 600 can be a spin-coated carbon layer, which is first formed within the trench 500 and on the hard mask layer 300 by a spin-coating process, and then the spin-coated carbon layer above the upper surface of the hard mask layer 300 is removed by an etching process or a CMP process, leaving only the spin-coated carbon layer located within the trench 500.

[0044] Then see Appendix Figure 3E A patterned first photoresist layer 700 is formed on the hard mask layer 300. The first photoresist layer 700 can be formed on the hard mask layer 300 by spin coating and patterned by photolithography. The patterned first photoresist layer 700 exposes the upper surface of the hard mask layer 300 within the area enclosed by the trench 500.

[0045] Then see Appendix Figure 3FUsing a patterned first photoresist layer 700 as a mask, the hard mask layer 300 and buffer layer 200 within the area enclosed by the trench 500 are removed by an etching process to form an opening 800. This etching process can be a dry etching process or a wet etching process. In this embodiment, when removing the hard mask layer 300 and buffer layer 200 within the area enclosed by the trench 500, a portion of the substrate 100 within the area enclosed by the trench 500 is also removed. That is, after removing the hard mask layer 300 and buffer layer 200 within the area enclosed by the trench 500, the exposed substrate 100 is further etched so that the bottom wall of the finally formed opening 800 is higher than the bottom wall of the trench 500 and lower than the lower surface of the buffer layer 200. In some other embodiments, the hard mask layer 300 and the buffer layer 200 within the area enclosed by the trench 500 can be removed by an etching process, but the exposed substrate 100 is not etched, and the bottom wall of the final opening 800 is flush with the lower surface of the buffer layer 200.

[0046] Then see Appendix Figure 3F and Figure 3G The first photoresist layer 700 and the protective layer 600 are removed. After the first photoresist layer 700 and the protective layer 600 are removed, the substrate 100 exposed by the trench 500 and the opening 800 has a morphology that is high in the middle and low around the edges.

[0047] In some other embodiments, the protective layer 600 can be a photoresist layer. In step S30, a patterned first photoresist layer can be formed on the hard mask layer 300 and in the trench 500. The first photoresist layer fills the trench 500, and the opening pattern in the first photoresist layer exposes the upper surface of the hard mask layer 300 within the area enclosed by the trench 500. The first photoresist layer can be formed on the hard mask layer 300 and in the trench 500 by spin coating and patterned by photolithography. It should be noted that the patterned first photoresist layer fills the trench 500, and the first photoresist layer in the trench 500 serves as a protective layer to protect the hard mask layer 300, buffer layer 200, and substrate 100 outside the area enclosed by the trench 500, so as to prevent them from being etched in subsequent steps.

[0048] Then, using the patterned first photoresist layer as a mask, the hard mask layer 300 and the buffer layer 200 within the area enclosed by the trench 500 are removed by an etching process to form the opening 800. This etching process can be a dry etching process or a wet etching process. For example, when removing the hard mask layer 300 and the buffer layer 200 within the area enclosed by the trench 500, a portion of the substrate 100 within the area enclosed by the trench 500 can also be removed. That is, after removing the hard mask layer 300 and the buffer layer 200 within the area enclosed by the trench 500, the exposed substrate 100 is further etched so that the bottom wall of the finally formed opening 800 is higher than the bottom wall of the trench 500 and lower than the lower surface of the buffer layer 200. For example, when the hard mask layer 300 and buffer layer 200 in the area enclosed by the trench 500 are removed by etching, the exposed substrate 100 may not be etched, and the bottom wall of the final opening 800 is flush with the lower surface of the buffer layer 200.

[0049] After the opening 800 is formed, the first photoresist layer on the hard mask layer 300 and the first photoresist layer (protective layer) in the trench 500 are removed. After the first photoresist layer is removed, the substrate 100 exposed by the trench 500 and the opening 800 has a shape that is high in the middle and low around the edges.

[0050] In step S40, see Appendix Figure 3H Local thermal oxidation is performed on the substrate 100 exposed by the trench 500 and the opening 800 to form an oxide layer 900.

[0051] Localized thermal oxidation refers to the oxidation of the substrate 100 exposed by trenches 500 and openings 800 using water vapor and oxygen at high temperatures (or through other suitable thermal oxidation methods) with hard mask layer 300 and buffer layer 200 as masks, to form an oxide layer 900. A portion of the oxide layer 900 is located on the substrate 100, and a portion protrudes from the upper surface of the substrate 100. Because the substrate 100 exposed by trenches 500 and openings 800 has a shape that is high in the middle and low around the edges, the central position of the formed oxide layer 900 will be significantly raised. Its height can be greater than or equal to the height of the protrusion of the hard mask layer 300 at the "bird's beak" location. Therefore, in subsequent CMP processes, it can share the grinding stress with the protruding hard mask layer 300 at the "bird's beak" location, thereby effectively reducing the risk of peeling off the hard mask layer 300 during the CMP process and reducing the generation of scratches.

[0052] For example, in some embodiments, when the hard mask layer 300 is a silicon nitride layer, the preparation method further includes removing the silicon oxynitride layer on the upper surface of the hard mask layer 300 before step S50. When the hard mask layer 300 is a silicon nitride layer, its upper surface will also be oxidized to a certain extent in step S40 to form a silicon oxynitride layer. Before step S50, this silicon oxynitride layer can be removed to improve the polishing effect of the CMP process in step S50. For example, the silicon oxynitride layer on the upper surface of the hard mask layer 300 can be removed by a wet cleaning process. In some embodiments, when the silicon oxynitride layer on the upper surface of the hard mask layer 300 is extremely thin and has minimal impact on the CMP process, the silicon oxynitride layer on the upper surface of the hard mask layer 300 may not be removed separately, but the CMP process can be performed directly to remove it.

[0053] In step S50, see Appendix Figure 3I The upper surfaces of oxide layer 900 and hard mask layer 300 are planarized using CMP process.

[0054] That is, the upper surfaces of the oxide layer 900 and the hard mask layer 300 are ground using a CMP process until their overall flatness meets the preset requirements. For example, in step S50, the upper surfaces of the oxide layer 900 and the hard mask layer 300 are ground to be flush using a CMP process.

[0055] For example, after step S50, the remaining hard mask layer 300 can be removed by a process such as wet etching.

[0056] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0057] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0058] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0059] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0060] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0061] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, a buffer layer is formed on the substrate, and a hard mask layer is formed on the buffer layer; A trench is formed that penetrates the hard mask layer and the buffer layer and extends into the substrate, wherein the trench forms a closed pattern; The hard mask layer and the buffer layer within the area enclosed by the trench are removed to form an opening, wherein the substrate exposed by the trench and the opening has a morphology that is high in the middle and low around the edges; The substrate exposed by the trenches and openings is subjected to localized thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process. The removal of the hard mask layer and the buffer layer within the area enclosed by the trench to form an opening includes: A protective layer is formed within the trench, and a patterned first photoresist layer is formed on the hard mask layer; Using the patterned first photoresist layer as a mask, the hard mask layer and the buffer layer in the area enclosed by the trench are removed by an etching process to form the opening; Remove the first photoresist layer and the protective layer.

2. The preparation method according to claim 1, characterized in that, The protective layer is a spin-coated carbon layer.

3. The preparation method according to claim 1, characterized in that, The protective layer is a photoresist layer.

4. The preparation method according to claim 1, characterized in that, When removing the hard mask layer and the buffer layer within the area enclosed by the trench, a portion of the substrate within the area enclosed by the trench is also removed; The bottom wall of the opening is higher than the bottom wall of the trench and lower than the lower surface of the buffer layer.

5. The preparation method according to claim 1, characterized in that, The buffer layer is a silicon oxide layer.

6. The preparation method according to claim 5, characterized in that, The substrate is a silicon substrate; The buffer layer is formed on the substrate by an ISSG process or a thermal oxidation process.

7. The preparation method according to claim 1, characterized in that, The hard mask layer is a silicon nitride layer.

8. The preparation method according to claim 7, characterized in that, The hard mask layer is formed on the buffer layer using an LPCVD process.

9. The preparation method according to claim 7, characterized in that, Before planarizing the upper surfaces of the oxide layer and the hard mask layer using a CMP process, the preparation method further includes: Remove the silicon oxynitride layer on the upper surface of the hard mask layer.

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