A method for manufacturing a semiconductor structure

Abstract

The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, forming a first groove on the upper part of the substrate, wherein the first groove is enclosed into a closed pattern, and the bottom size of the cross section of the first groove is larger than the top size of the cross section of the first groove; forming a buffer layer on the substrate, and forming a hard mask layer on the buffer layer, wherein the buffer layer encloses the upper opening of the first groove, so that a cavity is formed at the first groove; patterning the hard mask layer, wherein the projection of the opening pattern in the patterned hard mask layer on the substrate is located in the closed pattern; taking the patterned hard mask layer as a mask, and forming a second groove through the buffer layer and extending into the substrate by an etching process, wherein the second groove is not communicated with the cavity; locally oxidizing the substrate on the inner wall of the second groove to form an oxide layer; and flattening the upper surfaces of the oxide layer and the hard mask layer by a CMP process. The application can reduce the generation of scratches in the CMP process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor structure. Background Technology

[0002] Low-voltage IGBT (Insulated Gate Bipolar Transistor) devices typically employ a planar LOCOS (Local Oxidation of Silicon) structure, while high-voltage IGBT devices typically employ a trench LOCOS structure. The trench LOCOS structure effectively improves the device's breakdown voltage and increases device density.

[0003] Because the LOCOS process produces a bird's beak, and the impact of the beak on subsequent processes is significant, CMP (Chemical Mechanical Polishing) is used for planarization. However, the hard mask layer (such as a silicon nitride layer) protrudes much higher than other areas at the beak location, causing the hard mask layer to peel off during CMP polishing, resulting in severe scratches.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, the present invention provides a method for fabricating a semiconductor structure, comprising: A substrate is provided, and a first trench is formed on the upper part of the substrate, wherein the first trench forms a closed pattern, and the bottom dimension of the cross-section of the first trench is larger than the top dimension of the cross-section of the first trench; A buffer layer is formed on the substrate, and a hard mask layer is formed on the buffer layer, wherein the buffer layer closes the upper opening of the first trench to form a cavity at the first trench; The hard mask layer is patterned, wherein the projection of the opening pattern in the patterned hard mask layer onto the substrate lies within the closed pattern; Using the patterned hard mask layer as a mask, a second trench is formed through the buffer layer and extends into the substrate by an etching process, wherein the second trench is not connected to the cavity; The substrate on the inner wall of the second trench is subjected to localized thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process.

[0007] For example, the cross-section of the first trench is an isosceles trapezoid.

[0008] For example, the top dimension of the cross-section of the first trench is smaller than the thickness of the buffer layer.

[0009] For example, the first trench is formed by a dry etching process.

[0010] For example, the buffer layer is formed by a CVD process.

[0011] For example, the distance between the side of the second groove near the cavity and the cavity is less than or equal to the top dimension of the cross-section of the first groove.

[0012] For example, in the thickness direction of the substrate, the bottom surface of the second trench is not higher than the bottom surface of the first trench.

[0013] For example, the etching process is an anisotropic dry etching process.

[0014] For example, the buffer layer is a silicon oxide layer.

[0015] For example, the hard mask layer is a silicon nitride layer; The hard mask layer is formed on the buffer layer using an LPCVD process.

[0016] According to the semiconductor structure fabrication method of the present invention, by forming a cavity around the second trench that penetrates the buffer layer and extends into the substrate, a space can be provided for the lateral growth of the oxide layer when the substrate on the inner wall of the second trench is locally thermally oxidized. This can significantly reduce the protrusion height of the hard mask layer at the beak, avoid excessive warping of the hard mask layer at the beak, and thus effectively reduce the risk of peeling off the hard mask layer in the CMP process and reduce the generation of scratches. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings, Figures 1A-1DThese are cross-sectional schematic diagrams of the structures corresponding to each step of the semiconductor structure fabrication method in related technologies; Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 3A-3G This is a cross-sectional schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0018] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0019] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0021] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0024] See attached document Figures 1A-1D An exemplary method for fabricating semiconductor structures in related technologies is provided. This fabrication method includes the following steps: First, see appendix Figure 1A A substrate 10 is provided, and a buffer layer 20 is formed on the substrate 10 by a process such as thermal oxidation, and then a hard mask layer 30 is formed on the buffer layer 20 by a deposition process such as CVD (Chemical Vapor Deposition).

[0025] Then, see appendix. Figure 1B An opening 40 is formed through the hard mask layer 30 and the buffer layer 20 by photolithography and etching processes. For example, the opening 40 may extend into the substrate 10.

[0026] Then, see appendix. Figure 1C The substrate 10 on the inner wall of the opening 40 is locally thermally oxidized to form an oxide layer 50. In this step, a bird's beak is formed at the edge of the opening 40. Figure 1C The protrusion of the hard mask layer 30 at point A is much higher than at other locations.

[0027] Then, see appendix. Figure 1DThe upper surfaces of the oxide layer 50 and the hard mask layer 30 are planarized using a CMP process. During this process, because the protrusion of the hard mask layer 30 at the beak position is much higher than other positions, the protruding hard mask layer 30 will be subjected to greater stress during CMP polishing, which can easily lead to the hard mask layer 30 peeling off and producing severe scratches, especially arc scratches, during polishing.

[0028] The following is a reference to the appendix. Figure 2 An exemplary method for fabricating a semiconductor structure according to an embodiment of this application will be described, the method comprising the following steps: S10: Provide a substrate, and form a first trench on the upper part of the substrate, wherein the first trench forms a closed pattern, and the bottom dimension of the cross-section of the first trench is greater than the top dimension of the cross-section of the first trench.

[0029] S20: A buffer layer is formed on the substrate, and a hard mask layer is formed on the buffer layer, wherein the buffer layer closes the upper opening of the first trench so that a cavity is formed at the first trench.

[0030] S30: Patterned hard mask layer, wherein the projection of the opening pattern in the patterned hard mask layer onto the substrate lies within the closed pattern.

[0031] S40: Using a patterned hard mask layer as a mask, a second trench is formed through an etching process, penetrating the buffer layer and extending into the substrate, wherein the second trench is not connected to the cavity.

[0032] S50: Local thermal oxidation of the substrate on the inner wall of the second trench to form an oxide layer.

[0033] S60: The upper surfaces of the oxide layer and hard mask layer are planarized using the CMP process.

[0034] According to the semiconductor structure fabrication method of the present application, by forming a cavity around the second trench that penetrates the buffer layer and extends into the substrate, a space can be provided for the lateral growth of the oxide layer when the substrate on the inner wall of the second trench is locally thermally oxidized. This can significantly reduce the protrusion height of the hard mask layer at the beak, avoid excessive warping of the hard mask layer at the beak, and thus effectively reduce the risk of peeling off the hard mask layer in the CMP process and reduce the generation of scratches.

[0035] The following is a reference to the appendix. Figures 3A-3G A method for fabricating a semiconductor structure according to an embodiment of this application (including the steps S10-S60 described above) will be described in detail.

[0036] In step S10, see Appendix Figures 3A-3BA substrate 100 is provided, and a first trench 110 is formed on the upper part of the substrate 100. The first trench 110 forms a closed pattern, and the bottom dimension of the cross-section of the first trench 110 is larger than the top dimension of the cross-section of the first trench 110.

[0037] For details, please refer to the appendix. Figure 3A A patterned photoresist layer 400 is formed on the substrate 100. The photoresist layer 400 can be formed on the substrate 100 by spin coating and patterned by photolithography.

[0038] Then, see appendix. Figure 3B Using a patterned photoresist layer 400 as a mask, the substrate 100 is etched using a dry etching process to form the first trench 110. That is, the first trench 110 is formed by a dry etching process, which allows for better control over the morphology of the first trench 110.

[0039] In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may also be a substrate of other suitable materials that can be locally thermally oxidized to form an oxide layer 600.

[0040] The first groove 110 forms a closed shape, that is, from a top-down perspective ( Figure 3B From a top-down perspective, the extension path of the first groove 110 is closed, forming a closed outline. For example, the closed shape formed by the first groove 110 can be a rectangle (the first groove 110 is a rectangle from a top-down perspective), a circle (the first groove 110 is a rectangle from a top-down perspective), etc.

[0041] The bottom dimension of the cross-section of the first trench 110 is larger than the top dimension of the cross-section of the first trench 110. That is, the cross-section of the first trench 110 is wider at the bottom and narrower at the top. The bottom and top dimensions of the cross-section of the first trench 110 can refer to the bottom width and top width of the first trench 110. The smaller top dimension of the first trench 110 allows for better sealing of the upper opening of the first trench 110 when the buffer layer 200 is subsequently formed, so that a cavity 111 is formed at the first trench 110, preventing the first trench 110 from being completely filled when the buffer layer 200 is formed; the larger bottom dimension of the first trench 110 allows for a larger space within the first trench 110, that is, a larger space within the cavity 111, thereby providing more space for the growth of the oxide layer 600 during subsequent local thermal oxidation, and better reducing the protrusion height of the hard mask layer 300 at the beak. Using a patterned photoresist layer 400 as a mask, when etching the substrate 100 using a dry etching process, the bombardment direction of the ions can be controlled to etch more of the sidewalls of the first trench 110. This results in the final cross-section of the first trench 110 being wider at the bottom and narrower at the top, meaning the bottom dimension of the first trench 110's cross-section is larger than the top dimension. In some embodiments, the first trench 110 can also be formed using a wet etching process.

[0042] In this embodiment, the cross-section of the first groove 110 is an isosceles trapezoid. In some other embodiments, the two sides of the cross-section of the first groove 110 may also be curved rather than straight.

[0043] In step S20, see Appendix Figure 3C A buffer layer 200 is formed on the substrate 100, and a hard mask layer 300 is formed on the buffer layer 200. The buffer layer 200 closes the upper opening of the first trench 110 so that a cavity 111 is formed at the first trench 110.

[0044] The buffer layer 200 serves as a transition layer, providing stress buffering between the substrate 100 and the hard mask layer 300, thus mitigating stress mismatch between them. In this embodiment, the buffer layer 200 is a silicon oxide layer, formed on the substrate 100 using a CVD (Chemical Vapor Deposition) process. This process effectively seals the upper opening of the first trench 110, preventing it from being filled during the formation of the buffer layer 200. In this embodiment, the top dimension of the cross-section of the first trench 110 is smaller than the thickness of the buffer layer 200; that is, the width of the top opening of the first trench 110 is smaller than the thickness of the buffer layer 200. Preferably, the top dimension of the cross-section of the first trench 110 is less than or equal to half the thickness of the buffer layer 200. By setting the top dimension of the cross-section of the first groove 110 within the aforementioned range, the upper opening of the first groove 110 can be better sealed when the buffer layer 200 is formed, thus preventing the first groove 110 from being completely filled when the buffer layer 200 is formed.

[0045] In this embodiment, the hard mask layer 300 is a silicon nitride layer, but it can also be any other suitable hard mask material known to those skilled in the art. The hard mask layer 300 can be formed on the buffer layer 200 using a deposition process such as CVD. For example, the hard mask layer 300 is formed on the buffer layer 200 using LPCVD (Low Pressure Chemical Vapor Deposition). The LPCVD process can reduce the stress in the hard mask layer 300 by adjusting process parameters such as the ratio of reactant gases and the pressure in the reaction chamber, thereby reducing the thickness of the buffer layer 200. In other words, a thinner buffer layer 200 can effectively buffer the stress in the hard mask layer 300. In some embodiments, the hard mask layer 300 can also be formed on the buffer layer 200 using PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0046] In step S30, see Appendix Figure 3D A patterned hard mask layer 300 is provided, wherein the projection of the opening pattern 310 in the patterned hard mask layer 300 onto the substrate 100 is located within a closed pattern, that is, the projection of the opening pattern 310 in the patterned hard mask layer 300 onto the substrate 100 is located within the area enclosed by the first trench 110. For example, the projection of the opening pattern 310 onto the substrate 100 in the thickness direction does not overlap with the cavity 111.

[0047] Specifically, in step S30, a patterned photoresist layer can first be formed on the hard mask layer 300. The photoresist layer can be formed on the hard mask layer 300 by spin coating and patterned by photolithography. Then, using the photoresist layer as a mask, the hard mask layer 300 is etched by anisotropic dry etching to form an opening pattern 310 penetrating the hard mask layer 300, thus achieving patterning of the hard mask layer 300. After the hard mask layer 300 is patterned, the photoresist layer can be removed before proceeding to subsequent steps.

[0048] In step S40, see Appendix Figure 3E Using a patterned hard mask layer 300 as a mask, a second trench 500 is formed through an etching process, penetrating the buffer layer 200 and extending into the substrate 100. The second trench 500 is not connected to the cavity 111. For example, this etching process can be an anisotropic dry etching process. The cavity 111 circumferentially surrounds the second trench 500, and the circumferential edge of the second trench 500 is adjacent to the cavity 111.

[0049] For example, the distance between the side of the second trench 500 near the cavity 111 and the cavity 111 is less than or equal to the top dimension of the cross-section of the first trench 110. That is, the distance between the wall surface of the second trench 500 near the cavity 111 and the wall surface of the cavity 111 near the second trench 500 is less than or equal to the top dimension of the cross-section of the first trench 110. By setting the distance within the above range, when the substrate 100 on the inner wall of the second trench 500 is subsequently subjected to local thermal oxidation, the substrate 100 between the second trench 500 and the cavity 111 can be completely oxidized and grow laterally into the cavity 111, thereby effectively reducing the protrusion height of the hard mask layer 300 at the beak.

[0050] For example, in the thickness direction of substrate 100 (i.e. Figure 3E In the vertical direction (as shown in the image), the bottom surface of the second trench 500 is not higher than the bottom surface of the first trench 110; that is, the bottom surface of the second trench 500 is flush with or lower than the bottom surface of the first trench 110. This arrangement allows the substrate 100 between the second trench 500 and the cavity 111 to be fully oxidized and to grow laterally into the cavity 111, thereby effectively reducing the protrusion height of the hard mask layer 300 at the beak-like location.

[0051] In step S50, see Appendix Figure 3F The substrate 100 on the inner wall of the second trench 500 is locally thermally oxidized to form an oxide layer 600.

[0052] Localized thermal oxidation refers to oxidizing the substrate 100 on the inner wall of the second trench 500 using water vapor and oxygen at high temperature (or through other suitable thermal oxidation methods) with a hard mask layer 300 and a buffer layer 200 as masks, to form an oxide layer 600. A portion of the oxide layer 600 is located on the substrate 100, and a portion protrudes from the upper surface of the substrate 100. In this embodiment, both the oxide layer 600 and the buffer layer 200 are silicon oxide layers. Due to the presence of the cavity 111 surrounding the second trench 500 circumferentially, the substrate 100 between the second trench 500 and the cavity 111 can grow laterally into the cavity 111 after oxidation. This effectively reduces the protrusion height of the hard mask layer 300 at the "bird's beak" location, avoids excessive warping of the hard mask layer 300 at the "bird's beak" location, and further effectively reduces the risk of peeling off the hard mask layer 300 in subsequent CMP processes, reducing the generation of scratches.

[0053] For example, in some embodiments, when the hard mask layer 300 is a silicon nitride layer, the preparation method further includes removing the silicon oxynitride layer on the upper surface of the hard mask layer 300 before step S60. When the hard mask layer 300 is a silicon nitride layer, its upper surface will also be oxidized to a certain extent in step S50 to form a silicon oxynitride layer. Before step S60, this silicon oxynitride layer can be removed to improve the polishing effect of the CMP process in step S60. For example, the silicon oxynitride layer on the upper surface of the hard mask layer 300 can be removed by a wet cleaning process. In some embodiments, when the thickness of the silicon oxynitride layer on the upper surface of the hard mask layer 300 is extremely thin and its impact on the CMP process is minimal, the silicon oxynitride layer on the upper surface of the hard mask layer 300 may not be removed separately, but the CMP process can be performed directly to remove it.

[0054] In step S60, see Appendix Figure 3G The upper surfaces of the oxide layer 600 and the hard mask layer 300 are planarized using a CMP process.

[0055] That is, the upper surfaces of the oxide layer 600 and the hard mask layer 300 are ground using a CMP process until their overall flatness meets the preset requirements. For example, in step S60, the upper surfaces of the oxide layer 600 and the hard mask layer 300 are ground to be flush using a CMP process.

[0056] For example, after step S60, the remaining hard mask layer 300 can be removed by a process such as wet etching.

[0057] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0058] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0059] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0060] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0061] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0062] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first trench is formed on the upper part of the substrate, wherein the first trench forms a closed pattern, and the bottom dimension of the cross-section of the first trench is larger than the top dimension of the cross-section of the first trench; A buffer layer is formed on the substrate, and a hard mask layer is formed on the buffer layer, wherein the buffer layer closes the upper opening of the first trench to form a cavity at the first trench; The hard mask layer is patterned, wherein the projection of the opening pattern in the patterned hard mask layer onto the substrate lies within the closed pattern; Using the patterned hard mask layer as a mask, a second trench is formed through the buffer layer and extends into the substrate by an etching process, wherein the second trench is not connected to the cavity; The substrate on the inner wall of the second trench is subjected to localized thermal oxidation to form an oxide layer; The upper surfaces of the oxide layer and the hard mask layer are planarized using a CMP process.

2. The preparation method according to claim 1, characterized in that, The cross-section of the first trench is an isosceles trapezoid.

3. The preparation method according to claim 1, characterized in that, The top dimension of the cross-section of the first trench is smaller than the thickness of the buffer layer.

4. The preparation method according to claim 1, characterized in that, The first trench was formed by a dry etching process.

5. The preparation method according to claim 1, characterized in that, The buffer layer is formed by a CVD process.

6. The preparation method according to claim 1, characterized in that, The distance between the side of the second groove closest to the cavity and the cavity is less than or equal to the top dimension of the cross-section of the first groove.

7. The preparation method according to claim 1, characterized in that, In the thickness direction of the substrate, the bottom surface of the second trench is not higher than the bottom surface of the first trench.

8. The preparation method according to claim 1, characterized in that, The etching process is an anisotropic dry etching process.

9. The preparation method according to claim 1, characterized in that, The buffer layer is a silicon oxide layer.

10. The preparation method according to claim 1, characterized in that, The hard mask layer is a silicon nitride layer; The hard mask layer is formed on the buffer layer using an LPCVD process.

Images