Method for manufacturing a semiconductor structure and semiconductor device

Abstract

The application discloses a semiconductor structure manufacturing method and a semiconductor device. The manufacturing method comprises the following steps: forming an initial structure on a substrate; the initial structure comprises a plurality of semiconductor bodies arranged side by side along a first direction; the sidewall of the semiconductor body is covered with a first protective layer, and the gap between the semiconductor bodies is filled with a first isolation layer; a first mask layer covering the area outside the top of the protective layer is formed on the surface of the initial structure; the first protective layer is etched to a partial depth through the area not covered by the first mask layer; the first mask layer is removed, and the first isolation layer and the remaining first protective layer are etched synchronously until the thickness of the first isolation layer and the remaining first protective layer in a second direction both belong to a preset thickness range, and the thickness difference between the first isolation layer and the first protective layer is less than a preset thickness difference.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and a semiconductor device. Background Technology

[0002] In some semiconductor fabrication processes, particularly for highly integrated products like 3D transistors, it's necessary to create a structure of narrow semiconductor substrates arranged sequentially at intervals. Transistors of various shapes and orientations are then formed on these semiconductor substrates. During fabrication, trenches are formed between the semiconductor substrates, such as in STI (Shallow Trench Isolation). These trenches are filled with a dielectric material and then etched to a certain depth. The exposed semiconductor substrate structure is then processed to ultimately form the transistor.

[0003] With the continuous development of semiconductor technology and the improvement of product integration and device density, the dielectric material in the back-etch filling trench in the above manufacturing process will show a more obvious "similing" morphology. That is, after back etching, the dielectric material in the trench will show a morphology that is high on both sides (close to the semiconductor body) and low in the middle (away from the semiconductor body).

[0004] This phenomenon can affect the stability of subsequent processes, resulting in a smaller process window for some processes, making them more prone to process defects, deteriorating the morphology of subsequent structures, and thus reducing the product's WAT (Wafer Acceptance Test) performance. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor device.

[0006] On one hand, this disclosure provides a method for fabricating a semiconductor structure, comprising: forming an initial structure on a substrate; the initial structure comprising a plurality of semiconductor bodies extending along a first direction and arranged side by side; the sidewalls of the semiconductor bodies being covered with a first protective layer, and the gaps between the semiconductor bodies being filled with a first isolation layer; the first direction being parallel to the surface of the substrate; forming a first mask layer on the surface of the initial structure covering an area other than the top of the first protective layer; etching a portion of the first protective layer through the area not covered by the first mask layer; removing the first mask layer and simultaneously etching the first isolation layer and the remaining portion of the first protective layer until the thickness of the first isolation layer and the remaining portion of the first protective layer in a second direction is within a preset thickness range, and the thickness difference between the first isolation layer and the first protective layer is less than a preset thickness difference; wherein, the second direction is perpendicular to the surface of the substrate.

[0007] In some embodiments, the top of the semiconductor body is further covered with a second protective layer; the formation of a first mask layer covering the area outside the top of the first protective layer on the surface of the initial structure includes: forming an auxiliary layer that covers at least the surface of the first isolation layer and the sidewall of the second protective layer; forming a second mask layer covering the area above the first isolation layer on the surface of the auxiliary layer; wherein the second mask layer and the second protective layer constitute the first mask layer.

[0008] In some embodiments, forming an auxiliary layer that at least covers the surface of the first isolation layer and the sidewalls of the second protective layer includes depositing a first dielectric material on the surface of the first isolation layer, the surface of the second protective layer, and the sidewalls to form the auxiliary layer.

[0009] In some embodiments, forming a second mask layer covering the first isolation layer on the surface of the auxiliary layer includes: depositing a second dielectric material on the auxiliary layer such that the second dielectric material covers the first isolation layer and the second protective layer; grinding the second dielectric material until the second protective layer is exposed, with the remaining second dielectric material constituting the second mask layer.

[0010] In some embodiments, etching a portion of the first protective layer through the area not covered by the first mask layer includes: etching the auxiliary layer and the first protective layer between the second mask layer and the second protective layer until the first protective layer is removed to a predetermined depth.

[0011] In some embodiments, removing the first mask layer and simultaneously etching the first isolation layer and the remaining portion of the first protective layer includes: removing the first mask layer by a first etching process; and continuing to etch the first isolation layer and the first protective layer by the first etching process.

[0012] In some embodiments, removing the first mask layer and simultaneously etching the first isolation layer and the remaining portion of the first protective layer includes: removing the first mask layer using a preset process; etching the first isolation layer and the first protective layer using a second etching process; wherein the second etching process is different from the preset process.

[0013] In some embodiments, forming an initial structure on a substrate includes: forming a plurality of semiconductor bodies extending along the first direction and arranged side by side on a substrate; forming a first protective layer of a first dielectric material on the surface of the semiconductor bodies; filling the gaps between the semiconductor bodies with a liquid third dielectric material; and curing the third dielectric material to form the first isolation layer.

[0014] In some embodiments, the method further includes: performing ion implantation on the semiconductor body not covered by the first isolation layer and the first protective layer; forming a gate structure extending along a third direction and bridging the plurality of semiconductor bodies on the remaining first isolation layer and the first protective layer; the semiconductor bodies and the gate structure are used to form a transistor; wherein the third direction is parallel to the substrate surface and has an angle with the first direction.

[0015] In another aspect, embodiments of this disclosure also provide a semiconductor device, wherein at least a portion of the semiconductor structure in the semiconductor device is formed using any of the methods described above; or, the semiconductor device includes the semiconductor structure described above.

[0016] The semiconductor structure fabrication method provided in this disclosure involves forming a first mask layer to block areas outside the first protective layer before partially removing the first isolation layer and the first protective layer that fill the gaps between the semiconductor bodies. Then, a portion of the first protective layer is etched away, followed by simultaneous etching of the first protective layer and the first isolation layer. This results in a larger remaining etching window for the first isolation layer during simultaneous etching, reducing the occurrence of "smile" morphologies. Consequently, the final thickness of the retained first isolation layer and the first protective layer is substantially the same in the second direction, optimizing the structural morphology, facilitating a larger process window for subsequent processes, improving product yield, and optimizing WAT performance. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0018] Figure 2 This is a schematic diagram of the initial structure in a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0019] Figure 3 This is a schematic diagram of the structural morphology produced by a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0020] Figure 4 This is a schematic diagram illustrating the formation of a first mask layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0021] Figures 5A to 5B This is a schematic diagram illustrating two scenarios of forming a second protective layer in a semiconductor structure fabrication method according to embodiments of the present disclosure;

[0022] Figures 6A to 6C This is a schematic diagram illustrating the process of forming a first mask layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0023] Figure 7 This is a schematic diagram showing the etching of the first protective layer in a semiconductor structure fabrication method according to an embodiment of the present disclosure;

[0024] Figure 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0025] Figure 9 This is a semiconductor structure fabrication method based on an embodiment of the present disclosure. Figure 8 A schematic diagram of the semiconductor structure further forming a gate structure. Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0032] To facilitate the explanation of the semiconductor structure and its fabrication method provided in the embodiments of this disclosure, the first direction mentioned below may be the x direction illustrated in the figures, the second direction may be the z direction, and the third direction may be the y direction; the z direction is the thickness direction or vertical direction of the device, the x direction and the y direction may intersect or be perpendicular, and the xoy plane may intersect or be perpendicular to the z direction.

[0033] This disclosure provides a method for fabricating a semiconductor structure. Figure 1 The main steps involved in this method are shown. Figures 2 to 9The diagram illustrates the structural steps involved in the fabrication of a semiconductor structure. For example... Figure 1 As shown, the manufacturing method includes:

[0034] Step S101: An initial structure 120 is formed on the substrate 110. The initial structure 120 includes a plurality of semiconductor bodies 121 extending along a first direction x and arranged in parallel. The sidewalls of the semiconductor bodies 121 are covered with a first protective layer 122, and the gaps between the semiconductor bodies 121 are filled with a first isolation layer 123. The first direction x is parallel to the surface of the substrate 110.

[0035] Here, the substrate 110 can be a substrate, such as a wafer, or a wafer that has undergone some processing to have a specific shape and other structures; the substrate 110 can also be a semiconductor layer or other material layer. An initial structure 120 is formed on the substrate 110. Here, the initial structure 120 refers to the structure formed in one or more steps prior to the improved process steps in the embodiments of this disclosure. The embodiments of this disclosure only provide an exemplary description of the initial structure related to the improved steps of this disclosure, and do not limit other possible specific structures.

[0036] like Figure 2 As shown, the initial structure 120 includes semiconductor bodies 121 extending along the x-direction and arranged side-by-side along the y-direction. In some semiconductor structure fabrication processes including transistors, the semiconductor bodies of the transistors can be formed first. The semiconductor bodies can be doped to define the source, drain, and channel regions of the transistors. Doping processes may include, but are not limited to, diffusion and ion implantation. A conductive layer is formed as the gate of the transistor. Depending on the transistor's connection and layout, the continuous conductive layer may be cut to meet the circuit design requirements. The semiconductor body 121 provided in this embodiment can be a strip, ridge, fin, or other protruding structure protruding from the substrate 110. Its cross-sectional shape in the xy plane can be rectangular, trapezoidal, triangular, or other irregular polygons, and the top may include a circle, ellipse, or other arbitrary arc shape combined with the above-mentioned polygons. Furthermore, the semiconductor body 121 can be a structure used to constitute at least part of one or more transistors. The semiconductor body 121 in the initial structure 120 may have undergone partial or complete doping treatment, or it may not have undergone the above-mentioned doping treatment.

[0037] The constituent materials of the semiconductor body 121 may include, but are not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide, etc., are not limited in the embodiments disclosed herein.

[0038] If the semiconductor body 121 is used to form a partial structure of one or more transistors, the transistor may include, but is not limited to, a three-dimensional transistor, a multi-channel field-effect transistor, a vertical transistor, a planar transistor, or other types of transistors. Of course, the semiconductor body 121 may also be used to form any other arbitrary structure instead of a transistor structure. The embodiments disclosed herein do not limit the function of the semiconductor body 121.

[0039] Furthermore, the spacing between the multiple semiconductor bodies 121 arranged side by side can be equal, unequal, or some can have equal spacing while others have unequal spacing, arranged in a certain pattern, etc. Figure 2 One possible arrangement is shown, but the embodiments disclosed herein are not limited to this one. Figure 2 The method shown.

[0040] The sidewalls of the semiconductor body 121 may be covered with a first protective layer 122. This first protective layer 122 can be a dielectric material, such as a thin film composed of insulating materials like silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or aluminum oxide, or it can be other conductive or semiconductor materials. The first protective layer 122 is attached to the surface of the sidewalls of the semiconductor body 121 to protect or isolate the semiconductor body 121, ensuring that subsequent processes do not affect it. Furthermore, the first protective layer 122 can be etched to a certain thickness to define areas for further processing of the semiconductor body 121.

[0041] The first isolation layer 123 fills the spaces between the semiconductor bodies 121 covered by the first protective layer 122, serving to isolate each semiconductor body 121. It can also serve as a foundation for other structures located between the semiconductor bodies 121, such as gate electrode structures bridging each semiconductor body 121, which may be partially located on the first isolation layer 123. Furthermore, the first isolation layer 123 can be etched to a certain thickness to allow it to work together with the first protective layer 122 to position for further processing of the semiconductor bodies 121. Similar to the first protective layer 122, the first isolation layer 123 can also be a dielectric material, such as insulating materials like silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or aluminum oxide, or other materials capable of achieving the aforementioned purpose.

[0042] In some embodiments, step S101 described above, forming the initial structure 120 on the substrate 110, may include the following specific steps:

[0043] Step S11: Form a plurality of semiconductor bodies 121 extending along a first direction and arranged in parallel on the substrate;

[0044] Step S12: Form a first protective layer 122 of a first dielectric material on the surface of the semiconductor body 121;

[0045] Step S13: Fill the gaps between the semiconductor bodies 121 with a liquid third dielectric material;

[0046] Step S14: Curing the third medium material to form the first isolation layer 123.

[0047] In the embodiments of this disclosure, a plurality of semiconductor bodies 121 extending along a first direction and spaced apart from each other can be formed on a wafer substrate by one or more photolithography or etching processes. Specifically, for semiconductor bodies 121 with very small process dimensions, SADP (Self-Aligned Double Patterning) process technology can also be used to achieve fine semiconductor body 121 structure fabrication.

[0048] After the semiconductor substrates 121 are formed, the gaps between them need to be filled to facilitate subsequent processing. During filling, various deposition techniques, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), and ALD (Atomic Layer Deposition), are used to deposit dielectric materials, such as oxides or nitrides, into the gaps between the semiconductor substrates 121 to form the first isolation layer 123.

[0049] In this embodiment of the disclosure, to fill the gaps between semiconductor bodies 121 with small process dimensions or deep gaps, FCVD (Flowable Chemical Vapor Deposition) can be used. FCVD is an improved CVD technology that can form a more uniform film on the substrate surface by controlling the flowability of the reactants and the deposition conditions. It is very suitable for filling high aspect ratio structures and effectively reduces the problem of voids after filling.

[0050] For example, a liquid third dielectric material, such as an oxide or nitride, can be filled into the gaps between the semiconductor bodies 121. The third dielectric material flows in a liquid form to fill the gaps. Then, the third dielectric material is cured by means of laser, high temperature, or processing at a specific temperature in an inert atmosphere to form the first isolation layer 123.

[0051] During the FCVD filling and curing process described above, temperature, laser, or environment may affect the semiconductor substrate 121, such as causing oxidation of the semiconductor substrate 121. Therefore, a first protective layer 122 needs to be formed on the surface of the semiconductor substrate 121 before FCVD. Of course, if other methods are used to form the first isolation layer 123, the first protective layer 122 can also be formed on the surface of the semiconductor substrate 121 before forming the first isolation layer 123 to facilitate protection of the semiconductor substrate 121 in subsequent processes.

[0052] For example, an oxide film can be formed on the surface of the semiconductor body 121 as the first protective layer 122 by oxidation. For instance, by using ISSG (In-Situ Steam Generation), an oxide film is formed on the surface of the semiconductor body 121 by oxidation treatment with water vapor at high temperature. Alternatively, the first protective layer 122 can be formed by depositing a dielectric material such as an oxide on the surface of the semiconductor body 121 using ALD (Alternating Discharge) method.

[0053] It is understandable that the first protective layer 122 and the first isolation layer 123 formed through steps S12 and S13-S14 will have certain differences in material properties. For example, the first protective layer 122 and the first isolation layer 123 may be different dielectric materials; or the first protective layer 122 and the first isolation layer 123 may be the same dielectric material, such as silicon oxide, but they have different densities or hardnesses. This difference in properties will result in different etching selectivity ratios for the two films during the re-etching process, causing the etching rate of the first protective layer 122 to differ from that of the first isolation layer 123, thus leading to a final thickness difference. Figure 3 As shown, the thickness of the first protective layer 122 after etching is greater than the thickness of the first isolation layer 123. That is, there is a thickness difference of Δh between the center of the remaining first protective layer 122 and the center of the first isolation layer 123, resulting in a recessed shape resembling a "smiling" expression, i.e., a "smiling morphology". This morphology can cause some interference to subsequent processes. For example, it can cause residual metal or other materials formed later to remain in specific areas, reducing the performance of transistors and other devices and deteriorating WAT performance.

[0054] Therefore, the embodiments of this disclosure employ the following steps for further processing:

[0055] Step S102: Form a first mask layer 210 on the surface of the initial structure 120, covering the area outside the top of the first protective layer 122.

[0056] like Figure 4As shown, after preparing the mask layer material, a first mask layer 210 is formed using a patterning process. The first mask layer 210 includes a portion covering the top of the semiconductor body 121 and a portion covering the top of the first isolation layer 123, and exposes the top of the first protective layer 122 located on the sidewall of the semiconductor body 121 to define the etching opening area. This facilitates etching away part of the depth of the first protective layer 122 first, and then etching back to the required thickness. This reduces the "smiling morphology" caused by the different etching selectivity ratios of the first protective layer 122 and the first isolation layer 123, making the thickness of the first protective layer 122 and the first isolation layer 123 basically the same after etching.

[0057] In some embodiments, the first mask layer 210 may also be fabricated in other ways, such as Figure 5A As shown in Figure 5B, the top of the semiconductor body 121 is also covered with a second protective layer 211.

[0058] The coverage area of ​​the second protective layer 211 may be consistent with the area on top of the semiconductor body 121, and the second protective layer 211 does not cover the area where the top of the first protective layer 122 is located, so that the first protective layer 122 located on the sidewall of the semiconductor body 121 is outside the coverage area of ​​the second protective layer 211.

[0059] In an exemplary embodiment, the second protective layer 211 may be formed before the first protective layer 122 is formed, such as... Figure 5A As shown, the second protective layer 211 covers the surface of the top of the semiconductor body 121, and then the first protective layer 122 covering the sidewall of the semiconductor body 121 is formed by means of ISSG or ALD as described above.

[0060] In another exemplary embodiment, the second protective layer 211 may also be formed after the first protective layer 122 is formed, such as... Figure 5B As shown, a first protective layer 122 is formed on the surface of the semiconductor body 121 by means of the above-mentioned ISSG or ALD, so that the first protective layer 122 covers the entire surface of the semiconductor body 121. Then, the second protective layer is formed on the top of the semiconductor body 121 on which the first protective layer 122 is formed.

[0061] Here, the second protective layer 211 can be part of the first mask layer 210, covering the area on top of the semiconductor body 121. In subsequent processes, a structure covering the top area of ​​the first isolation layer 123 can be further formed as another part of the first mask layer 210, thereby forming a complete first mask layer 210 to shield the area outside the top of the first protective layer 122.

[0062] In some embodiments, step S102 above, forming a first mask layer 210 on the surface of the initial structure 120 covering the area other than the top of the first protective layer 122, includes:

[0063] Step S21, as follows Figure 6A As shown, an auxiliary layer 212 is formed that at least covers the surface of the first isolation layer 123 and the sidewalls of the second protective layer 211.

[0064] The auxiliary layer 212 at least covers the sidewalls of the second protective layer 211 and is integrally connected to the first protective layer 122 in the z-direction. Furthermore, by controlling the deposition parameters, the auxiliary layer 212 and the first protective layer 122 preferably have the same thickness, or the thickness of the auxiliary layer 212 is slightly greater than the thickness of the first protective layer 122. Here, the auxiliary layer can be deposited by ALD or other methods to form a structure covering the surface of the second protective layer 211.

[0065] The auxiliary layer 212 can be made of the same material as the first protective layer 122 with the same etching selectivity. For example, the material of the auxiliary layer 212 can be the same as that of the first protective layer 122. That is, the auxiliary layer 212 extends the first protective layer 122 along the z-direction to the surface of the first mask layer 210, thereby facilitating the etching of both the auxiliary layer 212 and the first protective layer 122 to a certain depth in subsequent processes. Of course, the auxiliary layer 212 can also be made of a different material than the first protective layer 122, or the two can have different etching selectivity ratios. However, in physical structure, the auxiliary layer 212 is always an extension of the first protective layer 122 along the z-direction, extending to the surface of the first mask layer 210, corresponding to the opening position required for etching the first protective layer 122.

[0066] Specifically, in some embodiments, step S21 above can be implemented in the following manner:

[0067] A first dielectric material is deposited on the surface of the first isolation layer, the surface of the second protective layer, and the sidewalls to form an auxiliary layer 212. For ease of implementation, it can be deposited directly on all surfaces including the sidewalls and top surface of the second protective layer 211, as well as the top of the isolation layer. Figure 6A As shown. This also allows the auxiliary layer 212 to extend along the z-direction on top of the first protective layer 122, while the auxiliary layer 212 covering other areas does not play a practical role and does not affect the processes before and after.

[0068] Here, the first dielectric material can be an oxide, such as silicon oxide.

[0069] Step S22, as follows Figure 6BAs shown, a second mask layer 213 is formed on the surface of the auxiliary layer 212, covering the first isolation layer 123; wherein, the second mask layer 213 and the second protective layer 211 constitute the first mask layer 210. Since the auxiliary layer 212 has extended the first protective layer 122 in the z direction, the area on the first isolation layer 123 forms a recessed area relative to the second protective layer 211 and the auxiliary layer 212 on its sidewalls. This recessed area can be filled with mask material, which can be the same material as the second protective layer 211, such as silicon nitride or any material that can be used as a hard mask.

[0070] In some embodiments, step S22 above can be implemented in the following manner:

[0071] like Figure 6C As shown, a second dielectric material is deposited on the auxiliary layer 212, so that the second dielectric material covers the first isolation layer and the second protective layer;

[0072] The second dielectric material is ground until the second protective layer 211 is exposed. The remaining second dielectric material forms the second mask layer 213, as described above. Figure 6B As shown.

[0073] Here, the second dielectric material is a different material from the first dielectric material, and the two have different etching selectivity ratios, allowing for selective etching in subsequent processes to first remove the auxiliary layer 212 and the first protective layer 122 formed by the first dielectric material. For example, the second dielectric material can be silicon nitride, silicon carbide, silicon carbonitride, silicon oxide, or other dielectric materials. Furthermore, the second dielectric material can be a material with the same etching selectivity ratio as the material of the second protective layer 211, or the same material.

[0074] Step S103: Etch a portion of the first protective layer 122 through the area not covered by the first mask layer 210.

[0075] The area not covered by the first mask layer 210 is the region located on top of the first protective layer 122 on the sidewall of the semiconductor body 121. By selective etching, this region is etched in the direction opposite to the z-direction, thereby removing a portion of the first protective layer 122. This results in the remaining thickness of the first protective layer 122 being less than the thickness of the first isolation layer 123, thus compensating for the problem that the remaining thickness of the first protective layer 122 is greater than the remaining thickness of the first isolation layer 123 due to the different etching rates of the first protective layer 122 and the first isolation layer 123 in subsequent steps.

[0076] For example, dry etching can be used here to remove a portion of the first protective layer 122.

[0077] In some embodiments, in step S103 above, etching a portion of the first protective layer 122 through the unmasked area of ​​the first mask layer 210 includes:

[0078] Step S31: Etch the auxiliary layer 212 and the first protective layer 122 between the second mask layer 213 and the second protective layer 211 until the first protective layer 122 at a preset depth Δs is removed, as shown. Figure 7 As shown.

[0079] As explained in the above embodiments, during the formation of the first mask layer 210, an area for etching openings can be left through the auxiliary layer 212. Therefore, the auxiliary layer 212 can be etched first to remove the auxiliary layer covering the sidewall of the second protective layer 211 to expose the top of the first protective layer 122, and then the first protective layer 122 can be etched until the first protective layer 122 at a preset depth is etched away.

[0080] It is understandable that, since the auxiliary layer 212 and the first protective layer 122 can be made of materials with the same etch selectivity, such as the same material, the aforementioned etching of the auxiliary layer 212 and the first protective layer 122 can essentially be implemented in the same process step. Of course, the auxiliary layer 212 and the first protective layer 122 can also be made of materials with different etch selectivity. During the etching process, the auxiliary layer can be etched first until the top of the first protective layer 122 located on the sidewall of the semiconductor body 121 is exposed; then, the first protective layer 122 is further etched until the first protective layer 122 at a predetermined depth is etched away. In the above etching process, the etching depth can be controlled by controlling parameters such as the etching process time or dosage, thus preserving the first protective layer 122 that meets the conditions.

[0081] The preset depth can be determined experimentally. The depth selected is one that satisfies the required thickness after subsequent etching of the first isolation layer 123 and the first protective layer 122. For example, to reduce the number of experiments, the depth can be determined by the thickness difference between the edge and center of the "smiling morphology" formed after directly and simultaneously etching the first protective layer 122 and the first isolation layer 123, without using the method described in the embodiments of this disclosure. For example, it is known that conventional processes result in a thickness difference of Δh, such as... Figure 3 As shown, in step S31 above, the preset etching depth Δs can be set to Δh, and the preset etching depth Δs can be finely adjusted based on this. That is, the preset depth can be increased or decreased based on the preset depth Δh according to the final morphology, so as to adjust the etching parameters and obtain the final thickness difference that meets the conditions (the thickness difference between the center of the remaining first protective layer 122 and the remaining first isolation layer 123 after re-etching).

[0082] Step S104: Remove the first mask layer 210 and simultaneously etch the first isolation layer 123 and the remaining portion of the first protective layer 122 until the thicknesses of the first isolation layer 123 and the remaining portion of the first protective layer 122 in the second direction z are both within a preset thickness range, and the thickness difference between the first isolation layer 123 and the first protective layer 122 is less than a preset thickness difference. For example, the preset thickness difference can be 3 nm. Figure 8 As shown.

[0083] In the previous steps, since the first protective layer 122 has been pre-treated, its remaining thickness is less than the thickness of the first insulating layer 123, such as... Figure 7 As shown. Therefore, during the simultaneous etching of the first isolation layer 123 and the first protective layer 122, even if the etching rate of the first isolation layer 123 is greater than the etching rate of the first protective layer 122, the remaining thickness of the first isolation layer 123 after etching will not be significantly less than the remaining thickness of the first protective layer 122, thus avoiding the problem of "smiling morphology".

[0084] It should be noted that the preset thickness range refers to the thickness of the first isolation layer 123 and the first protective layer 122 that need to be retained for subsequent processes or product structures. When this step etches away part of the first isolation layer 123 and the first protective layer 122 so that the remaining portion meets the preset thickness range, the etching purpose of this step has been achieved, and etching can be stopped. At this time, the remaining thickness of the first isolation layer 123 and the remaining thickness of the first protective layer 122 may be the same or different, but the thickness difference is less than the preset thickness difference. This minimizes the impact of "smiling morphology" caused by the remaining thickness of the first protective layer 122 being greater than the thickness of the first isolation layer 123, and also minimizes the impact of the first protective layer 122 being less than the thickness of the first isolation layer 123 (for example, too much of the first protective layer 122 was etched away in step S103).

[0085] In some embodiments, step S104 above, removing the first mask layer 210 and simultaneously etching the first isolation layer 123 and the remaining portion of the first protective layer 122, includes:

[0086] Step S41: Remove the first mask layer 210 by the first etching process;

[0087] Step S42: Continue etching the first isolation layer 123 and the first protective layer 122 through the first etching process.

[0088] In other embodiments, step S104 above, which involves removing the first mask layer 210 and simultaneously etching the first isolation layer 123 and the remaining portion of the first protective layer 122, may further include:

[0089] Step S51: Remove the first mask layer using a preset process;

[0090] Step S52: Etch the first isolation layer and the first protective layer using a second etching process; wherein the second etching process is different from the preset process.

[0091] Since the first isolation layer 123 and the top of the semiconductor body 121 are still covered by the first mask layer 210 after performing step 103, the first mask layer 210 needs to be removed first in order to etch back the first isolation layer 123 and the first protective layer 122. It is worth noting that the semiconductor body 121 needs to be retained regardless of how the first mask layer 210 is removed.

[0092] For example, the first mask layer 210 can be removed by any possible etching method, and the top surface of the semiconductor body 121 and the top surface of the first isolation layer 123 are used as etching stop layers. Then, further etching is performed on the area between the semiconductor bodies 121, thereby simultaneously etching back the first isolation layer 123 and the first protective layer 122.

[0093] The aforementioned preset process can be CMP (Chemical Mechanical Planarization) to grind and remove the first mask layer 210, with the top of the semiconductor body 121 serving as a grinding stop layer. Then, a second etching process is used to further etch the areas between the semiconductor bodies 121, thereby simultaneously etching back the first isolation layer 123 and the first protective layer 122.

[0094] Furthermore, step S104 can be achieved using the same etching process, namely the first etching process described above. Under conditions where the first mask layer 210 has a low etch selectivity with respect to the first isolation layer 123 and the first protective layer 122, for example, a suitable etching solution (hydrofluoric acid (HF) solution, BOE (Buffered Oxide Etch) solution, phosphoric acid (H3PO4) solution, or other acidic or alkaline solutions, etc.) can be selected to directly etch the first mask layer 210. After the first mask layer 210 is removed, the etching solution further etches the first isolation layer 123 and the first protective layer 122, as described in steps S41 and S42 above. That is, the first mask layer 210 is directly removed and the back etching of the first isolation layer 123 and the first protective layer 122 is completed in a single etching step. Of course, it should be noted that the selected etching solution needs to have a high etching selectivity for the material of the semiconductor body 121 in order to preserve the semiconductor body 121 and ensure that its morphology is not damaged as much as possible.

[0095] In some embodiments, such as Figure 9 As shown, the method for fabricating a semiconductor structure may also include:

[0096] Step S201: On the remaining first isolation layer 123 and first protective layer 122, a gate structure 310 is formed that extends along the third direction y and spans the plurality of semiconductor bodies 121; the semiconductor bodies 121 and the gate structure 310 are used to form a transistor.

[0097] This document provides a specific implementation of the subsequent process for the structure processed according to the embodiments of this disclosure. Taking a 3D transistor as an example, the above embodiments can be used in the STI (Shallow Trench Isolation) etch-back process applied to a 3D transistor. The first isolation layer 123 and the first protective layer 122, which fill the gaps between the semiconductor bodies 121, constitute the STI structure. Then, ion implantation is performed on the semiconductor body 121 structure exposed after the STI etch-back in step S201, which can be used to form the source, drain, and channel structures of the 3D transistor.

[0098] Then, in step S202, a gate structure 310 of the transistor is formed, including a gate oxide layer and a gate electrode. This gate structure 310 can be used to control one or more transistors.

[0099] Of course, the above-described solutions of this disclosure are not limited to the processing of STI structures of three-dimensional transistors, but can also be STI structures between other transistors or devices. Furthermore, the above-described solutions of this disclosure are not limited to the processing of STI structures, but can also be the back-etching process of fillers in any structure with similar trenches. After completing the back-etching process in steps S101 to S104, other processing can be performed on the exposed semiconductor body, such as adjusting the morphology of the semiconductor body or changing its conductivity. Other structures can also be further formed based on the structure after step S104. In summary, the above-described steps S201 and S202 are only an exemplary embodiment and are not intended to limit the role and application scenarios of the process steps in the embodiments provided in this disclosure.

[0100] Based on the same inventive concept, this disclosure also provides a semiconductor structure, such as... Figure 8 As shown, it includes:

[0101] An initial structure 120 is located on a substrate 110; the initial structure 120 includes a plurality of semiconductor bodies 121 extending in a first direction x and arranged side by side; the first direction x is parallel to the surface of the substrate;

[0102] A portion of the sidewalls of the semiconductor body 121 is covered with a first protective layer 122;

[0103] A first isolation layer 123 is filled in the gap between the semiconductor bodies 121 covered by the first protective layer 122; wherein the thickness of the first protective layer 122 and the first isolation layer 123 in the second direction z are both within a preset thickness range, and the thickness difference between the first isolation layer 123 and the first protective layer 122 is less than the preset thickness difference, for example, less than 3nm; the second direction z is perpendicular to the substrate surface.

[0104] Here, the structural requirements that the first protective layer 122 and the first isolation layer 123 must meet within a preset thickness range are defined by the thickness difference between them, which is the preset thickness difference. Since their thicknesses are determined in the same etching process, differences in their materials or properties may lead to differences in etching selectivity, resulting in a thickness difference in the final structure. An excessively large thickness difference may negatively impact the application of this semiconductor structure to other processes or specific devices. Therefore, the semiconductor structure provided in this embodiment optimizes the etching process to ensure that the thickness difference between the first protective layer 122 and the first isolation layer 123 is less than the aforementioned preset thickness difference, thereby improving the device performance or process reliability when the semiconductor structure is applied to other processes or specific devices.

[0105] Specifically, the semiconductor structure can be fabricated using any of the semiconductor structure fabrication methods provided in the embodiments of this disclosure. Its structural features and performance characteristics can be understood through the specific descriptions in any of the above embodiments, and will not be repeated here.

[0106] Furthermore, based on the same inventive concept, this disclosure also provides a semiconductor device, in which at least a portion of the structure is fabricated using the methods described in any of the above embodiments. Alternatively, the semiconductor device may include one or more of the semiconductor structures involved in any of the above embodiments. This semiconductor device can be at least a portion of a device used in various chips, memories, or integrated circuit products. The specific properties and structural characteristics of the semiconductor structures included in the semiconductor device can also be understood from the specific descriptions in any of the above embodiments, and will not be repeated here.

[0107] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0108] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0109] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: The initial structure is formed on the substrate; The initial structure includes a plurality of semiconductor bodies extending along a first direction and arranged side by side; the sidewalls of the semiconductor bodies are covered with a first protective layer, and the gaps between the semiconductor bodies are filled with a first isolation layer; the first direction is parallel to the surface of the substrate. A first mask layer is formed on the surface of the initial structure, covering the area outside the top of the first protective layer; The first protective layer is etched to a certain depth through the area not covered by the first mask layer; Remove the first mask layer and simultaneously etch the first isolation layer and the remaining portion of the first protective layer until the thickness of the first isolation layer and the remaining portion of the first protective layer in the second direction is within a preset thickness range, and the thickness difference between the first isolation layer and the first protective layer is less than the preset thickness difference; wherein, the second direction is perpendicular to the substrate surface.

2. The manufacturing method according to claim 1, characterized in that, The top of the semiconductor body is further covered with a second protective layer; the formation of a first mask layer on the surface of the initial structure covering the area outside the top of the first protective layer includes: An auxiliary layer is formed that at least covers the surface of the first isolation layer and the sidewalls of the second protective layer; A second mask layer is formed on the surface of the auxiliary layer, covering the first isolation layer; wherein the second mask layer and the second protective layer constitute the first mask layer.

3. The manufacturing method according to claim 2, characterized in that, The formation of the auxiliary layer, which at least covers the surface of the first insulating layer and the sidewalls of the second protective layer, includes: A first dielectric material is deposited on the surface of the first isolation layer, the surface of the second protective layer, and the sidewalls to form the auxiliary layer.

4. The manufacturing method according to claim 2, characterized in that, The process of forming a second mask layer on the surface of the auxiliary layer, covering the first isolation layer, includes: A second dielectric material is deposited on the auxiliary layer, such that the second dielectric material covers the first isolation layer and the second protective layer; The second dielectric material is ground until the second protective layer is exposed, and the remaining second dielectric material constitutes the second mask layer.

5. The manufacturing method according to claim 2, characterized in that, The etching of a portion of the first protective layer through the area not covered by the first mask layer includes: The auxiliary layer and the first protective layer between the second mask layer and the second protective layer are etched until the first protective layer is removed to a predetermined depth.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that, The step of removing the first mask layer and simultaneously etching the first isolation layer and the remaining portion of the first protective layer includes: The first mask layer is removed by the first etching process; Continue etching the first isolation layer and the first protective layer using the first etching process.

7. The manufacturing method according to any one of claims 1 to 5, characterized in that, The step of removing the first mask layer and simultaneously etching the first isolation layer and the remaining portion of the first protective layer includes: The first mask layer is removed using a preset process; The first isolation layer and the first protective layer are etched by a second etching process; wherein the second etching process is different from the preset process.

8. The manufacturing method according to any one of claims 1 to 5, characterized in that, The formation of the initial structure on the substrate includes: A plurality of semiconductor bodies are formed on the substrate, extending along the first direction and arranged side by side; A first protective layer of a first dielectric material is formed on the surface of the semiconductor body; The gaps between the semiconductor bodies are filled with a liquid third dielectric material; The third medium material is cured to form the first isolation layer.

9. The manufacturing method according to any one of claims 1 to 5, characterized in that, Also includes: On the remaining first isolation layer and first protective layer, a gate structure is formed that extends in a third direction and spans across the plurality of semiconductor bodies; The semiconductor body and the gate structure are used to form a transistor; wherein the third direction is parallel to the substrate surface and has an angle with the first direction.

10. A semiconductor device, characterized in that, At least a portion of the semiconductor structure in the semiconductor device is formed using the method described in any one of claims 1 to 9.

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