Integrated circuit device

Abstract

Integrated circuit devices are disclosed. The integrated circuit devices include a cell transistor including a nanosheet stack, a gate electrode, and a first source / drain region, the nanosheet stack including nanosheets spaced apart from each other in a vertical direction, the gate electrode on the nanosheet stack and extending in a horizontal direction, the first source / drain region connected to the nanosheet stack; a back contact under the cell transistor and connected to the first source / drain region; a first power via at a vertical level lower than a vertical level of the back contact and connected to the back contact; a front line structure on the cell transistor and connected to the cell transistor; and a back line structure under the first power via and connected to the cell transistor. The back line structure is configured such that the back line structure is connected to the first power via and the back contact. Also, a lower surface of the first power via does not overlap the back contact in the vertical direction and includes a recess.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0035528, filed on March 19, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to integrated circuit devices and methods of manufacturing integrated circuit devices, and more specifically, to integrated circuit devices and methods of manufacturing integrated circuit devices including a back-side power transport network (BSPDN) structure having wiring structures formed on the back surface of unit transistors. Background Technology

[0003] With the development of electronic technology, the miniaturization of integrated circuit devices has progressed rapidly. Therefore, in order to achieve high integration while ensuring the required functionality and operating speed in integrated circuit devices, research has been conducted on the efficient design of circuit structures. For example, a power distribution network (PDN) configured to supply power on the back surface of the unit transistors can be provided to minimize wiring congestion and reduce the area of ​​the integrated circuit device. Summary of the Invention

[0004] An integrated circuit device with improved electrical characteristics and a method for manufacturing the integrated circuit device are provided.

[0005] According to one aspect of the disclosure, an integrated circuit device includes: a unit transistor including a nanosheet stack, a gate electrode, and a first source / drain region, the nanosheet stack including a plurality of nanosheets spaced apart from each other in a vertical direction, the gate electrode on the nanosheet stack and extending in a horizontal direction, and the first source / drain region connected to the nanosheet stack; a back contact below the unit transistor and connected to the first source / drain region; a first power via at a vertical level lower than the vertical level of the back contact and connected to the back contact; a front circuit structure on the unit transistor and connected to the unit transistor; and a back circuit structure below the first power via and connected to the unit transistor, wherein the back circuit structure is connected to the first power via and the back contact, and wherein the lower surface of the first power via does not overlap with the back contact in the vertical direction and includes a recess.

[0006] According to one aspect of the disclosure, an integrated circuit device includes: a plurality of unit transistors, each including a plurality of nanosheet stacks, a plurality of gate electrodes, and a plurality of source / drain regions, each of the plurality of nanosheet stacks including a plurality of nanosheets spaced apart from each other in a vertical direction; the plurality of gate electrodes respectively on the plurality of nanosheet stacks and extending in a horizontal direction; the plurality of source / drain regions each between the gate electrodes among the plurality of gate electrodes and connected to one or more of the plurality of nanosheet stacks; a plurality of back contacts, below the plurality of unit transistors and connected to the plurality of source / drain regions; and a plurality of power vias, located above the plurality of back contacts in a vertical direction. A plurality of back contacts are located at a vertical level lower than the vertical level of the plurality of power vias and connected to the plurality of power vias; a front circuit structure is located on the plurality of unit transistors and connected to the plurality of unit transistors; and a back circuit structure is located on the lower surface of the plurality of power vias and connected to the plurality of unit transistors, wherein the back circuit structure is connected to the plurality of back contacts, the plurality of power vias and the plurality of back via contacts, and wherein the lower surface of the first power via, which is not vertically overlapping with the plurality of back contacts, includes a recess.

[0007] According to one aspect of the disclosure, an integrated circuit device includes: a plurality of unit transistors, each including a plurality of unit transistors, a plurality of gate electrodes, and a plurality of source / drain regions, each of the plurality of nanosheet stacks comprising a plurality of nanosheets spaced apart from each other in a vertical direction. The plurality of gate electrodes are respectively on the plurality of nanosheet stacks and extend in a horizontal direction, and the plurality of source / drain regions are respectively between gate electrodes among the plurality of gate electrodes and connected to one or more of the plurality of nanosheet stacks; an intermediate insulating layer below the plurality of unit transistors; a plurality of back contacts disposed below the plurality of unit transistors and electrically connected to a first source / drain region by passing through at least a portion of the intermediate insulating layer; a plurality of power vias connected to the plurality of back contacts and passing through at least a portion of the intermediate insulating layer at a vertical level lower than the vertical level of the plurality of back contacts; a plurality of back via contacts at a vertical level lower than the vertical level of the plurality of power vias and connected to the plurality of power vias; and a plurality of front contacts, on The plurality of unit transistors are on and connected to a second source / drain region among the plurality of source / drain regions; a plurality of gate contacts are on and connected to the plurality of gate electrodes; a front line structure is on the upper surface of each of the plurality of front contacts and the plurality of gate contacts and is connected to the plurality of unit transistors; and a back line structure is on the lower surface of the plurality of power vias and is connected to the plurality of unit transistors, wherein the front line structure is connected to the plurality of front contacts and the plurality of gate contacts, wherein the back line structure is connected to the plurality of power vias and the plurality of back via contacts, and wherein the lower surface of the first power via, which is not vertically overlapped with the plurality of back contacts, includes a recess.

[0008] According to another aspect of the disclosure, a method of manufacturing an integrated circuit device includes: forming a plurality of unit transistors on a substrate, including a plurality of gate structures, a plurality of nanosheet stacks, and a plurality of source / drain regions; forming a front circuit structure on the plurality of unit transistors; forming an intermediate insulating layer on the lower surface of the plurality of unit transistors, and forming a plurality of back contacts and a plurality of power vias passing through at least a portion of the intermediate insulating layer; and forming a back circuit structure on the lower surface of the plurality of power vias, wherein the step of forming the plurality of power vias includes: forming a recess in the lower surface of the plurality of power vias.

[0009] The steps of forming the plurality of power vias may include: forming a back via through at least a portion of an intermediate insulating layer; filling the back via with a conductive material; and forming a power via including a recess by removing a portion of the conductive material.

[0010] The step of removing a portion of the conductive material can be performed by at least one of chemical mechanical polishing (CMP), dry etching, wet etching, and laser ablation.

[0011] The step of forming a power via may include forming a recess in a first power via that is vertically stacked with the plurality of back contacts among the plurality of power vias.

[0012] The step of forming the recess may include: forming the recess into a tapered shape having a horizontal width that gradually decreases toward the plurality of unit transistors.

[0013] The method may further include: forming a vertically extending occupant at the lower part of the region where the plurality of source / drain regions will be disposed, prior to forming the plurality of unit transistors.

[0014] The method may further include forming a plurality of back via contacts on the lower surface of the plurality of power vias.

[0015] The step of forming the plurality of back through-hole contacts can be performed to form the plurality of back through-hole contacts at a vertical level higher than the vertical level of the recess.

[0016] The step of forming the plurality of back via contacts can be performed such that the plurality of power vias and the plurality of back via contacts comprise the same constituent material.

[0017] The step of forming the plurality of back via contacts can be performed such that the plurality of power vias and the plurality of back via contacts comprise different constituent materials.

[0018] The disclosure is not limited to the aspects and features mentioned above, and other aspects and features will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0019] The above and other aspects and features of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0020] Figure 1 This is a schematic diagram illustrating an integrated circuit device according to an embodiment.

[0021] Figure 2 It is along Figure 1 A sectional view taken by line X-X'.

[0022] Figure 3 yes Figure 2 A magnified view of region A.

[0023] Figure 4 This is a cross-sectional view showing an integrated circuit device according to an embodiment.

[0024] Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B as well as Figures 11 to 19 The manufacturing process is shown in sequence. Figures 1 to 3 A cross-sectional view of a method for an integrated circuit device is shown in the figure.

[0025] Figures 20 to 24 The manufacturing process is shown in the order of the embodiments. Figure 4 A cross-sectional view of a method for an integrated circuit device is shown in the figure. Detailed Implementation

[0026] In the following description, one or more embodiments are described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and therefore, repeated descriptions of them will be omitted. In the drawings, for ease of description and clarity, the thickness or dimensions of layers are exaggerated, and therefore may differ slightly from the actual shape and proportions.

[0027] The terms indicating spatial positions (e.g., "below," "under," "down," "upper," "above," etc.) are used solely for ease of understanding to describe the relative positional relationships between the elements shown in the accompanying drawings and are not intended to limit any intent of this disclosure. In addition to the directions described in the drawings, the terms used for relative spatial positions are intended to include changes in the orientation of the semiconductor device. That is, the semiconductor device may be oriented in various directions during use (or manufacture), and even in these cases, the terminology used in this specification will be understood by one of ordinary skill in the art.

[0028] As used herein, multiple “units,” “modules,” “components,” and “blocks” may be implemented as a single component, or a single “unit,” “module,” “component,” and “block” may include multiple components.

[0029] It will be understood that when a component is referred to as being “connected” to or “attached” to another component, it can be directly or indirectly connected to that other component.

[0030] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements, without excluding other elements, unless there is a specific description to the contrary.

[0031] Throughout the specification, when a component is "on" another component, this includes not only the configuration where the component is in contact with the other component, but also the configuration where there is another component between the two components.

[0032] As used herein, the expressions “at least one of a, b, or c” and “at least one of a, b, and c” indicate “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all of a, b, and c”.

[0033] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, the disclosure is not limited by these terms, and these terms are only used to distinguish one element from another.

[0034] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0035] Regarding any method or process described herein, identification codes may be used for ease of description, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than shown unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the disclosure context clearly indicates otherwise.

[0036] Figure 1 This is a schematic layout diagram illustrating an integrated circuit device 100 according to an embodiment. Figure 2 It is along Figure 1 A sectional view taken by line X-X'. Figure 3 yes Figure 2 A magnified view of region A.

[0037] Reference Figures 1 to 3 The integrated circuit device 100 may include a plurality of unit transistors CTRs, a front wiring structure FS, and a back wiring structure BS. The plurality of unit transistors CTRs are disposed at a first vertical level. The front wiring structure FS is disposed at a second vertical level higher than the first vertical level and is electrically connected to the plurality of unit transistors CTRs. The back wiring structure BS is disposed at a third vertical level lower than the first vertical level and is electrically connected to the plurality of unit transistors CTRs.

[0038] In the integrated circuit device 100, a plurality of gate structures 120, a plurality of nanosheet stacks NSS including stacked nanosheets (e.g., nanosheets N1, N2, N3, and N4), and a plurality of source / drain regions 130 may constitute unit transistors (CTRs). Each of the plurality of unit transistors (CTRs) may constitute various types of logic cells included in logic circuits. In one embodiment, the integrated circuit device 100 may include logic cells including multi-bridge channel field-effect transistor (MBCFET) devices. However, this disclosure is not limited thereto, and the integrated circuit device 100 may include planar field-effect transistor (FET) devices, gate-all-around-type FET devices, fin FET devices, FET devices based on two-dimensional materials (such as molybdenum disulfide (MoS2) semiconductor gate electrodes), etc.

[0039] The integrated circuit device 100 may include an active region extending in a first horizontal direction (X direction). The active region may be a p-type metal-oxide-semiconductor (PMOS) transistor region and / or an n-type metal-oxide-semiconductor (NMOS) transistor region. For example, a plurality of unit transistors CTR disposed in the active region may include PMOS transistors or NMOS transistors.

[0040] Multiple unit transistors (CTRs) may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The multiple unit transistors (CTRs) may include multiple nanosheet stacks (NSS), multiple gate structures 120, and multiple source / drain regions 130, wherein the nanosheets of each nanosheet stack (NSS) are spaced apart from each other in a vertical direction (Z direction), the multiple gate structures 120 extend in the second horizontal direction (Y direction) and at least partially surround the multiple nanosheet stacks (NSS), and the multiple source / drain regions 130 are disposed sequentially on both sides of the multiple gate structures 120 (e.g., on both sides of each gate structure 120).

[0041] In the specification, the direction parallel to the main surface of the unit transistor CTR is defined as the horizontal direction (X direction and / or Y direction), and the direction perpendicular to the horizontal direction (X direction and / or Y direction) is defined as the vertical direction (Z direction).

[0042] For ease of description, the source / drain region 130 that is superimposed on the back contact BCA in the vertical direction (Z direction) can be referred to as the first source / drain region 130-1, and the source / drain region 130 that is not superimposed on the back contact BCA in the vertical direction (Z direction) can be referred to as the second source / drain region 130-2.

[0043] In one embodiment, each of the plurality of nanosheet stacks NSS may include a group IV semiconductor (such as silicon (Si) or germanium (Ge)), a group IV-IV compound semiconductor (such as SiGe or silicon carbide (SiC)), or a group III-V compound semiconductor (such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)).

[0044] In one embodiment, a plurality of gate structures 120 may extend in a second horizontal direction (Y direction) to at least partially surround a plurality of nanosheet stacks NSS, and may be spaced apart from each other in a first horizontal direction (X direction).

[0045] In one embodiment, each of the plurality of gate structures 120 may include a gate electrode 122, a gate insulating layer 124, and a gate capping layer 126. For example, the gate electrode 122 may extend in a second horizontal direction (Y direction) to surround a plurality of nanosheet stacks NSS, and the gate insulating layer 124 may be disposed between the gate electrode 122 and each nanosheet stack NSS. The gate capping layer 126 may extend in the second horizontal direction (Y direction) on the upper surface of the gate electrode 122.

[0046] In one embodiment, the gate electrode 122 may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the gate electrode 122 may comprise aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or a combination thereof, but the disclosure is not limited thereto. In one embodiment, the gate electrode 122 may comprise a layer containing a work function metal and an interstitial metal layer. The layer containing the work function metal may include at least one metal selected from Ti, W, ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The interstitial metal layer may include a W layer or an Al layer. In one embodiment, the gate electrode 122 may include a stacked structure of titanium aluminum carbide (TiAlC) / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W, but the disclosure is not limited thereto.

[0047] In one embodiment, the gate insulating layer 124 may include a silicon oxide layer, a silicon oxynitride (SiON) layer, a high-dielectric layer having a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. The high-dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-dielectric layer that may be used as the gate insulating layer 124 may include hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof, but the disclosure is not limited thereto.

[0048] An insulating spacer 118 may be further disposed on the sidewall of the gate electrode 122. The insulating spacer 118 may extend in a second horizontal direction (Y direction) on the sidewall of the gate electrode 122.

[0049] Multiple gate cap layers 126 may be disposed on the insulating spacer 118 and the gate electrode 122. The multiple gate cap layers 126 may cover the upper surface of the insulating spacer 118 and the upper surface of the gate electrode 122. The multiple gate cap layers 126 may include silicon dioxide (SiO2), silicon nitride (Si3N4), SiON, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof.

[0050] Source / drain regions 130 may be formed on the sidewalls of gate structure 120. Source / drain regions 130 may be connected to the ends of nanosheet stacks NSS. Source / drain regions 130 have an upper surface at a vertical level higher than the upper surface of the plurality of nanosheet stacks NSS. At least a portion of the plurality of source / drain regions 130 may be connected to a front contact FCA, and at least a portion of the remaining portions of the plurality of source / drain regions 130 may be electrically connected to a back contact BCA.

[0051] In one embodiment, the source / drain region 130 may include a doped SiGe layer, a doped Ge layer, a doped SiC layer, or a doped indium gallium arsenide (InGaAs) layer, but this disclosure is not limited thereto. In one embodiment, the source / drain region 130 may include a plurality of semiconductor layers with different compositions. For example, the source / drain region 130 may include a lower semiconductor layer, an upper semiconductor layer, and a cap semiconductor layer stacked in sequence. For example, each of the lower semiconductor layer, the upper semiconductor layer, and the cap semiconductor layer may include SiC with different contents of Si and carbon (C).

[0052] Depending on the conductivity type of the multiple nanosheet stacks NSS and / or the conductivity type of the source / drain regions 130, the unit transistor CTR can be an NMOS transistor or a PMOS transistor.

[0053] An insulating liner 142 covering the upper surface of the source / drain region 130 may be disposed between the gate structures 120. The insulating liner 142 may include SiO2 or SiON.

[0054] An inter-gate insulating layer 144 may be disposed on an insulating liner 142. The inter-gate insulating layer 144 may include SiO2 or SiON.

[0055] A front contact FCA can be disposed on the source / drain region 130 through the inter-gate insulating layer 144. A front via contact FVA can be disposed on the front contact FCA. In one embodiment, the front contact FCA is electrically connected to the source / drain region 130 (e.g., a second source / drain region 130-2), and the front contact FCA and the front via contact FVA can be formed in a stacked structure such that the front via contact FVA is disposed on the front contact FCA. In one embodiment, the upper surface of the front contact FCA can be coplanar with the upper surfaces of the plurality of gate cap layers 126 and the lower surface of the front via contact FVA.

[0056] The upper insulating structure 180 may be disposed on the inter-gate insulating layer 144 and the plurality of gate cap layers 126. The upper insulating structure 180 may include an upper etch stop layer 182 and an upper insulating layer 184, the upper insulating layer 184 being disposed on the upper etch stop layer 182. The aforementioned front via contact FVA may be formed by passing through the upper insulating structure 180.

[0057] The gate contact GCA can be disposed on the gate electrode 122 through the inter-gate insulating layer 144 and the upper insulating structure 180. The upper surface of the front contact FCA may be coplanar with the upper surface of the inter-gate insulating layer 144 and the lower surface of the upper insulating structure 180. In one embodiment, the upper surface of the gate contact GCA may be at the same vertical level as the upper surface of the front via contact FVA. The gate contact GCA may be electrically connected to the gate electrode 122 and a plurality of upper wiring layers M1.

[0058] Each of the front contact FCA and the gate contact GCA may include a contact plug comprising Mo, Cu, W, Co, Ru, manganese (Mn), Ti, Ta, Al, combinations thereof, or alloys thereof. In one embodiment, each of the front contact FCA and the gate contact GCA may further include a conductive barrier pattern surrounding the contact plug. The conductive barrier pattern may comprise a metal or a metal nitride. For example, the conductive barrier pattern may comprise Ti, Ta, W, TiN, TaN, WN, tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), TaSiN, tungsten silicon nitride (WSiN), or combinations thereof, but the disclosure is not limited thereto.

[0059] An interlayer insulating layer 186 may be disposed on the upper insulating structure 180. The interlayer insulating layer 186 may cover the upper surface of the upper insulating structure 180. A plurality of upper wiring layers M1 passing through the interlayer insulating layer 186 may be disposed inside the interlayer insulating layer 186. The upper wiring layers M1 may be electrically connected to the front contact FCA, the front via contact FVA, and / or the gate contact GCA. For example, the upper wiring layers M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but the disclosure is not limited thereto.

[0060] The upper etch stop layer 182 may include SiC, silicon nitride (SiN), SiCN, silicon oxycarbide (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxycarbide (AlOC), or combinations thereof. The upper insulating layer 184 and the interlayer insulating layer 186 may include an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or combinations thereof. For example, the upper insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) oxide layer, a borosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a hydrogenated silicon carbon oxide (SiCOH) layer, or combinations thereof, but the disclosure is not limited thereto.

[0061] A first back-end process (BEOL) structure BS1 may be disposed on the interlayer insulating layer 186. The first BEOL structure BS1 may be referred to as the front circuit structure FS. The front circuit structure FS may be electrically connected to the unit transistor CTR. The front circuit structure FS may include a front via FSV, a front circuit layer FSW, and a front insulating layer FSI. In one embodiment, the front circuit layer FSW may include a circuit pattern disposed in one vertical horizontal position or a circuit pattern disposed in two or more vertical horizontal positions.

[0062] In one embodiment, the front insulating layer FSI may comprise an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or a combination thereof. The front wiring layer FSW may be electrically connected to the front contact FCA and the gate contact GCA. The front via FSV may be electrically connected to the front wiring layer FSW, and the sidewalls of the front wiring layer FSW and the front via FSV may be surrounded by the front insulating layer FSI.

[0063] The intermediate insulating layer 160 may extend to the lower surface (or bottom surface) of the unit transistor CTR (e.g., the bottom surface of the gate structure 120, and / or the bottom surface of the source / drain region 130). The intermediate insulating layer 160 may include SiO2, Si3N4, SiON, SiCN, SiOCN, or combinations thereof.

[0064] The back contact BCA can be electrically connected to the source / drain region 130 by passing through the intermediate insulating layer 160. The back contact BCA can extend to a vertical level higher than the vertical level of the bottom surface of the source / drain region 130 in order to increase the contact area between the back contact BCA and the source / drain region 130.

[0065] In one embodiment, the back contact BCA may comprise only a metal plug containing a single metal. In another embodiment, the back contact BCA may comprise a metal plug and a conductive barrier layer surrounding the metal plug. The metal plug may comprise Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, combinations thereof, or alloys thereof, but the disclosure is not limited thereto. The conductive barrier layer may comprise a metal or a conductive metal nitride. For example, the conductive barrier layer may comprise Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but the disclosure is not limited thereto.

[0066] In one embodiment, the back metal silicide layer 174 may be located between the source / drain region 130 and the back contact BCA. The back metal silicide layer 174 may include a metal comprising Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the back metal silicide layer 174 may include titanium silicide (TiSi), but the disclosure is not limited thereto.

[0067] A power via MPV may be disposed on the lower surface of the back contact BCA. One surface of the power via MPV may have a recess RS. In one embodiment, the lower surface of the power via MPV may have a recess RS. That is, the one of the two spaced-apart surfaces of the power via MPV that is farther from the first BEOL structure BS1 in the vertical direction (Z direction) may have a recess RS. The recess RS may be defined as a groove and / or indentation portion formed in one surface of the power via MPV. Thus, one surface of the power via MPV may have a recessed shape. In one embodiment, the lower surface of the power via MPV may have a recessed shape. In a plan view, the recess RS may be adjacent to the center of the power via MPV.

[0068] For ease of description, a power via MPV that does not overlap with the back contact member BCA in the vertical direction (Z direction) may be referred to as a first power via MPV1, and a power via MPV that overlaps with the back contact member BCA in the vertical direction (Z direction) may be referred to as a second power via MPV2. The first power via MPV1 may also include a recess RS. In one example, the lower surfaces of multiple power via MPVs including the first power via MPV1 and the second power via MPV2 may be at the same vertical level.

[0069] A power via MPV may extend horizontally (in the X and / or Y directions) on the back contact BCA. In a plan view, the power via MPV may have multiple line shapes spaced apart from each other. In one embodiment, a second power via MPV2 may be integrally formed with the back contact BCA. In another embodiment, the second power via MPV2 may be separately formed from the back contact BCA.

[0070] In one embodiment, the first power via MPV1, which is not superimposed on the back contact BCA in the vertical direction (Z direction), may include a recess RS. Furthermore, the first power via MPV1, which is not superimposed on the back via contact BVA in the vertical direction (Z direction), may include a recess RS. In a vertical cross-section, the recess RS may have a tapered shape with a horizontal width that gradually decreases toward the unit transistor CTR.

[0071] The first horizontal width HW1, which is the horizontal width of the recess RS, can be from about 5 nm to about 20 nm. Furthermore, the vertical depth D of the recess RS can be from about 5 nm to about 20 nm. When the power via MPV has the recess RS, the contact area between the power via MPV and the back via contact BVA can be increased. Therefore, the resistance between the power via MPV and the back via contact BVA can be reduced, thereby improving the electrical characteristics of the integrated circuit device 100.

[0072] A lower insulating structure 190 may be disposed on the lower surface of the intermediate insulating layer 160 and the lower surface of the power via MPV, covering the lower surface of each of the intermediate insulating layer 160 and the power via MPV. The lower insulating structure 190 may include a lower etch stop layer 192 and a lower insulating layer 194.

[0073] The lower etch stop layer 192 may comprise SiC, SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The lower insulating layer 194 may comprise an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or combinations thereof. For example, the lower insulating layer 194 may comprise a TEOS layer, an HDP oxide layer, a BPSG layer, an FCVD oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or combinations thereof, but the disclosure is not limited thereto.

[0074] The back-through-hole contact BVA can be electrically connected to the power via MPV by passing through the lower insulating structure 190. The upper surface of the back-through-hole contact BVA may have a vertical level that is higher than the vertical level of the upper surface of the recess RS of the first power via MPV1. Furthermore, at the same vertical level, the second horizontal width HW2, which is the horizontal width of the back-through-hole contact BVA, may be greater than the first horizontal width HW1, which is the horizontal width of the recess RS of the first power via MPV1.

[0075] In one embodiment, the power via MPV and the back via contact BVA may comprise different materials. In another embodiment, the power via MPV and the back via contact BVA may comprise the same material.

[0076] The back power rail MPR can be mounted on the lower surface of the back through hole contact BVA. The back power rail MPR can be electrically connected to the back through hole contact BVA.

[0077] The back-line structure BS may be disposed on the bottom surface of the unit transistor CTR (e.g., the bottom surface of the power via MPV or the bottom surface of the back power rail MPR). The back-line structure BS may include a power delivery network configured to apply power supply voltage and ground voltage to the unit transistor CTR. The back-line structure BS may include a back via BSV, a back line layer BSW, and a back insulating layer BSI.

[0078] In one embodiment, the back contact BCA, back via BSV, and / or back wiring layer BSW may include at least one of W, Co, Mo, Ni, Ru, Cu, Al, their silicides, and their alloys.

[0079] In one embodiment, a conductive barrier layer may also be formed around the upper surface and sidewalls of each of the back contact BCA, power via MPV, back via contact BVA, back power rail MPR, and / or back line layer BSW, and the conductive barrier layer may include at least one of Ru, Ti, TiN, Ta, TaN, W, TiSiN, TiSi, and tungsten silicide (WSi).

[0080] As the integrated circuit device 100 is miniaturized, a device structure has been proposed in which a front-line structure for signal transmission is disposed on the upper surface of the unit transistor CTR, and a back-line structure for applying power supply voltage and ground voltage is disposed on the bottom surface of the unit transistor CTR. When forming the second BEOL structure BS2, a recess RS can be formed in the power via MPV to increase the contact area between the power via MPV and the back via contact BVA. Therefore, the electrical characteristics between the power via MPV and the back via contact BVA can be improved. Thus, the electrical characteristics of the integrated circuit device 100 can be improved.

[0081] Figure 4 This is a cross-sectional view showing an integrated circuit device 100a according to an embodiment. Figure 4 yes Figure 1 The sectional view corresponding to line X-X'. Refer to the following: Figures 1 to 3 right Figure 4 Describe it.

[0082] Except for the integrated circuit device 100a, which includes the placeholder 170, Figure 4 The integrated circuit device 100a can be used with Figures 1 to 3 The integrated circuit device 100 is basically the same. Therefore, the placeholder 170 will be mainly described here.

[0083] Reference Figure 4 The placeholder 170 may be disposed on the bottom surface of at least one of the plurality of source / drain regions 130 (e.g., the second source / drain region 130-2). For example, the placeholder 170 may comprise SiGe and / or Si3N4.

[0084] The placeholder 170 may not overlap with the back contact BCA in the vertical direction (Z direction). In a plan view, the placeholder 170 may be spaced apart from the back contact BCA in the horizontal direction (X direction and / or Y direction). The placeholder 170 may extend downward from the bottom surface of the source / drain region 130 in the vertical direction (Z direction). The placeholder 170 may overlap with the first power via MPV1 in the vertical direction (Z direction).

[0085] The second intermediate insulating layer 162 may be disposed vertically (Z-direction) on the bottom surface of the first source / drain region 130-1 that overlaps with the back contact BCA, and the first intermediate insulating layer 161 may be disposed vertically (Z-direction) on the bottom surface of the second source / drain region 130-2 that does not overlap with the back contact BCA. The back contact BCA may be electrically connected to the source / drain region 130 by passing through the second intermediate insulating layer 162.

[0086] In other words, the occupant 170 and the first power via MPV1, which is not superimposed on the back contact member BCA in the vertical direction (Z direction), can be surrounded by the first intermediate insulating layer 161, and the back contact member BCA and the second power via MPV2 can be surrounded by the second intermediate insulating layer 162.

[0087] The first intermediate insulating layer 161 and the second intermediate insulating layer 162 may include SiO2, Si3N4, SiON, SiCN, SiOCN or combinations thereof.

[0088] Figures 5 to 19 The manufacturing process is shown in sequence. Figures 1 to 3 A cross-sectional view of the method of the integrated circuit device 100 shown in the figure, wherein, Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16, Figure 17 , Figure 18 and Figure 19 It is shown in the process sequence and along Figure 1 A sectional view of the part of the structure corresponding to the section cut by line X1-X1'. Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B It is shown in the process sequence and along Figure 1 A sectional view of the structure corresponding to the section cut by line Y1-Y1'. Figures 5 to 19 middle, Figures 1 to 3 The same reference numerals in the text refer to the same components, and therefore, their detailed descriptions are omitted here.

[0089] Reference Figure 5 A stacked structure can be formed by alternately and sequentially stacking a plurality of sacrificial semiconductor layers 104 and a plurality of semiconductor layers NS on the upper surface of substrate 110. In one embodiment, the plurality of sacrificial semiconductor layers 104 and the plurality of semiconductor layers NS can be formed by an epitaxial process. In the stacked structure, the plurality of sacrificial semiconductor layers 104 and the plurality of semiconductor layers NS may comprise semiconductor materials with different etch selectivity.

[0090] In one embodiment, the epitaxial process may include vapor phase epitaxy (VPE), chemical vapor deposition (CVD) processes (such as ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, or combinations thereof. In the epitaxial process, a liquid or vapor precursor may be used as the precursor required to form multiple sacrificial semiconductor layers 104 and multiple semiconductor layers NS.

[0091] For example, each of the plurality of sacrificial semiconductor layers 104 and the plurality of semiconductor layers NS may comprise a single crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. In one embodiment, the plurality of sacrificial semiconductor layers 104 may comprise SiGe, and the plurality of semiconductor layers NS may comprise Si. The SiGe layer constituting the sacrificial semiconductor layer 104 may have a specific Ge content ratio selected in the range of about 5 atomic percentages (atom%) to about 50 atom% (e.g., about 10 atom% to about 40 atom%). In one embodiment, each of the plurality of sacrificial semiconductor layers 104 may comprise a SiGe layer, and the Ge content ratio in each of the plurality of sacrificial semiconductor layers 104 may be the same.

[0092] Reference Figure 6A and Figure 6B ,exist Figure 5As a result, a portion of each of the plurality of sacrificial semiconductor layers 104, the plurality of semiconductor layers NS, and the substrate 110 can be etched to form a plurality of fin-type active regions F1 including a retained portion of the substrate 110. A plurality of device isolation trenches 112T can be defined in the substrate 110 by the plurality of fin-type active regions F1. A portion of the plurality of sacrificial semiconductor layers 104 and a portion of the plurality of semiconductor layers NS can be retained on the fin-like upper surface FF of each of the plurality of fin-type active regions F1 (see...). Figure 7A and Figure 7B )superior.

[0093] Subsequently, a device isolation layer 112 may be formed to fill multiple device isolation trenches 112T. The device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof. A portion of the multiple sacrificial semiconductor layers 104 and portions of the multiple semiconductor layers NS retained on the fin-like upper surface FF of each of the multiple fin-type active regions F1 may protrude upward from the upper surface of the device isolation layer 112.

[0094] Reference Figure 7A and Figure 7B , can Figure 6A and Figure 6B As a result, a plurality of dummy gate structures DGS are formed. Each of the plurality of dummy gate structures DGS may be formed to extend in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS may include a dummy oxide layer D122, a dummy gate layer D124, and a dummy capping layer D126 sequentially stacked on a stacked structure comprising a plurality of sacrificial semiconductor layers 104 and a plurality of semiconductor layers NS. In one embodiment, the dummy gate layer D124 may comprise polysilicon, and the dummy capping layer D126 may comprise a SiN layer.

[0095] Subsequently, a plurality of insulating spacers 118 may be formed, each insulating spacer 118 covering two sidewalls of each of the plurality of dummy gate structures (DGS). The plurality of insulating spacers 118 may include Si3N4, SiO2, SiOC, SiOCN, SiCN, silicon boron nitride (SiBN), SiON, silicon boron carbon nitride (SiBCN), silicon fluoride oxyfluoride (SiOF), carbon-doped silicon hydrogen oxide (SiOCH), or combinations thereof.

[0096] Multiple dummy gate structures (DGS) and multiple insulating spacers (118) can be used as etching masks to etch portions of multiple sacrificial semiconductor layers (104) and multiple semiconductor layers (NS), as well as portions of multiple finned active regions (F1), thereby dividing the multiple semiconductor layers (NS) into multiple nanosheet stacks (NSS), each comprising first to fourth nanosheets (N1, N2, N3, and N4), and forming multiple grooves (GR) on the multiple finned active regions (F1). Each of the first to fourth nanosheets (N1, N2, N3, and N4) may have a width defined by the multiple grooves (GR) in a first horizontal direction (X direction). To form the multiple grooves (GR), dry etching, wet etching, or a combination thereof can be used.

[0097] Reference Figure 8A and Figure 8B The source / drain regions 130 can be formed by epitaxially growing semiconductor material from corresponding surfaces exposed in the trench GR of “fin active region F1, first nanosheets to fourth nanosheets N1, N2, N3 and N4, and multiple sacrificial semiconductor layers 104”. Each of the multiple source / drain regions 130 may include an epitaxially grown semiconductor layer. In one embodiment, each of the multiple source / drain regions 130 may include a Si layer, a SiC layer, or a SiGe layer. In one embodiment, when the source / drain regions 130 constitute an NMOS transistor, the source / drain regions 130 may include a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). In one embodiment, when the source / drain regions 130 constitute a PMOS transistor, the source / drain regions 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and gallium (Ga).

[0098] Subsequently, an insulating liner 142 may be formed covering the result of forming a plurality of source / drain regions 130 therein, and an inter-gate insulating layer 144 may be formed on the insulating liner 142. The insulating liner 142 may include Si3N4, SiCN, SiBN, SiON, SiOCN, SiBCN, or combinations thereof, and the inter-gate insulating layer 144 may include a SiO2 layer, but the insulating liner 142 and the inter-gate insulating layer 144 are not limited thereto.

[0099] Subsequently, a portion of each of the insulating liner 142 and the inter-gate insulating layer 144 may be etched until the plurality of dummy capping layers D126 are exposed (see [link]). Figure 7A and Figure 7B The upper surface of the gate layer D124. Thereafter, multiple dummy capping layers D126 can be removed until the dummy gate layer D124 is exposed, and the insulating liner 142 and the inter-gate insulating layer 144 can be partially removed such that the upper surface of the inter-gate insulating layer 144 and the upper surface of the dummy gate layer D124 are at approximately the same vertical level.

[0100] Reference Figure 9A and Figure 9B From Figure 8A and Figure 8B The result is the removal of the dummy gate layer D124 and the dummy oxide layer D122 to prepare the gate space GS. Subsequently, the gate space GS can be used to selectively remove multiple sacrificial semiconductor layers 104 retained on the fin active region F1, such that the gate space GS extends into the space between the first to fourth nanosheets N1, N2, N3, and N4, and the space between the fin-like upper surface FF of the fin active region F1 and the first nanosheet N1.

[0101] Reference Figure 10A and Figure 10B ,exist Figure 9A and Figure 9B As a result, a gate insulating layer 124 can be formed covering the exposed surfaces of the first to fourth nanosheets N1, N2, N3, and N4, and the fin-type active region F1. The gate insulating layer 124 may include a stacked structure of an interface dielectric layer and a high-dielectric layer. The interface dielectric layer may include a low-dielectric material layer (e.g., a SiO2 layer, a SiON layer, or a combination thereof) having a dielectric constant of about 9 or less. In one embodiment, the interface dielectric layer may be omitted. The high-dielectric layer may include a material with a dielectric constant higher than that of the SiO2 layer. For example, the high-dielectric layer may have a dielectric constant of about 10 to about 25. The high-dielectric layer may include HfO2, but the disclosure is not limited thereto.

[0102] A gate-filled space GS can be formed on the gate insulating layer 124 (see...) Figure 9A and Figure 9B The plurality of gate electrodes 122 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the materials constituting the plurality of gate electrodes 122 are not limited thereto.

[0103] A portion of each of the gate electrode 122, gate insulating layer 124, and insulating spacer 118 may be removed from the upper surface of each of these elements to reduce their height, and a plurality of gate capping layers 126 may be formed, each covering the upper surface of each of these elements. Each of the plurality of gate capping layers 126 may include a Si3N4 layer.

[0104] Reference Figure 11 ,exist Figure 10A and Figure 10B As a result, a contact hole can be formed exposing a source / drain region 130 between two adjacent gate electrodes 122 among a plurality of gate electrodes 122. A front metal silicide layer 172 can be formed on the surface of the source / drain region 130 through the contact hole, and a front contact element FCA filling the contact hole can be formed on the front metal silicide layer 172. The front metal silicide layer 172 may include a metal comprising Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the front metal silicide layer 172 may include TiSi, but the disclosure is not limited thereto. In one embodiment, the front contact element FCA may consist only of a metal plug comprising a single metal. In another embodiment, the front contact element FCA may include a metal plug and a conductive barrier layer surrounding the metal plug. The metal plug may include Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, combinations thereof, or alloys thereof, but the disclosure is not limited thereto. The conductive barrier layer may include a metal or a conductive metal nitride. For example, the conductive barrier layer may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but the disclosure is not limited thereto.

[0105] Subsequently, an upper insulating structure 180 can be formed by sequentially forming an upper etch stop layer 182 and an upper insulating layer 184 covering the upper surfaces of each of the front contact FCA, the plurality of gate cap layers 126, and the inter-gate insulating layer 144. Thereafter, a front via contact FVA connected to the front contact FCA in the vertical direction (Z direction) via the upper insulating structure 180 and a gate contact GCA electrically connected to the gate electrode 122 through the upper insulating structure 180 and the gate cap layer 126 can be formed.

[0106] The upper etch stop layer 182 may comprise SiC, SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The upper insulating layer 184 may comprise an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or combinations thereof. For example, the upper insulating layer 184 may comprise a TEOS layer, an HDP oxide layer, a BPSG layer, an FCVD oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or combinations thereof, but the disclosure is not limited thereto.

[0107] Each of the front via contact (FVA) and the gate contact (GCA) may include a contact plug comprising Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof. In one embodiment, each of the front via contact (FVA) and the gate contact (GCA) may further include a conductive barrier pattern surrounding the contact plug. The conductive barrier pattern may include a metal or a metal nitride. For example, the conductive barrier pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, but the disclosure is not limited thereto.

[0108] Subsequently, an interlayer insulating layer 186 covering the upper insulating structure 180 and a plurality of upper wiring layers M1 passing through the interlayer insulating layer 186 can be formed. The constituent material of the interlayer insulating layer 186 may be generally the same as the constituent material of the upper insulating layer 184 described above. The upper wiring layers M1 may be connected to the front via contact FVA or the gate contact GCA. The upper wiring layers M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, combinations thereof, or alloys thereof, but the disclosure is not limited thereto.

[0109] Reference Figure 12 A first BEOL structure BS1 can be formed on multiple upper circuit layers M1 and interlayer insulation layers 186. The first BEOL structure BS1 may include a front via FSV, a front circuit layer FSW, and a front insulation layer FSI. The front via FSV and the front insulation layer FSI can constitute the front circuit structure FS.

[0110] For example, the front insulating layer FSI may include an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or a combination thereof. The front wiring layer FSW may be electrically connected to the front contact FCA and the front via contact FVA. The front via FSV may be electrically connected to the front wiring layer FSW, and the sidewalls of the front wiring layer FSW and the front via FSV may be surrounded by the front insulating layer FSI.

[0111] Reference Figure 13 A portion of the substrate 110 can be removed to reduce the size of the substrate 110 in the vertical direction (Z direction) (see...). Figure 12 The height of the device isolation layer 112 may be exposed in one embodiment. Figure 10B The bottom surface of ).

[0112] In one embodiment, the carrier substrate can be attached to the front circuit structure FS, the substrate 110 can be inverted so that the bottom surface of the substrate 110 faces upward, and a polishing process can be performed on the substrate 110. Figures 13 to 19 In this context, for ease of drawing, the carrier substrate is omitted, and Figures 13 to 19 The results are shown without being upside down.

[0113] Subsequently, substrate 110 can be removed. In one embodiment, the process for removing substrate 110 may include a wet etching process and / or a recessing process. In the wet etching process and / or the recessing process, device isolation layer 112 may be retained without being removed.

[0114] Reference Figure 14 An intermediate insulating layer 160 may be formed at the location where the substrate 110 has been removed. The intermediate insulating layer 160 may include SiO2, Si3N4, SiON, low-dielectric materials, etc. For example, the intermediate insulating layer 160 may include a low-dielectric insulating layer containing at least one of carbon-containing SiO2, carbon-containing SiON, carbon-containing Si3N4, and / or carbon-containing SiBCN.

[0115] Reference Figure 15 A mask pattern can be formed on the lower surface of the intermediate insulating layer 160 and used as an etching mask to partially remove the intermediate insulating layer 160 and the device isolation layer 112 (see [reference]). Figure 10B This forms the back hole (BH). For example, the mask pattern may include a spin-coated hard mask, a dielectric hard mask, and / or a dielectric metal hard mask.

[0116] The back via BH may be formed to overlap with at least a portion of the source / drain region 130 in the vertical direction (Z direction). The back via BH may expose at least a portion of the source / drain region 130. The back via BH may be a region in which a back contact BCA and a power via MPV will be formed in the future. The back via BH may include a back contact hole BCAH in which a back contact BCA will be formed in the future and a power via MPVH in which a power via MPV will be formed in the future. The power via MPVH may include a first power via MPVH1 in which a first power via MPV1 will be formed in the future and a second power via MPVH2 in which a second power via MPV2 will be formed in the future.

[0117] In one embodiment, the back via (BH) can be formed by multiple etching processes. The first etching process may be a process of etching the area in which the power via (MPV) will be formed in the future, and the second etching process may be a process of etching the area in which the back contact (BCA) will be formed in the future.

[0118] Reference Figure 16A back metallization layer 174 can be formed on the surface of the source / drain region 130 through the back contact hole BCAH. The material of the back metallization layer 174 is the same as that of the front metallization layer 172 described above. Subsequently, a back contact BCA and a pre-connected power via pMPV can be formed by filling the interior of the back hole BH and the lower surface of the intermediate insulating layer 160 with conductive material. The back contact BCA can be connected to the source / drain region 130 through the back metallization layer 174. In this specification, the back contact BCA may be referred to as a contact structure. The material of each of the back contact BCA and the pre-connected power via pMPV is the same as that of the front contact FCA described above.

[0119] Although reference Figure 16 The description describes the back contact BCA and power via MPV being formed in the same process, but this disclosure is not limited thereto. For example, the back contact BCA and power via MPV may be formed in different processes.

[0120] Reference Figure 17 The pre-existing power supply via pMPV can be removed (see [link]). Figure 16 At least a portion of the present power via (pMPV) is used to form a power via (pMPV). The present power via (pMPV) can be removed by a chemical mechanical polishing (CMP) process. In another embodiment, the present power via (pMPV) can be removed by a dry etching process, a wet etching process, and / or a laser ablation process.

[0121] In the process of removing at least a portion of the pre-existing power via pMPV, a recess RS can be formed in the power via MPV. As described above, the first horizontal width HW1, which is the horizontal width of the recess RS, can be from about 5 nm to about 20 nm, and the vertical depth D of the recess RS can be from about 5 nm to about 20 nm.

[0122] Reference Figure 18 The lower insulating structure 190 can be formed by sequentially forming a lower etch stop layer 192 and a lower insulating layer 194 covering the lower surfaces of each of the power via MPV and the intermediate insulating layer 160. Subsequently, a back via contact BVA can be formed that connects to the power via MPV in the vertical direction (Z direction) via the lower insulating structure 190 (e.g., a portion of the lower insulating structure 190). The corresponding constituent materials of the lower etch stop layer 192 and the lower insulating layer 194 can be the same as the corresponding constituent materials of the upper etch stop layer 182 and the upper insulating layer 184 described above. At least a portion of the back via contact BVA can be formed inside the power via MPV. In one embodiment, at least a portion of the back via contact BVA can be formed inside the power via MPV via a recess RS of the power via MPV.

[0123] The upper surface of the back via contact BVA may be formed at a vertical level higher than the upper surface of the recess RS of the first power via MPV1. In one embodiment, the power via MPV that overlaps with the back via contact BVA in the vertical direction (Z direction) may not include the recess RS due to the back via contact BVA.

[0124] As described above, in one embodiment, the power via MPV and the back via contact BVA may comprise different materials. In another embodiment, the power via MPV and the back via contact BVA may comprise the same material.

[0125] Subsequently, a back power rail MPR can be formed through the lower insulation layer 194. The back power rail MPR can be electrically connected to the back via contact BVA. The material of the back via contact BVA can be generally the same as the material of the aforementioned plurality of upper circuit layers M1.

[0126] Reference Figure 19 A second BEOL structure BS2 can be formed on the back power rail MPR. The second BEOL structure BS2 may include a back via BSV, a back wiring layer BSW, and a back insulation layer BSI. The back via BSV and the back insulation layer BSI can constitute the back wiring structure BS.

[0127] For example, the back insulating layer BSI may include an oxide layer, a nitride layer, a low dielectric layer having a dielectric constant of about 2.2 to about 2.4, or a combination thereof. The back wiring layer BSW may be electrically connected to the back contact BCA and the back via contact BVA. The back via BSV may be electrically connected to the back wiring layer BSW, and the sidewalls of the back wiring layer BSW and the back via BSV may be surrounded by the back insulating layer BSI.

[0128] According to already referenced Figures 5 to 19 The method for manufacturing the integrated circuit device 100 described above is referred to in the above text. Figures 1 to 3 As described, when a power via MPV is formed by removing at least a portion of the pre-existing power via pMPV, a recess RS can be formed. Therefore, the contact area between the power via MPV and the back via contact BVA can be increased, thereby reducing resistance. In other words, the electrical characteristics of the integrated circuit device 100 can be improved.

[0129] Figures 20 to 24 The manufacturing process is shown in sequence. Figure 4 A cross-sectional view of the method of the integrated circuit device 100a shown in the figure, wherein, Figures 20 to 24 It is shown in the process sequence and along Figure 1 A sectional view of the structure corresponding to the section cut by line X1-X1'. Figures 20 to 24 In, with Figure 4Reference numerals that are the same in the reference numerals indicate the same components, therefore, their detailed descriptions are omitted here.

[0130] Reference Figure 20 ,exist Figure 7A and Figure 7B As a result, a placeholder 170 can be formed in each of the recesses GR formed on both sides of the dummy gate structure DGS on the substrate 110, and a source / drain region 130 can be formed on the placeholder 170. Thereafter, the dummy gate structure DGS can be removed, and a gate structure 120 can be formed at the location where the dummy gate structure DGS has been removed.

[0131] Subsequently, an upper insulating structure 180, a front contact FCA, a front via contact FVA, a gate contact GCA, an interlayer insulating layer 186, an upper circuit layer M1, and a front circuit structure FS can be formed on the gate structure 120.

[0132] Reference Figure 21 The substrate 110 can be removed from the back surface of the substrate 110 (see...). Figure 20 In this case, device isolation layer 112 (see...) Figure 7B The substrate 110 and the placeholder 170 can be retained without being removed. The process for removing the substrate 110 can be the same as described above. Figure 13 The same as described above.

[0133] Reference Figure 22 This can form a covering and protective device isolation layer 112 (see...) Figure 7B The first intermediate insulating layer 161 includes the occupant 170 and the first intermediate insulating layer 161. The first intermediate insulating layer 161 may include SiO2, Si3N4, SiON, low dielectric materials, etc. For example, the first intermediate insulating layer 161 may include a low dielectric insulating layer, which includes at least one of carbon-containing SiO2, carbon-containing SiON, carbon-containing Si3N4 and / or SiBCN.

[0134] Reference Figure 23 A portion of the first intermediate insulating layer 161 can be removed, as well as the placeholder 170 at the location where the back contact BCA will be formed. A second intermediate insulating layer 162 can then be formed in the area where the first intermediate insulating layer 161 and the placeholder 170 have been removed. The second intermediate insulating layer 162 can cover the bottom surface of the source / drain region 130. The material of the second intermediate insulating layer 162 can be generally the same as the material of the first intermediate insulating layer 161.

[0135] Reference Figure 24 The back hole BH can be formed by removing at least a portion of each of the first intermediate insulating layer 161 and the second intermediate insulating layer 162. The method for forming the back hole BH is similar to that described above. Figure 15The description is the same. A power via MPVH can be formed on the first intermediate insulating layer 161, and a back contact hole BCAH and a power via MPVH can be formed on the second intermediate insulating layer 162.

[0136] As described above, the power via MPVH may include a first power via MPVH1 that will form a first power via MPV1 in the future and a second power via MPVH2 that will form a second power via MPV2 in the future. The first power via MPVH1 may be formed on the first intermediate insulating layer 161, and the second power via MPVH2 may be formed on the second intermediate insulating layer 162.

[0137] Subsequently, as referred to Figures 16 to 19 The described structure allows for the filling of the back hole BH with a conductive material, and the formation of a lower insulating structure 190, a back hole contact BVA, a back power rail MPR, and a second BEOL structure BS2, to form... Figure 4 Integrated circuit device 100a.

[0138] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A unit transistor includes a nanosheet stack, a gate electrode, and a first source / drain region. The nanosheet stack includes a plurality of nanosheets spaced apart from each other in a vertical direction. The gate electrode is on the nanosheet stack and extends in a horizontal direction. The first source / drain region is connected to the nanosheet stack. A back contact is located below the unit transistor and connected to the first source / drain region; The first power via is located at a vertical level lower than that of the back contact. The front-end circuit structure is on and connected to the unit transistor; as well as The back-side wiring structure is located below the first power via and connected to the unit transistor. The back wiring structure is connected to the first power via and the back contact, and The lower surface of the first power via does not overlap with the back contact member in the vertical direction and includes a recess.

2. The integrated circuit device as claimed in claim 1, wherein, The lower surface of the first power via has a recessed shape.

3. The integrated circuit device of claim 1, further comprising: Multiple power vias, including a first power via, are connected to the back contact. The plurality of power vias are located at the same vertical and horizontal position, and In the plan view, the plurality of power vias have the shape of lines spaced apart from each other.

4. The integrated circuit device as claimed in claim 1, wherein, The vertical depth of the concave portion is 5nm to 20nm.

5. The integrated circuit device as claimed in claim 1, wherein, The horizontal width of the recess is 5nm to 20nm.

6. The integrated circuit device according to any one of claims 1 to 5, further comprising: Second source / drain region; as well as The placeholder is located on the bottom surface of the second source / drain region.

7. The integrated circuit device of claim 6, wherein, The spacer is stacked vertically with the first power via.

8. An integrated circuit device, comprising: Multiple unit transistors include multiple nanosheet stacks, multiple gate electrodes, and multiple source / drain regions. Each of the multiple nanosheet stacks includes multiple nanosheets spaced apart from each other in a vertical direction. The multiple gate electrodes are respectively on the multiple nanosheet stacks and extend in a horizontal direction. The multiple source / drain regions are respectively between the gate electrodes among the multiple gate electrodes and connected to one or more of the multiple nanosheet stacks. Multiple back contacts are located below the multiple unit transistors and connected to the multiple source / drain regions; Multiple power vias are located at a vertical level lower than the vertical level of the multiple back contacts and are connected to the multiple back contacts; Multiple back-hole contacts are located at a vertical level lower than the vertical level of the multiple power vias and are connected to the multiple power vias. A front-end circuit structure is present on and connected to the plurality of unit transistors; as well as A back-side wiring structure is located on the lower surface of the plurality of power vias and connected to the plurality of unit transistors. The back wiring structure is connected to the plurality of back contacts, the plurality of power vias, and the plurality of back via contacts, and The lower surface of the first power via, which is not overlapped with the plurality of back contacts in the vertical direction, includes a recess.

9. The integrated circuit device of claim 8, wherein, The upper surface of the plurality of back-through hole contacts is at a vertical level that is higher than the vertical level of the recess.

10. The integrated circuit device of claim 8, further comprising: An insulating structure is provided on the lower surface of the plurality of power vias and includes an etch stop layer and an insulating layer. The plurality of back-through hole contacts pass through at least a portion of the insulating structure in the vertical direction.

11. The integrated circuit device of claim 8, further comprising: An intermediate insulating layer is located on the lower surface of the plurality of unit transistors. The plurality of back contacts and the plurality of power vias pass through at least a portion of the intermediate insulating layer in the vertical direction.

12. The integrated circuit device of claim 8, wherein, The plurality of back contacts are connected to the first source / drain region among the plurality of source / drain regions. The first power via does not overlap with the first source / drain region in the vertical direction.

13. The integrated circuit device of claim 8, wherein, The plurality of power vias are made of the same material as the plurality of back via contacts.

14. The integrated circuit device of claim 8, wherein, The plurality of power vias are made of a material different from that of the plurality of back via contacts.

15. The integrated circuit device according to any one of claims 8 to 14, wherein, The plurality of power vias includes a second power via located at the same vertical level as the first power via; The second power via is stacked vertically with the first back contact among the plurality of back contacts, and is integrally formed with the first back contact.

16. The integrated circuit device of claim 8, further comprising: The placeholder is located on the bottom surface of the second source / drain region among the plurality of source / drain regions. The first power via and the occupant are surrounded by a first intermediate insulating layer, and The plurality of back contacts are surrounded by a second intermediate insulating layer.

17. An integrated circuit device, comprising: Multiple unit transistors include multiple nanosheet stacks, multiple gate electrodes, and multiple source / drain regions. Each of the multiple nanosheet stacks includes multiple nanosheets spaced apart from each other in a vertical direction. The multiple gate electrodes are respectively on the multiple nanosheet stacks and extend in a horizontal direction. The multiple source / drain regions are respectively between the gate electrodes among the multiple gate electrodes and connected to one or more of the multiple nanosheet stacks. An intermediate insulating layer is located beneath the plurality of unit transistors; Multiple back contacts are disposed below the multiple unit transistors and are electrically connected to a first source / drain region among the multiple source / drain regions by passing through at least a portion of the intermediate insulating layer; Multiple power vias are connected to the multiple back contacts and pass through at least a portion of the intermediate insulating layer at a vertical level lower than the vertical level of the multiple back contacts. Multiple back-hole contacts are located at a vertical level lower than the vertical level of the multiple power vias and are connected to the multiple power vias. Multiple front contacts are on the multiple unit transistors and connected to a second source / drain region among the multiple source / drain regions; Multiple gate contacts are on the multiple unit transistors and connected to the multiple gate electrodes; A front-line structure is provided on the upper surface of each of the plurality of front contacts and the plurality of gate contacts, and is connected to the plurality of unit transistors; as well as A back-side wiring structure is located on the lower surface of the plurality of power vias and connected to the plurality of unit transistors. The front circuit structure is connected to the plurality of front contacts and the plurality of gate contacts. The back-line structure is connected to the plurality of power vias and the plurality of back-via contacts, and The lower surface of the first power via, which is not overlapped with the plurality of back contacts in the vertical direction, includes a recess.

18. The integrated circuit device of claim 17, wherein, The recess has a tapered shape, which has a horizontal width that decreases toward the plurality of unit transistors in a vertical cross-section.

19. The integrated circuit device of claim 17, wherein, At the same vertical level, the horizontal width of each of the plurality of back through-hole contacts is greater than the horizontal width of the recess of the first power through-hole.

20. The integrated circuit device according to any one of claims 17 to 19, wherein, The vertical depth of the recess is 5 nm to 20 nm, and the horizontal width of the recess is 5 nm to 20 nm.

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