Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method. A protective oxide layer is formed on a semiconductor substrate with a top metal layer. The protective oxide layer on the top metal layer is etched by a photolithography process, and a passivation layer is regrown. Thus, the SM problem caused by the lack of support of the sidewall of the top metal layer is solved, and the risk of damage to the passivation layer caused by poor coating of the photoresist of the top metal layer is solved, thereby improving the yield of chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] Currently, after forming the metal interconnect structure layer, semiconductor devices require a passivation layer to protect the top metal layer of the metal interconnect layer. When the thickness of the top metal layer is relatively thick (Multi Top Thick Metal, MTT), such as using a thick aluminum top layer process, the thickness of the passivation layer (PA) protecting the top metal layer will also increase accordingly. Using existing wafer passivation layer thin film deposition processes, the top metal layer is prone to pattern defects, which can lead to a combination of transistor threshold voltage (VT), drain current (DR), and wafer interface surface electrical properties (SM) failures. Furthermore, when the thickness of the top metal layer exceeds 2.5 μm, the passivation layer above an independent single metal trace will also suffer damage and failure.

[0003] To address structural defects in traditional passivation layer films (PA films), the common approach is to increase the passivation layer thickness and use chemical mechanical polishing (CMP) for global planarization. This can improve surface electrical anomalies (SM) on the MTT and passivation layer damage caused by poor photoresist coating. However, the residual thickness of the PA film varies greatly in different areas after polishing, and over-etching during subsequent passivation layer etching (PA ET) will generate more plasma, resulting in low chip yield. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating semiconductor devices, which solves the problem of passivation layer damage on the top metal layer and improves chip yield.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:

[0006] A semiconductor substrate is provided, wherein an interconnect structure is formed in the semiconductor substrate, and a strip-shaped top metal layer is formed on the top metal dielectric layer of the interconnect structure;

[0007] A protective oxide layer is formed, which covers the top metal layer and the top metal dielectric layer between the top metal layers;

[0008] Etch the protective oxide layer to expose the top metal layer;

[0009] A passivation layer is formed, the passivation layer covering the protective oxide layer and the top metal layer; and,

[0010] The passivation layer is etched to form an opening that exposes a portion of the top metal layer.

[0011] Optionally, the material of the top metal layer includes aluminum.

[0012] Optionally, the thickness of the top metal layer is 4 μm.

[0013] Optionally, the thickness of the protective oxide layer is 20% to 100% of the thickness of the top metal layer.

[0014] Optionally, etching the protective oxide layer to expose the top metal layer includes:

[0015] A patterned photoresist layer is formed on the protective oxide layer, and the patterned photoresist layer forms an opening at least on the top metal layer;

[0016] The protective oxide layer is etched using a patterned photoresist layer as a mask to expose the top metal layer;

[0017] Remove the patterned photoresist layer.

[0018] Optionally, the openings in the patterned photoresist layer expose the protective oxide layer in the sidewall region of the top metal layer.

[0019] Optionally, the passivation layer includes a first passivation layer and a second passivation layer stacked from bottom to top.

[0020] Optionally, the first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.

[0021] Optionally, the protective oxide layer and the passivation layer are formed by plasma-enhanced chemical vapor deposition.

[0022] In summary, this invention provides a method for fabricating a semiconductor device. A protective oxide layer is formed on a semiconductor substrate with a top metal layer. The protective oxide layer on the top metal layer is etched away by photolithography, and a passivation layer is then grown. This method can solve the SM problem caused by the lack of support on the sidewalls of the top metal layer, as well as the risk of passivation layer damage caused by poor photoresist coating of the top metal layer, thereby improving chip yield. Attached Figure Description

[0023] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0024] Figures 2A to 2E This is a schematic diagram of the structure corresponding to each step in the method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0025] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.

[0026] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.

[0027] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.

[0028] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment includes the following steps:

[0029] Step S01: Provide a semiconductor substrate in which an interconnect structure is formed, and form a strip-shaped top metal layer on the top metal dielectric layer of the interconnect structure;

[0030] Step S02: Form a protective oxide layer, which covers the top metal layer and the top metal dielectric layer between the top metal layers;

[0031] Step S03: Etch the protective oxide layer to expose the top metal layer;

[0032] Step S04: Forming a passivation layer, the passivation layer covering the protective oxide layer and the top metal layer; and

[0033] Step S05: Etch the passivation layer to form an opening that exposes a portion of the top metal layer;

[0034] Figures 2A to 2E This is a schematic diagram illustrating the structure corresponding to each step in the fabrication method of a semiconductor device according to an embodiment of the present invention. Please refer to... Figure 1 As shown, and in combination Figures 2A to 2E The present invention provides a detailed description of the method for fabricating the semiconductor device.

[0035] First, refer to Figure 2A As shown, in step S01, a semiconductor substrate 100 is provided, in which an interconnect structure is formed, and a strip-shaped top metal layer is formed on the top metal dielectric layer of the interconnect structure.

[0036] Specifically, a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC), or it can be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the semiconductor substrate 100 is only used as an example of a silicon substrate; this is merely an example, and the present invention is not limited thereto.

[0037] The top metal layer 101 is used to form a metal interconnect structure, enabling electrical connections for subsequent device structures. Specifically, other metal layers for forming the metal interconnect structure exist between the top metal layer 101 and the semiconductor substrate 100. A dielectric layer is formed on the semiconductor substrate 100, and at least one metal layer is embedded within the dielectric layer. For example, the metal layers include a first metal layer (M1), a second metal layer (M2), a third metal layer (M3), and a top metal layer (Mt), embedded from bottom to top. The number of metal layers embedded in the dielectric layer is not limited and can be set according to actual conditions. Several metal layers are electrically connected through plugs. The plug is a conductive layer filling a via in the dielectric layer between two metal layers.

[0038] Furthermore, a gate and a gate oxide layer are formed between the semiconductor substrate 100 and the metal layer. To better illustrate the inventive points of this embodiment, the description of the gate, the gate oxide layer, and other metal layers between the substrate 100 and the top metal layer 101 used to form metal interconnect structures is omitted in this embodiment. Meanwhile, Figures 2A-2E The diagram also omits the gate, gate oxide layer, and other metal layers between the semiconductor substrate 100 and the top metal layer 101 used to form the metal interconnect structure.

[0039] In this embodiment, the top metal layer 101 can be made of aluminum, i.e., the top metal layer 101 is a thick aluminum metal layer. In other embodiments, the top metal layer 101 can be made of one or a combination of at least two of aluminum, copper, titanium, nickel, aluminum nitride, titanium nitride, and nickel nitride. The top metal layer 101 can be formed by sputtering, using a thick aluminum process to form a strip-shaped top metal layer 101 on the top metal dielectric layer of the interconnect structure. The thickness of the top metal layer 101 can be 2.5 μm, 4 μm, or 5 μm, for example, the thickness of the top metal layer is 4 μm. Furthermore, the distribution of the top metal in different regions also varies, affecting the deposition and etching of subsequent passivation layers.

[0040] Next, continue to refer to Figure 2A As shown, step S02 is performed to form a protective oxide layer 102, which covers the top metal layer 101 and the top metal dielectric layer between the top metal layer 101.

[0041] Specifically, the protective oxide layer 102 can be formed by plasma-enhanced chemical vapor deposition. The protective oxide layer 102 can be a silicon oxide layer, or it can be an oxide layer including TEOS (tetraethoxysilane). The thickness of the protective oxide layer 102 is 20% to 100% of the thickness of the top metal layer 101.

[0042] Next, refer to Figure 2B and Figure 2C As shown, step S03 is performed to etch the protective oxide layer 102 and expose the top metal layer 101.

[0043] Specifically, firstly, a patterned photoresist layer 103 is formed on the protective oxide layer 102, and the patterned photoresist layer 103 has openings at least on the top metal layer 101, such as... Figure 2B As shown, then, using the patterned photoresist layer 103 as a mask, the protective oxide layer 102 is etched to expose the top metal layer 101, and the patterned photoresist layer 103 is removed, as follows. Figure 2C As shown.

[0044] Furthermore, the openings of the patterned photoresist layer 103 expose the protective oxide layer 103 in the sidewall region of the top metal layer 101. After etching the protective oxide layer 103, the upper surface of the top metal layer 101 is exposed, and the sidewall of the top metal layer 101 is covered with a protective oxide layer 102.

[0045] In existing processes, to address the passivation layer damage issue on the top metal layer, an oxide layer of a certain thickness is formed on the semiconductor substrate with the top metal layer, and then part of the oxide layer is removed using CMP (Chemical Motion Processing). However, the semiconductor substrate between the strip-shaped top metal layers has a height difference, meaning the resulting oxide layer also has a height difference. The linewidth of different strip-shaped top metal layers leads to significant differences in oxide layer thickness in different areas after CMP. In subsequent passivation layer etching processes, the lack of support on the sidewalls of the top metal layer causes SM (Stone Separation) problems, and uneven photoresist coating on the top metal layer leads to passivation layer damage. In this embodiment, the thickness of the top oxide layer (i.e., the protective oxide layer) is increased, but the protective oxide layer on the top metal layer is removed using photolithography, eliminating the need for CMP and avoiding the thickness differences caused by CMP, thereby preventing damage to the subsequently formed passivation layer.

[0046] Next, refer to Figure 2D As shown, step S04 is performed to form a passivation layer, which covers the protective oxide layer 102 and the top metal layer 101.

[0047] In this embodiment, the passivation layer includes a first passivation layer 104a and a second passivation layer 104b stacked from bottom to top. For example, the first passivation layer 104a is a silicon oxide layer, and the second passivation layer 104b is a silicon nitride layer. The stacked design of the passivation layer provides better thermodynamic and mechanical properties than a single-layer passivation layer. In semiconductor devices, it can absorb and counteract the mechanical and thermal stresses acting on the metal layer, ensuring that various stresses generated during manufacturing do not cause mechanical damage to the metal layer.

[0048] Next, refer to Figure 2E As shown, step S05 is performed to etch the passivation layer, forming an opening 105 that exposes a portion of the top metal layer 101.

[0049] Specifically, first, a patterned photoresist layer (not shown) is formed on the passivation layer. Then, using the patterned photoresist layer as a mask, the passivation layer is etched to form an opening 105 that exposes a portion of the top metal layer 101. Further, after removing the patterned photoresist layer, the top metal layer 101 can be brought out by filling the opening 105 with a conductive material to form a pad (PAD) structure. After forming the pads, the entire device containing the pads is wet-cleaned using an acidic solution. Next, the entire device with formed pads can be diced to divide it into individual semiconductor devices or integrated circuit chips. Finally, wires for connection to other devices or integrated circuits are bonded to the pads of each chip.

[0050] In this embodiment, the mask used to etch the protective oxide layer 102 in this step can be an inverse mask based on the mask used to etch the top metal layer 101, with an additional space added.

[0051] In summary, the present invention provides a method for fabricating a semiconductor device, wherein a protective oxide layer is formed on a semiconductor substrate having a top metal layer, the protective oxide layer on the top metal layer is etched away by photolithography, and a passivation layer is regrown. This method can solve the SM problem caused by the lack of support on the sidewalls of the top metal layer, and also solve the risk of passivation layer damage caused by poor photoresist coating of the top metal layer, thereby improving chip yield.

[0052] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, wherein an interconnect structure is formed in the semiconductor substrate, and a strip-shaped top metal layer is formed on the top metal dielectric layer of the interconnect structure; A protective oxide layer is formed, which covers the top metal layer and the top metal dielectric layer between the top metal layers; Etch the protective oxide layer to expose the top metal layer; A passivation layer is formed, which covers the protective oxide layer and the top metal layer; as well as, The passivation layer is etched to form an opening that exposes a portion of the top metal layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the top metal layer includes aluminum.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The thickness of the top metal layer is 4 μm.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The thickness of the protective oxide layer is 20% to 100% of the thickness of the top metal layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Etching the protective oxide layer to expose the top metal layer includes: A patterned photoresist layer is formed on the protective oxide layer, and the patterned photoresist layer forms an opening at least on the top metal layer; The protective oxide layer is etched using a patterned photoresist layer as a mask to expose the top metal layer; Remove the patterned photoresist layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The openings in the patterned photoresist layer expose the protective oxide layer in the sidewall region of the top metal layer.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer stacked from bottom to top.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The protective oxide layer and the passivation layer are formed by plasma-enhanced chemical vapor deposition.

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