A double-sided three-dimensional capacitor device based on TGV via and a preparation method thereof

Abstract

The application discloses a kind of double-sided three-dimensional capacitor devices based on TGV via and preparation method thereof, applied in three-dimensional semiconductor passive device IPD preparation technical field, and its technical solution main points are: including: insulating substrate, with opposite first surface and second surface, at least one TGV via is opened in insulating substrate and passes through first surface and second surface, TGV via is filled with TGV hole copper;C1 capacitor and C2 capacitor are respectively at least provided with one, respectively set in the first surface side and the second surface side of insulating substrate, including dielectric layer and side electrode, TGV hole copper is the public bottom electrode of C1 capacitor and C2 capacitor, so that C1 capacitor and C2 capacitor form series capacitor branch along the thickness direction of insulating substrate;RDL rewiring layer, first side electrode and second side electrode are connected to corresponding Bump external terminal based on RDL rewiring layer;With technical effect is: in limited area, higher withstand voltage, capacitance value and capacitance uniformity are considered.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional semiconductor passive device IPD fabrication technology, and in particular to a double-sided three-dimensional capacitor device based on TGV through-hole and its fabrication method. Background Technology

[0002] With the development of advanced packaging and integrated passive devices, the structure of passive devices in RF front-end modules is developing towards miniaturization, high frequency and three-dimensional integration. In particular, capacitors are key components in the field of glass substrate or passive device integration.

[0003] Existing MIM capacitors typically consist of a bottom electrode, a dielectric layer, and a top electrode sequentially formed on the substrate surface. The capacitor function is achieved through the dielectric layer between the two metal layers. However, the voltage withstand capability and capacitance value of MIM capacitors are often mutually restrictive: increasing the dielectric layer thickness to improve the voltage withstand capability leads to a decrease in capacitance value; conversely, decreasing the dielectric layer thickness to increase capacitance value leads to a decrease in voltage withstand capability; and increasing the electrode area or the number of capacitor cells to compensate for capacitance value increases the occupied area and the length of the metal traces, thereby increasing the parasitic resistance and inductance of the capacitor. Therefore, it is necessary to improve the structure and processing technology of existing capacitor devices to achieve a balance between high voltage withstand capability, capacitance value, and capacitance uniformity within a limited area. Summary of the Invention

[0004] The first objective of this invention is to provide a double-sided three-dimensional capacitor device based on TGV through-holes, which has the advantages of achieving high withstand voltage, capacitance value and capacitance uniformity within a limited area.

[0005] The above-mentioned technical objective of the present invention is achieved through the following technical solution: a double-sided three-dimensional capacitor device based on TGV through-hole, comprising: An insulating substrate has a first surface and a second surface opposite to each other. At least one TGV through-hole is formed in the insulating substrate, penetrating the first surface and the second surface. The TGV through-hole is filled with TGV copper. At least one capacitor C1 and one capacitor C2 are respectively disposed on the first surface side and the second surface side of the insulating substrate. The C1 capacitor includes a first dielectric layer and a first side electrode, with the first dielectric layer disposed between the corresponding TGV via copper and the first side electrode. The C2 capacitor includes a second dielectric layer and a second side electrode, with the second dielectric layer disposed between the corresponding TGV via copper and the second side electrode. The TGV via copper is a common bottom electrode for the C1 capacitor and the C2 capacitor, so that the C1 capacitor and the C2 capacitor form a series capacitor branch along the thickness direction of the insulating substrate. The RDL redistribution layer connects the first side electrode and the second side electrode to their respective bump external terminals.

[0006] The present invention is further configured such that: the first dielectric layer and the second dielectric layer cover the two end faces of the copper corresponding to the TGV hole, and the planar dimensions of the first side electrode and the second side electrode are smaller than the planar dimensions of the corresponding dielectric layer.

[0007] The present invention is further configured such that: the TGV via copper includes a first TGV via copper and a second TGV via copper arranged adjacent to each other; the first TGV via copper and the C1 capacitor and C2 capacitor correspondingly arranged at both ends of the first TGV via copper form a first series capacitor branch; the second TGV via copper and the C1 capacitor and C2 capacitor correspondingly arranged at both ends of the second TGV via copper form a second series capacitor branch; the two side electrodes of the first series capacitor branch and the two corresponding side electrodes of the second series capacitor branch are respectively connected through the RDL redistribution layer, so that the first series capacitor branch and the second series capacitor branch are connected in parallel.

[0008] The present invention is further configured such that adjacent C1 capacitors or C2 capacitors located on the first surface side and / or the second surface side of the insulating substrate share the same continuous dielectric layer, the continuous dielectric layer covering the end face region of the adjacent TGV via copper.

[0009] The invention is further configured such that: the insulating substrate has a groove communicating with the TGV via between adjacent TGV vias, the groove is filled with thick copper communicating with the copper of the adjacent TGV vias, the thick copper and the copper of the adjacent TGV vias form an integral hole-groove portion, the integral hole-groove portion serves as a common electrode and / or low-resistance connection portion of adjacent MIM capacitors, and the thickness of the thick copper is not less than 10μm.

[0010] The present invention is further configured such that: the first surface side and / or the second surface side of the insulating substrate are provided with at least two dielectric layers of different thicknesses.

[0011] The second objective of this invention is to provide a method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes, which has the advantage of achieving high withstand voltage, capacitance value, and capacitance uniformity within a limited area.

[0012] The above-mentioned technical objective of this invention is achieved through the following technical solution: a method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes, comprising: Step 1: Form TGV vias through the first surface and the second surface in the insulating substrate, and fill the TGV vias with TGV via copper. Step 2: First, a first dielectric layer is deposited on the first surface side of the insulating substrate and the surface of the first dielectric layer is patterned. Then, the first side electrode is formed on the first dielectric layer based on PVD combined with photolithography etching process, thereby completing the fabrication of C1 capacitor. Step 3: After applying PSPI negative adhesive to one side of the C1 capacitor, perform patterning to form a patterned insulating protective layer, and form a Via opening in the patterned insulating protective layer to expose the electrode connection area of ​​the C1 capacitor. Step 4: Form an RDL redistribution layer electrically connected to the C1 capacitor through the Via opening, and then prepare a protective layer to protect the corresponding side of the RDL redistribution layer; Step 5: Repeat the steps 2-4 to prepare a C2 capacitor and a patterned insulating protective layer on the second surface side of the insulating substrate, and prepare at least one RDL redistribution layer and a corresponding protective layer. Step 6: Fabricate the external Bump terminals so that capacitors C1 and C2 are connected to different external Bump terminals through the RDL redistribution layer.

[0013] The present invention is further configured such that, in step 4, the method for preparing the RDL redistribution layer and the protective layer is as follows: Step 4.1: First, a seed layer for forming the RDL redistribution layer is deposited using a PVD process; Step 4.2: Coat the seed layer with photoresist and expose and develop the photoresist; Step 4.3: Perform electrochemical electroplating deposition (ECD) in the developing area to form the RDL redistribution layer; Step 4.4: After the RDL redistribution layer is formed, PI material is coated and annealed to form a protective layer covering the RDL redistribution layer. The patterned insulating protective layer, the Via opening, the RDL redistribution layer, and the protective layer are formed sequentially according to the number of redistribution layers.

[0014] The present invention is further configured such that, when including multiple C1 capacitors or C2 capacitors, at least one of the following preparation methods is used to form a double-sided three-dimensional capacitor: C1 capacitors are formed on the first surfaces of two adjacent TGV via copper holes, and C2 capacitors are formed on the second surfaces of two adjacent TGV via copper holes, so that the corresponding C1 capacitors and C2 capacitors of the same TGV via copper hole form a series capacitor branch, and then the adjacent series capacitor branches are connected in parallel through the RDL redistribution layer. A continuous dielectric layer is formed by deposition on the first and / or second surfaces of the insulating substrate, covering the end face regions of adjacent TGV via copper, so that adjacent C1 capacitors or C2 capacitors share the same continuous dielectric layer. A groove is formed between two adjacent TGV via copper, and thick copper that is conductive to the adjacent TGV via copper is electroplated in the groove. The integral groove formed by the thick copper and the TGV via copper serves as a common electrode and / or low-resistance connection part for adjacent MIM capacitors.

[0015] The present invention is further configured such that: when at least two dielectric layers of different thicknesses are formed on the first surface and / or the second surface of the insulating substrate, based on a step-by-step deposition and step-by-step patterning process, the method includes: First, a thin first dielectric layer is deposited and patterned. Then, a first side electrode is formed on the first dielectric layer using PVD combined with photolithography etching process to complete the fabrication of the C1 capacitor corresponding to the first dielectric layer. Subsequently, a thicker second dielectric layer is deposited and patterned. Then, a second side electrode is formed on the second dielectric layer using PVD combined with photolithography etching process to complete the fabrication of the C2 capacitor corresponding to the second dielectric layer.

[0016] In summary, the present invention has the following beneficial effects: 1. This invention uses a copper TGV hole that penetrates the insulating substrate as the common bottom electrode for capacitors C1 and C2, thereby forming a series capacitor branch along the thickness direction of the insulating substrate. This allows the high voltage applied to the overall structure to be evenly distributed to the two capacitors, significantly reducing the voltage value borne by a single capacitor and greatly increasing the overall withstand voltage without increasing the thickness of the dielectric layer. 2. By forming multiple MIM capacitors between two adjacent TGV via copper and connecting multiple series capacitor branches in parallel through the RDL redistribution layer, the total capacitance value is increased while ensuring high withstand voltage capability. This avoids the problem of reduced capacitance value caused by the series capacitor branch structure and also reduces the equivalent series resistance. 3. By setting adjacent MIM capacitors to share the same continuous dielectric layer, the present invention reduces parasitic capacitance while ensuring the uniformity of the thickness of adjacent dielectric layers, thereby improving the capacitance ratio matching accuracy and the uniformity of capacitance values. 4. The present invention adds thick copper between adjacent TGV vias to form an integral via groove, which serves as a common electrode or low-resistance connection structure for adjacent MIM capacitors, thereby reducing the resistance value of the common connection area and improving heat dissipation performance. 5. By using step-by-step deposition and step-by-step patterning processes to form dielectric layers of different thicknesses, MIM capacitors with different capacitance values ​​or different voltage ratings can be fabricated in the same device, reducing the damage to the already fabricated MIM capacitors caused by subsequent processing. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the cross-sectional structure of the double-sided three-dimensional capacitor device in Example 1; Figure 2 This is a schematic diagram of the cross-sectional structure of the double-sided three-dimensional capacitor device in Example 2; Figure 3 This is a schematic diagram of the cross-sectional structure of the double-sided three-dimensional capacitor device in Example 3; Figure 4 This is a schematic diagram of the cross-sectional structure of the double-sided three-dimensional capacitor device in Example 4; Figure 5 This is a schematic diagram of the cross-sectional structure of the double-sided three-dimensional capacitor device in Example 5; Figure 6 This is a flowchart illustrating steps 1-4 in Example 6; Figure 7 This is a flowchart illustrating step 5 in Example 6; Figure 8 This is a flowchart illustrating step 6 in Example 6.

[0018] Reference numerals: 1. Insulating substrate; 2. TGV via; 3. TGV via copper; 31. First TGV via copper; 32. Second TGV via copper; 4. C1 capacitor; 41. First dielectric layer; 42. First side electrode; 5. C2 capacitor; 51. Second dielectric layer; 52. Second side electrode; 6. RDL redistribution layer; 7. Bump external terminal; 8. Continuous dielectric layer; 9. Integrated via slot; 10. Patterned insulating protective layer; 11. Via opening; 12. Protective layer. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings.

[0020] Example 1: refer to Figure 1 A double-sided three-dimensional capacitor based on TGV vias includes an insulating substrate 1, a C1 capacitor 4, a C2 capacitor 5, an RDL redistribution layer 6, and a bump external terminal 7. The insulating substrate 1 has opposing first and second surfaces. The insulating substrate 1 can be made of BF33 glass, borosilicate glass, low thermal expansion coefficient quartz glass, or other glass materials suitable for laser modification and wet drilling. At least one TGV via 2 penetrating the first and second surfaces is formed in the insulating substrate 1, and the TGV via 2 is filled with TGV via copper 3. At least one capacitor C1 (4) and one capacitor C2 (5) are respectively disposed on the first surface side and the second surface side of the insulating substrate 1. The capacitor C1 (4) includes a first dielectric layer 41 and a first side electrode 42. The first dielectric layer 41 is disposed between the corresponding TGV via copper 3 and the first side electrode 42, so that the TGV via copper 3 serves as one electrode of the capacitor C1 (4). Similarly, the capacitor C2 (5) includes a second dielectric layer 51 and a second side electrode 52. The second dielectric layer 51 is disposed between the corresponding TGV via copper 3 and the second side electrode 52, so that the TGV via copper 3 serves as one electrode of the capacitor C2 (5). The first side electrode 42 and the second side electrode 52 are connected to the corresponding bump external terminal 7 based on the RDL redistribution layer 6. The TGV via copper 3 serves as the common bottom electrode for capacitors C1 (4) and C2 (5), forming a series capacitor branch along the thickness direction of the insulating substrate 1. This series capacitor branch evenly distributes the high voltage applied to the overall structure to the two capacitors, significantly reducing the voltage value borne by a single capacitor. This greatly increases the overall withstand voltage without increasing the thickness of the dielectric layer. However, if the capacitance value of capacitor C1 (4) is C1 and the capacitance value of capacitor C2 (5) is C2, then the equivalent capacitance of the series capacitor branch, Ceq = C1 × C2 / (C1 + C2), directly reduces the equivalent capacitance value of the capacitor. In this embodiment, the first dielectric layer 41 and the second dielectric layer 51 can be SiNx dielectric layer, SiOx dielectric layer, or other materials.

[0021] Specifically, the first dielectric layer 41 and the second dielectric layer 51 cover the two end faces of the corresponding TGV via copper 3, and the planar dimensions of the first side electrode 42 and the second side electrode 52 are smaller than the planar dimensions of the corresponding dielectric layer. The single-sided bias of the first dielectric layer 41 and the second dielectric layer 51 relative to the outer edge of the end of the TGV via copper 3 is greater than 10 μm, and the single-sided indentation of the side electrode relative to the edge of the corresponding dielectric layer is 5 ± 2 μm, which helps to avoid the problem of field strength concentration at the electrode edge and improves breakdown stability.

[0022] Example 2: refer to Figure 2Compared to Embodiment 1, in this embodiment, the TGV via copper 3 includes a first TGV via copper 31 and a second TGV via copper 32 disposed adjacent to each other. The first TGV via copper 31 and the C1 capacitor 4 and C2 capacitor 5 correspondingly disposed at both ends of the first TGV via copper 31 form a first series capacitor branch. The second TGV via copper 32 and the C1 capacitor 4 and C2 capacitor 5 correspondingly disposed at both ends of the second TGV via copper 32 form a second series capacitor branch. The two side electrodes of the first series capacitor branch are respectively connected to the two corresponding side electrodes of the second series capacitor branch through the RDL redistribution layer 6, so that the first series... The first series capacitor branch and the second series capacitor branch are connected in parallel. If the capacitance values ​​of the two MIM capacitors in the first series capacitor branch are C1 and C3, and the capacitance values ​​of the two MIM capacitors in the second series capacitor branch are C2 and C4, then the total equivalent capacitance is Ceq=C1*C3 / (C1+C3)+C2*C4 / (C2+C4). By connecting the first series capacitor branch and the second series capacitor branch in parallel through the RDL redistribution layer 6, the equivalent series resistance is reduced while increasing the total capacitance value, and voltage distribution is achieved, avoiding the problem of the total capacitance value being reduced due to a single series capacitor branch.

[0023] Example 3: refer to Figure 3 Compared to Embodiment 1, in this embodiment, adjacent C1 capacitors 4 or C2 capacitors 5 located on the first surface and / or the second surface of the insulating substrate 1 share the same continuous dielectric layer 8. Specifically, this includes: two adjacent C1 capacitors 4 located on the first surface of the insulating substrate 1 sharing the same continuous dielectric layer 8, or two adjacent C2 capacitors 5 located on the second surface of the insulating substrate 1 sharing the same continuous dielectric layer 8, or two adjacent C1 capacitors 4 and C2 capacitors 5 located on both the first and second surfaces each sharing the same continuous dielectric layer. The continuous dielectric layer 8 covers the end face area of ​​adjacent TGV via copper 3. The continuous dielectric layer 8 is formed in one deposition and patterning process, thereby ensuring good consistency in the dielectric layer thickness and dielectric material between adjacent capacitors. This improves the capacitance matching accuracy between adjacent capacitors, reduces parasitic capacitance, and also ensures the uniformity of the thickness of adjacent dielectric layers. This is suitable for differential circuits, RF filter circuits, or capacitor array structures that require high matching accuracy.

[0024] Example 4: refer to Figure 4Compared with Embodiment 2 or Embodiment 3, in this embodiment, the insulating substrate 1 has a groove connected to the TGV via 2 between adjacent TGV vias 2. The groove is filled with thick copper that is connected to the adjacent TGV via copper 3. The thick copper and the adjacent TGV via copper 3 form an integral via groove 9. The integral via groove 9 serves as a common electrode and / or low-resistance connection part for adjacent MIM capacitors. The thickness of the thick copper is not less than 10μm. Since the integral via groove has a large conductive cross-sectional area, it can effectively reduce the resistance of the common electrode and the parallel connection area and improve the local heat dissipation capacity compared with the traditional RDL redistribution layer 6 conductive structure.

[0025] Example 5: refer to Figure 5 Compared with Embodiment 4, in this embodiment, the first surface side and / or the second surface side of the insulating substrate 1 are provided with at least two dielectric layers of different thicknesses, thereby further improving the flexibility of capacitor design on the upper and lower sides of the insulating substrate 1.

[0026] Example 6: refer to Figures 6 to 8 A method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes, using a double-sided three-dimensional capacitor based on TGV through-holes as shown in the above embodiments, includes: Step 1: Form a TGV via 2 penetrating the first surface and the second surface in the insulating substrate 1, and fill the TGV via 2 with TGV copper via 3. The specific preparation method of the TGV via 2 and the TGV copper via 3 is as follows: Step 1.1 First, the insulating substrate 1 is laser modified to form the predetermined position of the TGV through hole 2 in the glass substrate. The center distance between adjacent TGV through holes 2 needs to be greater than 100μm, preferably 200-300μm. Step 1.2: Perform wet drilling on the laser-modified insulating substrate 1 to achieve interconnection of the top and bottom holes. NaOH or HF is used for wet drilling. NaOH has a high etching rate and is suitable for a variety of glasses. HF is suitable for a slightly smaller variety of glasses and cannot be used for high Ga glasses. The top hole size is usually 50-100μm. Step 1.3: Deposit a seed layer on the hole wall of TGV via 2 and on the first and second surfaces of the insulating substrate 1. The seed layer can be a Ti / Cu combination or a chemical plating method. Then, fill the TGV via 2 with copper through an electrochemical deposition process (ECD process) to form TGV via copper 3. Step 1.4 After electroplating, the excess copper layer on the surface of the insulating substrate 1 is removed by CMP process so that the end of the TGV hole copper 3 forms a planarized plane with the surface of the insulating substrate 1, providing a metal base surface for the dielectric layer and RDL redistribution layer 6. Step 2: Firstly, a first dielectric layer 41 is deposited on the first surface side of the insulating substrate 1 and the surface of the first dielectric layer 41 is patterned so that the first dielectric layer 41 covers the peripheral area of ​​the TGV via copper 3 on the first surface side. Then, the first side electrode 42 is formed on the first dielectric layer 41 based on PVD combined with photolithography etching process, thereby completing the fabrication of C1 capacitor 4. Step 3: After applying PSPI negative adhesive to one side of the C1 capacitor 4, perform patterning to form a patterned insulating protective layer 10, and form a Via opening 11 in the patterned insulating protective layer 10 to expose the electrode connection area of ​​the C1 capacitor 4. Step 4: Form an RDL redistribution layer 6 electrically connected to capacitor C1 4 through the Via opening 11. Then, fabricate a protective layer 12 to protect the corresponding side of the RDL redistribution layer 6. The fabrication methods of the RDL redistribution layer 6 and the protective layer 12 are as follows: Step 4.1: First, a seed layer for forming the RDL redistribution layer 6 is deposited using a PVD process. The seed layer can be a Ti / Cu composite seed layer. Step 4.2: Coat the seed layer with photoresist and expose and develop the photoresist; Step 4.3: Perform electrochemical electroplating deposition (ECD) in the developing area to form the RDL redistribution layer 6; Step 4.4: After the RDL redistribution layer 6 is formed, PI material is coated and annealed to form a protective layer 12 covering the RDL redistribution layer 6. The protective layer 12 is used to protect the RDL redistribution layer 6 and achieve insulation between adjacent metal layers. The patterned insulating protective layer 10, Via opening 11, RDL redistribution layer 6 and protective layer 12 are formed sequentially according to the number of redistribution layers. Step 5: Repeat the steps 2-4 to prepare C2 capacitor 5 and patterned insulating protective layer 10 on the second surface side of insulating substrate 1, and prepare at least one RDL redistribution layer 6 and corresponding protective layer 12. Step 6: Fabricate the Bump external terminal 7 so that capacitors C1 4 and C2 5 are connected to different Bump external terminals 7 through the RDL redistribution layer 6. The Bump external terminal 7 is used to electrically connect the double-sided three-dimensional capacitor to the external package structure or circuit board.

[0027] Example 7: refer to Figure 4 , Figures 6 to 8 Compared to Example 6, in this example, when multiple C1 capacitors 4 or C2 capacitors 5 are included, at least one of the following fabrication methods is used to form a double-sided three-dimensional capacitor: C1 capacitors 4 are formed on the first surfaces of two adjacent TGV via copper 3, and C2 capacitors 5 are formed on the second surfaces of two adjacent TGV via copper 3, so that the corresponding C1 capacitors 4 and C2 capacitors 5 of the same TGV via copper 3 form a series capacitor branch. Then, the adjacent series capacitor branches are connected in parallel through the RDL redistribution layer 6. Based on this, voltage distribution is achieved through the series capacitor branches, and the total capacitance value is compensated by connecting the two series capacitor branches in parallel, taking into account both the capacitor withstand voltage and the capacitance value. A continuous dielectric layer 8 is formed on the first and / or second surfaces of the insulating substrate 1 by deposition, covering the end face region of the adjacent TGV via copper 3, so that adjacent C1 capacitor 4 or C2 capacitor 5 share the same continuous dielectric layer 8, thereby improving the uniformity of dielectric layer thickness, enhancing the capacitance ratio matching accuracy and capacitance value uniformity. A groove is formed between two adjacent TGV via copper 3, and thick copper that is conductive to the adjacent TGV via copper 3 is electroplated in the groove. The integrated groove part 9 composed of thick copper and TGV via copper 3 serves as a common electrode and / or low resistance connection part for adjacent MIM capacitors. The integrated groove step reduces the resistance of the connection area and improves the heat dissipation performance.

[0028] Example 8: refer to Figures 5 to 8 Compared to Example 6, in this example, when at least two dielectric layers of different thicknesses are formed on the first and / or second surfaces of the insulating substrate 1, the process, based on step-by-step deposition and step-by-step patterning, includes: First, a thin first dielectric layer 41 is deposited and patterned. Then, a first side electrode 42 is formed on the first dielectric layer 41 based on PVD combined with photolithography etching process to complete the preparation of C1 capacitor 4 corresponding to the first dielectric layer 41. Subsequently, a thicker second dielectric layer 51 is deposited and patterned. Then, a second side electrode 52 is formed on the second dielectric layer 51 using PVD combined with photolithography etching process to complete the fabrication of the C2 capacitor 5 corresponding to the second dielectric layer 51. By forming dielectric layers of different thicknesses through stepwise deposition and stepwise patterning processes, MIM capacitors with different capacitance values ​​or different voltage ratings can be fabricated in the same device, reducing the damage to the already fabricated MIM capacitors caused by subsequent processing.

[0029] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make inventive modifications to this embodiment as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A double-sided three-dimensional capacitor device based on TGV through-holes, characterized in that, include: An insulating substrate (1) has a first surface and a second surface opposite to each other. At least one TGV through hole (2) is formed in the insulating substrate (1) through the first surface and the second surface. The TGV through hole (2) is filled with TGV copper (3). At least one C1 capacitor (4) and one C2 capacitor (5) are respectively disposed on the first surface side and the second surface side of the insulating substrate (1). The C1 capacitor (4) includes a first dielectric layer (41) and a first side electrode (42). The first dielectric layer (41) is disposed between the corresponding TGV via copper (3) and the first side electrode (42). The C2 capacitor (5) includes a second dielectric layer (51) and a second side electrode (52). The second dielectric layer (51) is disposed between the corresponding TGV via copper (3) and the second side electrode (52). The TGV via copper (3) is the common bottom electrode of the C1 capacitor (4) and the C2 capacitor (5), so that the C1 capacitor (4) and the C2 capacitor (5) form a series capacitor branch along the thickness direction of the insulating substrate (1). The RDL redistribution layer (6) is used to connect the first side electrode (42) and the second side electrode (52) to the corresponding Bump external terminals (7) based on the RDL redistribution layer (6).

2. The double-sided three-dimensional capacitor device based on TGV through-hole according to claim 1, characterized in that, The first dielectric layer (41) and the second dielectric layer (51) cover the two end faces of the corresponding TGV hole copper (3), and the planar dimensions of the first side electrode (42) and the second side electrode (52) are smaller than the planar dimensions of the corresponding dielectric layer.

3. A double-sided three-dimensional capacitor device based on TGV through-holes according to claim 1, characterized in that, The TGV via copper (3) includes a first TGV via copper (31) and a second TGV via copper (32) arranged adjacent to each other. The first TGV via copper (31) forms a first series capacitor branch with the C1 capacitor (4) and C2 capacitor (5) respectively arranged at both ends of the first TGV via copper (31). The second TGV via copper (32) forms a second series capacitor branch with the C1 capacitor (4) and C2 capacitor (5) respectively arranged at both ends of the second TGV via copper (32). The two side electrodes of the first series capacitor branch and the two corresponding side electrodes of the second series capacitor branch are respectively connected through the RDL redistribution layer (6) so that the first series capacitor branch and the second series capacitor branch are connected in parallel.

4. A double-sided three-dimensional capacitor device based on TGV through-holes according to claim 3, characterized in that, The adjacent C1 capacitor (4) or C2 capacitor (5) located on the first surface side and / or the second surface side of the insulating substrate (1) share the same continuous dielectric layer (8), which covers the end face area of ​​the adjacent TGV via copper (3).

5. A double-sided three-dimensional capacitor device based on TGV through-holes according to claim 3 or 4, characterized in that, The insulating substrate (1) has a groove between adjacent TGV vias (2) that communicates with the TGV vias (2). The groove is filled with thick copper that is in communication with the adjacent TGV via copper (3). The thick copper and the adjacent TGV via copper (3) form an integral hole-groove portion (9). The integral hole-groove portion (9) serves as a common electrode and / or low-resistance connection portion for adjacent MIM capacitors. The thickness of the thick copper is not less than 10 μm.

6. A double-sided three-dimensional capacitor device based on TGV through-holes according to claim 5, characterized in that, The insulating substrate (1) has at least two dielectric layers of different thicknesses on its first surface side and / or second surface side.

7. A method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes, using the double-sided three-dimensional capacitor based on TGV through-holes as described in claim 6, characterized in that... include: Step 1: Form a TGV through hole (2) through the first surface and the second surface in the insulating substrate (1), and fill the TGV through hole (2) with TGV copper (3); Step 2: Firstly, a first dielectric layer (41) is deposited on the first surface side of the insulating substrate (1) and the surface of the first dielectric layer (41) is patterned. Then, a first side electrode (42) is formed on the first dielectric layer (41) based on PVD combined with photolithography etching process, thereby completing the fabrication of C1 capacitor (4). Step 3: After applying PSPI negative adhesive to one side of the C1 capacitor (4), a patterned insulating protective layer (10) is formed, and a Via opening (11) is formed in the patterned insulating protective layer (10) to expose the electrode connection area of ​​the C1 capacitor (4). Step 4: Form an RDL redistribution layer (6) electrically connected to the C1 capacitor (4) through the Via opening (11), and then prepare a protective layer (12) to protect the RDL redistribution layer (6) on the corresponding side. Step 5: Repeat the steps 2-4 to prepare a C2 capacitor (5) and a patterned insulating protective layer (10) on the second surface side of the insulating substrate (1), and prepare at least one RDL redistribution layer (6) and a corresponding protective layer (12). Step 6: Fabricate the Bump external terminal (7) so that the C1 capacitor (4) and C2 capacitor (5) are respectively connected to different Bump external terminals (7) through the RDL redistribution layer (6).

8. A method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes according to claim 7, characterized in that, In step 4, the preparation methods for the RDL redistribution layer (6) and the protective layer (12) are as follows: Step 4.1: First, a seed layer for forming the RDL redistribution layer (6) is deposited using a PVD process; Step 4.2: Coat the seed layer with photoresist and expose and develop the photoresist; Step 4.3: Electrochemical electroplating deposition (ECD) is performed in the developing area to form the RDL redistribution layer (6); Step 4.4 After the RDL redistribution layer (6) is formed, PI material is coated and annealed to form a protective layer (12) covering the RDL redistribution layer (6). The patterned insulating protective layer (10), the Via opening (11), the RDL redistribution layer (6) and the protective layer (12) are formed sequentially according to the number of redistribution layers.

9. The method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes according to claim 7, characterized in that, When multiple C1 capacitors (4) or C2 capacitors (5) are included, a double-sided three-dimensional capacitor is formed using at least one of the following fabrication methods: C1 capacitors (4) are formed on the first surfaces of two adjacent TGV via copper (3), and C2 capacitors (5) are formed on the second surfaces of two adjacent TGV via copper (3), so that the corresponding C1 capacitors (4) and C2 capacitors (5) of the same TGV via copper (3) form a series capacitor branch, and then the adjacent series capacitor branches are connected in parallel through the RDL redistribution layer (6). A continuous dielectric layer (8) is formed by deposition on the first and / or second surfaces of the insulating substrate (1) to cover the end face regions of the adjacent TGV via copper (3), so that the adjacent C1 capacitor (4) or C2 capacitor (5) shares the same continuous dielectric layer (8). A tank is formed between two adjacent TGV copper holes (3), and thick copper that is conductive to the adjacent TGV copper holes (3) is electroplated in the tank. The integrated hole-groove portion (9) composed of the thick copper and the TGV copper holes (3) serves as a common electrode and / or low-resistance connection portion for adjacent MIM capacitors.

10. The method for fabricating a double-sided three-dimensional capacitor based on TGV through-holes according to claim 7, characterized in that, When at least two dielectric layers of different thicknesses are formed on the first and / or second surfaces of the insulating substrate (1), the process includes step-by-step deposition and step-by-step patterning. First, a thin first dielectric layer (41) is deposited and patterned. Then, a first side electrode (42) is formed on the first dielectric layer (41) based on PVD combined with photolithography etching process to complete the preparation of C1 capacitor (4) corresponding to the first dielectric layer (41). Subsequently, a thicker second dielectric layer (51) is deposited and patterned. Then, a second side electrode (52) is formed on the second dielectric layer (51) using PVD combined with photolithography etching process to complete the fabrication of the C2 capacitor (5) corresponding to the second dielectric layer (51).

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