Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and a method for manufacturing the same. The method includes the following steps: providing a semiconductor substrate and forming a dielectric layer on the substrate, the dielectric layer having a gradient of doped ions; forming a plurality of conductive plugs, each conductive plug penetrating the dielectric layer; forming trench structures in the dielectric layer between adjacent conductive plugs using photolithography and etching processes; performing wet etching on the trench structures to form a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom; forming a first masking layer on the dielectric layer, the first masking layer sealing the upper port of the trench structure to form an air gap. This invention reduces the dielectric constant k by forming air gaps, thereby reducing RC delay.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] With the continuous shrinking of integrated circuit technology nodes and the dramatic increase in interconnect wiring density, the parasitic effect of resistive-capacitive (RC) coupling caused by resistors and capacitors in interconnect systems grows rapidly, affecting the signal transmission speed of devices. The signal transmission speed of a circuit depends on the product of resistance (R) and capacitance (C), therefore, RC coupling parasitic effects affect the overall performance of the chip, especially as the operating frequency increases, the delay becomes very large. Therefore, effectively solving the RC delay problem is very urgent.

[0003] Currently, reducing RC delay can be achieved by reducing resistance (R) and capacitance (C) respectively. Resistance R = ρL / a, where a and L are the cross-sectional area of ​​the conductor perpendicular to the current direction and the length of the conductor in the current direction, respectively. These are parameters determined during geometric scaling. ρ is the resistivity value, and copper interconnect technology has been introduced to replace aluminum. Copper interconnect will be used at least until the 22nm technology node. Capacitance C = kA / d, where A and d are the area of ​​the conductors facing each other and the distance between the conductors, respectively. These parameters were also determined during geometric scaling. Therefore, the capacitance C can only be reduced by decreasing the dielectric constant k of the material, thereby reducing RC delay.

[0004] The k-value for low-k (low dielectric constant) materials in the industry has evolved from 3.6 to the current 2.5, but as device sizes shrink, the k-value for low-k materials needs to be even lower. Research has found that air is the insulating medium with the lowest dielectric constant (k=1). In the nanoscale world of copper interconnects, using air instead of chemical materials as a barrier can minimize RC delay. The introduction of the air gap concept allows air to be used as a low-k material, but currently, specific methods for fabricating air gaps are lacking.

[0005] Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same, which reduces the dielectric constant k by forming an air gap, thereby reducing the RC delay. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which reduces the dielectric constant k by forming an air gap, thereby reducing RC delay.

[0007] To achieve the above-mentioned objectives and other related objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0008] A semiconductor substrate is provided, and a dielectric layer is formed on the semiconductor substrate, the dielectric layer having doped ions of varying concentrations;

[0009] Multiple conductive plugs are formed, and each of the conductive plugs penetrates the dielectric layer;

[0010] A trench structure is formed in the dielectric layer between adjacent conductive plugs using photolithography and etching processes;

[0011] The trench structure is subjected to wet etching to form a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom.

[0012] A first masking layer is formed on the dielectric layer, and the first masking layer seals the upper port of the trench structure to form an air gap.

[0013] Optionally, in the semiconductor device manufacturing method, the dielectric layer is formed using a chemical vapor deposition process, wherein the reactants used in the chemical vapor deposition process include silicon-containing compounds, oxygen, and compounds containing doped ions.

[0014] Optionally, in the semiconductor device manufacturing method, when the dopant ions in the dielectric layer include phosphorus, the compound containing the dopant ions includes triethyl phosphate. During the formation of the dielectric layer, the flow rate of the compound containing the dopant ions gradually decreases or alternates between gradually increasing and gradually decreasing, and finally stops after gradually decreasing. The flow rate of the compound containing the dopant ions ranges from 50 mg / min to 300 mg / min.

[0015] When the dopant ions of the dielectric layer include boron, the compound containing the dopant ions includes one of triethoxyboron and diborane. During the formation of the dielectric layer, the flow rate of the compound containing the dopant ions gradually increases or gradually decreases and gradually increases, and finally the flow of the compound containing the dopant ions stops after gradually increasing. The flow rate of the compound containing the dopant ions ranges from 50 mg / min to 300 mg / min.

[0016] Optionally, in the semiconductor device manufacturing method, the dielectric layer is made of silicon oxide, and the thickness of the dielectric layer is [missing information].

[0017] Optionally, in the semiconductor device manufacturing method, the doping method of the dopant ions in the dielectric layer includes ion implantation.

[0018] Optionally, in the method for manufacturing the semiconductor device, the step of forming the trench structure using photolithography and etching processes includes:

[0019] A second masking layer and a protective layer are sequentially formed on the dielectric layer and the conductive plug;

[0020] A photoresist layer is formed on the protective layer and the photoresist layer is patterned, with the patterned photoresist layer exposing a portion of the upper surface of the protective layer between adjacent conductive plugs.

[0021] The patterned photoresist layer is used as a mask to sequentially perform dry etching on the protective layer, the second masking layer, and the dielectric layer to form the trench structure.

[0022] Optionally, in the method for manufacturing the semiconductor device, the step of performing wet etching on the trench structure includes:

[0023] The patterned photoresist layer is used as a mask to perform wet etching on the trench structure, so that the trench structure is narrow at the top and wide at the bottom or has multiple alternating narrow and wide shapes from top to bottom.

[0024] Optionally, in the semiconductor device manufacturing method, the solution for the wet etching process includes a hydrofluoric acid solution.

[0025] To achieve the above and other related objectives, the present invention also provides a semiconductor device prepared by the semiconductor device manufacturing method described above.

[0026] Optionally, in the semiconductor device, an air gap is formed in the dielectric layer of the semiconductor device, and the air gap has a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the semiconductor device manufacturing method provided by the present invention, the concentration of doped ions in the dielectric layer gradually changes, and the etching rate of wet etching changes with the concentration of doped ions, so that the trench structure forms a shape that is narrow at the top and wide at the bottom or a shape that alternates between narrow and wide at the top and bottom. That is, the upper port of the trench structure is relatively narrow. Therefore, when forming the first masking layer, the first masking layer can seal the upper port of the trench structure to form an air gap, thereby reducing the dielectric constant k value and thus reducing the RC delay.

[0029] Secondly, when the dopant ions in the dielectric layer are phosphorus, the concentration of dopant ions in the dielectric layer gradually decreases or alternates between gradually increasing and gradually decreasing from bottom to top (along the direction from the semiconductor substrate to the dielectric layer), and finally ends after gradually decreasing. The etching rate of wet etching increases with the increase of phosphorus concentration. During the wet etching process of the trench structure, the amount of dielectric layer etched away on the sidewall of the trench structure gradually increases or alternates between gradually increasing and gradually decreasing from top to bottom, thereby making the trench structure form a shape that is narrow at the top and wide at the bottom, or a shape that is narrow and wide multiple times from top to bottom.

[0030] Furthermore, when the dopant ions in the dielectric layer are boron, the concentration of the dopant ions in the dielectric layer gradually increases or decreases and increases alternately from bottom to top (along the direction from the semiconductor substrate to the dielectric layer), and finally increases and ends. Meanwhile, the etching rate of wet etching decreases as the boron concentration increases. During the wet etching process on the trench structure, the amount of dielectric layer etched away on the sidewalls of the trench structure gradually increases or decreases alternately from top to bottom, thereby causing the trench structure to form a shape that is narrow at the top and wide at the bottom, or a shape that is narrow and wide multiple times from top to bottom. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the product structure after step S21 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram of the product structure after step S22 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram of the product structure after step S24 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of the product structure after step S25 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the product structure after step S31 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0036] Figure 6 This is a schematic diagram of the product structure after step S32 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0037] Figure 7 This is a schematic diagram of the product structure after step S33 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0038] Figure 8 This is a schematic diagram of the product structure after step S4 is performed in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0039] Figure 9 This is a schematic diagram of the product structure after removing the patterned second photoresist layer and the second protective layer in a semiconductor device manufacturing method according to an embodiment of the present invention.

[0040] Figure 10 This is a schematic diagram of a structure in a semiconductor device manufacturing method according to an embodiment of the present invention, showing a gap that is narrow at the top and wide at the bottom.

[0041] Figure 11 This is a schematic diagram of a structure in which the gap formed in the manufacturing method of a semiconductor device according to an embodiment of the present invention has a shape that is wide in the middle and narrow at the top and bottom;

[0042] Figures 1-11 middle,

[0043] 11-Base layer, 12-Third masking layer, 13-Dielectric layer, 14-First protective layer, 15-Opening, 16-Conductive plug, 17-Second photoresist layer, 18-Trench structure, 21-Top-narrow-bottom-wide shape structure, 22-First masking layer, 23-Air gap, 24-First photoresist layer, 25-Second masking layer, 26-Second protective layer. Detailed Implementation

[0044] The semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0045] See Figures 1 to 11 The present invention provides a method for manufacturing a semiconductor device, which may include the following steps:

[0046] Step S1: Provide a semiconductor substrate and form a dielectric layer 13 on the semiconductor substrate, the dielectric layer 13 having a gradient of doped ions;

[0047] Step S2: Form a plurality of conductive plugs 16, wherein each of the conductive plugs 16 penetrates the dielectric layer 13;

[0048] Step S3: Using photolithography and etching processes, trench structures 18 are formed in the dielectric layer 13 between adjacent conductive plugs 16;

[0049] Step S4: Perform wet etching on the trench structure 18 to form a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom.

[0050] Step S5: A first masking layer 22 is formed on the dielectric layer 13, and the first masking layer 22 seals the upper port of the trench structure 18 to form an air gap 23.

[0051] See Figure 1 Step S1 is executed to provide a semiconductor substrate. In this embodiment, the semiconductor substrate may include a substrate layer 11 and a third masking layer 12 stacked sequentially, with the dielectric layer 13 located on the third masking layer 12. The substrate layer 11 may be a semiconductor material such as single-crystal silicon, polycrystalline silicon, or germanium-silicon compound; furthermore, a semiconductor structure may be formed in the substrate layer 11, such as a shallow trench isolation structure or other necessary structure for forming a semiconductor device; the above semiconductor structure is determined according to the actual semiconductor device manufacturing process and is well known to those skilled in the art, so it will not be described in detail here. The material of the third masking layer 12 may be set according to process requirements. Further, the material of the third masking layer 12 is preferably a Si-containing compound, such as at least one of SiO2, SiN, and NDC. The formation process of the third masking layer 12 may be atomic layer deposition, physical vapor deposition, or chemical vapor deposition, but is not limited to these.

[0052] Continue reading Figure 1 A dielectric layer 13 is formed on the third masking layer 12. The dielectric layer 13 is preferably made of silicon oxide, and its thickness is preferably... The dopant ions in the dielectric layer 13 can be phosphorus (P) or boron (B), but are not limited to these. The dielectric layer 13 is preferably formed using a chemical vapor deposition (CVD) process, and the reactants used in the CVD process can include silicon-containing compounds, oxygen (O2), and compounds containing dopant ions. When the dopant ion in the dielectric layer 13 is phosphorus, the compound containing the dopant ion is preferably triethylphosphate (TEPO), but is not limited to this; when the dopant ion in the dielectric layer 13 is boron, the compound containing the dopant ion is preferably one of triethoxyboron (TEB) and diborane (B2H6), but is not limited to this. The silicon-containing compound is preferably tetraethoxysilane (TEOS), but is not limited to this. In this embodiment, dielectric layers 13 with different dopant ion concentrations can be formed in the same reaction chamber in a single step.

[0053] When phosphorus is used as the dopant ion in the dielectric layer 13, TEOS, O2, and triethyl phosphate are introduced during the formation of the dielectric layer 13 using a chemical vapor deposition process. The TEOS flow rate is in the range of 500 mg / min to 5000 mg / min, the O2 flow rate is in the range of 500 sccm to 10000 sccm, and the triethyl phosphate flow rate is in the range of 50 mg / min to 300 mg / min. During the formation process, the triethyl phosphate flow rate is gradually decreased or alternately increased and decreased. The process temperature is preferably 350°C to 600°C, and the ambient pressure is preferably 0.1 Torr to 600 Torr. During the formation process (from bottom to top), the triethyl phosphate flow rate is gradually decreased or alternately increased and decreased, and finally, the introduction of triethyl phosphate is stopped after gradually decreasing, so that the phosphorus concentration in the dielectric layer 13 gradually decreases or alternately increases and decreases from bottom to top (i.e., along the direction from the semiconductor substrate to the dielectric layer 13). The phosphorus concentration on the surface of the dielectric layer 13 away from the semiconductor substrate is preferably minimized. In this embodiment, since the flow of triethyl phosphate is gradually reduced and then stopped at the end, the phosphorus concentration of the dielectric layer 13 gradually decreases in the final stage of the formation process. For example, the flow rate of triethyl phosphate gradually decreases during the formation process, causing the phosphorus concentration of the dielectric layer 13 to gradually decrease from bottom to top. Alternatively, the flow rate of triethyl phosphate may gradually increase and then gradually decrease during the formation process, causing the phosphorus concentration of the dielectric layer 13 to gradually increase and then gradually decrease from bottom to top. Or, for example, the flow rate of triethyl phosphate may gradually decrease, then gradually increase, and then gradually decrease during the formation process, causing the phosphorus concentration of the dielectric layer 13 to gradually decrease, then gradually increase, and then gradually decrease from bottom to top.

[0054] When the doped ions in the dielectric layer 13 can be boron, TEOS, O2, and triethoxyboron (or diborane) are introduced during the formation of the dielectric layer 13 using a chemical vapor deposition process. The TEOS flow rate is in the range of 500 mg / min to 5000 mg / min, the O2 flow rate is in the range of 500 sccm to 10000 sccm, and the triethoxyboron (or diborane) flow rate is in the range of 50 mg / min to 300 mg / min. During the formation process, the flow rate of triethoxyboron (or diborane) is gradually increased or alternately decreased and increased. The process temperature is preferably 350°C to 600°C, and the ambient pressure is preferably 0.1 Torr to 600 Torr. During the formation process (from bottom to top), the flow rate of triethoxyborane (or diborane) gradually increases, decreases, or alternates between increasing and decreasing, and finally, after gradually increasing, the flow of triethoxyborane (or diborane) is stopped. This causes the boron concentration of the dielectric layer 13 to gradually increase, decrease, or alternate between increasing and decreasing from bottom to top (i.e., along the direction from the semiconductor substrate to the dielectric layer 13). Preferably, the boron concentration is highest on the surface of the dielectric layer 13 furthest from the semiconductor substrate. In this embodiment, because the flow of triethoxyborane (or diborane) is stopped after gradually increasing, the boron concentration of the dielectric layer 13 gradually increases in the final stage of the formation process.

[0055] In other embodiments, the doping method of the dopant ions in the dielectric layer 13 can be ion implantation, and the dopant ions can be phosphorus or boron, but are not limited to these. When the dopant ion in the dielectric layer 13 is phosphorus, the concentration of the dopant ion in the dielectric layer 13 gradually decreases from bottom to top (along the direction from the semiconductor substrate to the dielectric layer 13) or alternates between gradually increasing and gradually decreasing, and finally ends after gradually decreasing; when the dopant ion in the dielectric layer 13 is boron, the concentration of the dopant ion in the dielectric layer gradually increases from bottom to top (along the direction from the semiconductor substrate to the dielectric layer 13) or alternates between gradually decreasing and gradually increasing, and finally ends after gradually increasing. This embodiment can use conventional ion implantation, which will not be described in detail here.

[0056] See Figures 1 to 4 Step S2 is executed to form a plurality of conductive plugs 16. Each conductive plug 16 sequentially penetrates the dielectric layer 13 and the third masking layer 12 and contacts the substrate layer 11. In this embodiment, the material of the conductive plug 16 is preferably copper, but is not limited thereto. The step of forming a plurality of conductive plugs 16 may include:

[0057] Step S21: Sequentially form a first protective layer 14 and a first photoresist layer 24 on the dielectric layer 13, and pattern the first photoresist layer 24;

[0058] Step S22: Using the patterned first photoresist layer 24 as a mask, the first protective layer 14, the dielectric layer 13 and the third masking layer 12 are sequentially etched to form an opening 15, which exposes the base layer 11.

[0059] Step S23: Remove the first photoresist layer 24;

[0060] Step S24: Form a conductive plug 16 in the opening 15 using an electroplating process;

[0061] Step S25: Remove the first protective layer 14 and the conductive plug 16 on the first protective layer 14 using a chemical mechanical polishing process.

[0062] Continue reading Figure 1 Step S21 is executed to form the first protective layer 14 and the first photoresist layer 24, and the first photoresist layer 24 is patterned. In this embodiment, the first protective layer 14 can be a single-layer structure or a multi-layer structure. For example, the first protective layer 14 includes an organic carbon layer and a bottom anti-reflection layer stacked sequentially. In this embodiment, the first photoresist layer 24 is patterned using a photolithography process.

[0063] See Figure 2 Step S22 is executed to form an opening 15. In this embodiment, the first protective layer 14, the dielectric layer 13, and the third masking layer 12 are etched using the patterned first photoresist layer 24 as a mask to form the opening 15, which exposes the upper surface of the substrate layer 11. The etching process in this step is preferably a dry etching process.

[0064] Step S23 is performed to remove the first photoresist layer 24. In this embodiment, the removal process of the first photoresist layer 24 is preferably an ashing process, but it is not limited thereto.

[0065] See Figure 3 Step S24 is executed to form the conductive plug 16. In this embodiment, the conductive plug 16 in the opening 15 can be formed by an electroplating process, and the conductive plug 16 in this step will extend to cover the upper surface of the first protective layer 14.

[0066] See Figure 4 Step S25 is executed to remove the first protective layer 14 and the conductive plug 16 on the first protective layer 14. In this embodiment, chemical mechanical polishing (CMP) is preferably used to remove the first protective layer 14 and the conductive plug 16 on the first protective layer 14. In this embodiment, a portion of the dielectric layer 13 thickness and the conductive plug 16 in that portion of the dielectric layer 13 can also be removed; specifically, the conductive plug 16 can be made to a specified height according to process requirements.

[0067] See Figures 5 to 7 Step S3 is executed to form a trench structure 18. In this embodiment, the trench structure 18 is preferably formed using photolithography and etching processes. The trench structure 18 is located in the dielectric layer 13 between adjacent conductive plugs 16, and the trench structure 18 can extend from the upper surface of the dielectric layer 13 to a portion of the depth of the dielectric layer 13, or it can penetrate the dielectric layer 13, exposing the upper surface of the third masking layer 12. The formation process of the trench structure 18 may include:

[0068] Step S31: Sequentially form a second masking layer 25 and a protective layer (i.e., a second protective layer 26) on the dielectric layer 13 and the conductive plug 16;

[0069] Step S32: Form a photoresist layer on the second protective layer 26 and pattern the photoresist layer, the patterned photoresist layer exposing a portion of the upper surface of the second protective layer 26 between adjacent conductive plugs 16;

[0070] Step S33: Using the patterned photoresist layer as a mask, the protective layer, the second masking layer 25 and the dielectric layer 13 are sequentially dry etched to form the trench structure 18.

[0071] See Figure 5 Step S31 is executed to form a second masking layer 25 and a second protective layer 26. In this embodiment, the material and formation method of the second masking layer 25 are preferably the same as those of the third masking layer 12. The thickness of the second masking layer 25 is preferably less than the thickness of the third masking layer 12. The material of the second protective layer 26 is preferably silicon oxide, but is not limited thereto. The function of the second protective layer 26 is to prevent the second photoresist layer 17 from contacting the second masking layer 25, and the thickness of the second protective layer 26 can be set conventionally.

[0072] See Figure 6 Step S32 is executed to form a photoresist layer and pattern the photoresist layer. The photoresist layer in this step is the second photoresist layer 17. In this embodiment, the patterning of the second photoresist layer 17 can be achieved through photolithography.

[0073] See Figure 7 Step S33 is executed to form the trench structure 18. In this embodiment, the second protective layer 26, the second masking layer 25, and the dielectric layer 13 are sequentially etched using the patterned second photoresist layer 17 as a mask to form the trench structure 18. The etching process in this step is preferably a dry etching process.

[0074] In this embodiment, after the trench structure 18 is formed, step S4 can be executed directly, that is, the patterned second photoresist layer 17 can be used as the mask layer in step S4.

[0075] See Figure 8 Step S4 involves performing wet etching on the trench structure 18 to create a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom. The trench structure 18 can be a shape that is wide in the middle and narrow at the top and bottom (i.e., narrow-wide-narrow). In this embodiment, the trench structure 18 must gradually widen from the top port away from the semiconductor substrate towards the bottom port; that is, the top port of the trench structure 18 is narrow. Preferably, the top port of the trench structure 18 is the narrowest point in this embodiment. Figure 8 Only the structure corresponding to the wet etching process that forms the trench structure 18 into a shape that is narrow at the top and wide at the bottom is shown.

[0076] The specific process of step S4 may include:

[0077] The trench structure 18 is wet-etched using the patterned photoresist layer as a mask, so that the trench structure 18 is formed into a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom.

[0078] This embodiment performs wet etching to form the trench structure 18 into a shape that is narrower at the top and wider at the bottom, or a shape that alternates between narrow and wide sections from top to bottom. Furthermore, the longitudinal section of the trench structure 18 is also formed into a shape that is narrower at the top and wider at the bottom, or a shape that alternates between narrow and wide sections from top to bottom. The patterned photoresist layer in this step can be a patterned second photoresist layer 17. The solution used for wet etching includes, but is not limited to, a hydrofluoric acid solution. Preferably, the H₂O:HF ratio in the hydrofluoric acid solution is 100:1. During the wet etching process, the dielectric layer 13 on the sidewalls of the trench structure 18 is etched away. The etching rate varies with the concentration of dopant ions. Specifically, the etching rate increases with increasing phosphorus concentration, while it decreases with increasing boron concentration. For example, during wet etching of the trench structure 18, when the doped ions in the dielectric layer 13 are phosphorus (or boron), and the concentration of phosphorus is set to gradually decrease from bottom to top (i.e., along the direction from the semiconductor substrate to the dielectric layer 13) (or the concentration of boron is set to gradually increase from bottom to top), the amount of dielectric layer 13 etched away on the sidewalls of the trench structure 18 gradually decreases from bottom to top. That is, less dielectric layer 13 is etched away on the upper sidewall of the trench structure 18, and more dielectric layer 13 is etched away on the lower sidewall of the trench structure 18, resulting in a trench structure 18 that is narrower at the top and wider at the bottom. (See also...) Figure 8The trench structure 18 has a shape that is narrower at the top and wider at the bottom. For example, during wet etching of the trench structure 18, when the dielectric layer 13 is doped with phosphorus (or boron), and the phosphorus concentration is set to gradually increase and then decrease from bottom to top (or the boron concentration is set to gradually decrease and then increase from bottom to top), the amount of dielectric layer 13 etched away on the sidewalls of the trench structure 18 gradually increases and then decreases from bottom to top. That is, less dielectric layer 13 is etched away on the upper and lower sidewalls of the trench structure 18, and more dielectric layer 13 is etched away on the middle sidewalls of the trench structure 18, resulting in a shape that is wider in the middle and narrower at the top and bottom. Simultaneously, due to the isotropic nature of wet etching, part of the dielectric layer 13 can also be etched away along the Y direction, which can further reduce RC delay.

[0079] See Figure 9 In this embodiment, after performing step S4, the semiconductor device manufacturing method may further include: removing the patterned second photoresist layer 17 and the second protective layer 26. In this embodiment, the second photoresist layer 17 can be removed by an ashing process or by using SPM (H2SO4:H2O2 = 5:1). In this embodiment, the second protective layer 26 can be removed by HF, but is not limited thereto.

[0080] See Figure 10 and Figure 11 Step S5 is executed to form an air gap 23. In this embodiment, the air gap 23 is formed by forming a first masking layer 22 on the dielectric layer 13. Since the trench structure 18 after wet etching is narrow at the top and wide at the bottom, or has an alternating shape of narrow and wide at the top and bottom, the upper port of the trench structure 18 is narrow. Therefore, when the first masking layer 22 is deposited, the upper port of the trench structure 18 will be sealed in advance, thereby forming an air gap 23. When the trench structure 18 after wet etching is narrow at the top and wide at the bottom, the shape of the formed air gap 23 is also narrow at the top and wide at the bottom, as can be seen in [reference]. Figure 10 When the groove structure 18 after wet etching has a shape that alternates between narrow and wide from top to bottom, the shape of the resulting air gap 23 also alternates between narrow and wide from top to bottom. For example, when the groove structure 18 after wet etching has a shape that is wide in the middle and narrow at the top and bottom, the shape of the resulting air gap 23 is also wide in the middle and narrow at the top and bottom, as can be seen in [reference needed]. Figure 11 The material and formation method of the first masking layer 22 are preferably the same as those of the third masking layer 12. Since the dielectric constant of the air gap 23 is very small, RC delay can be reduced.

[0081] In this embodiment, after the step of forming the air gap 23, the structure after forming the air gap 23 can be used as a semiconductor substrate, and steps S1 to S5 can be repeated to prepare the stacked structure.

[0082] Furthermore, the present invention also provides a semiconductor device, which can be fabricated using the above-described semiconductor device manufacturing method, specifically using steps S1 to S5. The semiconductor device may include: a substrate layer 11, a third masking layer 12 located on the substrate layer 11, a dielectric layer 13 located on the third masking layer 12, an air gap 23 located in the dielectric layer 13, a first masking layer 22 located on the dielectric layer 13, and a plurality of conductive plugs 16 penetrating the dielectric layer 13 and the third masking layer 12, wherein the air gap 23 is located in the dielectric layer 13 between adjacent conductive plugs 16. The semiconductor device may further include a second masking layer 25 located between the dielectric layer 13 and the first masking layer 22. The shape of the air gap 23 may be narrow at the top and wide at the bottom, or it may be a shape that alternates between narrow and wide from top to bottom, for example, a shape that is wide in the middle and narrow at the top and bottom.

[0083] An air gap is formed in the dielectric layer of the semiconductor device in this embodiment of the invention, which reduces the dielectric constant k and thus reduces RC delay.

[0084] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

[0085] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and a dielectric layer is formed on the semiconductor substrate, the dielectric layer having doped ions of varying concentrations; Multiple conductive plugs are formed, and each of the conductive plugs penetrates the dielectric layer; A trench structure is formed in the dielectric layer between adjacent conductive plugs using photolithography and etching processes; The trench structure is subjected to wet etching to form a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom. A first masking layer is formed on the dielectric layer, and the first masking layer seals the upper port of the trench structure to form an air gap.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The dielectric layer is formed using a chemical vapor deposition process, wherein the reactants used in the chemical vapor deposition process include silicon-containing compounds, oxygen, and compounds containing doped ions.

3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, When the doping ions of the dielectric layer include phosphorus, the compound containing the doping ions includes triethyl phosphate. During the formation of the dielectric layer, the flow rate of the compound containing the doping ions gradually decreases or gradually increases and gradually decreases alternately, and finally the flow of the compound containing the doping ions stops after gradually decreasing. The flow rate range of the compound containing the doping ions is 50 mg / min to 300 mg / min. When the dopant ions of the dielectric layer include boron, the compound containing the dopant ions includes one of triethoxyboron and diborane. During the formation of the dielectric layer, the flow rate of the compound containing the dopant ions gradually increases or gradually decreases and gradually increases, and finally the flow of the compound containing the dopant ions stops after gradually increasing. The flow rate of the compound containing the dopant ions ranges from 50 mg / min to 300 mg / min.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The dielectric layer is made of silicon oxide, and the thickness of the dielectric layer is [missing information].

5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The doping methods for the doped ions in the dielectric layer include ion implantation.

6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps for forming the trench structure using photolithography and etching processes include: A second masking layer and a protective layer are sequentially formed on the dielectric layer and the conductive plug; A photoresist layer is formed on the protective layer and the photoresist layer is patterned, with the patterned photoresist layer exposing a portion of the upper surface of the protective layer between adjacent conductive plugs. The patterned photoresist layer is used as a mask to sequentially perform dry etching on the protective layer, the second masking layer, and the dielectric layer to form the trench structure.

7. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The steps of performing wet etching on the trench structure include: The patterned photoresist layer is used as a mask to perform wet etching on the trench structure, so that the trench structure is narrow at the top and wide at the bottom or has multiple alternating narrow and wide shapes from top to bottom.

8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The solution used in the wet etching process includes a hydrofluoric acid solution.

9. A semiconductor device, characterized in that, It is prepared by the manufacturing method of any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, An air gap is formed in the dielectric layer of the semiconductor device, and the air gap has a shape that is narrow at the top and wide at the bottom, or a shape that alternates between narrow and wide at the top and bottom.

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